FX003

TPS51219 TI

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www.ti.com SLUSAG1B –MARCH 2011–REVISED OCTOBER 2011 HighPerformance,Single-SynchronousStep-DownController withDifferentialVoltageFeedback 1FEATURES DESCRIPTION The TPS51219 isa small-sizedsinglebuck controller 23• DifferentialVoltageFeedback withadaptiveon-timecontrol.Itprovidesa choiceof• DC Compensation forAccurateRegulation controlmodes (D-CAP™ or D-CAP2 ™) to meet a

• Wide InputVoltageRange: 3 V to28 V wide rangeofsystem requirements.Itisdesignedfor tightDC regulationrequirementssuch as theVCCIO• Output VoltageRange: 0.5V to2.0V with applicationfor Intel® notebooks.The performanceFixedOptions of1.05V and 1.00V and flexibilityof the TPS51219 makes itsuitablefor• Wide Output Load Range: 0 A to20 A+ low outputvoltage,high current,PC system power
• AdaptiveOn-Time ModulationwithSelectable railsand similarpoint-of-load(POL) power supplies. ControlArchitectureand Frequency Differentialvoltage feedback and the voltage compensation functioncombine to provide high– D-CAP ™ Mode at300 kHz/400kHz forFast precisionpower toloaddevices.TransientResponse A smallpackage,fixedvoltageoptionsand minimal– D-CAP2 ™ Mode at500 kHz/670kHz for externalcomponent count saves cost and space,Ceramic Output Capacitor while a dedicatedEN pin and pre-setfrequency• 4700 ppm/ °C, Low-Side R DS(on) CurrentSensing selectionsminimizedesigneffort.The skip-modeat
• R SENSE AccurateCurrentSense Option lightloadcondition,stronggatedrivers,and low-side FET R DS(on) currentsensingprovideshighefficiency• Internal,1-ms VoltageServo Softstart operationover a broad load range. The external• Built-InOutput Discharge resistorcurrent sense option enables accurate
• Power Good Output currentsensing.The conversioninputvoltage(the high-sideFET drainvoltage)rangesfrom3 V to28 V• IntegratedBoost Switch and outputvoltageranges from 0.5 V to 2.0 V. The• Built-InOVP/UVP/OCP devicerequiresan external5-V supply.• Thermal Shutdown (Non-latched) The TPS51219 isavailableina 16-pin,QFN package• 3 mm × 3 mm, 16-Pin,QFN (RTE) Package and isspecifiedforambienttemperaturefrom -40°C to85°C.APPLICATIONS
• Notebook Computers
• I/OSupplies Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsofTexas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2D-CAP, D-CAP2 aretrademarksofTexas Instruments. 3Intelisa registeredtrademarkofIntel. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 2011,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.

SLUSAG1B –MARCH 2011–REVISED OCTOBER 2011 www.ti.com These deviceshave limitedbuilt-inESD protection.The leadsshouldbe shortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamage totheMOS gates. ORDERING INFORMATION (1) ORDERABLE DEVICE OUTPUT MINIMUMTA PACKAGE PINSNUMBER SUPPLY QUANTITY TPS51219RTER Tape and reel 3000 –40°C to85°C PlasticQuad FlatPack (QFN) 16 TPS51219RTET Mini-reel 250 (1) Forthemost currentpackage and orderinginformationsee thePackage OptionAddendum attheend ofthisdocument,orsee theTI web siteatwww.ti.com. ABSOLUTE MAXIMUM RATINGS (1) overoperatingfree-airtemperaturerange(unlessotherwisenoted) VALUE UNIT MIN MAX BST –0.3 36 BST (3) –0.3 6 SW –5 30 Inputvoltagerange(2) EN, MODE, TRIP,V5 –0.3 6.0 V COMP, REFIN, VSNS –0.3 3.6 GSNS –0.35 0.35 PGND –0.3 0.3 DH –5 36 DH (3) –0.3 6 Outputvoltagerange(2) DL –0.3 6 V PGOOD –0.3 6 VREF –0.3 3.6 Junctiontemperaturerange,TJ 125 °C Storagetemperaturerange,TSTG –55 150 °C (1) Stressesbeyond thoselistedunderabsolutemaximum ratingsmay cause permanentdamage tothedevice.These arestressratings onlyand functionaloperationofthedeviceattheseorany otherconditionsbeyond thoseindicatedunderrecommended operating conditionsisnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmay affectdevicereliability. (2) Allvoltagevaluesarewithrespecttothenetworkgroundterminalunlessotherwisenoted. (3) VoltagevaluesarewithrespecttotheSW terminal.

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www.ti.com SLUSAG1B –MARCH 2011–REVISED OCTOBER 2011 RECOMMENDED OPERATING CONDITIONS MIN TYP MAX UNIT Supplyvoltage V5 4.5 5.5 V BST –0.1 33.5 BST (1) –0.1 5.5 SW -3 28 SW (2) –4.5 28 Inputvoltagerange V EN, TRIP,MODE –0.1 5.5 REFIN, VSNS, COMP –0.1 3.5 GSNS –0.3 0.3 PGND –0.1 0.1 DH –3 33.5 DH (1) –0.1 5.5 DH (2) –4.5 33.5 Outputvoltagerange V DL –0.1 5.5 PGOOD –0.1 5.5 VREF –0.1 3.5 TA Operatingfree-airtemperature –40 85 °C (1) VoltagevaluesarewithrespecttotheSW terminal. (2) Thisvoltageshouldbe appliedforlessthan30% oftherepetitiveperiod. THERMAL INFORMATION TPS51219 THERMAL METRIC (1) RTE UNITS

16 PINS

θJA Junction-to-ambientthermalresistance(2) 48.5 θJCtop Junction-to-case(top)thermalresistance(3) 49.5 θJB Junction-to-boardthermalresistance(4) 22.1 °C/W ψJT Junction-to-topcharacterizationparameter(5) 0.7 ψJB Junction-to-boardcharacterizationparameter(6) 22.1 θJCbot Junction-to-case(bottom)thermalresistance(7) 7.1 (1) Formore informationabouttraditionaland new thermalmetrics,see theIC Package ThermalMetricsapplicationreport,SPRA953 . (2) The junction-to-ambientthermalresistanceundernaturalconvectionisobtainedina simulationon a JEDEC-standard,high-Kboard,as specifiedinJESD51-7,inan environmentdescribedinJESD51-2a. (3) The junction-to-case(top)thermalresistanceisobtainedby simulatinga coldplateteston thepackage top.No specific JEDEC-standardtestexists,buta closedescriptioncan be foundintheANSI SEMI standardG30-88. (4) The junction-to-boardthermalresistanceisobtainedby simulatinginan environmentwitha ringcoldplatefixturetocontrolthePCB temperature,as describedinJESD51-8. (5) The junction-to-topcharacterizationparameter,ψJT,estimatesthejunctiontemperatureofa deviceina realsystemand isextracted fromthesimulationdataforobtainingθJA,usinga proceduredescribedinJESD51-2a (sections6 and 7). (6) The junction-to-boardcharacterizationparameter,ψJB,estimatesthejunctiontemperatureofa deviceina realsystemand isextracted fromthesimulationdataforobtainingθJA ,usinga proceduredescribedinJESD51-2a (sections6 and 7). (7) The junction-to-case(bottom)thermalresistanceisobtainedby simulatinga coldplateteston theexposed (power)pad.No specific JEDEC standardtestexists,buta closedescriptioncan be foundintheANSI SEMI standardG30-88. Copyright© 2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3

SLUSAG1B –MARCH 2011–REVISED OCTOBER 2011 www.ti.com

ELECTRICAL CHARACTERISTICS

overoperatingfree-airtemperaturerange,VV5 = 5 V,VMODE = 0 V,VEN = 5 V (unlessotherwisenoted) PARAMETER TEST CONDITION MIN TYP MAX UNIT SUPPLY CURRENT IV5 V5 supplycurrent TA = 25°C, No load,VEN = 5 V 560 μA IV5SDN V5 shutdowncurrent TA = 25°C, No load,VEN = 0 V 0.5 2.0 μA VREF OUTPUT VVREF Outputvoltage IVREF = 0 μA wrtGSNS 2.000 V 0 μA ≤ IVREF < 30 μA,TA = 0°C to85°C -0.8% 0.8% VVREF(tol) Outputvoltagetolerance 0 μA ≤ IVREF < 300 μA,TA = –40°C to85°C -1.2% 1.2% IVREF(ocl) Currentlimit VVREF-GSNS = 1.7V 0.4 1.0 mA OUTPUT VOLTAGE VREFIN = 0 V 1.000 V VVSNS VSNS sense voltage VREFIN = 3.3V 1.050 V 0.5V ≤ VREFIN ≤ 2 V VREFIN V VREFIN = 0 V,0°C ≤ TA ≤ 85°C –9 9 VREFIN = 0 V,-40°C ≤ TA ≤ 85°C -14 14 VVSNS(tol) VSNS regulationvoltagetolerance VREFIN = 3.3V,0°C ≤ TA ≤ 85°C –9 9 mV VREFIN = 3.3V,-40°C ≤ TA ≤ 85°C -14 14 VREFIN = 0.5V and VREFIN = 2.0V -5 5 VREFIN1 REFIN voltagefor1.00-Voutput 0.3 V VREFIN1P05 REFIN voltagefor1.05-Voutput 2.2 V VOFF_LPCMP Loop comparatoroffsetvoltage VREFIN = 1 V,VSNS shortedtoCOMP -5 5 mV VREFIN = 0 V,VVSNS = 0.95V 0.885 V VCOMPCLP COMP clamp voltage VREFIN = 0 V,VVSNS = 1.05V 1.115 V gM Erroramplifiertransconductance VREFIN = 0 V 130 μS IVSNS VSNS inputcurrent VVSNS = 1.05V -1 1 μA IREFIN REFIN inputcurrent VREFIN = 0 V –1 1 μA IVSNS(dis) VSNS dischargecurrent VEN = 0 V,VVSNS = 0.5V 5 12 mA SWITCH MODE POWER SUPPLY (SMPS) FREQUENCY VIN = 12 V,VVSNS = 1.8V,VMODE = 2.5V 400 VIN = 12 V,VVSNS = 1.8V,VMODE = 1.67V 300 fSW Switchingfrequency kHz VIN = 12 V,VVSNS = 1.8V,VMODE = 0.2V 670 VIN = 12 V,VVSNS = 1.8V,VMODE = 0.033V 500 tON(min) Minimum on time DH risingtofalling(1) 60 ns tOFF(min) Minimum offtime DH fallingtorising 320 MOSFET DRIVERS Source,IDH = –50 mA 1.6 3.0 R DH DH resistance Sink,IDH = 50 mA 0.6 1.5 Ω Source,IDL = –50 mA 0.9 2.0 R DL DL resistance Sink,IDL = 50 mA 0.5 1.2 DH-offtoDL-on 10 tDEAD Dead time ns DL-offtoDH-on 20 INTERNAL BOOT STRAP SWITCH VFBST Forwardvoltage VV5-BST ,TA = 25°C, IF = 10 mA 0.1 0.2 V IBSTLK BST leakagecurrent TA = 25°C, VBST = 33 V,VSW = 28 V 0.01 1.5 μA (1) Ensuredby design.Not productiontested.

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www.ti.com SLUSAG1B –MARCH 2011–REVISED OCTOBER 2011 ELECTRICAL CHARACTERISTICS (continued) overoperatingfree-airtemperaturerange,VV5 = 5 V,VMODE = 0 V,VEN = 5 V (unlessotherwisenoted) PARAMETER TEST CONDITION MIN TYP MAX UNIT LOGIC THRESHOLD IMODE MODE sourcecurrent 15.6 16.7 17.8 μA MODE 0-1 113 143 173 MODE 1-2 253 283 313 MODE 2-3 433 458 483 VTHMODE MODE thresholdvoltage MODE 3-4 644 667 690 mV MODE 4-5 914 949 984 MODE 5-6 1329 1369 1409 MODE 6-7 1950 2000 2050 VLL EN low-levelvoltage 0.5 VLH EN high-levelvoltage 1.8 V VLHYST EN hysteresisvoltage 0.25 ILLK EN inputleakagecurrent –1 0 1 μA SOFT START tSS Soft-starttime Internalsoft-starttime 1.1 ms POWERGOOD COMPARATOR PGOOD infromhigher 106% 108% 110% PGOOD infromlower 90% 92% 94% VTHPG PGOOD threshold PGOOD outtohigher 114% 116% 118% PGOOD outtolower 82% 84% 86% IPG PGOOD sinkcurrent VPGOOD = 0.5V 3 6 mA DelayforPGOOD in 0.8 1.0 1.2 ms tPGDLY PGOOD delaytime DelayforPGOOD out,with100 mV overdrive 0.25 µs tPGCMPSS PGOOD start-updelay PGOOD comparatorwake-up delay 2.5 ms IPG(leak) PGOOD leakagecurrent -1 0 1 µA CURRENT DETECTION ITRIP TRIP sourcecurrent TA = 25°C, VTRIP = 0.4V,R DS(on) sensing 9 10 11 μA TRIP sourcecurrenttemperatureTC ITRIP (2) R DS(on) sensing 4700 ppm/°Ccoefficient(2) VTRIP VTRIP voltagerange R DS(on) sensing 0.2 3 V VTRIP = 3.0V,R DS(on) sensing 360 375 390 VOCL Currentlimitthreshold VTRIP = 1.6V,R DS(on) sensing 190 200 210 mV VTRIP = 0.2V,R DS(on) sensing 20 25 30 VTRIP = 3.0V,R DS(on) sensing –390 –375 –360 VOCLN Negativecurrentlimitthreshold VTRIP = 1.6V,R DS(on) sensing –212 –200 –188 mV VTRIP = 0.2V,R DS(on) sensing –30 –25 –20 VRTRIP Resistorsense tripvoltage Resistorsensing 25 mV VZC Zerocrossdetectionoffset 0 mV (2) Ensuredby design.Not productiontested. Copyright© 2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5

SLUSAG1B –MARCH 2011–REVISED OCTOBER 2011 www.ti.com ELECTRICAL CHARACTERISTICS (continued) overoperatingfree-airtemperaturerange,VV5 = 5 V,VMODE = 0 V,VEN = 5 V (unlessotherwisenoted) PARAMETER TEST CONDITION MIN TYP MAX UNIT PROTECTIONS Wake-up 4.2 4.4 4.5 VUVLO V5 UVLO thresholdvoltage V Shutdown 3.7 3.9 4.1 VOVP OVP thresholdvoltage OVP detectvoltage 118% 120% 122% tOVPDLY OVP propagationdelay With100 mV overdrive 370 ns VUVP UVP thresholdvoltage UVP detectvoltage 66% 68% 70% tUVPDLY UVP delay 1 ms tUVPENDLY UVP enabledelay 1.4 ms THERMAL SHUTDOWN Shutdown temperature(3) 140 TSDN Thermalshutdownthreshold °C Hysteresis(3) 10 (3) Ensuredby design.Not productiontested.

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www.ti.com SLUSAG1B –MARCH 2011–REVISED OCTOBER 2011 DEVICE INFORMATION RTE PACKAGE (TOP VIEW) PIN FUNCTIONS PIN I/O DESCRIPTION NAME NO. BST 13 I High-sideMOSFET gatedriverbootstrapvoltageinput.Connecta capacitorfromtheBST pintotheSW pin. ConnectionfortheDC compensationintegratorforimprovedload-lineperformance.Connecta capacitorfrom thispintotheVSNS pin(when operatinginD-CAP2 mode),ortothepositiveterminaloftheoutputcapacitorCOMP 5 I (when operatinginD-CAP mode).ConnectdirectlytotheVSNS pinwithoutcapacitortodisabletheintegrator function. DH 11 O High-sideMOSFET gatedriveroutput. DL 10 O Low-sideMOSFET gatedriveroutput. EN 14 I Enablepin.3.3-VI/Olevel,100 ns de-bounce.ShorttoGND todisablethedevice. GND 7 – Deviceanalogground;Connecttoa quietpointon thesystemGND plane GSNS 3 I Voltagesense returntieddirectlytotheGND sense pointoftheload.ShorttoGND ifremotesense isnotused. Connecta resistortoGND toconfigureswitchingfrequency,controlmode and currentsense scheme. (SeeMODE 15 I Table2) Synchronouslow-sideMOSFET gatedriverreturn.Alsoserveas thecurrentsensinginput(+).ConnecttothePGND 8 – GND pinas closeas possibletothedevice. PGOOD 16 O Powergood signalopen drainoutput.PGOOD goes highwhen theoutputvoltageiswithinthetargetrange. REFIN 2 I Outputvoltagesettingpin.See theVREF and REFIN, OutputVoltagesection. SW 12 I/O High-sideMOSFET gatedriverreturn.R DS(on) currentsensinginput(–)when usingR DS(on) currentsensing. Currentsense comparatorinput(-)forresistorcurrentsensing.Or overcurrentthresholdsettingpinforR DS(on) TRIP 6 I currentsensingifconnectedtoGND throughan OCL settingresistor.ForR DS(on) currentsensingoperation,10 μA atroom temperature,TC =4700ppm/°C, issourcedtosetthetripvoltage. VSNS 4 I Voltagesense linetieddirectlytotheloadvoltagesense point. VREF 1 O 2.0-V±0.8% voltagereferenceoutput. V5 9 I 5V power supplyinputforinternalcircuitsand MOSFET gatedrivers. Thermal – – Thermalpad.ConnectdirectlytosystemGND planewithmultiplevias.pad Copyright© 2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7

13 BST

16 PGOOD

VREFIN + 20% VSNS 11 DH 10 DL tON One- Shot UV OV VREFIN – 32% 14EN Soft-Start NOC 1VREF Reference 7 R R Control Mode On-Time Current Sense Selection 16.7 /c109A

15 MODE

VREFIN +8/16% VREFIN – 8/16% Discharge V5OK 4.3 V/3.9 V UVPOVP COMP 5 VBG 5-V UVLO TPS51219 UDG-11007 EN 3GSNS 7GND ENSet_1p05v Set_adj Discharge R 8 R +VREFIN 2.2 V 0.3 V Set_adj Set_1p05v EN 25 mV Set_resistor_sensing Set_resistor_sensing TPS51219 SLUSAG1B –MARCH 2011–REVISED OCTOBER 2011 www.ti.com FUNCTIONAL BLOCK DIAGRAM

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−50 −25 0 25 50 75 100 125 Junction Temperature (°C) V5 Supply Current (µA) VV5 = 5 V VEN = 5 V No Load −50 −25 0 25 50 75 100 125 Junction Temperature (°C) V5 Shutdown Current (µA) VV5 = 5 V VEN = 0 V No Load −50 −25 0 25 50 75 100 125 Junction Temperature (°C) Trip Source Current (µA) VV5 = 5 V VTRIP = 0.5 V 100 110 120 130 140 150 −50 −25 0 25 50 75 100 125 Junction Temperature (°C) UVP/OVP Threshold (%) UVP OVP VV5 = 5 V VREFIN = 0 V 1.980 1.985 1.990 1.995 2.000 2.005 2.010 2.015 2.020 0 50 100 150 200 250 300 350 400 VREF Current (µA) VREF Voltage (V) VV5 = 5 V TA = 27°C 200 300 400 500 600 700 800 900 6 8 10 12 14 16 18 20 22 Input Voltage (V) Switching Frequency (kHz) R MODE = 1 kΩ R MODE = 12 kΩ R MODE = 100 kΩ R MODE = 200 kΩ IOUT = 10 A TPS51219 www.ti.com SLUSAG1B –MARCH 2011–REVISED OCTOBER 2011 TYPICAL CHARACTERISTICS Figure1.V5 Supply Currentvs JunctionTemperature Figure2.V5 Shutdown Currentvs JunctionTemperature Figure3.CurrentSense Currentvs JunctionTemperature Figure4.OVP/UVP Thresholdvs JunctionTemperature Figure5.VREF Load Regulation Figure6.SwitchingFrequency vs InputVoltage Copyright© 2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 9

0 2 4 6 8 10 12 14 16 18 20 Output Current (A) Switching Frequency (kHz) R MODE = 100 kΩ VIN = 12 V VOUT = 1.05 V L = 0.56 µH 100 200 300 400 500 600 700 800 0 2 4 6 8 10 12 14 16 18 20 Output Current (A) Switching Frequency (kHz) R MODE = 200 kΩ VIN = 12 V VOUT = 1.05 V L = 0.56 µH 100 200 300 400 500 600 700 800 0 2 4 6 8 10 12 14 16 18 20 Output Current (A) Switching Frequency (kHz) R MODE = 1 kΩ VIN = 12 V VOUT = 1.05 V L = 0.45 µH 100 200 300 400 500 600 700 800 0 2 4 6 8 10 12 14 16 18 20 Output Current (A) Switching Frequency (kHz) R MODE = 12 kΩ VIN = 12 V VOUT = 1.05 V L = 0.36 µH 1.030 1.035 1.040 1.045 1.050 1.055 1.060 1.065 1.070 0 2 4 6 8 10 12 14 16 18 20 1.05−V Output Current (A) VSNS−GSNS − 1.05−V Output Voltage (V) R MODE = 1 kΩ VIN = 12 V G001 1.030 1.035 1.040 1.045 1.050 1.055 1.060 1.065 1.070 6 8 10 12 14 16 18 20 22 Input Voltage (V) VSNS−GSNS − 1.05−V Output Voltage (V) IOUT = 0 A IOUT = 10 A R MODE = 1 kΩ G001 TPS51219 SLUSAG1B –MARCH 2011–REVISED OCTOBER 2011 www.ti.com TYPICAL CHARACTERISTICS Figure11 and Figure12 refertotheapplicationschematicinFigure33. Figure7.SwitchingFrequency vs Load Current Figure8.SwitchingFrequency vs Load Current Figure9.SwitchingFrequency vs Load Current Figure10.SwitchingFrequency vs Load Current Figure11.1.05-VOutput Load Regulation Figure12.1.05-VOutput LineRegulation

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0.980 0.985 0.990 0.995 1.000 1.005 1.010 1.015 1.020 0 2 4 6 8 10 1.00−V Output Current (A) VSNS−GSNS − 1.00−V Output Voltage (V) R MODE = 1 kΩ VIN = 12 V G001 100 0.001 0.01 0.1 1 10 100 1.05−V Output Current (A) Efficiency (%) VIN = 8 V VIN = 12 V VIN = 20 VR MODE = 1 kΩ 0.980 0.985 0.990 0.995 1.000 1.005 1.010 1.015 1.020 6 8 10 12 14 16 18 20 22 Input Voltage (V) VSNS−GSNS − 1.00−V Output Voltage (V) IOUT = 0 A IOUT = 10 A R MODE = 1 kΩ G001 100 0.001 0.01 0.1 1 10 100 1.00−V Output Current (A) Efficiency (%) VIN = 8 V VIN = 12 V VIN = 20 VR MODE = 1 kΩ TPS51219 www.ti.com SLUSAG1B –MARCH 2011–REVISED OCTOBER 2011 TYPICAL CHARACTERISTICS Figure11,Figure12,and Figure13 refertotheapplicationschematicinFigure33. Figure14,Figure15 and Figure16,refertotheapplicationschematicinFigure33 excepttheparameters ofL1 (0.56µH),C7 (2× 330 µF)and Q3 (notused). Figure13.1.05-VOutput Efficiency Figure14.1.00-VOutput Load Regulation Figure15.1.00-VOutput LineRegulation Figure16.1.00-VOutput Efficiency Copyright© 2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 11

VIN=20 V VSNS-GSNS (20 mV/div) offset: 1.05 V IOUT (8 A/div) offset: 6 A COUT = 5 x 330 µF(Bulk) + 12 x 22 µF(MLCC) VIN=20 V VSNS-GSNS (20 mV/div) offset: 1.00 V IOUT (8 A/div) COUT = 2 x 330 µF(Bulk) + 12 x 22 µF(MLCC) EN (5 V/div) VSNS-GSNS (500mV/div) PGOOD (5V/div) Time (400 µs/div) IOUT = 15A Time (400 µs/div) EN (5 V/div) VSNS-GSNS (500mV/div) PGOOD (5V/div) IOUT = 0 A 0.5-V Pre-biased TPS51219 SLUSAG1B –MARCH 2011–REVISED OCTOBER 2011 www.ti.com TYPICAL CHARACTERISTICS Figure17.1.05-VLoad TransientResponse Figure18.1.00-VLoad TransientResponse

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Time (100 ms/div) EN (5 V/div) VSNS-GSNS (500mV/div) PGOOD (5V/div) IOUT = 0 A 100 1000 10000 100000 1000000 −80 −60 −40 −20 −180 −135 −90 −45 135 180 Frequency (Hz) Gain (dB) Phase (°) Gain Phase VIN =12 V IOUT =15 A R MODE =1 kΩ TPS51219 www.ti.com SLUSAG1B –MARCH 2011–REVISED OCTOBER 2011 TYPICAL CHARACTERISTICS Figure22 referstoapplicationschematicofFigure33. Figure21.1.05-VSoft-stopWaveforms Figure22.Bode Plot,VOUT =1.05V Copyright© 2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 13

0,1 /c109F UDG-11042 TPS51219 SLUSAG1B –MARCH 2011–REVISED OCTOBER 2011 www.ti.com

APPLICATION INFORMATION

Swtich Mode Power Supply Control The TPS51219 isa highperformance,single-synchronousstep-downcontrollerwithdifferentialvoltagefeedback. The TPS51219 realizesaccurateregulationatthespecificloadpointoverwide loadrangewiththecombination ofthreefunctions.

• 2-V Reference with0.8% Tolerance.Internalvoltagedividerprovidesprecisereference(See Table1 inthe VREF and REFIN, OutputVoltagesection).A valueof0.1µF isrecommended as thedecouplingcapacitance between VREF and GSNS pins.
• Integrator.Feedback capacitanceconnectedfromtheoutput(COMP pin)totheinput(VSNS pin)oftheerror amplifiercomprisesintegrator,which increasesgain at DC to low frequencyregionand improves load regulationoftheoutputvoltage.10nF isrecommended as thecapacitancebetween VSNS and COMP pins.
• Differentialremote sensing. Differentialfeedbackprovidespreciseoutputvoltagecontrolat the pointof load.Connect VSNS and GSNS directlyto outputvoltagesense pointand ground returnpointat the load device,respectively.ShortGSNS toGND ifremotesense isnotused. The TPS51219 supportstwo controlarchitectures,D-CAP ™ mode and D-CAP2 ™ mode. Both controlmodes do not requirecomplex externalcompensation networks and are suitablefor designs with small external components counts.The D-CAP ™ mode providesfasttransientresponsewithappropriateamount ofequivalent seriesresistance(ESR) on theoutputcapacitors.The D-CAP2 ™ mode isdedicatedfora configurationwithvery low ESR outputcapacitorssuch as multi-layerceramiccapacitors(MLCC). For the both modes, an adaptive on-timecontrolscheme isused toachievepseudo-constantfrequency.The TPS51219 adjuststheon-time(tON ) tobe inverselyproportionaltotheinputvoltage(VIN) and proportionaltotheSMPS outputvoltage(VOUT ).The switchingfrequencyremainsnearlyconstantover the variationof inputvoltageat the steady-statecondition. Controlmodes and switchingfrequencyareselectedby theMODE pindescribedinTable2. VREF and REFIN, Output Voltage The deviceprovidesa 2.0-V,±0.8% accurate,voltagereferencefrom VREF. Thisoutputhas a 300-µA current capabilitytodrivetheREFIN inputvoltagethrougha voltagedividercircuit.A capacitorwitha valueof0.1-µF or largershouldbe attachedclosetotheVREF terminal. The SMPS outputvoltageisdefinedby REFIN voltage,withintherangebetween 0.5V and 2.0V, programmed by theresister-dividerconnectedbetween VREF and GSNS. (See Figure23 and ExternalComponents Selection section.)A few nano-faradsofcapacitancefromREFIN toGSNS isrecommended forstableoperation.A voltage dividerand a filtercapacitortothispinshouldbe referencedtoGSNS. Fixedoutputvoltagecan be setas shown inTable1. XXXX Table1.Output VoltageSelection REFIN VOLTAGE (V) OUTPUT VOLTAGE (V) 3.3 1.05 GSNS 1.00 ResistorDivider Adjustable XXXX XXXX XXXX XXXXFigure23. VoltageReferenceConnections XXXX

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700 /c109s400 /c109s 1.4 ms EN VREF VOUT PGOOD UDG-11008 TPS51219 www.ti.com SLUSAG1B –MARCH 2011–REVISED OCTOBER 2011 Soft-Startand Powergood Providea voltagesupplyto VIN and V5 beforeassertingEN to high.TPS51219 providesintegratedsoft-start functionsto suppressin-rushcurrentat start-up.The soft-startisachievedby controllinginternalreference voltagerampingup.Figure24 shows thestart-upwaveforms.The switchingregulatorwaitsfor400μs afterEN assertion.The MODE pinvoltageisreadinthisperiod.A typicalVOUT ramp up durationis700 μs. THe TPS51219 has a powergood open-drainoutputthatindicatestheVOUT voltageiswithinthetargetrange. The targetvoltagewindow and transitiondelaytimesofthePGOOD comparatorare ±8% (typ)and 1-ms delay forassertion(lowto high),and ±16% (typ)and 2-µs delayforde-assertion(highto low)duringrunning.The PGOOD start-updelayis2.5 ms afterEN isassertedto high.The timeconstant,which iscomposed of the REFIN capacitorand a resistordivider,needs to be shortenough to reach the targetvaluebeforePGOOD comparatorenabled. Figure24. TypicalStart-upWaveforms MODE Pin Configuration The TPS51219 reads the MODE pin voltagewhen the EN signalisraisedhigh and storesthe statusin a register.A 16.7-μA currentissourcedfromtheMODE pinduringthistimetoreadthevoltageacrosstheresistor connectedbetween the pinand GND. Table 2 shows resistorvalues,correspondingcontrolmode, switching frequencyand currentsense operationconfigurations. Table2.MODE Selection RESISTANCE BETWEEN CONTROL SWITCHING CURRENT SENSEMODE NO. MODE AND GND (kΩ) MODE FREQUENCY (kHz) OPERATION 7 200 400 R DS(on) 6 100 300 D-CAP ™ 5 68 300 Resistor 4 47 400 3 33 500 Resistor 2 22 670 D-CAP2 ™ 1 12 670 R DS(on) 0 1 500 Copyright© 2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 15

gM=130 /c109S VSNS REFIN VREF Control Logic and DriverR1 DH DL + 2.0 V VIN Lx ESR COUT RLOAD UDG-11009 VOUT COMP PWM /c61 /c163/c112 /c180 /c180 SW OUT f1f 2 ESR C 3 /c163/c112 /c180 f0Mg

2 C 1 10

SLUSAG1B –MARCH 2011–REVISED OCTOBER 2011 www.ti.com D-CAP ™ Mode Figure25 shows a simplifiedmodel ofD-CAP ™ mode architectureintheTPS51219. Figure25. SimplifiedD-CAP ™ Model The transconductanceamplifierand thecapacitanceC1 configurean integrator.The VSNS voltageiscompared withREFIN voltage.Ripplevoltagegeneratedby ESR oftheoutputcapacitanceisfedback throughtheC1 so thatC1 shouldbe properlyconnectedtothepositiveterminalofoutputcapacitor,notattheremotepointofload. The PWM comparatorcreatesa setsignaltoturnon thehigh-sideMOSFET each cycle.The D-CAP ™ mode offersflexibilityon outputinductanceand capacitanceselectionswithease-of-usewithoutcomplex feedbackloop calculationand externalcomponents.However,itdoes requiresufficientamount ofESR thatrepresentsinductor currentinformationforstableoperationand good jitterperformance.Organic semiconductorcapacitor(s)or specialtypolymercapacitor(s)arerecommended. The requirementforloop stabilityis simple and is describedin Equation 1. The 0-dB frequency,f0, is recommended to be lowerthan 1/3 of the switchingfrequencyto secureproperphase margin.The integrator timeconstantshouldbe longenough compared tof0,forexample one decade low,as describedinEquation2. where

• ESR istheeffectiveseriesresistanceoftheoutputcapacitor
• C OUT isthecapacitanceoftheoutputcapacitor
• fSW istheswitchingfrequency (1) where
• gM istransconductanceoftheerroramplifier(typically130 µS) (2)

16 SubmitDocumentationFeedback Copyright© 2011,Texas InstrumentsIncorporated

(1) (2) tON tOFF Slope (2) Jitter 20 mV Slope (1) Jitter UDG-11010 VREFIN +Noise Time /c180 /c179/c180 OUT SW X V ESR 20 mVf L TPS51219 www.ti.com SLUSAG1B –MARCH 2011–REVISED OCTOBER 2011 Jitterisanotherattributecaused by signal-to-noiseratioof the feedbacksignal.One of the major factorsthat determinejitterperformanceinD-CAP ™ mode isthedown-slopeangleoftheVSNS ripplevoltage.Figure26 shows,inthesame noisecondition,thatjitterisimprovedby making theslopeanglelarger. Figure26. RippleVoltageSlope and JitterPerformance Fora good jitterperformance,use therecommended down slopeofapproximately20 mV perswitchingperiodas shown inFigure26 and Equation3. where

• VOUT istheSMPS outputvoltage
• LX istheinductance (3) Copyright© 2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 17

G REFIN VREF + 2.0 V RC1 CC2 RC2 TPS51219 VOUT ESR COUT SW COMP /c180/c61 /c163/c112 /c180 /c180 /c180 C C SW X OUT R C ff 2 G L C 3 /c163/c112 /c180 f0Mg SLUSAG1B –MARCH 2011–REVISED OCTOBER 2011 www.ti.com D-CAP2 ™ Mode Operation Figure27 shows simplifiedmodel ofD-CAP2 ™ architecture. Figure27. SimplifiedModulatorUsing D-CAP2 ™ Mode When theTPS51219 operatesinD-CAP2 ™ mode, connecttheCOMP and VSNS pinsas shown inFigure27. The transconductanceamplifierand thecapacitanceC1 configurestheintegrator.The D-CAP2 ™ mode inthe TPS51219 includesan internalfeedbacknetworkenablingtheuse ofverylow ESR outputcapacitor(s)such as multi-layerceramiccapacitors(MLCC). The roleoftheinternalnetworkistosense theripple component ofthe inductorcurrentinformationand thencombine itwiththevoltagefeedbacksignal. Using R C1 =R C2 ≡R C and C C1 =C C2 ≡C C , 0-dB frequencyof the D-CAP2 ™ mode isgivenby Equation4. f0 is recommended to be lowerthan 1/3 of the switchingfrequencyto secureproperphase margin.The integrator timeconstantshouldbe longenough compared tof0,forexample one decade low,as describedinEquation5. where

• G isgainoftheamplifierwhichamplifiestheripplecurrentinformationgeneratedby thecompensation circuit (4) (5) The typicalG valueis0.25,and typicalR C C C timeconstantvaluesfor500 kHz and 670 kHz operationare32 μs and 23 μs,respectively. For example,when fSW = 500 kHz and LX=0.45 μH, C OUT shouldbe largerthan 272 μF. At the selectionof capacitor,pay attentionto itscharacteristics.For MLCC use X5R or betterdielectricand take intoaccount deratingofthecapacitanceby bothDC biasand AC bias.When deratingby DC biasand AC biasare80% and 50%, respectively,theeffectivederatingis40% because 0.8x 0.5= 0.4.The capacitanceofspecialtypolymer capacitorsmay change depending on the operatingfrequency.Consultcapacitormanufacturersforspecific characteristics.

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/c40 /c41 /c45/c61 /c180 /c180 /c180 IN OUT OUT LOAD(LL) X IN SW V V V 1I 2 L V f /c230 /c246/c61 /c180 /c231 /c247 /c232 /c248 TRIP OCTRIP TRIP IV R 8 /c40 /c41 /c40 /c41 /c230 /c246 /c230 /c246 /c45/c231 /c247 /c231 /c247/c61 /c43 /c61 /c43 /c180 /c180/c231 /c247 /c231 /c247 /c180/c232 /c248 /c232 /c248 IND(ripple)OCTRIP OCTRIP IN OUT OUT OCL X SW INDS on DS on IV V V V V 1I R 2 R 2 L f V TPS51219 www.ti.com SLUSAG1B –MARCH 2011–REVISED OCTOBER 2011 Light-LoadOperation Inauto-skipmode, theTPS51219 SMPS controllogicautomaticallyreducesitsswitchingfrequencytoimprove light-loadefficiency.To achievethisintelligence,a zerocrossdetectioncomparatorisused topreventnegative inductorcurrentby turningoffthelow-sideMOSFET. Equation6 shows theboundaryloadconditionofthisskip mode and continuousconductionoperation. (6) CurrentSensing Inordertoprovidebothcosteffectivesolutionand good accuracy,TPS51219 supportsbothofMOSFET R DS(on) sensingand externalresistorsensing.For R DS(on) sensingscheme, TRIP pin shouldbe connectedto GND throughthetripvoltagesettingresistor,R TRIP.Inthisscheme, TRIP terminalsources10µA ofITRIP currentand the triplevelisset to 1/8 of the voltageacrossthe R TRIP. The inductorcurrentismonitoredby the voltage between thePGND pinand theSW pinso thattheSW pinisconnectedtothedrainterminalofthelow-side MOSFET. ITRIP has a 4700ppm/°C temperatureslopetocompensate thetemperaturedependency oftheR DS(on). For resistorsensingscheme, an appropriatecurrentsensingresistorshouldbe connectedbetween thesource terminalofthelow-sideMOSFET and PGND. The TRIP pinisconnectedtotheMOSFET sourceterminalnode. The inductorcurrentismonitoredby thevoltagebetween PGND pinand TRIP pin.Ineitherscheme, PGND is used as the positivecurrentsensingnode so thatPGND shouldbe connectedto the propercurrentsensing device,i.e.thesense resistororthesourceterminalofthelow-sideMOSFET. OvercurrentProtection TPS51219 has cycle-by-cycleovercurrentlimitingprotection.The inductorcurrentis monitoredduringthe off-stateand the controllermaintainsthe off-statewhen the inductorcurrentislargerthan the overcurrenttrip level.The tripleveland currentsense operationare determinedby the MODE pin settingand TRIP pin connection(See Table 2 and CurrentSensing section).For R DS(on) sensingscheme, TRIP terminalsources 10 µA and thetriplevelissetto1/8ofthevoltageacrossthisR TRIP resistor.The overcurrenttriplevel,VOCTRIP , isdeterminedby Equation7. (7) Fora resistorsensingscheme, thetriplevel,VOCTRIP ,isa fixedvalueof25 mV. Because thecomparisonismade duringtheoff-state,VOCTRIP setsthevalleyleveloftheinductorcurrent.The loadcurrentOCL level,IOCL ,can be calculatedby consideringtheinductorripplecurrent. OvercurrentlimitingusingR DS(on) sensingisshown inEquation8. where

• IIND(ripple)isinductorripplecurrent (8) Copyright© 2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 19

/c230 /c246 /c230 /c246 /c45/c61 /c43 /c61 /c43 /c180 /c180/c231 /c247 /c231 /c247 /c180/c232 /c248 /c232 /c248 IND(ripple) IN OUT OUT OCL EXT EXT X SW IN I V V V25 mV 25 mV 1I R 2 R 2 L f V TPS51219 SLUSAG1B –MARCH 2011–REVISED OCTOBER 2011 www.ti.com Overcurrentlimitingusingresistorsensingisshown inEquation9. where

• IIND(ripple)isinductorripplecurrent
• R EXT istheexternalcurrentsense resistance (9) Inan overcurrentcondition,thecurrenttotheloadexceeds thecurrenttotheoutputcapacitor,thustheoutput voltagetendstofalldown. Eventually,itcrossestheundervoltageprotectionthresholdand shutsdown. Overvoltageand UndervoltageProtection The TPS51219 setstheovervoltageprotection(OVP) when VSNS voltagereachesa level20% (typ)higherthan theREFIN voltage.When an OV eventisdetected,thecontrollerchanges theoutputtargetvoltageto0 V. This usuallyturnsoffDH and forcesDL to be on. When the inductorcurrentbeginsto flowthroughthe low-side MOSFET and reachesthenegativeOCL, DL isturnedoffand DH isturnedon,fora minimum on-time. Aftertheminimum on-timeexpires,DH isturnedoffand DL isturnedon again.Thisactionminimizestheoutput node undershootdue toLC resonance.When theVSNS reaches0 V, thedriveroutputislatchedas DH off,DL on. The undervoltageprotection(UVP) latchissetwhen the VSNS voltageremainslowerthan 68% (typ)of the REFIN voltagefor1 ms orlonger.Inthisfaultcondition,thecontrollerlatchesDH lowand DL lowand discharges theVOUT .UVP detectionfunctionisenabledafter1.2ms ofSMPS operationtoensurestartup. To releasetheOVP and UVP latches,toggleEN oradjusttheV5 voltagedown and up beyond theundervoltage lockoutthreshold. V5 UndervoltageLockout Protection TPS51219 has a 5-V supplyundervoltagelockoutprotection(UVLO) threshold.When the V5 voltageislower thanUVLO thresholdvoltage,typically3.9V,VOUT isshutoff.Thisisa non-latchprotection. Thermal Shutdown TPS51219 includesan internaltemperaturemonitor.Ifthetemperatureexceedsthethresholdvalue,140°C (typ), VOUT isshutoff.The stateofVOUT isopen atthermalshutdown.Thisisa non-latchprotectionand theoperation isrestartedwithsoft-startsequence when thedevicetemperatureisreducedby 10°C (typ).

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/c40 /c41 /c61 /c230 /c246 /c231 /c247 /c231 /c247 /c231 /c247 /c45/c180/c230 /c246/c231 /c247 /c231 /c247/c45/c231 /c247 /c231 /c247/c231 /c247 /c232 /c248/c232 /c248 IND ripple OUT R1R2 2.0 1I ESR V 2 /c40 /c41 /c40 /c41/c40 /c41 /c40 /c41 /c40 /c41 /c40 /c41/c40 /c41 /c40 /c41 /c45 /c180 /c45 /c180 /c61 /c180 /c61 /c180 /c180 /c180 IN OUT OUT IN OUT OUTmax max X SW IN O SW ININD ripple max max max V V V V V V1 3L I f V I f V /c40 /c41 /c40 /c41 /c40 /c41/c40 /c41 /c40 /c41 /c45 /c180 /c61 /c43 /c180 /c180 /c180 IN OUT OUTmaxTRIP IND peak X SW INDS on max V V VV 1I 8 R L f V /c40 /c41 /c40 /c41 /c40 /c41 /c230 /c246 /c230 /c246 /c45/c231 /c247/c180 /c45 /c180 /c180 /c231 /c247 /c231 /c247/c231 /c247 /c180 /c180/c232 /c248/c232 /c248/c61 IN OUT OUT OCL DS(on) X SW IN TRIP TRIP V V V8 I R2 L f V R I /c61 /c230 /c246 /c45/c45 /c180 /c231 /c247 /c180 /c180/c232 /c248 EXT IN OUT OUT OCL X SW IN 25 mVR V V VI 2 L f V /c180 /c61X X EXT ESLC R R TPS51219 www.ti.com SLUSAG1B –MARCH 2011–REVISED OCTOBER 2011 ExternalComponents Selection The externalcomponents selectionissimpleinD-CAP ™ mode. 1.DETERMINE THE VALUE OF R1 AND R2 The outputvoltageisdeterminedby thevalueofthevoltage-dividerresistor,R1 and R2 as shown inFigure25. R1 isconnectedbetween VREF and REFIN pins,and R2 isconnectedbetween the REFIN pinand GSNS. SettingR1 as 10-kΩ isa good startingpoint.DetermineR2 usingEquation10. (10) 2.CHOOSE THE INDUCTOR The inductancevalueshouldbe determinedtoyielda ripplecurrentofapproximately¼ to½ ofmaximum output current.Largerripplecurrentincreasesoutputripplevoltageand improvesthe signal-to-noiseratioand helps stableoperation. (11) The inductorneeds a low directcurrentresistance(DCR) toachievegood efficiency,as wellas enough room above peak inductorcurrentbeforesaturation.The peak inductorcurrentcan be estimatedinEquation12. (12) 3.CHOOSE THE OCL SETTING RESISTANCE R TRIP forR DS(on) Sensing CombiningEquation7 and Equation8,R TRIP can be obtainedusingEquation13. (13) R EXT forResistorSetting CombiningEquation7 and Equation9,R EXT can be obtainedusingEquation14. (14) For more accuratecurrentsensingwithan externalresistor,thefollowingtechniqueisrecommended. Addingan RC filtertocanceltheparasiticinductance(ESL)ofresistor,thisfiltervalueiscalculatedusingEquation15. (15) The time-constantofC X and R X shouldmatch theone ofESL and R EXT .Even when C X isnotused,an R X of 100 Ω isrecommended fornoisesuppression. Copyright© 2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 21

+ 25 mV (typ) Lx IOUT TPS51219 DL TRIP UDG-11044 REXT Cx ESL RX + 25 mV (typ) Lx IOUT RXC /c40 /c41/c180 /c61X X XC EXT ESLC R R R /c230 /c246 /c230 /c246 /c43 /c45/c61 /c43 /c43 /c180/c231 /c247 /c231 /c247 /c180 /c180/c232 /c248 /c232 /c248 X XC IN OUT OUT OCL EXT XC X SW IN R R V V V25 mVI R R 2 L f V /c40 /c41 /c40 /c41/c230 /c246 /c43/c61 /c180 /c231 /c247 /c231 /c247/c230 /c246 /c45 /c232 /c248/c45 /c180 /c231 /c247 /c231 /c247 /c180 /c180/c232 /c248 X XC EXT XCIN OUT OUT OCL X SW IN R R25 mVR RV V VI 2 L f V /c61 /c163/c112 /c180 /c180 SW OUT f1f 2 ESR C 3 /c163/c112 /c180 f0Mg /c180 /c179/c180 OUT SW V ESR 20 mVf Lx TPS51219 SLUSAG1B –MARCH 2011–REVISED OCTOBER 2011 www.ti.com Figure28.ResistorSensing withCompensation Figure29.Adjustment ofOvercurrentLimitationin ResistorSensing A voltagedividercan be configuredtoadjustforovercurrentlimitation,as describedinFigure29.For R X,R XC and C X can be calculatedas shown inEquation16,and theovercurrentlimitationvaluecan be calculatedas shown inEquation17. (16) (17) Therefore,R EXT can be obtainedusingEquation18. (18) 4.CHOOSE THE OUTPUT CAPACITORS D-CAP ™ Mode Organicsemiconductorcapacitor(s)or specialtypolymer capacitor(s)are recommended. Determinethe ESR valuetomeet smallsignalstabilityand recommended ripplevoltage.A quickreferenceisshown inEquation19 and Equation20. (19) where

• gM is130 µS (typ)
• C1 isthecapacitanceconnectedbetween theVSNS and COMP pins (20) (21)

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/c40 /c41 /c180 /c163/c112 /c180 /c180 /c180 C C SW X OUT R C f

2 G L C 3

/c163/c112 /c180 f0Mg www.ti.com SLUSAG1B –MARCH 2011–REVISED OCTOBER 2011 D-CAP2 ™ Mode Determineoutputcapacitancetomeet smallsignalstabilityas shown inEquation22 and Equation23. where

• G = 0.25 (22) where
• theR C × C C timeconstantis32 µs foroperationat500 kHz.(23µs foroperationat670 kHz) (23) Copyright© 2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 23

2.2 /c109F PwrPad TRIP VSNS GSNS 0.1 /c109F 10 nF TPS51219 SLUSAG1B –MARCH 2011–REVISED OCTOBER 2011 www.ti.com Layout Considerations Certainissuesmust be consideredbeforedesigninga layoutusingtheTPS51219. Figure30. DC/DC ConverterGround System

• VIN capacitor(s),VOUT capacitor(s)and MOSFETs are thepower components and shouldbe placedon one sideofthePCB (solderside).Othersmallsignalcomponents shouldbe placedon anotherside(component side).At leastone innerplaneshouldbe inserted,connectedto ground,inorderto shieldand isolatethe smallsignaltracesfromnoisypower lines.
• Allsensitiveanalogtracesand components such as VSNS, COMP, MODE, REFIN, VREF and TRIP should be placedaway from high-voltageswitchingnodes such as SW, DH, DL or BST to avoidcoupling.Use internallayer(s)as groundplane(s)and shieldfeedbacktracefrompower tracesand components.
• The DC/DC converterhas severalhigh-currentloops.The areaoftheseloopsshouldbe minimizedinorderto suppressgeneratingswitchingnoise. – Loop #1.The most importantlooptominimizetheareaofisthepathfromtheVIN capacitor(s)throughthe highand low-sideMOSFETs, and back tothecapacitor(s)throughground.Connect thenegativenode of theVIN capacitor(s)and thesourceofthelow-sideMOSFET atgroundas closeas possible.(Refertoloop #1 ofFigure30) – Loop #2. The second importantloopisthe path from the low-sideMOSFET throughinductorand VOUT capacitor(s),and back tosourceofthelow-sideMOSFET throughground.Connect sourceofthelow-side MOSFET and negativenode of VOUT capacitor(s)at ground as closeas possible.(Referto loop#2 of Figure30) – Loop #3. The thirdimportantloopisof gate drivingsystem forthe low-sideMOSFET. To turnon the low-sideMOSFET, highcurrentflowsfrom V5 capacitorthroughgatedriverand thelow-sideMOSFET, and back tonegativenode ofthecapacitorthroughground.To turnoffthelow-sideMOSFET, highcurrent flowsfrom gateofthelow-sideMOSFET throughthegatedriverand PGND, and back tosourceofthe low-sideMOSFET throughground.Connect negativenode of V5 capacitor,source of the low-side MOSFET and PGND atgroundas closeas possible.(Refertoloop#3 ofFigure30)
• ConnectthePGND and GND pinsdirectlyatthedevice.

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C TPS51219 SW DH DL PGND GND BST GND VSNS GSNS C R VIAs to inner ground layer C COMP C TPS51219 SW DH DL PGND GND BST GND VSNS GSNS C R VIAs to inner ground layer COMP C C R To output bulk capacitance TPS51219 www.ti.com SLUSAG1B –MARCH 2011–REVISED OCTOBER 2011

• Connect VSNS directlytotheoutputvoltagesense pointattheloaddevice.Connect GSNS togroundreturn pointsattheloaddevice.Inserta 10-Ω,1-nF,R-C filterbetween thesense pointand theVSNS pinwhere the COMP capacitanceisconnectedas shown in Case 1 (Figure31).When the COMP pin capacitanceis connectedtooutputbulkcapacitance,connecttheR-C filterinseriestoboththeVSNS pinand theCOMP capacitanceas shown inCase 2 (Figure32). Figure31. Case 1:COMP Pin CapacitanceConnected toVSNS Figure32. Case 2:COMP Pin CapacitanceConnected toOutput Bulk Capacitance
• Connect the overcurrentsettingresistorsfrom TRIP pinto ground and make the connectionsas closeas possibletothedevice.The tracefromTRIP pintoresistorand fromresistortogroundshouldavoidcoupling toa high-voltageswitchingnode.
• Connect thefrequencyand mode settingresistorfrom MODE pintoground,and make theconnectionsas closeas possibletothedevice.The tracefromtheMODE pintotheresistorand fromtheresistortoground shouldavoidcouplingtoa high-voltageswitchingnode. Copyright© 2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 25

0.1uF 100k 2.2uF 0.1uF 1 - 3 1 - 3 FDMS8680 FDMS8670AS 1 - 3 FDMS8670AS 0.45uH 5x330uF 12x22uF C5 C6 4x10uF /25V 0.1uF /50V 0.01uF VSNS GSNS REFIN DL DH2

1 VREF SW

8 BST

1.05V/20A 4.5V to 5.5V Vout_GND 3.3V 1nF TPS51219 SLUSAG1B –MARCH 2011–REVISED OCTOBER 2011 www.ti.com

• Connectionsfromgatedriverstotherespectivegateofthehigh-sideorthelow-sideMOSFET shouldbe as shortas possibletoreducestrayinductance.Use 0.65mm (25mils)orwidertraceand via(s)ofatleast0.5 mm (20mils)diameteralongthistrace.
• The PCB tracedefinedas SW node,whichconnectstothesourceoftheswitchingMOSFET, thedrainofthe rectifyingMOSFET and thehigh-voltagesideoftheinductor,shouldbe as shortand wideas possible.
• In orderto effectivelyremove heat from the package,preparethe thermallandand solderto the package thermalpad. Wide traceof the component-sidecopper,connectedto thisthermalland,helpsto dissipate heat. Numerous viaswitha 0.3-mm diameterconnectedfrom the thermallandto the internal/solder-side ground plane(s)shouldbe used tohelpdissipation. TPS51219 1.05-V/20-A,D-CAP2 ™ 500-kHz,R DS(on) Sensing ApplicationCircuit Figure33. 1.05-V/20-A,D-CAP2 ™ 500-kHz,R DS(on) Sensing Table3.1.05-V/20-A,D-CAP2 ™ 500-kHz,R DS(on) Sensing,ListofMaterials REFERENCE QTY SPECIFICATION MANUFACTURE PART NUMBERDESIGNATOR C6 4 10 µF,25 V TaiyoYuden TMK325BJ106MM C7 5 330 µF,2 V,6 m Ω Panasonic EEFSX0D331XE C8 12 22 µF,6.3V Murata GRM21BB30J226ME38 L1 1 0.45µH, 17 A,1.1m Ω Panasonic ETQP4LR45XFC Q1 1 30 V,35 A,8.5m Ω Fairchild FDMS8680 Q2, Q3 2 30 V,42 A,3.5m Ω Fairchild FDMS8670AS

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0.1uF 100k 2.2uF 0.1uF 1 - 3 1 - 3 FDMS8680 FDMS8670AS 1 - 3 FDMS8670AS 0.45uH 5x330uF 12x22uF C5 C6 4x10uF /25V 0.1uF /50V 200k 0.01uF VSNS GSNS REFIN DL DH2 1.05V/20A 4.5V to 5.5V Vout_GND 3.3V 1nF R7 C10 1nF TPS51219 www.ti.com SLUSAG1B –MARCH 2011–REVISED OCTOBER 2011 1.05-V/20-A,D-CAP ™ 400-kHz,R DS(on) Sensing ApplicationCircuit Figure34. 1.05-V/20-A,D-CAP ™ 400-kHz,R DS(on) Sensing Table4.1.05-V/20-A,D-CAP ™ 400-kHz,R DS(on) Sensing,ListofMaterials REFERENCE QTY SPECIFICATION MANUFACTURE PART NUMBERDESIGNATOR C6 4 10 µF,25 V TaiyoYuden TMK325BJ106MM C7 5 330 µF,2.5V,18 m Ω Sanyo 2R5TPE330MI C8 12 22 µF,6.3V Murata GRM21BB30J226ME38 L1 1 0.45µH, 17 A,1.1m Ω Panasonic ETQP4LR45XFC Q1 1 30 V,35 A,8.5m Ω Fairchild FDMS8680 Q2,Q3 2 30 V,42 A,3.5m Ω Fairchild FDMS8670AS Copyright© 2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 27

0.1uF 100k 2.2uF 0.1uF 1 - 3 1 - 3 FDMS8680 FDMS8670AS 0.45uH C8C7 2x330uF 12x22uF C5 C6 4x10uF /25V 0.1uF /50V 33k 0.01uF VSNS GSNS REFIN DL DH2 1.00V/10.4A 4.5V to 5.5V Vout_GNDR5 3 m 1nF C10 0.01uF 100 TPS51219 SLUSAG1B –MARCH 2011–REVISED OCTOBER 2011 www.ti.com TPS51219 1.00-V/10.4-A,D-CAP2 ™ 500-kHz,ResistorSensing ApplicationCircuit Figure35. 1.00-V/10.4-A,D-CAP2 ™ 500-kHz,ResistorSensing Table5.1.00-V/10.4-A,D-CAP2 ™ 500-kHz,ResistorSensing,ListofMaterials REFERENCE QTY SPECIFICATION MANUFACTURE PART NUMBERDESIGNATOR C6 4 10 µF,25 V TaiyoYuden TMK325BJ106MM C7 2 330 µF,2 V,6 m Ω Panasonic EEFSX0D331XE C8 12 22 µF,6.3V Murata GRM21BB30J226ME38 L1 1 0.45µH, 17 A,1.1m Ω Panasonic ETQP4LR45XFC Q1 1 30 V,35 A,8.5m Ω Fairchild FDMS8680 Q2 1 30 V,42 A,3.5m Ω Fairchild FDMS8670AS R5 1 3 m Ω,1 W KOA TLR2HDTD3L00F

28 SubmitDocumentationFeedback Copyright© 2011,Texas InstrumentsIncorporated

0.1uF 100k 2.2uF 0. 1uF 1 - 3 1 - 3 FDMS8680 FDMS8670AS 0.45uH C8C7 2x330uF 12x22uF C5 C6 4x10uF /25V 0.1uF /50V 47k VSNS GSNS REFIN DL DH2 1.00V/10.4A 4.5V to 5.5V Vout_GND 0.01uF C9 0.01uF 100 C10 1nF R8 C11 1nF TPS51219 www.ti.com SLUSAG1B –MARCH 2011–REVISED OCTOBER 2011 TPS51219 1.00-V/10.4-A,D-CAP ™ 400-kHz,ResistorSensing ApplicationCircuit Figure36. 1.00-V/10.4-A,D-CAP ™ 400-kHz,ResistorSensing Table6.1.00-V/10.4-A,D-CAP ™ 400-kHz,ResistorSensing,ListofMaterials REFERENCE QTY SPECIFICATION MANUFACTURE PART NUMBERDESIGNATOR C6 4 10 µF,25 V TaiyoYuden TMK325BJ106MM C7 2 330 µF,2 V,9 m Ω Panasonic EEFSX0D331ER C8 12 22 µF,6.3V Murata GRM21BB30J226ME38 L1 1 0.45µH, 17 A,1.1m Ω Panasonic ETQP4LR45XFC Q1 1 30 V,35 A,8.5m Ω Fairchild FDMS8680 Q2 1 30 V,42 A,3.5m Ω Fairchild FDMS8670AS R5 1 3 m Ω,1 W KOA TLR2HDTD3L00F Copyright© 2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 29

www.ti.com 7-Oct-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) FX003 Active Production WQFN (RTE) | 16 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 51219 TPS51219RTER Active Production WQFN (RTE) | 16 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 51219 TPS51219RTER.B Active Production WQFN (RTE) | 16 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 51219 TPS51219RTERG4 Active Production WQFN (RTE) | 16 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 51219 TPS51219RTERG4.B Active Production WQFN (RTE) | 16 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 51219 TPS51219RTET Active Production WQFN (RTE) | 16 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 51219 TPS51219RTET.B Active Production WQFN (RTE) | 16 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 51219 (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

www.ti.com 7-Oct-2025 Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 23-Jul-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 23-Jul-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS51219RTER WQFN RTE 16 3000 353.0 353.0 32.0 TPS51219RTERG4 WQFN RTE 16 3000 353.0 353.0 32.0 TPS51219RTET WQFN RTE 16 250 338.0 355.0 50.0 Pack Materials-Page 2

www.ti.com GENERIC PACKAGE VIEW This image is a representation of the package family, actual package may vary. Refer to the product data sheet for package details. WQFN - 0.8 mm max heightRTE 16 PLASTIC QUAD FLATPACK - NO LEAD3 x 3, 0.5 mm pitch 4225944/A

www.ti.com PACKAGE OUTLINE C 16X 0.30 0.18 1.68 0.07 16X 0.5 0.3

0.8 MAX

(DIM A) TYP 0.05 0.00 12X 0.5 1.5 A 3.1 2.9 B 3.1 2.9 WQFN - 0.8 mm max heightRTE0016C PLASTIC QUAD FLATPACK - NO LEAD 4219117/B 04/2022 SIDE WALL METAL THICKNESS DIM A OPTION 1 OPTION 2 0.1 0.2 PIN 1 INDEX AREA 0.08 SEATING PLANE 4 9 5 8 16 13 (OPTIONAL) PIN 1 ID 0.1 C A B 0.05 EXPOSED THERMAL PAD

17 SYMM

NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. SCALE 3.600

www.ti.com EXAMPLE BOARD LAYOUT

0.07 MIN

0.07 MAX

16X (0.24) 16X (0.6) ( 0.2) TYP VIA 12X (0.5) (2.8) (2.8) (0.58) TYP ( 1.68) (R0.05) ALL PAD CORNERS (0.58) TYP WQFN - 0.8 mm max heightRTE0016C PLASTIC QUAD FLATPACK - NO LEAD 4219117/B 04/2022 SYMM 5 8 1316 SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:20X NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL METAL SOLDER MASK OPENINGSOLDER MASK DETAILS NON SOLDER MASK DEFINED (PREFERRED) EXPOSED METAL

www.ti.com EXAMPLE STENCIL DESIGN 16X (0.6) 16X (0.24) 12X (0.5) (2.8) (2.8) ( 1.55) (R0.05) TYP WQFN - 0.8 mm max heightRTE0016C PLASTIC QUAD FLATPACK - NO LEAD 4219117/B 04/2022 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SYMM ALL AROUND METAL SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 17: 85% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SCALE:25X SYMM 5 8 1316

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