FM3104 ETC1

Document overview

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Technical content

Features

High Integration Device Replaces Multiple Parts

  • Serial Nonvolatile Memory
  • Real-time Clock (RTC)
  • Low Voltage Reset
  • Watchdog Timer
  • Early Power-Fail Warning/NMI
  • Two 16-bit Event Counters
  • Serial Number with Write-lock for Security Ferroelectric Nonvolatile RAM
  • 4Kb, 16Kb, 64Kb, and 256Kb versions
  • Unlimited Read/Write Endurance
  • 10 year Data Retention
  • NoDelay™ Writes Real-time Clock/Calendar
  • Backup Current under 1 µA
  • Seconds through Centuries in BCD format
  • Tracks Leap Years through 2099
  • Uses Standard 32.768 kHz Crystal (6pF)
  • Software Calibration
  • Supports Battery or Capacitor Backup Processor Companion
  • Active-low Reset Output for VDD and Watchdog
  • Programmable VDD Reset Trip Point
  • Manual Reset Filtered and De-bounced
  • Programmable Watchdog Timer
  • Dual Battery-backed Event Counter Tracks System Intrusions or other Events
  • Comparator for Early Power-Fail Interrupt
  • 64-bit Programmable Serial Number with Lock Fast Two-wire Serial Interface
  • Up to 1 MHz Maximum Bus Frequency
  • Supports Legacy Timing for 100 kHz & 400 kHz
  • Device Select Pins for up to 4 Memory Devices
  • RTC, Supervisor Controlled via 2-wire Interface Easy to Use Configurations
  • Operates from 2.7 to 5.5V
  • Small Footprint 14-pin SOIC
  • Low Operating Current
  • -40°C to +85°C Operation

Description

The FM31xxx is a family of integrated devices that includes the most commonly needed functions for processor-based systems. Major features include nonvolatile memory available in various sizes, real- time clock, low-VDD reset, watchdog timer, nonvolatile event counter, lockable 64-bit serial number area, and general purpose comparator that can be used for an early power-fail (NMI) interrupt or other purpose. The family operates from 2.7 to 5.5V. Each FM31xxx provides nonvolatile RAM available in sizes including 4Kb, 16Kb, 64Kb, and 256Kb versions. Fast write speed and unlimited endurance allow the memory to serve as extra RAM or conventional nonvolatile storage. This memory is truly nonvolatile rather than battery backed. The real-time clock (RTC) provides time and date information in BCD format. It can be permanently powered from external backup voltage source, either a battery or a capacitor. The timekeeper uses a common external 32.768 kHz crystal and provides a calibration mode that allows software adjustment of timekeeping accuracy. The processor companion includes commonly needed CPU support functions. Supervisory functions include a reset output signal controlled by either a low VDD condition or a watchdog timeout. /RST goes active when VDD drops below a programmable threshold and remains active for 100 ms after VDD rises above the trip point. A programmable watchdog timer runs from 100 ms to 3 seconds. The watchdog timer is optional, but if enabled it will assert the reset signal for 100 ms if not restarted by the host before the timeout. A flag-bit indicates the source of the reset. A general-purpose comparator compares an external input pin to the onboard 1.2V reference. This is useful for generating a power-fail interrupt (NMI) but can be used for any purpose. The family also includes a programmable 64-bit serial number that can be locked making it unalterable. Additionally it offers a dual battery-backed event counter that tracks the number of rising or falling edges detected on dedicated input pins.

Rev 0.2 May 2003 Page 2 of 22 Pin Configuration Pin Name Function CNT1, CNT2 Event Counter Inputs A0, A1 Device Select inputs CAL/PFO Clock Calibration and Early Power-fail Output /RST Reset Input/Output PFI Early Power-fail Input X1, X2 Crystal Connections SDA Serial Data SCL Serial Clock VBAK Battery-Backup Supply VDD Supply Voltage VSS Ground

Ordering Information

Base Configuration Memory Size Operating Voltage Reset Threshold Ordering Part Number Other memory configurations may be available. Please contact the factory for more information. VDD VBAK SCL SDA VSS CAL/PFO CNT1 PFI RST CNT2

Figure 1. Block Diagram contained in the device address. The device select pins are pulled down internally. detected on the corresponding CNT pin. The polarity is programmable. calibration. In normal operation, this is the early power-fail output. /RST I/O Active low reset output with weak pull-up. Also input for manual reset. open-drain and is intended to be wire-OR’d with other devices on the two-wire bus. driver includes slope control for falling edges. A pull-up resistor is required. Schmitt trigger input for noise immunity. an early power failure. This pin should not be left floating. supply is used, this pin should be left floating and the VBC bit should be set.

nonvolatile memory with a standard device ID value. maintaining the most recently used memory address. x 8. The memory is based on FRAM technology. is described further on page 13. containing these bits are described in detail below. or other purposes, and a 64-bit serial number. will be completed internally. Figure 2. Low Voltage Reset

application is not limited to the NMI function.

512 Hz square wave and the comparator will be

on system operations using the comparator. is limited to 3.75V under normal operating conditions. increment. CNT2 is not used in this mode. is CC, bit 2; and the Read Counter bit is RC bit 3. Figure 6. Event Counter still be read by the system. The serial number is located in registers 11h to 18h. registers, and the SNL bit cannot be cleared. calibration feature that allows high accuracy. diagram (Figure 7) illustrates the RTC function. Setting the W bit to 1 locks the user registers. core occur continuously except when locked. power fails, the voltage on the VDD pin will drop. in order to maximize battery or capacitor life.

regardless of the backup power source. guaranteed to be less than IBAK(max). resistor as a safety element. Figure 7. Real-Time Clock Core Block Diagram

  1. When the CAL bit is 0, the CAL/PFO pin will

revert to the power fail output function.

512 Hz W

Rev 0.2 May 2003 Page 8 of 22 7 511.9856 511.9833 28.22 32.55 100111 8 511.9833 511.9811 32.56 36.89 101000 9 511.9811 511.9789 36.90 41.23 101001 10 511.9789 511.9767 41.24 45.57 101010 11 511.9767 511.9744 45.58 49.91 101011 12 511.9744 511.9722 49.92 54.25 101100 13 511.9722 511.9700 54.26 58.59 101101 14 511.9700 511.9678 58.60 62.93 101110 15 511.9678 511.9656 62.94 67.27 101111 16 511.9656 511.9633 67.28 71.61 110000 17 511.9633 511.9611 71.62 75.95 110001 18 511.9611 511.9589 75.96 80.29 110010 19 511.9589 511.9567 80.30 84.63 110011 20 511.9567 511.9544 84.64 88.97 110100 21 511.9544 511.9522 88.98 93.31 110101 22 511.9522 511.9500 93.32 97.65 110110 23 511.9500 511.9478 97.66 101.99 110111 24 511.9478 511.9456 102.00 106.33 111000 25 511.9456 511.9433 106.34 110.67 111001 26 511.9433 511.9411 110.68 115.01 111010 27 511.9411 511.9389 115.02 119.35 111011 28 511.9389 511.9367 119.36 123.69 111100 29 511.9367 511.9344 123.70 128.03 111101 30 511.9344 511.9322 128.04 132.37 111110 31 511.9322 511.9300 132.38 136.71 111111 Negative Calibration for fast clocks: Calibration will achieve +/- 2.17 PPM after calibration Measured Frequency Range Error Range (PPM) Min Max Min Max Program Calibration Register to: 0 512.0000 512.0011 0 2.17 000000 1 512.0011 512.0033 2.18 6.51 000001 2 512.0033 512.0056 6.52 10.85 000010 3 512.0056 512.0078 10.86 15.19 000011 4 512.0078 512.0100 15.20 19.53 000100 5 512.0100 512.0122 19.54 23.87 000101 6 512.0122 512.0144 23.88 28.21 000110 7 512.0144 512.0167 28.22 32.55 000111 8 512.0167 512.0189 32.56 36.89 001000 9 512.0189 512.0211 36.90 41.23 001001 10 512.0211 512.0233 41.24 45.57 001010 11 512.0233 512.0256 45.58 49.91 001011 12 512.0256 512.0278 49.92 54.25 001100 13 512.0278 512.0300 54.26 58.59 001101 14 512.0300 512.0322 58.60 62.93 001110 15 512.0322 512.0344 62.94 67.27 001111 16 512.0344 512.0367 67.28 71.61 010000 17 512.0367 512.0389 71.62 75.95 010001 18 512.0389 512.0411 75.96 80.29 010010 19 512.0411 512.0433 80.30 84.63 010011 20 512.0433 512.0456 84.64 88.97 010100 21 512.0456 512.0478 88.98 93.31 010101 22 512.0478 512.0500 93.32 97.65 010110 23 512.0500 512.0522 97.66 101.99 010111 24 512.0522 512.0544 102.00 106.33 011000 25 512.0544 512.0567 106.34 110.67 011001 26 512.0567 512.0589 110.68 115.01 011010 27 512.0589 512.0611 115.02 119.35 011011 28 512.0611 512.0633 119.36 123.69 011100 29 512.0633 512.0656 123.70 128.03 011101 30 512.0656 512.0678 128.04 132.37 011110 31 512.0678 512.0700 132.38 136.71 011111

Rev 0.2 May 2003 Page 9 of 22 Register Map The RTC and processor companion functions are accessed via 25 special function registers mapped to a separate 2- wire device ID. The interface protocol is described below. The registers contain timekeeping data, control bits, or information flags. A description of each register follows the summary table below. Register Map Summary Table Nonvolatile = Battery-backed = Data Address D7 D6 D5 D4 D3 D2 D1 D0 Function Range Serial Number Byte 7 Serial Number 7 FFh Serial Number Byte 6 Serial Number 6 FFh Serial Number Byte 5 Serial Number 5 FFh Serial Number Byte 4 Serial Number 4 FFh Serial Number Byte 3 Serial Number 3 FFh Serial Number Byte 2 Serial Number 2 FFh Serial Number Byte 1 Serial Number 1 FFh Serial Number Byte 0 Serial Number 0 FFh 10h Counter 2 MSB Event Counter 2 MSB FFh 0Fh Counter 2 LSB Event Counter 2 LSB FFh 0Eh Counter 1 MSB Event Counter 1 MSB FFh 0Dh Counter 1 LSB Event Counter 1 LSB FFh 0Ch RC CC C2P C1P Event Count Control 0Bh SNL - - WP1 WP0 VBC VTP1 VTP0 Companion Control 0Ah WDE - - WDT4 WDT3 WDT2 WDT1 WDT0 Watchdo g Control 09h WTR POR LB - WR3 WR2 WR1 WR0 Watchdo g Restart/Flags 08h 10 years years Years 00-99 07h 000 1 0 m o months Month 1-12 06h 00 10 date date Date 1-31 05h 00000 day Day 1-7 04h 00 10 hours hours Hours 0-23 03h 0 10 minutes minutes Minutes 0-59 02h 0 10 seconds seconds Seconds 0-59 01h /OSCEN reserved CALS CAL4 CAL3 CAL2 CAL1 CAL0 CAL/Control 00h reserved CF reserved reserved reserved CAL W R RTC Control 18h 17h 11h 16h 15h 14h 13h 12h

Rev 0.2 May 2003 Page 10 of 22 Register Description Address Description 18h Serial Number Byte 7 D7 D6 D5 D4 D3 D2 D1 D0 Upper byte of the serial number. Read/write when SNL=0, read-only when SNL=1. Nonvolatile. 17h Serial Number Byte 6 D7 D6 D5 D4 D3 D2 D1 D0 Byte 6 of the serial number. Read/write when SNL=0, read-only when SNL=1. Nonvolatile. 16h Serial Number Byte 5 D7 D6 D5 D4 D3 D2 D1 D0 Byte 5 of the serial number. Read/write when SNL=0, read-only when SNL=1. Nonvolatile. 15h Serial Number Byte 4 D7 D6 D5 D4 D3 D2 D1 D0 Byte 4 of the serial number. Read/write when SNL=0, read-only when SNL=1. Nonvolatile. 14h Serial Number Byte 3 D7 D6 D5 D4 D3 D2 D1 D0 Byte 3 of the serial number. Read/write when SNL=0, read-only when SNL=1. Nonvolatile. 13h Serial Number Byte 2 D7 D6 D5 D4 D3 D2 D1 D0 Byte 2 of the serial number. Read/write when SNL=0, read-only when SNL=1. Nonvolatile. 12h Serial Number Byte 1 D7 D6 D5 D4 D3 D2 D1 D0 Byte 1 of the serial number. Read/write when SNL=0, read-only when SNL=1. Nonvolatile. 11h Serial Number Byte 0 D7 D6 D5 D4 D3 D2 D1 D0 LSB of the serial number. Read/write when SNL=0, read-only when SNL=1. Nonvolatile. 10h Counter 2 MSB D7 D6 D5 D4 D3 D2 D1 D0 Event Counter 2 MSB. Increments on overflows from Counter 2 LSB. Battery-backed, read/write. 0Fh Counter 2 LSB D7 D6 D5 D4 D3 D2 D1 D0 Event Counter 2 LSB. Increments on programmed edge event on CNT2 input or overflows from Counter 1 MSB when CC=1. Battery-backed, read/write . 0Eh Counter 1 MSB D7 D6 D5 D4 D3 D2 D1 D0 Event Counter 1 MSB. Increments on overflows from Counter 1 LSB. Battery-backed, read/write. 0Dh Counter 1 LSB D7 D6 D5 D4 D3 D2 D1 D0 Event Counter 1 LSB. Increments on programmed edge event on CNT1 input. Battery-backed, read/write.

Rev 0.2 May 2003 Page 11 of 22 0Ch Event Counter Control D7 D6 D5 D4 D3 D2 D1 D0 - - - - RC CC C2P C1P RC Read Counter. Setting this bit to 1 takes a snapshot of the four counters bytes allowing the system to read the values without missing count events. The RC bit will be automatically cleared. CC Counter Cascade. When CC=0, the event counters operate independently according to the edge programmed by C1P and C2P respectively. When CC=1, the counters are cascaded to create one 32-bit counter. The registers of Counter 2 represent the most significant 16-bits of the counter and CNT1 is the controlling input. Bit C2P has no effect when CC=1. Battery-backed, read/write. C2P CNT2 detects falling edges when C2P = 0, rising edges when C2P = 1. C2P has no effect when CC=1. Battery- backed, read/write. C1P CNT1 detects falling edges when C1P = 0, rising edges when C1P = 1. Battery-backed, read/write. 0Bh Companion Control D7 D6 D5 D4 D3 D2 D1 D0 SNL - - WP1 WP0 VBC VTP1 VTP0 SNL Serial Number Lock. Setting to a 1 makes registers 11h to 18h and SNL permanently read-only. SNL cannot be cleared once set to 1. Nonvolatile, read/write. WP1-0 Write Protect. These bits control the write protection of the memory array. Nonvolatile, read/write. Write protect addresses WP1 WP0 None 0 0 Bottom 1/4 0 1 Bottom 1/2 1 0 Full array 1 1 VBC VBAK Charger Control. Setting VBC to 1 causes a 4 µA trickle charge current to be supplied on VBAK. Clearing VBC to 0 disables the charge current. Nonvolatile, read/write. VTP1-0 VTP select. These bits control the reset trip point for the low VDD reset function. Nonvolatile, read/write. VTP VTP1 VTP0 2.6V 0 0 2.9V 0 1 3.9V 1 0 4.4V 1 1 0Ah Watchdog Control D7 D6 D5 D4 D3 D2 D1 D0 WDE - - WDT4 WDT3 WDT2 WDT1 WDT0 WDE Watchdog Enable. When WDE=1 the watchdog timer can cause the /RST signal to go active. When WDE = 0 the timer runs but has no effect on /RST. Note as the timer is free-running, users should restart the timer using WR3-0 prior to setting WDE=1. This assures a full watchdog timeout interval occurs. Nonvolatile, read/write. WDT4-0 Watchdog Timeout. Indicates the minimum watchdog timeout interval with 100 ms resolution. New watchdog timeouts are loaded when the timer is restarted by writing the 1010b pattern to WR3-0. Nonvolatile, read/write. Watchdog timeout WDT4 WDT3 WDT2 WDT1 WDT0 Invalid – default 100 ms 0 0 0 0 0 100 ms 0 0 0 0 1 200 ms 0 0 0 1 0 300 ms 0 0 0 1 1 . . 2000 ms 1 0 1 0 0 2100 ms 1 0 1 0 1 2200 ms 1 0 1 1 0 . . 2900 ms 1 1 1 0 1 3000 ms 1 1 1 1 0 Disable counter 1 1 1 1 1

Rev 0.2 May 2003 Page 12 of 22 09h Watchdog Restart & Flags D7 D6 D5 D4 D3 D2 D1 D0 WTR POR LB - WR3 WR2 WR1 WR0 WTR Watchdog Timer Reset Flag: When the /RST signal is activated by the watchdog the WTR bit will be set to 1. It must be cleared by the user. Note that both WTR and POR could be set if both reset sources have occurred since the flags were cleared by the user. Battery-backed. Read/Write (internally set, user can only clear this bit). POR Power-on Reset Flag: When the /RST signal is activated by VDD < VTP, the POR bit will be set to 1. It must be cleared by the user. Note that both WTR and POR could be set if both reset sources have occurred since the flags were cleared by the user. Battery-backed. Read/Write (internally set, user can only clear this bit). LB Low Backup Flag: On power up, if the VBAK source is below the minimum voltage to operate the RTC and event counters, this bit will be set to 1. The user should clear it to 0 when initializing the system. Battery-backed. Read/Write (internally set, user can only clear this bit). WR3-0 Watchdog Restart: Writing a pattern 1010b to WR3-0 restarts the watchdog timer. The upper nibble contents do not affect this operation. Writing any pattern other than 1010b to WR3-0 has no effect on the timer. This allows users to set or clear the WTR and POR flags without affecting the watchdog timer. Write-only. 08h Timekeeping – Years D7 D6 D5 D4 D3 D2 D1 D0 Contains the lower two BCD digits of the year. Lower nibble contains the value for years; upper nibble contains the value for 10s of years. Each nibble operates from 0 to 9. The range for the register is 0-99. Battery-backed, read/write. 07h Timekeeping – Months D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 10 Month Month.3 Month.2 Month.1 Month.0 Contains the BCD digits for the month. Lower nibble contains the lower digit and operates from 0 to 9; upper nibble (one bit) contains the upper digit and operates from 0 to 1. The range for the register is 1-12. Battery- backed, read/write. 06h Timekeeping – Date of the month D7 D6 D5 D4 D3 D2 D1 D0 Contains the BCD digits for the date of the month. Lower nibble contains the lower digit and operates from 0 to 9; upper nibble contains the upper digit and operates from 0 to 3. The range for the register is 1-31. Battery-backed, read/write. 05h Timekeeping – Day of the week D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 Day.2 Day.1 Day.0 Lower nibble contains a value that correlates to day of the week. Day of the week is a ring counter that counts from 1 to 7 then returns to 1. The user must assign meaning to the day value, as the day is not integrated with the date. Battery-backed, read/write. 04h Timekeeping – Hours D7 D6 D5 D4 D3 D2 D1 D0 Contains the BCD value of hours in 24-hour format. Lower nibble contains the lower digit and operates from 0 to 9; upper nibble (two bits) contains the upper digit and operates from 0 to 2. The range for the register is 0-23. Battery-backed, read/write. 03h Timekeeping – Minutes D7 D6 D5 D4 D3 D2 D1 D0 Contains the BCD value of minutes. Lower nibble contains the lower digit and operates from 0 to 9; upper nibble contains the upper minutes digit and operates from 0 to 5. The range for the register is 0-59. Battery-backed, read/write. 02h Timekeeping – Seconds D7 D6 D5 D4 D3 D2 D1 D0 Contains the BCD value of seconds. Lower nibble contains the lower digit and operates from 0 to 9; upper nibble contains the upper digit and operates from 0 to 5. The range for the register is 0-59. Battery-backed, read/write.

Reserved Reserved bits. Do not use. Should remain set to 0. the time-base. Calibration is explained on page 7. Nonvolatile, read/write. CAL.4-0 These five bits control the calibration of the clock. Nonvolatile, read/write. century information as needed. This bit is cleared to 0 when the Flag register is read. It is read-only for the user. normally, and the CAL/PFO pin is controlled by the power fail comparator. Read/write. timekeeping counters. Read/write. going from 0 to 1 causes the timekeeping capture, so the bit must be returned to 0 prior to reading again. Reserved Reserved bits. Do not use. Should remain set to 0. Slave Address (Slave ID = 1101b). in the Electrical Specifications section. Figure 8. Data Transfer Protocol

Rev 0.2 May 2003 Page 16 of 22 Memory Read Operation There are two types of memory read operations. They are current address read and selective address read. In a current address read, the FM31xxx uses the internal address latch to supply the address. In a selective read, the user performs a procedure to first set the address to a specific value. Current Address & Sequential Read As mentioned above the FM31xxx uses an internal latch to supply the address for a read operation. A current address read uses the existing value in the address latch as a starting place for the read operation. The system reads from the address immediately following that of the last operation. To perform a current address read, the bus master supplies a slave address with the LSB set to 1. This indicates that a read operation is requested. After receiving the complete device address, the FM31xxx will begin shifting data out from the current address on the next clock. The current address is the value held in the internal address latch. Beginning with the current address, the bus master can read any number of bytes. Thus, a sequential read is simply a current address read with multiple byte transfers. After each byte the internal address counter will be incremented. Each time the bus master acknowledges a byte, this indicates that the FM31xxx should read out the next sequential byte. There are four ways to terminate a read operation. Failing to properly terminate the read will most likely create a bus contention as the FM31xxx attempts to read out additional data onto the bus. The four valid methods follow. 1. The bus master issues a NACK in the 9 th clock cycle and a Stop in the 10 th clock cycle. This is illustrated in the diagrams below and is preferred. 2. The bus master issues a NACK in the 9 th clock cycle and a Start in the 10th. 3. The bus master issues a Stop in the 9 th clock cycle. 4. The bus master issues a Start in the 9 th clock cycle. If the internal address reaches the top of memory, it will wrap around to 0000h on the next read cycle. The figures below show the proper operation for current address reads. Selective (Random) Read There is a simple technique that allows a user to select a random address location as the starting point for a read operation. This involves using the first three bytes of a write operation to set the internal address followed by subsequent read operations. To perform a selective read, the bus master sends out the slave address with the LSB set to 0. This specifies a write operation. According to the write protocol, the bus master then sends the address bytes that are loaded into the internal address latch. After the FM31xxx acknowledges the address, the bus master issues a Start condition. This simultaneously aborts the write operation and allows the read command to be issued with the slave address LSB set to a 1. The operation is now a read from the current address. Read operations are illustrated below. RTC/Companion Write Operation All RTC and Companion writes operate in a similar manner to memory writes. The distinction is that a different device ID is used and only one byte address is needed instead of two. Figure 16 illustrates a single byte write to this device. RTC/Companion Read Operation As with writes, a read operation begins with the Slave Address. To perform a register read, the bus master supplies a Slave Address with the LSB set to 1. This indicates that a read operation is requested. After receiving the complete Slave Address, the FM31xxx will begin shifting data out from the current register address on the next clock. Auto- increment operates for the special function registers as with the memory address. A current address read for the registers look exactly like the memory except that the device ID is different. The FM31xxx contains two separate address registers, one for the memory address and the other for the register address. This allows the contents of one address register to be modified without affecting the current address of the other register. For example, this would allow an interrupted read to the memory while still providing fast access to an RTC register. A subsequent memory read will then continue from the memory address where it previously left off, without requiring the load of a new memory address. However, a write sequence always requires an address to be supplied.

Rev 0.2 May 2003 Page 18 of 22 Electrical Specifications Absolute Maximum Ratings Symbol Description Ratings VDD Power Supply Voltage with respect to V SS -1.0V to +7.0V VIN Voltage on any signal pin with respect to V SS -1.0V to +7.0V and VIN ≤ VDD+1.0V except SCL, SDA VBAK Backup Supply Voltage -1.0V to +4.5V TSTG Storage Temperature -55°C to + 125°C TLEAD Lead Temperature (Soldering, 10 seconds) 300° C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only, and the functional operation of the device at these or any other conditions above those listed in the operational section of this specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability. DC Operating Conditions (TA = -40° C to + 85° C, VDD = 2.7V to 5.5V unless otherwise specified) Symbol Parameter Min Typ Max Units Notes VDD Main Power Supply 2.7 5.5 V 8 IDD V DD Supply Current @ SCL = 100 kHz @ SCL = 400 kHz @ SCL = 1 MHz 500 900 1500 µA µA µA ISB Standby Current 150 µA 2 VBAK RTC Backup Supply Voltage 2.0 3.0 3.75 V 10 IBAK RTC Backup Supply Current 1 µA 5 IBAKTC Trickle Charge Current 4.0 8.0 µA 11 VTPT Tolerance on V DD trip point voltage -50 - +50 mV 6 VRST VDD for valid /RST @ IOL = 80 µA at VOL VBAK > VBAK min VBAK < VBAK min 1.6 V V ILI Input Leakage Current 1 µA 3 ILO Output Leakage Current 1 µA 3 VIL Input Low Voltage All inputs except as listed CNT1-2 battery backed (V DD < 2.5V) CNT1-2 (VDD > 2.5V) -0.3 -0.3 -0.3 0.3 V DD 0.5 0.8 V V V VIH Input High Voltage All inputs except as listed PFI (power fail input) CNT1-2 battery backed (V DD < 2.5V) CNT1-2 VDD > 2.5V

0.7 VDD

VBAK – 0.5 TBD VDD + 0.5 VBAK VBAK + 0.5 VDD + 0.5 V V V V VOL Output Low Voltage (I OL = 3 mA) 0.4 V VOH Output High Voltage (I OH = -2 mA) 2.4 V RRST Pull-up resistance for /RST inactive 50 400 KΩ RIN Input Resistance A1-A0 for VIN = VIL max A1-A0 for VIN = VIH min PFI input KΩ MΩ MΩ VHYS Power Fail Input (PFI) Hysteresis 100 400 mV 4 Notes 1. SCL toggling between VDD-0.3V and VSS, other inputs VSS or VDD-0.3V 2. All inputs at VSS or VDD, static. Stop command issued. 3. VIN or VOUT = VSS to VDD. Does not apply to A0, A1, PFI, or /RST pins. 4. This parameter is characterized but not tested. 5. VBAK = 3.0V, VDD < 2.4V, oscillator running, CNT1-2 at VBAK. 6. /RST is asserted active when VDD < VTP.

Rev 0.2 May 2003 Page 19 of 22 7. The minimum VDD to guarantee the level of /RST remains a valid VOL level. 8. Full complete operation. Supervisory circuits, RTC, etc operate to lower voltages as specified. 9. Includes /RST input detection of external reset condition to trigger driving of /RST signal by FM31xxx. 10. The VBAK trickle charger automatically regulates the maximum voltage on this pin for capacitor backup applications. 11. VBAK will source current when trickle charge is enabled (VBC bit=1), VDD > VBAK, and VBAK < VBAK max. AC Parameters (TA = -40° C to + 85° C, VDD = 2.7V to 5.5V, CL = 100 pF unless otherwise specified) Symbol Parameter Min Max Min Max Min Max Units Notes fSCL SCL Clock Frequency 0 100 0 400 0 1000 kHz tLOW Clock Low Period 4.7 1.3 0.6 µs tHIGH Clock High Period 4.0 0.6 0.4 µs tAA SCL Low to SDA Data Out Valid 3 0.9 0.55 µs tBUF Bus Free Before New Transmission 4.7 1.3 0.5 µs tHD:STA Start Condition Hold Time 4.0 0.6 0.25 µs tSU:STA Start Condition Setup for Repeated Start 4.7 0.6 0.25 µs tHD:DAT Data In Hold Time 0 0 0 ns tSU:DAT Data In Setup Time 250 100 100 ns tR Input Rise Time 1000 300 300 ns 1 tF Input Fall Time 300 300 100 ns 1 tSU:STO Stop Condition Setup Time 4.0 0.6 0.25 µs tDH Data Output Hold (from SCL @ VIL) 0 0 0 ns tSP Noise Suppression Time Constant on SCL, SDA 50 50 50 ns All SCL specifications as well as start and stop conditions apply to both read and write operations. Supervisor Timing (TA = -40° C to + 85° C, VDD = 2.7V to 5.5V) Symbol Parameter Min Max Units Notes tRPU Reset active after V DD>VTP 100 200 ms tRNR V DD < VTP noise immunity 10 25 µs 1 tVF Fall time of VDD from V TP to 0V 100 µs 1,2 tVR Rise time of VDD from 0V to VTP 100 µs 1,2 tWDP Pulse Width of /RST for Watchdog Reset 100 200 ms tWDOG Timeout of Watchdog t DOG 2*t DOG ms 3 fCNT Frequency of Event Counters 0 10 MHz Data Retention (TA = -40° C to + 85° C, VDD = 2.7V to 5.5V) Parameter Min Units Notes Data Retention 10 Years Capacitance (TA = 25° C, f=1.0 MHz, VDD = 3.0V) Symbol Parameter Max Units Notes CIO Input/output capacitance 8 pF 1 CXTAL X1, X2 Crystal pin capacitance 12 pF 1, 4 Notes 1 This parameter is characterized but not tested. 2 Slew rate for proper transition between the battery-backed and normal operation. 3 tDOG is the programmed time in register 0Ah, VDD > VTP and tRPU satisfied. 4 The crystal attached to the X1/X2 pins must be rated as 6pF.

Rev 0.2 May 2003 Page 20 of 22 AC Test Conditions Equivalent AC Load Circuit Input Pulse Levels 0.1 V DD to 0.9 VDD Input rise and fall times 10 ns Input and output timing levels 0.5 V DD Diagram Notes All start and stop timing parameters apply to both read and write cycles. Clock specifications are identical for read and write cycles. Write timing parameters apply to slave address, word address, and write data bits. Functional relationships are illustrated in the relevant data sheet sections. These diagrams illustrate the timing parameters only. Read Bus Timing tSU:SDA Start tR tF Stop Start tBUF tHIGH 1/fSCL tLOW tSP tSP Acknowledge tHD:DAT tSU:DAT tAA tDH SCL SDA Write Bus Timing tSU:STO Start Stop Start Acknowledge tAA tHD:DAT tHD:STA tSU:DAT SCL SDA /RST Timing VD D VTP VR ST RST tRPU tVF tRNR tVR 5.5V Output 1700 Ω 100 pF

Rev 0.2 May 2003 Page 21 of 22 14-pin SOIC (JEDEC Standard MS-012 variation AA) E H D Index Area AA1 e α h L C B .10 mm .004 in. Controlling dimensions in millimeters. Conversions to inches are not exact. Symbol Dim Min Nom. Max A mm in. 1.35 0.053 1.75 0.069 A1 mm in. 0.10 0.004 0.25 0.010 B mm in. 0.33 0.013 0.51 0.020 D mm in. 8.53 0.336 8.74 0.344 E mm in. 5.80 0.147 6.20 0.153 e mm in.

1.27 BSC

0.050 BSC

in. 5.80 0.228 6.20 0.244 L mm in. 0.51 0.02 0.76 0.030 α 0° 8°

Rev 0.2 May 2003 Page 22 of 22

Revision History

0.1 2/28/03 Internal release. 0.2 5/22/03 Initial release.