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Document overview
- Manufacturer or author: Provided By www.digicamel.com(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 22
Technical content
Datasheet sections
- 1.1 Pin Diagram
- 1.2 Pin Descriptions
- 7.1 Default Start-up
- 7.2 Logic Control
- 7.3 External Vss
- 7.4 Power Supplies
- 7.5 Control Pin Interface
- 11.1 External Supply Setup
- 11.2 Logic Control Setup
- 11.3 Using External Control Logic
- 11.4 Turn on Procedure
- 11.5 Turn off Procedure
Features
- Four symmetric, absorptive RF ports
- High Isolation: 50dB at 4000MHz
- Low Insertion Loss: 1.1 dB at 4000MHz
- High Linearity: o IIP2 of 114 dBm at 2000MHz o IIP3 of 60 dBm at 4000MHz
- High Operating Power Handling: o 33 dBm CW on selected RF port o 27 dBm on terminated ports
- Single 2.7V to 5.5V supply voltage
- External Negative Supply Option
- 3.3V and 1.8V compatible control logic
- Operating temperature -40°C to +105°C
- 4 × 4 mm 24-pin QFN package
- Pin compatible with competitors Competitive Advantage The F2914 provides constant impedance in all RF ports during transitions improving a system’s hot- switching ruggedness. The device also supports high power handling, and high isolation; particularly important for DPD receiver use.
- Constant impedance K|Z| during switching transition
- RFX to RFC Isolation = 50dB at 4GHz
- Insertion Loss = 1.1 dB at 4GHz
- IIP3: +60 dBm at 4GHz
- Extended temperature: -40°C to +105°C
Applications
- Base Station 2G, 3G, 4G
- Portable Wireless
- Repeaters and E911 systems
- Digital Pre-Distortion
- Point to Point Infrastructure
- Public Safety Infrastructure
- Military Systems, JTRS radios
- Cable Infrastructure
- Test / ATE Equipment
X0007072 Rev.1.0 Dec.1.20 Page 3 1. Pin Information
1.1 Pin Diagram
CircuitE.P. RF4 RF3 RF2 GND RF1 GND GND GND GND RFC 50Ω 50Ω 50Ω 50Ω GND
1.2 Pin Descriptions
15, 21, 23, 24 GND Ground these pins as close to the device as possible.
2 GND
This pin is internally connected to the exposed paddle. This pin can be left open or grounded. Note: The EVKIT layout has a floating RF trace connected to this pin to make the board compatible with the F2915. 5 RF4 RF4 Port. Matched to 50 ohms. If this pin is not 0V DC, then an external coupling capacitor must be used. 8 RF3 RF3 Port. Matched to 50 ohms. If this pin is not 0V DC, then an external coupling capacitor must be used. 11 RF2 RF2 Port. Matched to 50 ohms. If this pin is not 0V DC, then an external coupling capacitor must be used. 14 RF1 RF1 Port. Matched to 50 ohms. If this pin is not 0V DC, then an external coupling capacitor must be used. 16 VDD Power Supply. Bypass to GND with capacitors shown in the Typical Application Circuit as close as possible to pin. 17 V1 Control pin to set switch state. See Table 1 or Table 2. 18 V2 Control pin to set switch state. See Table 1 or Table 2. 19 V3 Control pin to set switch state. See Table 1 or Table 2. 20 VSSEXT External VSS negative voltage control. Connect to ground to enable on chip negative voltage generator. To bypass and disable on chip generator connect this pin to an external VSS. 22 RFC RF Common Port. Matched to 50 ohms when one of the 4 RF ports is selected. If this pin is not 0V DC, then an external coupling capacitor must be used. 25 — EP Exposed Pad. Internally connected to GND. Solder this exposed pad to a PCB pad that uses multiple ground vias to provide heat transfer out of the device into the PCB ground planes. These multiple ground vias are also required to achieve the specified RF performance.
Table 1. Absolute Maximum Ratings Input Power for any one selected RF through port. Input Power for RFC when in the all off state. not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
- Package Thermal and Moisture Characteristics
Table 2. Package Thermal and Moisture Characteristics
- Recommended Operating Conditions
Table 3. Recommended Operating Conditions
- For normal operation, connect VSSEXT = 0 V (pin 20) to GND to enable the internal negative voltage generator. By applying VSSEXT to
pin 20, the negative voltage generator is disabled thereby completely eliminating any generator spurious responses.
- Levels based on TC ≤ 85 °C. See Figure 1 power derating curve for higher case temperatures.
- In any of the insertion loss modes or switching into any insertion loss mode, the 3 remaining terminated port paths can be each
exposed to the maximum stated power level during continuous or hot switching operation. Figure 1. Maximum RF Input Power vs. RF Frequency
- Electrical Specifications
input ports, PCB board trace and connector losses are de-embedded unless otherwise noted. Table 4. Electrical Specifications
2700 MHz – 4000 MHz 46 50
4000 MHz – 5000 MHz 46 50
2100 MHz – 2700 MHz 47 52
4000 MHz – 5000 MHz 40 45
5000 MHz – 8000 MHz 29 36
RFC port. 50 MHz – 5000 MHz.
X0007072 Rev.1.0 Dec.1.20 Page 7 Parameter Symbol Conditions Min Typ Max Units Minimum Return Loss (RFX Port ) RFXRL 400 MHz –4000 MHz Active 13 dB Terminated 17 Input 0.1dB Compression3 ICP0.1dB 35 dBm Input IP2 IIP2 FRF1 = 2000 MHz, FRF2 = 2010 MHz RF Input = RFX, PIN = +20 dBm / tone FRF1 + FRF2 Term 114 dBm Input IP3 IIP3 Δ F = 1 MHz RF Input = RFX PIN = +20 dBm / tone FRF = 2000 MHz 59.5 dBm FRF = 4000 MHz 60 Switching Time4 TSW Bypass Mode 50% CTRL to 90% RF 256 345 ns 50% CTRL to 10% RF 256 345 50% CTRL to RF settled within +/- 0.1 dB of I.L. value. 285 Maximum Switching Rate5 SWRATE Pin 20 = GND 25 kHz Pin 20 = VSSEXT applied 290 Maximum spurious level on any RF port6 SpurMAX RF ports terminated into 50Ω RFX connected to RFC -120 dBm 1. Items in min/max columns in bold italics are guaranteed by Test. 2. Items in min/max columns that are not bold/italics are guaranteed by Design Characterization. 3. The input 0.1dB compression point is a linearity figure of merit. Refer to Absolute Maximum Ratings section for the maximum RF input power and Figure 1 for maximum operating RF input power. 4. FRF = 1GHz. 5. Minimum time required between switching of states =1/ (Maximum Switching Rate). 6. Spurious due to on-chip negative voltage generator. Typical generator fundamental frequency is 2.2 MHz.
Table 5. 3-Pin Switch Control Truth Table
- * Redundant state with state “100”
- Note 1 - Pin 19 (V3) must be grounded for 2-pin control.
- Note 2 – 2-pin control can be used if All Off mode is not required.
X0007072 Rev.1.0 Dec.1.20 Page 9 6. Typical Operating Conditions (TOC) Unless otherwise noted for the TOC graphs on the following pages, the following conditions apply.
- VDD = 3.3 V.
- TCASE = +25 ºC (TCASE = Temperature of exposed paddle).
- FRF = 2000 MHz.
- RFX is the driven RF port and RFC is the output port.
- Pin = 10 dBm for all small signal tests.
- Pin = +15 dBm/tone applied to selected RFX port for two tone linearity tests.
- Two tone frequency spacing = 5 MHz.
- ZS = ZL = 50 ohms.
- All unused RF ports terminated into 50 ohms.
- For Insertion Loss and Isolation plots, RF trace and connector losses are de-embedded (see EVKIT Board and Connector loss plot).
- Plots for Isolation and Insertion Loss over temperature and voltage are for a typical path. For performance of a specific path, refer to the online S-Parameter file.
X0007072 Rev.1.0 Dec.1.20 Page 10 Insertion Loss vs. Selected Switch Path Insertion Loss vs. Temperature Insertion Loss vs. Voltage RFX RFC Isolation vs. Temperature RFX RFC Isolation vs. Voltage RFX RFX Isolation vs. Temperature -2.5 -1.5 -0.5 0 1 2 3 4 5 6 7 8 Insertion Loss (dB) Frequency (GHz) RF1 RF2 RF3 RF4 -2.5 -1.5 -0.5 0 1 2 3 4 5 6 7 8 Insertion Loss (dB) Frequency (GHz) -40C 25C 105C -2.5 -1.5 -0.5 0 1 2 3 4 5 6 7 8 Insertion Loss (dB) Frequency (GHz) 2.7V 3.3V 5.0V 5.5V -90 -80 -70 -60 -50 -40 -30 -20 -10 0 1 2 3 4 5 6 7 8 Isolation (dB) Frequency (GHz) -40C 25C 105C -90 -80 -70 -60 -50 -40 -30 -20 -10 0 1 2 3 4 5 6 7 8 Isolation (dB) Frequency (GHz) 2.7V 3.3V 5.0V 5.5V -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 1 2 3 4 5 6 7 8 Isolation (dB) Frequency (GHz) -40C 25C 105C
X0007072 Rev.1.0 Dec.1.20 Page 11 RFX RFX Isolation vs. Voltage RFX Return Loss vs. Selected RFX Port RFX Selected Return Loss vs. Temperature RFX Selected Return Loss vs. Voltage RFC Return Loss vs. Selected RFX Port RFC Return Loss with RFX Selected vs. Temperature -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 1 2 3 4 5 6 7 8 Isolation (dB) Frequency (GHz) 2.7V 3.3V 5.0V 5.5V -40 -30 -20 -10 0 1 2 3 4 5 6 7 8 Return Loss (dB) Frequency (GHz) RF1 RF2 RF3 RF4 -40 -30 -20 -10 0 1 2 3 4 5 6 7 8 Return Loss (dB) Frequency (GHz) -40C 25C 105C -40 -30 -20 -10 0 1 2 3 4 5 6 7 8 Return Loss (dB) Frequency (GHz) 2.7V 3.3V 5.0V 5.5V -40 -30 -20 -10 0 1 2 3 4 5 6 7 8 Return Loss (dB) Frequency (GHz) RF1 RF2 RF3 RF4 -40 -30 -20 -10 0 1 2 3 4 5 6 7 8 Return Loss (dB) Frequency (GHz) -40C 25C 105C
X0007072 Rev.1.0 Dec.1.20 Page 12 RFC Return Loss with RFX Selected vs. Voltage RFX Terminated Return Loss vs. RFX Port RFX Terminated Return Loss vs. Temperature RFX Terminated Return Loss vs. Voltage Return Loss (During Switching) vs. Time VSWR (During Switching) vs. Time -40 -30 -20 -10 0 1 2 3 4 5 6 7 8 Return Loss (dB) Frequency (GHz) 2.7V 3.3V 5.0V 5.5V -50 -40 -30 -20 -10 0 1 2 3 4 5 6 7 8 Return Loss (dB) Frequency (GHz) RF1 RF2 RF3 RF4 -50 -40 -30 -20 -10 0 1 2 3 4 5 6 7 8 Return Loss (dB) Frequency (GHz) -40C 25C 105C -50 -40 -30 -20 -10 0 1 2 3 4 5 6 7 8 Return Loss (dB) Frequency (GHz) 2.7V 3.3V 5.0V 5.5V -40 -35 -30 -25 -20 -15 -10 Return Loss Time (µsec) RFX Term ---> RFX Active RFX Active ---> RFX Term 1.2 1.4 1.6 1.8 2.2 2.4 2.6 2.8 VSWR Time (µsec) RFX Term ---> RFX Active RFX Active ---> RFX Term
X0007072 Rev.1.0 Dec.1.20 Page 13 RFX Switching Time [RFX Terminated to RFX Active] RFX Switching Time [RFX Active to RFX Terminated] RFX IIP3 vs. Selected RFX Port RFX IIP3 vs. Temperature and Voltage EVKIT Trace and Connector Loss vs. Temperature -0.5 -0.4 -0.3 -0.2 -0.1 0.1 0.2 0.3 0.4 0.5 Settling to IL State (dB) Time (µsec) 50% CTRL to Insertion Loss -70 -60 -50 -40 -30 -20 -10 Settling to Isolation (dB) Time (µsec) 50% CTRL to Isolation 0.5 1 1.5 2 2.5 3 3.5 4 IIP3 (dBm) Frequency (GHz) RF1 RF2 RF3 RF4 0.5 1 1.5 2 2.5 3 3.5 4 IIP3 (dBm) Frequency (GHz) 25C, 3.0V 25C, 3.3V 25C, 5.0V 25C, 5.5V 105C, 2.7V 105C, 3V 105C, 3.3V 105C, 5V 105C, 5.5V -1.2 -0.8 -0.6 -0.4 -0.2 0 1 2 3 4 5 6 7 8 Loss (dB) Frequency (GHz) -40C 25C 105C
X0007072 Rev.1.0 Dec.1.20 Page 14 7. Applications Information
7.1 Default Start-up
Control pins include no internal pull-down resistors to logic LOW or pull-up resistors to logic HIGH.
7.2 Logic Control
Three control pins V1, V2, and V3 are used to set the state of the SP4T switch (see Table 1 or Table 2).
7.3 External Vss
The F2914 is designed with an on-chip negative voltage generator. This on-chip generator is enabled by connecting pin 20 of the device to ground. To disable the on-chip generator apply a negative voltage to pin 20 (VSSEXT) of the device within the range stated in the Recommended Operating Conditions Table.
7.4 Power Supplies
A common VDD power supply should be used for all pins requiring DC power. All supply pins should be bypassed with external capacitors to minimize noise and fast transients. Supply noise can degrade noise figure and fast transients can trigger ESD clamps and cause them to fail. Supply voltage change or transients should have a slew rate smaller than 1V/20uS. In addition, all control pins should remain at 0 V (+/-0.3 V) while the supply voltage ramps or while it returns to zero.
7.5 Control Pin Interface
If control signal integrity is a concern and clean signals cannot be guaranteed due to overshoot, undershoot, ringing, etc., the following circuit at the input of each control pin is recommended. This applies to control pins 17, 18, and 19 as shown below.
X0007072 Rev.1.0 Dec.1.20 Page 15 8. EvKit Picture Top View Bottom View
X0007072 Rev.1.0 Dec.1.20 Page 16 9. EVkit / Applications Circuit
X0007072 Rev.1.0 Dec.1.20 Page 17 10. EVKit BOM Part Reference QTY DESCRIPTION Mfr. Part # Mfr. C1, C3, C5, C7, C8, C9 6 100 pF ±5%, 50V, C0G Ceramic Capacitor (0402) GRM1555C1H101J Murata C2 0 Not Installed (0603) C4 0 Not Installed (0603) C6 1 1000 pF ±5%, 50V, C0G Ceramic Capacitor (0603) GRM1885C1H102J Murata R1, R2, R3 3 0 Ω ±1%, 1/10W, Resistor (0402) ERJ-2GE0R00X Panasonic R4, R5, R6 3 100 kΩ ±1%, 1/10W, Resistor (0402) ERJ-2RKF1003X Panasonic R7 1 15 kΩ ±1%, 1/10W, Resistor (0402) ERJ-2RKF1502X Panasonic R8 1 22 kΩ ±1%, 1/10W, Resistor (0402) ERJ-2RKF2202X Panasonic J1, J3-J8 7 Edge Launch SMA (0.375 inch pitch ground tabs) 142-0701-851 Emerson Johnson J9 1 CONN HEADER VERT DBL 10 X 2 POS GOLD 67997-120HLF FCI U1 1 SP4T Switch 4 mm x 4 mm QFN24-EP F2914NBGK IDT 1 Printed Circuit Board F29XX EVKIT Rev 02.0 IDT
X0007072 Rev.1.0 Dec.1.20 Page 18 11. EVkit Operation
11.1 External Supply Setup
Set up a VDD power supply in the voltage range of 2.7 V to 5.5 V and disable the power supply output. If using the on-chip negative voltage generator install a 2-pin shunt to short out pins 3 and 4 of J9. If an external negative voltage supply is to be used set the supply voltage within the range of -3.6 V to -3.2 V and disable the negative voltage power supply output. Also, be sure there are no jumper connections on pins 3 and 4 of J9.
11.2 Logic Control Setup
Using the EVKIT to manually set the control logic: On connector J9 connect a 2-pin shunt from pin 7 (VDD) to pin 8 (VDD_CTRL). This connection provides the VDD voltage supply to the Eval Board logic control pull up network. On connector J9 connect a 2-pin shunt from pin 9 (LVSEL2) to pin 10 (LVSEL). This connection enables R7 (15 kΩ) and R8 (22 kΩ) to form a voltage divider to set the proper logic control levels to support the full voltage range of VDD. Note that when using the on-board R7 / R8 voltage divider the current draw from the VDD supply will be higher by approximately VDD / 37 kΩ. Connector J9 has 3 logic input pins: V1 (pin 20), V2 (pin 18), and V3 (pin 16). See Table 1 or Table 2 for Logic Truth Table. With the pullup network enabled (as noted above), these pins open will provide a logic high through pull up resistors R4, R5, and R6. To set a logic low to V1, V2, and V3 connect 2-pin shunts from pin 16 to pin 15, pin 18 to pin 17 and pin 20 to pin 19 respectively.
11.3 Using External Control Logic
Pins 6, 7, 8, 9, and 10 of J9 should have no connection. External logic controls would be applied to J9 pins 16 (V3), 18 (V2) and 20 (V1). See Table 1 or Table 2 for Logic Truth Table.
11.4 Turn on Procedure
- Setup the supplies and Eval Board as noted in the External Supply Setup and Logic Control Setup sections above. 2. Connect the preset disabled VDD power supply to pin 2 (VDD) and pin 1 (GND) of J9. 3. If the external negative voltage source is to be used, connect the disabled supply to pin 4 (VSSEXT) and pin 3 (GND) of J9. If using on-chip negative supply be sure the 2-pin shunt is installed connecting pin 3 to pin 4. 4. Enable the VDD supply then enable the VSSEXT supply (if used). 5. Set the desired logic setting using V1, V2, and V3 to achieve the desired Table 1 or Table 2 setting. Note that external control logic should not be applied without VDD being applied first.
11.5 Turn off Procedure
- If using external control logic for V1, V2, V3 then set to a logic low. 2. Disable any external VSSEXT supply. 3. Disable the VDD supply.
X0007072 Rev.1.0 Dec.1.20 Page 19 12. Package Outline Drawings The package outline drawings are appended at the end of this document. The package information is the most current data available. 13. Marking Diagram IDTF2914 NBGK Z1528ACL Part Number Date Code [YYWW] (Week 28 of 2015) ASM Test Step Assembler Code 14. Ordering Information Part Number Description Temperature Range (°C) Carrier Type F2914NBGK8 4.0 x 4.0 x 0.80 mm 0.50mm Pitch 24- VFQFPN -40 to +85 15. Revision History Revision Date Description 1.0 Dec.1.20 • Updated RFX to RFC and RFX to RFX isolation specifications.
- Added Total Coupling RFC to RFX specification. N/A Jun.19.20 Completed minor changes throughout. N/A Mar.1.16 Initial release.
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