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Technical content
Features
Insertion Loss 0.55dB at 2GHz High Isolation 51dB at 2GHz High Linearity IIP3 of 65dBm Wide Single Positive Supply Voltage Range 3.3V and 1.8V compatible control logic Operating temperature -55°C to +105°C 2 x 2 mm 8-DFN package Block Diagram Figure 1. Block Diagram
Figure 2. Pin Assignments for 2 mm x 2 mm x 0.9 mm 8-VFQFP-N – Top View Table 1. Pin Descriptions 1, 4 NC This pin may be connected to the paddle and can be grounded. coupling capacitor must be used. 7 V1 Logic control pin. See Table 6 for proper logic setting. 8 RF2 RF2 Port. Matched to 50 Ω. If this pin is not 0V DC, then an external coupling capacitor must be used. ground vias are also required to achieve the specified RF performance.
conditions for extended periods may affect device reliability. Table 2. Absolute Maximum Ratings
Table 3. Recommended Operating Conditions a. Items in min/max columns in bold italics are Guaranteed by Test. b. Items in min/max columns that are not bold/italics are Guaranteed by Design Characterization. Figure 3. Maximum RF Input Operating Power vs. RF Frequency
© 2020 Renesas Electronics Corporation 5 August 31, 2020
Electrical Characteristics
Table 4. Electrical Characteristics 5 GHz based on application circuit (Figure 20) using best RF PCB design practices. See note c for details.
0.03 GHz 85
0.35 GHz 66 73
1.0 GHz 55 61
2.0 GHz 45 51
3.0 GHz 40 46
4.0 GHz 35 41
5.0 GHz 30 37
6.0 GHz 33 [c]
7.0 GHz 29 [c]
8.0 GHz 26 [c]
2.0 GHz 27
3.0 GHz 25
4.0 GHz 20
5.0 GHz 18
6.0 GHz 20 [c]
7.0 GHz 25 [c]
8.0 GHz 13 [c]
a. Items in min/max columns in bold italics are Guaranteed by Test. b. Items in min/max columns that are not bold/italics are Guaranteed by Design Characterization. the evaluation board per the application circuit (Figure 20) is required. See the appropriate Typical Operating Conditions graphs.
© 2020 Renesas Electronics Corporation 6 August 31, 2020 Electrical Characteristics (Cont.) Typical Application Circuit: VDD = 3.3 V, TCASE = +25 °C, FRF = 2 GHz, Driven Port = RF2, Input power = 0 dBm, Z S = ZL = 50 Ω. PCB board trace and connector losses are de-embedded unless otherwise noted. IIP2 / IIP3: PIN = 13 dBm / tone, 50 MHz spacing. Performance beyond 5 GHz based on application circuit (Figure 20) using best RF PCB design practices. See note c for details. Parameter Symbol Condition Minimum Typical Maximum Units RF2 Return Loss (Isolation State) RFRLT
3.0 GHz 27
4.0 GHz 25
5.0 GHz 20
6.0 GHz 15 [c]
7.0 GHz 12 [c]
8.0 GHz 10 [c]
Input 1dB Compression [d] ICP1dB
0.03 GHz 34
dBm 3.0 GHz 35
4.0 GHz 35
Input 0.1dB Compression [d] ICP0.1dB
0.03 GHz 33
dBm 3.0 GHz 34
4.0 GHz 34
Input IP2 [e] IIP2 F1 = 0.35 GHz, F2 = 0.40 GHz 123 dBm F1 = 0.95 GHz, F2 = 1.00 GHz 124 F1 = 2.40 GHz, F2 = 2.45 GHz 118 Input IP3 [e] IIP3
0.03 GHz 65
dBm 0.35 GHz 65
1.00 GHz 68
2.40 GHz 67
Non-RF Driven Spurious [f] SpurMAX Any port when externally terminated into 50 Ω -102 dBm Switching Time [g] TSW 50% control to 90% RF 265 500 ns 50% control to 10% RF 225 500 50% control to RF settled to within +/- 0.1 dB of insertion loss value 280 Maximum Switching Rate SWRATE 25 kHz Maximum Video Feed-through on RF Ports VIDFT Peak transients during switching. Measured with 20 ns rise-time, 0 to 3.3 V control pulse Rise Time 25 mVpp Fall Time 45 a. Items in min/max columns in bold italics are Guaranteed by Test. b. Items in min/max columns that are not bold/italics are Guaranteed by Design Characterization. c. To achieve performance beyond 5 GHz, the use of bypass capacitors (BOM C2, C3, and C5) installed close to the device as embodied in the evaluation board per the application circuit (Figure 20) is required. See the appropriate Typical Operating Conditions graphs. d. The input 0.1 and 1 dB compression point is a linearity figure of merit. Refer to Absolute Maximum Ratings section for the maximum RF input power. e. RF1 or RF2 driven IIP2 / IIP3 results when in insertion loss state. IP2 Frequency = F1 + F2. f. Spurious due to on-chip negative voltage generator. Spurious fundamental is approximately 5.7 MHz. g. FRF = 1 GHz.
Table 5. Package Thermal Characteristics Junction to Case Thermal Resistance. ZL = ZS = 50 Ohms Single Ended. PIN = 13 dBm / tone applied to RF2 port for two tone linearity tests. Two tone frequency spacing = 50 MHz. All temperatures are referenced to the exposed paddle. Evaluation Kit traces and connector losses are de-embedded. Figure 10 to Figure 13 when application circuit with bypass capacitors is not utilized. Unless otherwise noted, C2, C3 and C5 are installed in following plots.
Table 6. Switch Control Truth Table
0 Isolation RF1 port reflective, RF2 port terminated into 50 ohms
1 Insertion Loss RF1 and RF2 port matched to 50 ohm
Figure 20. Electrical Schematic evaluation board with best practices followed for PCB design.
Table 7. Bill of Material (BOM)
1 Printed Circuit Board F2910 EVKIT REV 01 IDT
Control pins include no internal pull-down resistors to logic LOW or pull-up resistors to logic HIGH. minimize noise and fast transients. Supply noise can degrade noise figure and fast transients can trigger ESD clamps and cause them to fail. (± 0.3 V) while the supply voltage ramps or while it returns to zero. shown in Figure 21 is not necessary. Figure 21. Control Pin signal integrity improvement circuit
© 2020 Renesas Electronics Corporation 15 August 31, 2020 External Supply Setup Set up a VCC power supply in the voltage range of 2.7 V to 5.5 V with the power supply output disabled. Logic Control Setup Using the EVKIT to manually set the control logic: On connector J5, connect a 2-pin shunt from VCC (pin 3) to VLOGIC (pin 4). This connection provides the VCC voltage supply to the Eval Board logic control pull-up network. Resistors R1 and R2 form a voltage divider to set the VIH level over the 2.7 V to 5.5 V VCC range for manual logic control. Connector J5 has one logic input pin: V1 (pin 5). See Table 6 for Logic Truth Table. With the pull-up network enabled (as noted above) this pin can be left open to provide a logic high through pull-up resistor R1. To set a logic low for V1, connect a 2-pin shunt on J5 from VCTL (pin 5) to GND (pin 6). Note that when using the on board R1/R2 voltage divider, the current draw from the VCC supply will be higher by approximately VCC / 33 kΩ. Using external control logic: Pins 3, 4, 6, 7, and 8 of J5 should have no external connections. External logic control is applied to J5 V1 (pin 5). See Table 5 for the Logic Truth Table. Turn On Procedure Setup the supplies and EVKIT as noted in the External Supply Setup and Logic Control Setup sections above. Enable the VCC Supply Set the desired logic setting to achieve the desired Table 5 configuration. Note that external control logic should not be applied without V CC being present. Turn Off Procedure Set the logic control to a logic low. Disable the VCC supply.
© 2020 Renesas Electronics Corporation 16 August 31, 2020 Package Outline Drawings The package outline drawings are appended at the end of this document and are accessible from the link below. The package information is the most current data available. https://www.idt.com/document/psc/8-dfn-package-outline-drawing-20-x-20-x-09-mm-body-epad-08-x-16-mm-05mm-pitch- nbnbg8p3?language=en
Ordering Information
Orderable Part Number Package MSL Rating Shipping Packaging Orientation Temperature F2910NBGP 2 x 2 x 0.9 mm 8-VFQFP-N MSL1 Bulk -55° to +105°C F2910NBGP8 2 x 2 x 0.9 mm 8-VFQFP-N MSL1 Tape and Reel EIA-481-C[a] -55° to +105°C F2910EVBI Evaluation Board a. Contact IDT for additional information on tape and reel orientation Marking Diagram 2910 6UAG 1. Line 1 is the part number. 2. Line 2 – “6” is last digit of the year. 3. Line 2 – “U” is the workweek code 4. Line 2 – AG is the sequential code
Revision History
Revision Date Description of Change August 31, 2020 • Updated the package outline drawings; however, no mechanical changes October 25, 2020 • Added orientation information and F2910NBGP/W part number. August 29, 2016 Initial release.
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,QWHJUDWHG'HYLFH7HFKQRORJ\\,QF Package Revision HistoryRev No.Date CreatedDescriptionOct 9, 2017Rev 01New Format
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