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Technical content
Features
Frequency: 5MHz to 3000MHz Serial and 6-bit parallel interface 31.5dB control range 0.5dB step Glitch-FreeTM technology, low transient overshoot 3.0V to 5.25V supply 1.8V or 3.3V control logic Attenuator step error: 0.1dB at 1GHz Low insertion loss: 1.2dB at 1GHz Ultra-linear IIP3: +64dBm IIP2: +125dBm typical Stable integral non-linearity over temperature Low current consumption: 550µA typical Bi-directional Operating temperature: -40°C to +105°C 4mm 4mm, 20-pin QFN package Block Diagram Figure 1. Block Diagram
Figure 2. Pin Assignments for 4mm 4mm 0.75mm, 20-pin QFN Package – Top View (Through Package)
Table 1. Pin Descriptions 2 RF1 Device RF input or output (bi-directional). 3 DATA Serial interface data input. 4 CLK Serial interface clock input. 13 VMODE Pull this pin HIGH for Serial Control Mode. Ground this pin for Parallel Control Mode. 14 RF2 Device RF input or output (bi-directional). ground planes. These multiple ground vias are also required to achieve the specified RF performance. [a] There is a 100kΩ pull-up resistor to the internally regulated 2.5V power supply.
The absolute maximum ratings are stress ratings only . Stresses greater than those listed below can cause permanent damage to the device . Table 2. Absolute Maximum Ratings
Table 3. Recommended Operating Conditions Figure 3. Maximum Continuous Operating RF Input Power versus Input Frequency (+25C)
© 2017 Integrated Device Technology, Inc. 6 Rev 1 September 21, 2017
Electrical Characteristics
The specifications in Table 4 apply at VDD = +3.3V, TEP = +25°C, fRF = 1000MHz, PIN = 0dBm, Serial Mode, ZS = ZL = 75Ω, Evaluation Board (EVKit) trace and connector losses are de-embedded, unless otherwise noted. Table 4. Electrical Characteristics that are not shown in bold italics are guaranteed by design characterization. [b] Current is tested using the Serial Mode with parallel pins floating. If parallel pins are grounded, add 25µA per pin.
(EVKit) trace and connector losses are de-embedded, unless otherwise noted. Table 5. Electrical Characteristics power. This specification is measured in a 50Ω system. [d] Spurious due to on-chip negative voltage generator. Typical generator fundamental frequency is 2.2MHz. [e] Speeds are measured after SPI programming is completed (data latched with LE = HIGH).
Table 6. Package Thermal Characteristics Unless otherwise noted for the TOC graphs on the following pages, the following conditions apply.
Figure 4. Insertion Loss vs. Frequency Figure 5. Insertion Loss vs. Attenuation State Figure 6. RF1 Return Loss vs. Frequency Figure 7. RF1 Return Loss vs. Attenuation Figure 8. RF2 Return Loss vs. Frequency Figure 9. RF2 Return Loss vs. Attenuation
1 GHz, -40 C
1 GHz, +25 C
1 GHz, +105 C
by floating VMODE or pulling it to a logic HIGH, and Parallel Mode is selected by setting VMODE to a logic LOW. in the most significant bit (MSB) (D5 bit) first. Table 7. 6 Bit SPI DATA Word Sequence Table 8. Truth Table for Serial Control Word Bits
be dropped LOW. This allows shifting new data into the shift register without uploading it to the active register until the next time LE goes HIGH. The timing specification intervals are shown in blue font in Figure 18. Figure 18. Serial Register Timing Diagram latched into the active register, a single programming event. Table 9. Serial Mode Timing Table
When the device is first powered up, it will default to the maximum attenuation of 31.5dB independent of the parallel pin [D5:D0] conditions. Table 10. Default Control Word for the Serial Mode For the F1975, the user has the option of programming in one of two parallel modes: Direct Parallel Mode or Latched Parallel Mode. The Latched Parallel Mode is selected when VMODE is set to a logic LOW and LE (pin 5) is toggled from a logic LOW to a logic HIGH. Set the LE pin to a logic LOW. Toggle LE to a logic HIGH. The device will then transition to the attenuation settings reflected by pins D5 through D0.
The Latched Parallel Mode establishes a default attenuation state when the device is first powered up which is the maximum attenuation. Table 11. Truth Table for the Parallel Pins Figure 19. Latched Parallel Mode Timing Diagram Table 12. Latched Parallel Mode Timing
these pins will exhibit a voltage to ground as indicated. Table 13. Voltage and Resistance to Ground for the Logic Pins 13 VMODE 2.5V 100kΩ pull-up resistor to internally regulated 2.5V. 3, 4, 5 DATA, CLK, LE 2.5V 100kΩ pull-up resistor to internally regulated 2.5V. D2, D1, D0 2.5V 100kΩ pull-up resistor to internally regulated 2.5V.
Figure 20. F1975EVBI Evaluation Board – Top View
Figure 21. F1975EVBI Evaluation Board – Back View
Figure 22. Electrical Schematic
Table 14. Evaluation Kit Bill of Material
1 Printed Circuit Board F1975 EVKit Rev 02 IDT
shown in Figure 24. To use the Serial Mode, set U2 switch 7 to the “+” or “O” position. The attenuation setting can be programmed according to Table 8. Figure 24. Serial Logic Connections or “Serial Logic Control Setup” sections above. Enable the proper attenuation setting according to Figure 20 and Table 8 for Serial Mode or Table 11 for the Parallel Mode. Set the logic control pins to a logic LOW.
© 2017 Integrated Device Technology, Inc. 23 Rev 1 September 21, 2017 Package Drawings The package outline drawings are located at the end of this document. The package information is the most current data available and is subject to change without notice or revision of this document. Marking Diagram IDTF19 75NCGI ZA515BEG 1. Line 1 and 2 are the part number. 2. Line 3: “ZA” is for die version. 3. Line 3: “yww” = “515” = one digit year and two digit week that the part was assembled. 4. Line 3: “BEG” denotes assembly site.
Ordering Information
Orderable Part Number Description and Package MSL Rating Shipping Packaging Temperature F1975NCGI 4mm x 4mm x 0.75mm QFN 1 Tray -40°C to +105°C F1975NCGI8 4mm x 4mm x 0.75mm QFN 1 Reel -40°C to +105°C F1975EVBI Evaluation Board F1975EVSI Evaluation Solution including the Evaluation Board, Controller Board, and cable. The Evaluation Software is available for download on the product page on the IDT website: www.IDT.com/F1975
© 2017 Integrated Device Technology, Inc. 24 Rev 1 September 21, 2017
Revision History
Revision Revision Date Description of Change 1 September 21, 2017 Updated evaluation board images, top markings, and updated to the latest template. O July 31, 2017 Initial release of the datasheet.
I// I 0. 10 IC I 20X I C:i I 0.08 IC I NOTE: 2 Q 0.15 2 Q 0.15 TOP VIEW
0.20 REF
- ALL DIMENSION ARE IN MM. ANGLES IN DEGREES NCG20P1, PSC-4445-01, Rev 01, Page 1 0.65 0.45 2.16 2.16 1.96 1.96 0.35 -1 1 1-o.30 0.20 INDEX MARK 20X 0.10@ C A B 0.05@ C BOTTOM VIEW -j o.so r 10.70 2. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS COPLANARITY SHALL NOT EXCEED 0.06 MM l 3. WARPAGE SHALL NOT EXCEED 0.10 4. REFER JEDEC M0-220 00"'0.05
NOTE: INDEX MARK NCG20P1, PSC-4445-01, Rev 01, Page 2 ---2.70---t 1-0,30 J 2.15 1.00 1.00 RECOMMENDED LAND PATTERN DIMENSION 1. ALL DIMENSION ARE IN MM. ANGLES IN DEGREES 2. TOP DOWN VIEW AS VIEWED ON PCB 3. LAND PATTERN RECOMMENDATION PER IPC-7351 B GENERIC REQUIREMENT FOR SURFACE MPOUNT DESIGN AND LAND PATTERN Package Revision History Date Created Rev No. Description Sept 12, 2017 Rev 0 1 Correct Title Sept 11, 2017 Rev 00 Initial Release
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