EEU-FM1V151

SIC403_12 VISHAY

Document overview

• Manufacturer or author: Provided By www.digicamel.com(free datasheet download site)
• PDF pages: 26

Technical content

Document Number: 66550 S12-0628-Rev. C, 19-Mar-12 www.vishay.com This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 For technical support, please contact: analogswitchtechsupport@vishay.com microBUCK® SiC403

6 A, 28 V Integrated Buck Regulator with Programmable LDO

DESCRIPTION

The Vishay Siliconix SiC403 is an advanced stand-alone synchronous buck regulator featuring integrated power MOSFETs, bootstrap switch, and a programmable LDO in a space-saving MLPQ 5 x 5 - 32 pin package. The SiC403 is capable of operating with all ceramic solutions and switching frequencies up to 1 MHz. The programmable frequency, synchronous operation and selectable power-save allow operation at high efficiency across the full range of load current. The internal LDO may be used to supply 5 V for the gate drive circuits or it may be bypassed with an external 5 V for optimum efficiency and used to drive external n-channel MOSFETs or other loads. Additional features include cycle-by- cycle current limit, voltage soft-start, under-voltage protection, programmable over-current protection, soft shutdown and selectable power-save. The Vishay Siliconix SiC403 also provides an enable input and a power good output.

FEATURES

• High efficiency > 95 %  6 A continuous output current capability  Integrated bootstrap switch  Programmable 200 mA LDO with bypass logic  Temperature compensated current limit  Pseudo fixed-frequency adaptive on-time control  All ceramic solution enabled  Programmable input UVLO threshold  Independent enable pin for switcher and LDO  Selectable ultra-sonic power-save mode  Programmable soft-start  Soft-shutdown  1 % internal reference voltage  Power good output  Under and over voltage protection  Material categorization: For definitions of compliance please see www.vishay.com/doc?99912

APPLICATIONS

 Notebook, desktop, and server computers  Digital HDTV and digital consumer applications  Networking and telecommunication equipment  Printers, DSL, and STB applications  Embedded applications  Point of load power supplies TYPICAL APPLICATION CIRCUIT PRODUCT SUMMARY Input Voltage Range 3 V to 28 V Output Voltage Range 0.75 V to 5.5 V Operating Frequency 200 kHz to 1 MHz Continuous Output Current 6 A Peak Efficiency 95 % at 300 kHz Package MLPQ 5 mm x 5 mm PAD 1 AGND LX PAD 3 LX PAD 2 VIN PGND LX PGND PGND PGND PGND PGND TON AGND EN\\PSV LX ILIM PGOOD BST VIN FBL AGND VDD VOUT FB 1 SS PGND VIN VIN VIN NC LX NC 24 LX ENL VIN VOUT VOUT PGOOD 3.3 V EN/PSV (Tri-State) LDO_EN SiC403 (MLP 5 x 5-32L) PGND 31 30 29 25 26272832

www.vishay.com Document Number: 66550 S12-0628-Rev. C, 19-Mar-12 Vishay Siliconix SiC403 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 For technical support, please contact: analogswitchtechsupport@vishay.com PIN CONFIGURATION (TOP VIEW) PAD 1 AGND LX PAD 3 LX PAD 2 VIN PGND LX PGND PGND PGND PGND PGND TON AGND EN\\PSV LX ILIM PGOOD BST VIN FBL AGND VDD VOUT FB 1 SS PGND VIN VIN VIN NC LX NC 16PGND 24 LX ENL 31 30 29 25 26272832 PIN DESCRIPTION Pin Number Symbol Description 1F B Feedback input for switching regulator. Connect to an external resistor divider from output to program output voltage. 2V OUT Output voltage input to the controller. Additionally may be used to by pass LDO to supply VDD directly. 3V DD Bias for internal logic circuitry and gate drivers. Connect to external 5V po wer supply or configure the internal LDO for 5 V. 4, 30, PAD 1 A GND Analog ground 5F B L Feedback input for internal LDO. Connect to an external resistor divider from VDD to AGND to program LDO output. 6, 9-11, PAD 2 V IN Power stage input (HS FET Drain)

7 SS Connect to an external capacitor to A GND to program softstart ramp

8 BST Bootstrap pin. A capacitor is connected between BST and LX to provide HS driver voltage.

12 NC Not internally connected

13, 23-25, 28, PAD 3 LX Switching node (HS FET Source and LS FET Drain)

14 NC Not internally connected

15-22 P GND Power ground (LS FET Source) 26 P GOOD Open-drain power good indicator. Externally pull-up resistor is required.

27 I LIM Connect to an external resistor between ILIM and LX to program over current limit

29 EN/PSV Tri-state pin. Pull low to A GND to disable the regulator. Float to enable forced continuous current mode. Pull high to VDD to enable power save mode.

31 T ON Connect to an external resistor to AGND program on-time

32 ENL Enable input for internal LDO. Pull down to A GND to disable internal LDO.

ORDERING INFORMATION

Document Number: 66550 S12-0628-Rev. C, 19-Mar-12 www.vishay.com Vishay Siliconix SiC403 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 For technical support, please contact: analogswitchtechsupport@vishay.com FUNCTIONAL BLOCK DIAGRAM Stresses beyond those listed under "Absolute Maximum Ratings" may c ause permanent damage to the device. These are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating/conditions for extended periods may affect device reliability. Note: For proper operation, the device should be used within the recommended conditions. Gate Drive Control On-Time Generator Zero Cross Detector FB Comparator Soft Start Reference VDD 26 29 AGND 4, 30, PAD 1 P GOOD Control and Status EN/PSV FB TON VOUT Valley1-LimitBypass Comparator A B Y LDO

32 ENL

13, 23 to 25, 28, PAD 3 6, 9-11, PAD 2 VDD FBL SS ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted) Parameter Symbol Min. Max. Unit LX to P GND Voltage V LX - 0.3 + 30 V LX to PGND Voltage (transient - 100 ns) V LX - 2 + 30 VIN to PGND Voltage V IN - 0.3 + 30 EN/PSV, PGOOD, ILIM, to AGND - 0.3 V DD + 0.3 BST Bootstrap to LX; VDD to PGND - 0.3 + 6 AGND to PGND VAG-PG - 0.3 + 0.3 EN/PSV, PGOOD, ILIM, VOUT, VLDO, FB, FBL to GND - 0.3 + (VDD + 0.3) tON to PGND - 0.3 + (V DD - 1.5) BST to PGND - 0.3 + 35 RECOMMENDED OPERATING CONDITIONS Parameter Symbol Min. Typ. Max. Unit Input Voltage V IN 32 8 VVDD to PGND VDD 35 . 5 VOUT to PGND VOUT 0.75 5.5 THERMAL RESISTANCE RATINGS Parameter Symbol Min. Typ. Max. Unit Storage Temperature T STG - 40 + 150 °CMaximum Junction Temperature TJ - 150 Operation Junction Temperature TJ - 25 + 125

www.vishay.com Document Number: 66550 S12-0628-Rev. C, 19-Mar-12 Vishay Siliconix SiC403 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 For technical support, please contact: analogswitchtechsupport@vishay.com Notes: a. This device is ESD sensitive. Use of standard ESD handling precautions is required. b. Calculated from package in still air, mounted to 3 x 4.5 (in), 4 layer FR4 PCB with thermal vias under the exposed pad per JESD51 standards. Exceeding the above specifications may result in permanent damage to the devic e or device malfunction. Operation outside of the parameters specififed in the Electrical Characteristics section is not recommended. Parameter Symbol Min. Typ. Max. Unit Thermal Resistance, Junction-to-Ambient b High-Side MOSFET Low-Side MOSFET PWM Controller and LDO Thermal Resistance °C/W Peak IR Reflow Temperature T Reflow - 260 °C ELECTRICAL SPECIFICATIONS Parameter Symbol Test Conditions Unless Specified VIN = 12 V, VDD = 5 V, TA = + 25 °C for typ., - 40 °C to + 85 °C for min. and max., TJ = < 125 °C Min. Typ. Max. Unit Input Supplies V IN UVLO Threshold Voltagea VIN_UV+ Sensed at ENL pin, rising edge 2.4 2.6 2.95 V VIN_UV- Sensed at ENL pin, falling edge 2.235 2.4 2.565 VIN UVLO Hysteresis V IN_UV_HY EN/PSV = High 0.2 VDD UVLO Threshold Voltage VDD_UV+ Measured at VDD pin, rising edge 2.5 2.8 3 VDD_UV- Measured at VDD pin, falling edge 2.4 2.6 2.9 VDD UVLO Hysteresis V DD_UV_HY 0.2 VIN Supply Current IIN EN/PSV, ENL = 0 V, VIN = 28 V 8.5 20 µAStandby mode: ENL = VDD, EN/PSV = 0 V 130 VDD Supply Current IVDD EN/PSV, ENL = 0 V 3 7 EN/PSV = VDD, no load (fSW = 25 kHz), VFB > 750 mV 2 mAfSW = 250 kHz, EN/PSV = floating, no loadb 25°C bench testing 10 Controller FB On-Time Threshold V FB-TH Static VIN and load, - 40 °C to + 85 °C 0.7425 0.750 0.7599 V Frequency Rangeb FPWM continuous mode, 25°C bench testing 200 1000 kHz Bootstrap Switch Resistance 10  Timing On-Time t ON Continuous mode operation VIN = 15 V, VOUT = 5 V, Rton = 300 k 2386 2650 2915 nsMinimum On-Timeb tON 25°C bench testing 80 Minimum Off-Timeb tOFF 25°C bench testing 320 Soft Start Soft Start Current b ISS IOUT = ILIM/2, 25°C bench testing 2.75 µA Analog Inputs/Outputs V OUT Input Resistance R O-IN 500 k  Current Sense Zero-Crossing Detector Threshold Voltage V Sense-th LX-PGND - 3.5 0.5 + 3.5 mV Power Good Power Good Threshold Voltage PG_V TH_UPPER VFB > internal reference 750 mV + 20 Power Good Threshold Voltage PG_VTH_LOWER VFB < internal reference 750 mV - 10 Start-Up Delay Time PG_T d Css = 10 nF 12 ms Fault (noise-immunity) Delay Timeb PG_ICC VEN = 0 V, 25°C bench testing 5 µs Power Good Leakage Current PG_I LK VEN = 0 V 1 µA Power Good On-Resistance PG_R DS-ON VEN = 0 V 10  THERMAL RESISTANCE RATINGS

Document Number: 66550 S12-0628-Rev. C, 19-Mar-12 www.vishay.com Vishay Siliconix SiC403 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 For technical support, please contact: analogswitchtechsupport@vishay.com Notes: a. V IN UVLO is programmable using a resistor divider from VIN to ENL to AGND. The ENL voltage is compared to an internal reference. b. Guaranteed by design. c. The switch-over threshold is the maximum voltage diff erential between the V LDO and V OUT pins which ensures that V LDO will internally switch-over to VOUT. The non-switch-over threshold is the minimum voltage diff erential between the VLDO and VOUT pins which ensures that VLDO will not switch-over to VOUT. d. The LDO drop out voltage is the voltage at which the LDO output drops 2 % below the nominal regulation point. Fault Protection I LIM Source Current I LIM 8µ A Valley Current Limit RILIM = 6 kVDD = 5 V, 25°C bench testing 4.5 6 7.2 A Output Under-Voltage Fault V OUV_Fault VFB with respect to Internal 500 mV reference, 8 consecutive clocks - 25 % Smart Power-Save Protection Threshold Voltage b PSAVE_VTH VFB with respect to internal 500 mV reference, 25°C bench testing + 10 Over-Voltage Protection Threshold VFB with respect to internal 500 mV reference + 20 Over-Voltage Fault Delayb tOV-Delay 25°C bench testing 5 µs Over Temperature Shutdownb TShut 10 °C hysteresis, 25°C bench testing 150 °C Logic Inputs/Outputs Logic Input High Voltage V IH EN, ENL, PSV 1 VLogic Input Low Voltage VIL 0.4 EN/PSV Input Bias Current IEN EN/PSV = VDD or AGND - 10 + 10 µAENL Input Bias Current IENL VIN = 28 V 11 18 FBL, FB Input Bias Current FBL_ILK FBL, FB = VDD or AGND - 1 + 1 Linear Dropout Regulator FBL Accuracy FBL ACC VLDO load = 10 mA 0.735 0.750 0.765 V LDO Current Limit LDO_I LIM Start-up and foldback, VIN = 12 V 115 mAOperating current limit, VIN = 12 V 134 200 VLDO to VOUT Switch-Over Thresholdc VLDO-BPS - 130 + 130 mVVLDO to VOUT Non-Switch-Over Thresholdc VLDO-NBPS - 500 + 500 VLDO to VOUT Switch-Over Resistance RLDO VOUT = 5 V 2  LDO Drop Out Voltaged From VIN to VVLDO, VVLDO = + 5 V, IVLDO = 100 mA 1.2 V ELECTRICAL SPECIFICATIONS Parameter Symbol Test Conditions Unless Specified VIN = 12 V, VDD = 5 V, TA = + 25 °C for typ., - 40 °C to + 85 °C for min. and max., TJ = < 125 °C Min. Typ. Max. Unit

www.vishay.com Document Number: 66550 S12-0628-Rev. C, 19-Mar-12 Vishay Siliconix SiC403 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 For technical support, please contact: analogswitchtechsupport@vishay.com

ELECTRICAL CHARACTERISTICS

Efficiency vs. IOUT (in Continuous Conduction Mode) VOUT vs. IOUT (in Continuous Conduction Mode) VOUT vs. VIN at IOUT = 0 A (in Continuous Conduction Mode, FSW = 500 kHz) 0.01 0.1 1 10 Efficiency (%) IOUT (A) VIN = 12 V, VOUT = 1 V, FSW = 500 kHz 0.992 0.994 0.996 0.998 1.002 1.004 1.006 01234567 VOUT (V) VIN = 12 V, VOUT = 1 V, FSW = 500 kHz IOUT (A) 0.998 1.002 1.004 1.006 1.008 1.010 1.012 5 7 9 1 11 31 51 71 92 12 3 VOUT (V) VIN (V) VOUT = 1 V, FSW = 500 kHz, Continuous Conduction Mode Efficiency vs. IOUT (in Power-Save-Mode) VOUT vs. IOUT (in Power-Save-Mode) VOUT vs. VIN at IOUT = 6 A (in Continuous Conduction Mode, FSW = 500 kHz) Efficiency (%) IOUT (A) 0.10.01 1 10 VIN = 12 V, VOUT = 1 V, FSW = 500 kHz 0.992 0.994 0.996 0.998 1.002 1.004 1.006 1.008VOUT (V) 06 543721 IOUT (A) VIN = 12 V, VOUT = 1 V, FSW = 500 kHz 0.95 0.96 0.97 0.98 0.99 1.01 1.02 1.03 1.04 1.05 VOUT (V) VOUT = 1 V, FSW = 500 kHz, Continuous Conduction Mode 5 7 9 11 13 15 17 19 23 21 VIN (V)

Document Number: 66550 S12-0628-Rev. C, 19-Mar-12 www.vishay.com This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 For technical support, please contact: analogswitchtechsupport@vi- VOUT vs. VIN (IOUT = 0 A in Power-Save-Mode) VOUT Ripple vs. VIN (IOUT = 0 A in Continuous Conduction Mode) FSW vs. IOUT (in Continuous Conduction Mode) 0.9 0.95 1.05 1.1 6 8 10 12 14 16 18 20 22 24 VOUT (V) VIN (V) VOUT = 1 V, FSW = 500 kHz, Power Saving Mode 0 5 10 15 20 25 VOUT Ripple (mV) VIN (V) VOUT =1 V, IOUT = 0 A, FSW = 500 kHz FSW (kHz) IOUT (A) 350 370 390 410 430 450 470 490 510 530 550 01234567 VIN = 12 V, VOUT = 1 V VOUT Ripple vs. VIN (IOUT = 6 A in Continuous Conduction Mode) VOUT Ripple vs. VIN (IOUT = 0 A in Power-Save-Mode) FSW vs. IOUT (in Power-Save-Mode) 0 5 10 15 20 25 VOUT Ripple (mV) VIN (V) VOUT = 1 V, IOUT = 6 A, FSW = 500 kHz 6 8 10 12 14 16 18 20 VOUT Ripple (mV) VIN (V) VOUT = 1 V, IOUT = 0 A, FSW = 500 kHz 100 200 300 400 500 600 0 1 234567 FSW (kHz) IOUT (A) VIN = 12 V, VOUT = 1 V

www.vishay.com Document Number: 66550 S12-0628-Rev. C, 19-Mar-12 Vishay Siliconix SiC403 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 For technical support, please contact: analogswitchtechsupport@vishay.com VOUT Ripple in Power Save Mode (No Load) (VIN = 12 V, VOUT = 1 V) Transient Response in Continuous Conduction Mode (6 A to 0.2 A) (VIN = 12 V, VOUT = 1 V, FSW = 500 kHz) Transient Response in Power Save Mode (6 A to 0.2 A) (VIN = 12 V, VOUT = 1 V, FSW = 500 kHz at 6 A) Ch2: Output ripple Voltage (20mV/div) Ch1: LX Switching Node (5V/div) Time: 20 μs/div Ch3: Output Current (2A/div) Ch2: Output Voltage (50mV/div) Time: 5 μs/div Ch3: Output Current (2A/div) Ch2: Output Voltage (50mV/div) Time: 10 μs/div VOUT Ripple in Continuous Conduction Mode (No Load) (VIN = 12 V, VOUT = 1 V, FSW = 500 kHz) Transient Response in Continuous Conduction Mode (0.2 A to 6 A) (VIN = 12 V, VOUT = 1 V, FSW = 500 kHz) Transient Response in Power Save Mode (0.2 A to 6 A) (VIN = 12 V, VOUT = 1 V, FSW = 500 kHz at 6 A) Ch2: Output ripple Voltage (20mV/div) Ch1: LX Switching Node (5V/div) Time: 2 μs/div Ch3: Output Current (2A/div) Ch2: Output Voltage (50mV/div) Time: 5 μs/div Ch3: Output Current (2A/div) Ch2: Output Voltage (50mV/div) Time: 10 μs/div

Document Number: 66550 S12-0628-Rev. C, 19-Mar-12 www.vishay.com This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 For technical support, please contact: analogswitchtechsupport@vi- Start-up with VIN Ramping up (VIN = 12 V, VOUT = 1 V, FSW = 500 kHz) Ch4: Vin (5V/div) Ch2: Vout (500mV/div) Ch3: Power Good (5V/div) Ch1: Switching Node (5V/div) Time: 10 ms/div Over-Current Protection (VIN = 12 V, VOUT = 1 V, FSW = 500 kHz ) Ch4: Iout (10A/div) Ch2: Vout (1V/div) Ch3: Power good (5V/div) Ch1: Switching Node (10V/div) Time: 10 ms/div Efficiency with 12 VIN, 5 VOUT, 300 kHz 100 01234 5 6 7 Efficiency (%) IOUT (A) VIN = 12 V, VOUT = 5 V, FSW = 300 kHz

This document is subject to change without notice.

1 MHz, enables the user to optimize the solution for minimum

board space and optimum efficiency. components used in the system. the output voltage discharges through an internal FET. figure 1. The ripple voltage generated at the output capacitor trigger the on-time of the controller. condition and at the selected frequency. traditional control methods used in the controllers today. on-chip implementation of on-time generation.

www.vishay.com Document Number: 66550 S12-0628-Rev. C, 19-Mar-12 Vishay Siliconix SiC403 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 For technical support, please contact: analogswitchtechsupport@vishay.com The LDO output voltage is set by the following equation. A minimum 0.1 µF capa citor referenced to A GND is equired along with a minimum 1 µF capacitor referenced to PGND to filter the gate drive pulses. Refer to the layout guidelines section for component placement suggestions. LDO ENL Functions The ENL input is used to control the internal LDO. When ENL is low (grounded), the LDO is off. When ENL is above the V IN UVLO threshold, the LDO is enabled and the switcher is also enabled if EN/PSV and VDD meet the thresholds. The ENL pin also acts as the switcher UVLO (undervoltage lockout) for the V IN supply. The V IN UVLO voltage is programmable via a resistor divider at the V IN, ENL and AGND pins. If the ENL pin transitions from high to low within 2 switching cycles and is less than 1 V, then the LDO will turn off but the switcher remains on. If the ENL goes below the V IN UVLO threshold and stays above 1 V, then the switcher will turn off but the LDO remains on. The V IN UVLO function has a typical threshold of 2.6 V on the V IN rising edge. The falling edge threshold is 2.4 V. Note that it is possible to operate the switcher with the LDO disabled, but the ENL pin must be below the logic low threshold (0.4 V max.). In this case, the UVLO function for the input voltage cannot be used. The table below summarizes the function of the ENL and EN pins, with respect to the rising edge of ENL. Figure 10 shows the ENL voltage thresholds and their effect on LDO and switcher operation. Before start-up, the LDO checks the status of the following signals to ensure proper operation can be maintained. E N L p i n IN input voltage When the ENL pin is high and VIN is above the UVLO point, the LDO will begin start-up. During the initial phase, when the V DD voltage (which is the LDO output voltage) is less than

0.75 V, the LDO initiates a cu rrent-limited start-up (typically

65 mA) to charge the output capacitors while protecting from a short circuit event. When V DD is greater than 0.75 V but still less than 90 % of its final value (as sensed at the FBL pin), the LDO current limit is increased to ~ 115mA. When V DD has reached 90 % of the final value (as sensed at the FBL pin), the LDO current limit is increased to ~ 200 mA and the LDO output is quickly driven to the nominal value by the internal LDO regulator. It is recommended that during LDO start-up to hold the PWM switching off until the LDO has reached 90 % of the final value. This prevents overloading the current-limited LDO output during the LDO start-up. Due to the initial current limitations on the LDO during power up (figure 11), any external load attached to the V DD pin must be limited to 20 mA before the LDO has reached 90 % of it final regulation value. LDO Switchover Function The SiC403 includes a switch-over function for the LDO. The switch-over function is designed to increase efficiency by using the more efficient DC/DC converter to power the LDO output, avoiding the less efficient LDO regulator when possible. The switch-over function connects the V LDO pin directly to the V OUT pin using an internal switch. When the switch-over is complete the LDO is turned off, which results Figure 9 - LDO Voltage Divider EN ENL LDO Status Switcher Status Low Low, < 0.4 V Off Off High Low, < 0.4 V Off On Low High, < 2.6 V On Off High High, < 2.6 V On Off Low High, > 2.6 V On Off High High, > 2.6 V On On VDD RLDO1 RLDO2 to FBL pin VLDO = 750 mV x 1 +() RLDO1 RLDO2 Figure 10 - ENL Threshold Figure 11 - LDO Start-Up

Document Number: 66550 S12-0628-Rev. C, 19-Mar-12 www.vishay.com This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 For technical support, please contact: analogswitchtechsupport@vi- in a power savings and maximi zes efficiency. If the LDO output is used to bias the SiC403, then after switch-over the device is self-powered from the switching regulator with the LDO turned off. The switch-over logic waits fo r 32 switching cycles before it starts the switch-over. There are two methods that determine the switch-over of V LDO to VOUT. In the first method, the LDO is already in regulation and the DC/DC converter is later enabled. As soon as the P GOOD output goes high, the 32 cycles are started. The voltages at the V LDO and V OUT pins are then compared; if the two voltages are within ± 300 mV of each other, the V LDO pin connects to the V OUT pin using an internal switch, and the LDO is turned off. In the second method, the DC /DC converter is already running and the LDO is enabled. In this case the 32 cycles are started as soon as the LDO reaches 90 % of its final value. At this time, the V LDO and VOUT pins are compared, and if within ± 300 mV the switch-over occurs and the LDO is turned off. Benefits of having a switchover circuit The switchover function is designed to get maximum efficiency out of the DC/DC converter. The efficiency for an LDO is very low especially for high input voltages. Using the switchover function we tie any rails connected to V LDO through a switch directly to V OUT. Once switchover is complete LDO is turned off which saves power. This gives us the maximum efficiency out of the SiC403. If the LDO output is used to bias the SiC403, then after switchover the V OUT self biases the SiC403 and operates in self-powered mode. Steps to follow when using the on chip LDO to bias the SiC403:  Always tie the V DD to VLDO before enabling the LDO  Enable the LDO before enabling the switcher  LDO has a current limit of 40 mA at start-up, so do not connect any load between V LDO and ground  The current limit for the LDO goes up to 200 mA once the VLDO reaches 90 % of its final values and can easily supply the required bias current to the IC. Switch-over Limitations on VOUT and VLDO Because the internal switch -over circuit always compares the VOUT and VLDO pins at start-up, there are limitations on permissible combinations of V OUT and V LDO. Consider the case where V OUT is programmed to 1.5 V and V LDO is programmed to 1.8 V. After start-up, the device would connect V OUT to V LDO and disable the LDO, since the two voltages are within the ± 300 mV switch-over window. To avoid unwanted switch-over, the minimum difference between the voltages for V OUT and V LDO should be ± 500 mV. It is not recommended to use the switch-over feature for an output voltage less than 3 V since this does not provide sufficient voltage for the gate-source drive to the internal p-channel switch-over MOSFET. Switch-Over MOSFET Parasitic Diodes The switch-over MOSFET contains parasitic diodes that are inherent to its construction, as shown in figure 12. There are some important design rules that must be followed to prevent forward bias of these diodes. The following two conditions need to be satisfied in order for the parasitic diodes to stay off.  V DD  VLDO  VDD  VOUT If either VLDO or VOUT is higher than VDD, then the respective diode will turn on and the SiC403 operating current will flow through this diode. This has the potential of damaging the device. ENL Pin and V IN UVLO The ENL pin also acts as the switcher under-voltage lockout for the V IN supply. The V IN UVLO voltage is programmable via a resistor divider at the VIN, ENL and AGND pins. ENL is the enable/disable signal for the LDO. In order to implement the V IN UVLO there is also a timing requirement that needs to be satisfied. If the ENL pin transitions low within 2 switching cycles and is < 0.4 V, then the LDO will turn off but the switcher remains on. If ENL goes below the V IN UVLO threshold and stays above 1 V, then the switcher will turn off but the LDO remains on. The V IN UVLO function has a typical threshold of 2.6 V on the VIN rising edge. The falling edge threshold is 2.4 V. Note that it is possible to operate the switcher with the LDO disabled, but the ENL pin must be below the logic low threshold (0.4 V maximum). ENL Logic Control of PWM Operation When the ENL input is driven above 2.6 V, it is impossible to determine if the LDO output is going to be used to power the device or not. In self-powered operation where the LDO will power the device, it is necessary during the LDO start-up to hold the PWM switching off until the LDO has reached 90 % of the final value. This is to prevent overloading the Figure 12- Switch-over MOSFET Parasitic Diodes VOUTVLDO V5V Parastic diodeParastic diode Switchover MOSFET Switchover control

www.vishay.com Document Number: 66550 S12-0628-Rev. C, 19-Mar-12 Vishay Siliconix SiC403 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 For technical support, please contact: analogswitchtechsupport@vishay.com current-limited LDO output during the LDO start-up. However, if the switcher was previously operating (with EN/ PSV high but ENL at ground, and V DD supplied externally), then it is undesirable to shut down the switcher. To prevent this, when the ENL input is taken above 2.6 V (above the V IN UVLO threshold), the internal logic checks the PGOOD signal. If PGOOD is high, then the switcher is already running and the LDO will run through the start-up cycle without affecting the switcher. If P GOOD is low, then the LDO will not allow any PWM switching until the LDO output has reached 90 % of it's final value. On-Chip LDO Bias the SiC403 The following steps must be followed when using the onchip LDO to bias the device.  Connect V DD to VLDO before enabling the LDO.  The LDO has an initial current limit of 40 mA at start-up, therefore, do not connect any external load to VLDO during start-up.  When V LDO reaches 90 % of its final value, the LDO current limit increases to 200 mA. At this time the LDO may be used to supply the required bias current to the device. Attempting to operate in self-powered mode in any other configuration can cause unpredictable results and may damage the device. Design Procedure When designing a switch mode power supply, the input voltage range, load current, switching frequency, and inductor ripple current must be specified. The maximum input voltage (V INMAX) is the highest specified input voltage. The minimum input voltage (V INMIN) is determined by the lowest input voltage after evaluating the voltage drops due to connectors, fuses, switches, and PCB traces. The following parameters define the design:  Nominal output voltage (V OUT)  Static or DC output tolerance  Transient response  Maximum load current (I OUT) There are two values of load current to evaluate - continuous load current and peak load current. Continuous load current relates to thermal stresses wh ich drive the selection of the inductor and input capacitors. Peak load current determines instantaneous component stresses and filtering requirements such as inductor saturation, output capacitors, and design of the current limit circuit. The following values are used in this design:  V IN = 12 V ± 10 %  VOUT = 1.05 V ± 4 %  fSW = 250 kHz  Load = 6 A maximum Frequency Selection Selection of the switching frequency requires making a trade-off between the size and cost of the external filter components (inductor and output capacitor) and the power conversion efficiency. The desired switching frequency is 250 kHz which results from using component selected for optimum size and cost. A resistor (R TON) is used to program the on-time (indirectly setting the frequency) using the following equation. To select R TON, use the maximum value for VIN, and for tON use the value associated with maximum VIN. tON = 318 ns at 13.2 VIN, 1.05 VOUT, 250 kHz Substituting for RTON results in the following solution RTON = 154.9 k, use RTON = 154 k. Inductor Selection In order to determine the inductance, the ripple current must first be defined. Low inductor values result in smaller size but create higher ripple current which can reduce efficiency. Higher inductor values will reduce the ripple current and voltage and for a given DC resistance are more efficient. However, larger inductance tran slates directly into larger packages and higher cost. Cost, size, output ripple, and efficiency are all used in the selection process. The ripple current will also set the boundary for power-save operation. The switching will typically enter power-save mode when the load current decreases to 1/2 of the ripple current. For example, if ripple current is 4 A then power-save operation will typically start for loads less than 2 A. If ripple current is set at 40 % of maximum load current, then power-save will start for loads less than 20 % of maximum current. The inductor value is typically selected to provide a ripple current that is between 25 % to 50 % of the maximum load current. This provides an optimal trade-off between cost, efficiency, and transient performance. During the DH on-time, voltage across the inductor is IN - V OUT). The equation for determining inductance is shown next. Example In this example, the inductor ripple current is set equal to 50 % of the maximum load current. Thus ripple current will be 50 % x 6 A or 3 A. To find the minimum inductance needed, use the V IN and TON values that correspond to VINMAX. Rton = (tON - 10 ns) x VIN 25 pF x VOUT tON = VOUT VINMAX. x fSW L = (VIN - VOUT) x tON IRIPPLE L = (13.2 - 1.05) x 318 ns 3 A = 1.28 µH

Document Number: 66550 S12-0628-Rev. C, 19-Mar-12 www.vishay.com This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 For technical support, please contact: analogswitchtechsupport@vi- A slightly larger value of 1.3 µH is selected. This will decrease the maximum IRIPPLE to 2.9 A. Note that the inductor must be rated for the maximum DC load current plus 1/2 of the ripple current. The ripple current under minimum V IN conditions is also checked using the following equations. Capacitor Selection The output capacitors are c hosen based on required ESR and capacitance. The maximum ESR requirement is controlled by the output ri pple requirement and the DC tolerance. The output voltage has a DC value that is equal to the valley of the output ripple plus 1/2 of the peak-to-peak ripple. Change in the output ripple voltage will lead to a change in DC voltage at the output. The design goal is that th e output voltage regulation be ± 4 % under static conditions. The internal 500 mV reference tolerance is 1 %. Allowing 1 % tolerance from the FB resistor divider, this allows 2 % tolerance due to V OUT ripple. Since this 2 % error comes from 1/2 of the ripple voltage, the allowable ripple is 4 %, or 42 mV for a 1.05 V output. The maximum ripple current of 4.4 A creates a ripple voltage across the ESR. The maximum ESR value allowed is shown by the following equations. The output capacitance is usual ly chosen to meet transient requirements. A worst-case load release, from maximum load to no load at the exact moment when inductor current is at the peak, determines the required capacitance. If the load release is instantaneous (load changes from maximum to zero in < 1 µs), the output capacitor must absorb all the inductor's stored energy. This will cause a peak voltage on the capacitor according to the following equation. Assuming a peak voltage V PEAK of 1.150 (100 mV rise upon load release), and a 10 A load release, the required capacitance is shown by the next equation. If the load release is relatively slow, the output capacitance can be reduced. At heavy loads during normal switching, when the FB pin is above th e 750 mV reference, the DL output is high and the low-si de MOSFET is on. During this time, the voltage across the inductor is approximately - V OUT. This causes a down-slope or falling di/dt in the inductor. If the load dI/dt is not much faster than the - dI/dt in the inductor, then the inductor current will tend to track the falling load current. This will reduce the excess inductive energy that must be absorbed by the out put capacitor, therefore a smaller capacitance can be used. The following can be used to calculate the needed capacitance for a given dI LOAD/dt: Peak inductor current is shown by the next equation. I LPK = IMAX + 1/2 x IRIPPLEMAX ILPK = 6 + 1/2 x 2.9 = 7.45 A Rate of change of load current = dILOAD/dt IMAX = maximum load release = 6 A Example This would cause the output current to move from 10 A to zero in 4 µs as shown by the following equation. Note that C OUT is much smaller in this example, 254 µF compared to 328 µF based on a worst-case load release. To meet the two design criteria of minimum 254 µF and maximum 9 m ESR, select two capacitors rated at 150 µF and 18 m ESR. It is recommended that an additional small capacitor be placed in parallel with C OUT in order to filter high frequency switching noise. Stability Considerations Unstable operation is possible with adaptive on-time controllers, and usually takes the form of double-pulsing or ESR loop instability. Double-pulsing occurs due to switching noise seen at the FB input or because the FB ripple voltage is too low. This causes the FB comparator to trigger prematurely after the 250 ns minimum off-time has expired. In extreme cases the noise can cause three or more successive on-times. Double-pulsing will result in higher ripple voltage at the output, but in most applications it will not affect operation. TON_VINMIN = 25 pF x RTON x VOUT VINMIN IRIPPLE = (VIN - VOUT) x TON L IRIPPLE_VIN = (10.8 - 1.05) x 384 ns 1.3 µH = 2.88 A ESRMAX = VRIPPLE IRIPPLEMAX ESRMAX = 9.5 mΩ = 42 mV 2.9 A COUT_MIN = L (IOUT + x IRIPPLEMAX)2 (VPEAK)2 - (VOUT)2 COUT_MIN = (1.15)2 - (1.05)2 COUT_MIN = 328 µF COUT = ILPK x L x - x dt 2 (VPK - VOUT) ILPK VOUT IMAX dlLOAD Load dlLOAD dt = 2.5 A µs COUT = 7.45 x 1.3 µH x - x 1 µs 2 (1.15 - 1.05) 7.45 1.05 2.5 COUT = 254 µF

Document Number: 66550 S12-0628-Rev. C, 19-Mar-12 www.vishay.com This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 For technical support, please contact: analogswitchtechsupport@vi- System DC Accuracy (VOUT Controller) Three factors affect V OUT accuracy: the trip point of the FB error comparator, the ripple voltage variation with line and load, and the external resistor tolerance. The error comparator off set is trimmed so that under static conditions it trips when the feedback pin is 750 mV, 1 %. The on-time pulse from the SiC403 in the design example is calculated to give a pseudo-fixed frequency of 250 kHz. Some frequency variation with line and load is expected. This variation changes the output ripple voltage. Because constant on-time converters regulate to the valley of the output ripple, ½ of the output ripple appears as a DC regulation error. For example, if the output ripple is 50 mV with V IN = 6 V, then the measured DC output will be 25 mV above the comparator trip point. If the ripple increases to 80 mV with V IN = 25 V, then the measured DC output will be 40 mV above the comparator trip. The best way to minimize this effect is to minimize the output ripple. To compensate for valley regulation, it may be desirable to use passive droop. Take the feedback directly from the output side of the inductor and place a small amount of trace resistance between the inductor and output capacitor. This trace resistance should be optimized so that at full load the output droops to near the lower regulation limit. Passive droop minimizes the required output capacitance because the voltage excursions due to load steps are reduced as seen at the load. The use of 1 % feedback resist ors contributes up to 1 % error. If tighter DC accuracy is required, 0.1 % resistors should be used. The output inductor value may change with current. This will change the output ripple and therefore will have a minor effect on the DC output voltage. The output ESR also affects the output ripple and thus has a minor effect on the DC output voltage. Switching Frequency Variations The switching frequency will vary depending on line and load conditions. The line variations are a result of fixed propagation delays in the on-time one-shot, as well as unavoidable delays in the external MOSFET switching. As V IN increases, these factors make the actual DH on-time slightly longer than the ideal on-time. The net effect is that frequency tends to falls slightly with increasing input voltage. The switching frequency also varies with load current as a result of the power losses in the MOSFETs and the inductor. For a conventional PWM constant-frequency converter, as load increases the duty cycle also increases slightly to compensate for IR and swit ching losses in the MOSFETs and inductor. A constant on-time converter must also compensate for the same losses by increasing th e effective duty cycle (more time is spent drawing energy from V IN as losses increase). The on-time is essentiall y constant for a given V OUT/VIN combination, to off set the losses the off-time will tend to reduce slightly as load incr eases. The net effect is that switching frequency increases slightly with increasing load.

This document is subject to change without notice. Figure 15. Evaluation Board Schematic

1 R4 1R01R4 1R01

Document Number: 66550 S12-0628-Rev. C, 19-Mar-12 www.vishay.com This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 For technical support, please contact: analogswitchtechsupport@vi- BILL OF MATERIALS Item Qty. Reference Value Voltage PCB Footprint Part Number Manufacturer

11 B 1 VIN SOLDER-BANANA 575-4 Keystone

21 B 2 VIN_GND SOLDER-BANANA 575-4 Keystone

3 1 B3 Vo SOLDER-BANANA 575-4 Keystone

41 B 4 V

O_GND SOLDER-BANANA 575-4 Keystone 5 4 C1, C2, C3, C4 22 µF 16 V SM/C_1210 GRM32ER71C226ME18L Murata 6 1 C5 0.1 µF 16 V SM/C_0402 EMK105BJ104KV-F Taiyo Yuden 7 1 C6 0.1 µF 50 V SM/C_0603 VJ0603Y104KXACW1BC Murata 8 3 C7, C11, C14 0.1 µF 50 V SM/C_0603 VJ0603Y104KXACW1BC Vishay 9 3 C10, C20, C22 220 µF 25 V 595D-D 593D227X0010E2TE3 Vishay 10 1 C12 150 µF 35 V D8X11.5-D0.6X3.5 EEU-FM1V151 Panasonic 11 1 C13 0.01 µF 50 V SM/C_0402 VJ0402Y103KXACW1BC Vishay 12 2 C15, C21 10 µF 16 V SM/C_1206 C3216X7R1C106M TDK 13 3 C16, C17, C18 220 µF 10 V 595D-D 593D227X0010E2TE3 Vishay 14 1 C19 1 µ  SM/C_0603 15 1 C24 10 n  SM/C_0603 16 1 C25 68 pF 50 V SM/C_0402 0402YA680JAT2A AVX 17 2 C26, C27 4.7 µF 10 V SM/C_0805 LMK212B7475KG-T TAIYO YUDEN 18 1 C28 0.1 µF 10 V SM/C_0603 GRM155R61A105KE19D Murata 19 1 C29 22 nF 16 V SM/C_0603 Murata 20 1 C30 100 pF 50 V SM/C_0402 VJ0402Y101KXACW1BC Vishay 21 1 C36 1 nF 50 V SM/C_0402 C0402C102K3RA Vishay 22 1 C37 10 nF 50 V SM/C_0402 VJ0402A103KXACW1BC Vishay 23 1 J5 Probe Test Pin LECROY PROBE PIN PK007-015 24 1 L1 0.78 µH IHLP4040 IHLP4040DZERR78M11 Vishay 25 4 M1, M2, M3, M4 M HOLE2 STACKING SPACER 8834 Keystone 26 1 P1 V DD Probe Hook - d76 1573-3 Keystone 27 1 P2 EN_PSV Probe Hook - d76 1573-3 Keystone 28 1 P3 Step_I_Sense Probe Hook - d76 1573-3 Keystone 29 1 P4 LDTRG Probe Hook - d76 1573-3 Keystone 30 1 P5 V CTL Probe Hook - d76 1573-3 Keystone 31 1 P6 ENL Probe Hook - d76 1573-3 Keystone 32 1 P7 PGOOD Probe Hook - d76 1573-3 Keystone 33 1 P8 V IN Probe Hook - d76 1573-3 Keystone 34 1 P9 VIN_GND Probe Hook - d76 1573-3 Keystone 35 1 P10 VOUT Probe Hook - d76 1573-3 Keystone 36 1 P11 VO_GND Probe Hook - d76 1573-3 Keystone 37 1 Q1 Si4812BDY 30 V SO-8 Si4812BDY Vishay 38 1 R1 300K 50 V SM/C_0603 CRCW060310K0FKEA Vishay 39 1 R2 300K 50 V SM/C_0603 CRCW06030000FKEA Vishay 40 1 R4 1R01 200 V C_2512 CRCW25121R00FKTA Vishay 41 2 R5, R6 100K 50 V SM/C_0603 CRCW0603100KFKEA Vishay 42 1 R7 0R 50 V SM/C_0603 CRCW06030000Z0EA Vishay

www.vishay.com Document Number: 66550 S12-0628-Rev. C, 19-Mar-12 Vishay Semiconductors SiC403 New Product This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 43 3 R8, R10, R29 10K 50 V SM/C_0603 CRCW060310K0FKEA Vishay 44 1 R9  SM/C_0603 45 1 R12 57.6K 50 V SM/C_0603 CRCW060357K6FKEA Vishay 46 1 R13 10K 50 V SM/C_0402 CRCW040210K0FKED Vishay 47 1 R14 100 50 V SM/C_0402 CRCW040210K0FKED Vishay 48 1 R15 1.5K SM/C_0603 CRCW06031K50FKEA Vishay 49 1 R23 7k15 SM/C_0603 CRCW06037K15FKEA Vishay 50 1 R30 154K SM/C_0603 CRCW0603154KFKEA Vishay 51 1 R39 0R SM/C_0402 CRCW04020000Z0ED Vishay 52 1 R51 1R SM/C_0805 CRCW08051R00FNEA Vishay 53 1 R52 31K6 50 V SM/C_0603 CRCW060331K6FKEA Vishay 54 1 U1 SiC401/2/3 MLPQ5x5-32L Vishay BILL OF MATERIALS

www.vishay.com Document Number: 66550 S12-0628-Rev. C, 19-Mar-12 Vishay Semiconductors SiC403 New Product This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 PACKAGE DIMENSIONS AND MARKING INFO Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locatio ns. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?66550. 5.000 ± 0.075 5.000 ± 0.075 Pin # 1 (Laser Marked) Top View A C0.10 C 0.08 C 0.900 ± 0.100 0.050 0.000 B 0.200 ref. Bare Copper 0.460

0.10 C A B

0.500 0.460 3.480 ± 0.100 R Full17 24 C L CL 1.485 ± 0.100 0.250 ± 0.050 1.660 ± 0.100 Bottom View 1.050 ± 0.100 0.400 ± 0.100 R0.200 Pin 1 I.D. 1.970 ± 0.100

Document Number: 64714 www.vishay.com Revision: 29-Dec-08 1

Package Information

PowerPAK® MLP55-32L CASE OUTLINE Notes 1. Use millimeters as the primary measurement. 2. Dimensioning and tolerances conform to ASME Y14.5M. - 1994. 3. N is the number of terminals. Nd is the number of terminals in X-direction and Ne is the number of terminals in Y-direction. 4. Dimension b applies to plated terminal and is m easured between 0.20 mm and 0.25 mm from terminal tip. 5. The pin #1 identifier must be existed on the top surface of the package by using indentation mark or other feature of package body. 6. Exact shape and size of this feature is optional. 7. Package warpage max. 0.08 mm. 8. Applied only for terminals. by marking E Pin 1 dot Top View D (5 mm x 5 mm) 32L T/SLP E2 - 2 (Nd-1) Xe Ref. Bottom ViewSide View D2 - 1 R0.200 Pin #1 identification b e D2 - 4 D2 - 3 E2 - 3 25 32 A 0.10 C B 0.08 C C A B (Nd-1) Xe Ref. L 0.36 0.360 5 6 0.10 C A B D2 - 2 E2 - 1 0.10 C A 0.45 MILLIMETERS INCHES A2 0.20 REF. 0.008 REF. D 5.00 BSC 0.196 BSC e 0.50 BSC 0.019 BSC E 5.00 BSC 0.196 BSC N(3) 32 32 Nd(3) 88 Ne(3) 88 ECN: T-08957-Rev. A, 29-Dec-08 DWG: 5983

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