DS99R101

DS99R101/DS99R102 3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer datasheet (Rev. D)

Document overview

• Manufacturer or author: Texas Instruments, Incorporated [SNLS240,D]
• PDF pages: 28

Technical content

DS99R101,DS99R102 www.ti.com SNLS240D –MARCH 2007–REVISED APRIL 2013 DS99R101/DS99R1023-40MHzDC-Balanced24-BitLVDSSerializerandDeserializer Check forSamples: DS99R101 ,DS99R102 1FEATURES Receiver

• 48-PinTQFP Package 2• 3 MHz –40 MHz Clock Embedded and DC- Balancing24:1and 1:24Data Transmissions • Pure CMOS .35μm Process
• User SelectableClock Edge forParallelData • Power Supply Range 3.3V± 10% on Both Transmitterand Receiver • Temperature Range 0°C to+70°C
• InternalDC BalancingEncode/Decode – • 8 kV HBM ESD Tolerance Supports AC-Coupling InterfacewithNo ExternalCoding Required DESCRIPTION
• IndividualPower-Down ControlsforBoth The DS99R101/DS99R102 Chipsettranslatesa 24- Transmitterand Receiver bitparallelbus intoa fullytransparentdata/control LVDS serialstreamwithembedded clockinformation.• Embedded Clock CDR (Clockand Data Thissingleserialstreamsimplifiestransferringa 24-Recovery)on Receiverand No ExternalSource bitbus overPCB tracesand cableby eliminatingtheofReferenceClock Needed skew problems between paralleldata and clock• AllCodes RDL (Random Data Lock) toSupport paths.Itsaves system costby narrowingdatapaths Live-PluggableApplications thatin turnreduce PCB layers,cable width,and connectorsizeand pins.• LOCK Output FlagtoEnsure Data Integrityat ReceiverSide The DS99R101/DS99R102 incorporates LVDS
• Balanced TSETUP /THOLD Between RCLK and signalingon thehigh-speedI/O.LVDS providesa low power and low noise environment for reliablyRDATA on ReceiverSide transferringdata over a serialtransmissionpath.By• PTO (ProgressiveTurn-On)LVCMOS Outputs optimizingthe serializeroutputedge rate for thetoReduce EMI and MinimizeSSO Effects operatingfrequencyrangeEMI isfurtherreduced.
• AllLVCMOS Inputsand ControlPins Have InternalDC balancedencoding/decodingisused toInternalPulldown supportAC-Coupled interconnects.• On-Chip FiltersforPLLs on Transmitterand Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsof Texas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2Alltrademarksarethepropertyoftheirrespectiveowners. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 2007–2013,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.

SERIALIZER ± DS99R101 PLL Timing and Control D OUT - R T = 100 RT = 100 :R IN- DESERIALIZER ± DS99R102 D OUT + R IN+ PLL Timing and Control R OUT LOCK RCLKClock Recovery Output Latch Serial to Parallel DC Balance Decode Input Latch Parallel to Serial DC Balance Encode CLK1bit0bit1bit2bit3bit4bit5bit bit bit bit bit bit DCA DCB bit bit bit bit bit bit bit bit bit bit bit bit CLK0 DS99R101,DS99R102 SNLS240D –MARCH 2007–REVISED APRIL 2013 www.ti.com Block Diagram These deviceshave limitedbuilt-inESD protection.The leadsshouldbe shortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamage totheMOS gates. AbsoluteMaximum Ratings (1)(2) SupplyVoltage(VDD ) −0.3Vto+4V LVCMOS/LVTTL InputVoltage −0.3Vto(VDD +0.3V) LVCMOS/LVTTL OutputVoltage −0.3Vto(VDD +0.3V) LVDS ReceiverInputVoltage −0.3Vto3.9V LVDS DriverOutputVoltage −0.3Vto3.9V LVDS OutputShortCircuitDuration 10 ms JunctionTemperature +150°C StorageTemperature −65°C to+150°C Lead Temperature(Soldering,4 seconds) +260°C Maximum Package Power DissipationCapacity 48L TQFP Package De-rating: 1/θJA °C/W above +25°C DS99R101 θJA 45.8(4L(3));75.4(2L(3))°C/W θJC 21.0°C/W DS99R102 θJA 45.4(4L(3));75.0(2L(3))°C/W θJC 21.1°C/W ESD Rating(HBM) ≥±8 kV (1) “AbsoluteMaximum Ratings”indicatelimitsbeyond whichdamage tothedevicemay occur,includinginoperabilityand degradationof devicereliabilityand/orperformance.Functionaloperationofthedeviceand/ornon-degradationattheAbsoluteMaximum Ratingsor otherconditionsbeyond thoseindicatedintheRecommended OperatingConditionsisnotimplied.The Recommended Operating Conditionsindicateconditionsatwhichthedeviceisfunctionaland thedeviceshouldnotbe operatedbeyond such conditions. (2) IfMilitary/Aerospacespecifieddevicesarerequired,pleasecontacttheTISalesOffice/Distributorsforavailabilityand specifications. (3) JEDEC

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DS99R101,DS99R102 www.ti.com SNLS240D –MARCH 2007–REVISED APRIL 2013 Recommended OperatingConditions Min Nom Max Units SupplyVoltage(VDD ) 3.0 3.3 3.6 V OperatingFreeAirTemperature(TA) 0 +25 +70 °C ClockRate 3 40 MHz SupplyNoise ±100 mV P-P ElectricalCharacteristics(1)(2)(3) Over recommended operatingsupplyand temperaturerangesunlessotherwisespecified. Symbol Parameter Conditions Pin/Freq. Min Typ Max Units LVCMOS/LVTTL DC SPECIFICATIONS VIH HighLevelVoltage Tx:DIN[23:0],TCLK, 2.0 1.5 VDD V TPWDNB, DEN, TRFB,VIL Low LevelInputVoltage GND 1.5 0.8 VDCAOFF, DCBOFF, VCL InputClamp Voltage ICL = −18 mA (4) VODSEL −0.8 −1.5 VRx: RPWDNB, RRFB, REN IIN InputCurrent VIN = 0V or3.6V Tx:DIN[23:0],TCLK, TPWDNB, DEN, TRFB, −10 ±5 +10 µADCAOFF, DCBOFF, VODSEL Rx: RPWDNB, RRFB, −20 ±5 +20 µAREN VOH HighLevelOutputVoltage IOH = −4 mA Rx: ROUT[23:0],RCLK, 2.3 3.0 VDD V LOCKVOL Low LevelOutputVoltage IOL = +4 mA GND 0.33 0.5 V IOS OutputShortCircuitCurrent VOUT = 0V (4) −40 −70 −110 mA IOZ TRI-STATE ™ OutputCurrent RPWDNB, REN = 0V Rx: ROUT[23:0],RCLK, −15 ±0.4 +15 µAVOUT = 0V or2.4V LOCK LVDS DC SPECIFICATIONS VTH DifferentialThresholdHigh VCM = +1.2V Rx: R IN+,R IN− +50 mVVoltage VTL DifferentialThresholdLow −50 mVVoltage IIN InputCurrent VIN = +2.4V,VDD = 3.6V ±200 µA VIN = 0V,VDD = 3.6V ±200 µA (1) The ElectricalCharacteristicstableslistguaranteedspecificationsunderthelistedRecommended OperatingConditionsexceptas otherwisemodifiedorspecifiedby theElectricalCharacteristicsConditionsand/orNotes.Typicalspecificationsareestimationsonlyand arenotguaranteed. (2) Typicalvaluesrepresentmost likelyparametricnorms atVCC = 3.3V,Ta = +25 degC, and attheRecommended OperationConditions atthetimeofproductcharacterizationand arenotguaranteed. (3) Currentintodevicepinsisdefinedas positive.Currentoutofa devicepinisdefinedas negative.Voltagesarereferencedtoground exceptVOD, ΔVOD, VTH and VTL whicharedifferentialvoltages. (4) Specificationisguaranteedby characterizationand isnottestedinproduction. Copyright© 2007–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:DS99R101 DS99R102

DS99R101,DS99R102 SNLS240D –MARCH 2007–REVISED APRIL 2013 www.ti.com ElectricalCharacteristics(1)(2)(3)(continued) Over recommended operatingsupplyand temperaturerangesunlessotherwisespecified. Symbol Parameter Conditions Pin/Freq. Min Typ Max Units VOD OutputDifferentialVoltage R L = 100Ω Tx:D OUT+ ,D OUT − 250 400 600 mV(DOUT+ )–(DOUT −) VODSEL = L (Figure10) R L = 100Ω 450 750 1200 mVVODSEL = H (Figure10) ΔVOD OutputDifferentialVoltage R L = 100Ω 4 50 mVUnbalance VOS OffsetVoltage R L = 100Ω 1.00 1.25 1.50 V ΔVOS OffsetVoltageUnbalance R L = 100Ω 1 50 mV IOS OutputShortCircuitCurrent DOUT = 0V,DIN = H, TPWDNB, DEN = 2.4V, −2 −5 −8 mA VODSEL = L DOUT = 0V,DIN = H, TPWDNB, DEN = 2.4V, −7 −10 −13 mA VODSEL = H IOZ TRI-STATE OutputCurrent TPWDNB, DEN = 0V, −15 ±1 +15 µADOUT = 0V or2.4V SER/DES SUPPLY CURRENT (DVDD (5),PVDD (5)and AVDD (5)pins) IDDT Serializer(Tx) R L = 100Ω f= 40 MHz TotalSupplyCurrent VODSEL = L 40 80 mA (includesloadcurrent) Checker-boardpattern(Figure1)(6) R L = 100Ω f= 40 MHz VODSEL = H 40 85 mA Checker-boardpattern(Figure1)(6) IDDTZ Serializer(Tx) TPWDNB = 0V 1 100 µASupplyCurrentPower-down (AllotherLVCMOS Inputs= 0V) IDDR Deserializer(Rx) C L = 8 pF LVCMOS Output f= 40 MHz TotalSupplyCurrent Checker-boardpattern 95 mA (includesloadcurrent) (Figure2)(6) Deserializer(Rx) C L = 8 pF LVCMOS Output f= 40 MHz TotalSupplyCurrent Random pattern 90 mA (includesloadcurrent) IDDRZ Deserializer(Rx) RPWDNB = 0V SupplyCurrentPower-down (AllotherLVCMOS Inputs= 0V, 1 50 µA R IN+/R IN-= 0V) (5) Digital,PLL,and AnalogVDDs (6) Figure1,Figure2,Figure8,Figure12,Figure14 show a fallingedge datastrobe(TCLK IN/RCLK OUT). SerializerTiming Requirements forTCLK Over recommended operatingsupplyand temperaturerangesunlessotherwisespecified. Symbol Parameter Conditions Min Typ Max Units tTCP TransmitClockPeriod Figure5(1) 25 T 333 ns tTCIH TransmitClockHighTime 0.4T 0.5T 0.6T ns tTCIL TransmitClockLow Time 0.4T 0.5T 0.6T ns tCLKT TCLK InputTransitionTime Figure4 3 6 ns tJIT TCLK InputJitter See (2) ps33 (RMS) (1) Figure5,Figure15 show a risingedge datastrobe(TCLK IN/RCLK OUT). (2) tJIT(@BER of10e-9)specifiestheallowablejitteron TCLK. tJITnotincludedinTxOUT_E_O parameter.

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DS99R101,DS99R102 www.ti.com SNLS240D –MARCH 2007–REVISED APRIL 2013 SerializerSwitchingCharacteristics Over recommended operatingsupplyand temperaturerangesunlessotherwisespecified. Symbol Parameter Conditions Min Typ Max Units tLLHT LVDS Low-to-HighTransitionTime R L = 100Ω,(Figure3) 0.6 ns C L = 10 pF toGNDtLHLT LVDS High-to-LowTransitionTime 0.6 nsVODSEL = L tDIS DIN (23:0)SetuptoTCLK R L = 100Ω, 5 ns C L = 10 pF toGND (1) tDIH DIN (23:0)HoldfromTCLK 5 ns tHZD DOUT ± HIGH toTRI-STATE Delay R L = 100Ω, 15 ns C L = 10 pF toGNDtLZD DOUT ± LOW toTRI-STATE Delay 15 ns(Figure6)(2) tZHD DOUT ± TRI-STATE toHIGH Delay 200 ns tZLD DOUT ± TRI-STATE toLOW Delay 200 ns tPLD SerializerPLL Lock Time R L = 100Ω,(Figure7) 10 ms tSD SerializerDelay R L = 100Ω,(Figure8)(3) 3.5T3.5T+ 2.85 nsVODSEL = L,TRFB = H + 10 R L = 100Ω,(Figure8)(3) 3.5T3.5T+ 2.85 nsVODSEL = L,TRFB = L + 10 TxOUT_E_O TxOUT_Eye_Opening 3–40 MHz 0.68 UI(5) (respecttoideal) (Figure9)(4) (1) Specificationisguaranteedby characterizationand isnottestedinproduction. (2) When theSerializeroutputisatTRI-STATE, theDeserializerwilllosePLL lock.ResynchronizationMUST occurbeforedatatransfer. (3) Figure1,Figure2,Figure8,Figure12,Figure14 show a fallingedge datastrobe(TCLK IN/RCLK OUT). (4) tJIT(@BER of10e-9)specifiestheallowablejitteron TCLK. tJITnotincludedinTxOUT_E_O parameter. (5) UI – UnitInterval,equivalenttoone idealserializeddatabitwidth.The UI scaleswithfrequency. DeserializerSwitchingCharacteristics Over recommended operatingsupplyand temperaturerangesunlessotherwisespecified. Symbol Parameter Conditions Pin/Freq. Min Typ Max Units tRCP R eceiveroutC lockPeriod tRCP = tTCP (1) RCLK 25 T 333 ns tRDC R CLK D utyC ycle RCLK 45 50 55 % tCLH LVC MOS Low-to-H igh C L = 8 pF ROUT [23:0], 2.5 3.5 nsTransitionTime (lumpedload) LOCK, RCLK (Figure11)tCHL LVC MOS H igh-to-Low 2.5 3.5 nsTransitionTime tROS RO UT (7:0)SetupData to (Figure15)(2) ROUT [7:0] (0.40)* (29/56)*tRCP nsRCLK (Group1) tRCP tROH RO UT (7:0)H oldData toRCLK (0.40)* (27/56)*tRCP ns(Group1) tRCP tROS RO UT (15:8)SetupData to (Figure15)(2) ROUT [15:8], (0.40)* 0.5*tRCP nsRCLK (Group2) LOCK tRCP tROH RO UT (15:8)H oldData to (0.40)* 0.5*tRCP nsRCLK (Group2) tRCP tROS RO UT (23:16)SetupData to (Figure15)(2) ROUT [23:16] (0.40)* (27/56)*tRCP nsRCLK (Group3) tRCP tROH RO UT (23:16)H oldData to (0.40)* (29/56)*tRCP nsRCLK (Group3) tRCP tHZR H IGH toTRI-STATE Delay (Figure13) ROUT [23:0], 3 10 ns RCLK, LOCKtLZR LOW toTRI-STATE Delay 3 10 ns tZHR TRI-STATE toH IGH Delay 3 10 ns tZLR TRI-STATE toLOW Delay 3 10 ns tDD D eserializerD elay (Figure12)(3) RCLK [4+(3/56)]T [4+(3/56)]T ns +5.9 +18.5 (1) Specificationisguaranteedby characterizationand isnottestedinproduction. (2) Figure5,Figure15 show a risingedge datastrobe(TCLK IN/RCLK OUT). (3) Figure1,Figure2,Figure8,Figure12,Figure14 show a fallingedge datastrobe(TCLK IN/RCLK OUT). Copyright© 2007–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:DS99R101 DS99R102

80% 20% 80% 20% Vdiff = 0V tLLHT tLHLT Differential Signal Vdiff = (DOUT+) - (DOUT-) 100: DOUT+ DOUT- 10 pF 10 pF RCLK ODD ROUT EVEN ROUT Signal PatternDevice Pin Name TCLK ODD DIN EVEN DIN Signal PatternDevice Pin Name DS99R101,DS99R102 SNLS240D –MARCH 2007–REVISED APRIL 2013 www.ti.com DeserializerSwitchingCharacteristics(continued) Over recommended operatingsupplyand temperaturerangesunlessotherwisespecified. Symbol Parameter Conditions Pin/Freq. Min Typ Max Units tDRDL DeserializerPLL Lock Time (Figure14) (3) 3 MHz 5 50 ms fromPowerdown (4) (5)(1)

40 MHz 5 50 ms

RxIN_TOL_L R eceiverINputTOL erance (Figure16) 3 MHz –40 MHz 0.25 UILeft (6)(1)(7) RxIN_TOL_R R eceiverINputTOL erance (Figure16) 3 MHz –40 MHz 0.25 UIR ight (6)(1)(7) (4) tDRDL isthetimerequiredby thedeserializertoobtainlockwhen exitingpowerdown mode. tDRDL isspecifiedwithan external synchronizationpattern. (5) The DeserializerPLL locktime(tDRDL )may varydependingon inputdatapatternsand thenumber oftransitionswithinthepattern. (6) RxIN_TOL isa measure ofhow much phase noise(jitter)thedeserializercan tolerateintheincomingdatastreambeforebiterrors occur.Itisa measurement inreferencewiththeidealbitposition,pleasesee AN-1217 (SNLA053 )fordetail. (7) UI – UnitInterval,equivalenttoone idealserializeddatabitwidth.The UI scaleswithfrequency. AC Timing Diagrams and TestCircuits Figure1. SerializerInputChecker-boardPattern Figure2. DeserializerOutput Checker-boardPattern Figure3. SerializerLVDS Output Load and TransitionTimes

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100: Parasitic package and Trace capcitance 200 mV DCA DCA DCA DCA $OOGDWD³0´V CLK1 tZLD tTCP DCADCADCADCA CLK1 tTCP 200 mV DEN (single-ended) 200 mV DCA DCA DCA DCA $OOGDWD³1´V CLK0 tZHD tTCP DCADCADCADCA CLK0 tTCP 200 mV DOUT± (differential) VCC /2 DOUT± (differential) VCC /2 tHZD DEN (single-ended) VCC /2 0V 0V VCC /2 tLZD SetupVDD /2 Hold tDIHtDIS TCLK DIN [0:23] tTCP VDD /2 VDD /2 V DD /2VDD /2 VDD 80% 20% 80% 20% tCLKT tCLK TCLK VDD DS99R101,DS99R102 www.ti.com SNLS240D –MARCH 2007–REVISED APRIL 2013 Figure4. SerializerInputClock TransitionTimes Figure5. SerializerSetup/HoldTimes Figure6. SerializerTRI-STATE TestCircuitand Delay Copyright© 2007–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:DS99R101 DS99R102

Ideal Center Position (tBIT/2) tBIT (1UI) TxOUT_E_O Ideal Data Bit End Ideal Data Bit Beginning tBIT(1/2UI) tBIT(1/2UI) 232 1 0 START BIT STOP BITSYMBOL N 232 1 0 START BIT STOP BITSYMBOL N-1 232 1 0 START BIT STOP BITSYMBOL N-2 232 1 0 START BIT STOP BITSYMBOL N-3 232 1 0 STOP BITSYMBOL N-4 DOUT0-23 DCA, DCB TCLK tSD DIN SYMBOL N+1SYMBOL N SYMBOL N+2 SYMBOL N+3 | | 2.0V 0.8V TCLK DOUT± tHZD or tLZD tZHD or tZLD Output Active tPLD PWDWN TRI-STATE TRI-STATE DS99R101,DS99R102 SNLS240D –MARCH 2007–REVISED APRIL 2013 www.ti.com Figure7. SerializerPLL Lock Time,and TPWDNB TRI-STATE Delays Figure8. SerializerDelay Figure9. TransmitterOutput Eye Opening (TxOUT_E_O)

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DCA, DCB RCLK tDD ROUT0-23 SYMBOL N-1 SYMBOL NSYMBOL N-2SYMBOL N-3 80% 20% 80% 20% tCLH Deserializer 8 pF lumped Single-ended Signal tCHL PARALLEL-TO-SERIAL DOUT+ DOUT- DIN R L TCLK DS99R101,DS99R102 www.ti.com SNLS240D –MARCH 2007–REVISED APRIL 2013 VOD = (DOUT+ )– (DOUT -) Differentialoutputsignalisshown as (DOUT+ )– (DOUT -),deviceinData Transfermode. Figure10. SerializerVOD Diagram Figure11. DeserializerLVCMOS/LVTTL Output Load and TransitionTimes Figure12. DeserializerDelay Copyright© 2007–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:DS99R101 DS99R102

RIN± TRI-STATE TRI-STATE TRI-STATE TRI-STATE TRI-STATE ROUT [0:23] RCLK TRI-STATELOCK }v[šŒ tHZR or tLZR tDRDL REN PWDN 2.0V 0.8V VOH REN VOL + 0.5V VOL ROUT [23:0] VOL + 0.5V tLZR 500: VREF = VDD /2 for tZLR or tLZR , VOH - 0.5V VOH + 0.5V tZLR tHZR tZHR VDD /2 VDD /2 VOH VOL REN VREF + - VREF = 0V for tZHR or tHZRC L = 8pF DS99R101,DS99R102 SNLS240D –MARCH 2007–REVISED APRIL 2013 www.ti.com Note:C L includesinstrumentationand fixturecapacitancewithin6 cm ofROUT[23:0] Figure13. DeserializerTRI-STATE TestCircuitand Timing Figure14. DeserializerPLL Lock Times and RPWDNB TRI-STATE Delay

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(1UI) Sampling Window Ideal Data Bit End Ideal Data Bit Beginning RxIN_TOL -L tBIT ( ) RxIN_TOL -R Data Valid Before RCLK Data Valid After RCLKROUT [7:0] Data Valid Before RCLK Data Valid After RCLKROUT [15:8], LOCK Data Valid Before RCLK Data Valid After RCLK VDD /2ROUT [23:16] RCLK tLOW tHIGH tROS tROH tROS tROH (group 1) (group 1) (group 2) (group 2) 1/2 UI 1/2 UI tROS tROH (group 3) (group 3) 1/2 UI 1/2 UI VDD /2 VDD /2VDD /2 VDD /2VDD /2 VDD /2VDD /2 DS99R101,DS99R102 www.ti.com SNLS240D –MARCH 2007–REVISED APRIL 2013 Figure15. DeserializerSetup and Hold Times RxIN_TOL_L istheidealnoisemarginon theleftofthefigure,withrespecttoideal. RxIN_TOL_R istheidealnoisemarginon therightofthefigure,withrespecttoideal. Figure16. ReceiverInputTolerance(RxIN_TOL) and Sampling Window Copyright© 2007–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:DS99R101 DS99R102

DS99R101,DS99R102 SNLS240D –MARCH 2007–REVISED APRIL 2013 www.ti.com DS99R101 SerializerPin Descriptions Pin # Pin Name I/O Description LVCMOS PARALLEL INTERFACE PINS 4-1, DIN[23:0] LVCMOS_I TransmitterParallelInterfaceData InputsPins.TieLOW ifunused,do notfloat. 48-44, 41-32, 29-25 10 TCLK LVCMOS_I TransmitterParallelInterfaceClockInputPin.Strobeedge setby TRFB configurationpin. CONTROL AND CONFIGURATION PINS

9 TPWDNB LVCMOS_I TransmitterPower Down Bar

TPWDNB = H; TransmitterisEnabledand ON TPWDNB = L;Transmitterisinpower down mode (Sleep),LVDS DriverDOUT (+/-)Outputsare inTRI-STATE stand-bymode, PLL isshutdowntominimizepower consumption.

18 DEN LVCMOS_I TransmitterData Enable

DEN = H; LVDS DriverOutputsareEnabled(ON). DEN = L;LVDS DriverOutputsareDisabled(OFF),TransmitterLVDS DriverDOUT (+/-)Outputs areinTRI-STATE, PLL stilloperationaland lockedtoTCLK.

11 TRFB LVCMOS_I TransmitterR ising/FallingB ar

TRFB = H; DIN LVCMOS Inputclockedon RisingTCLK TRFB = L;DIN LVCMOS Inputclockedon FallingTCLK

12 VODSEL LVCMOS_I VOD LevelSelect

VODSEL = L;LVDS DriverOutputis≈±400 mV (RL = 100Ω) VODSEL = H; LVDS DriverOutputis≈±750 mV (RL = 100Ω) 5 DCAOFF LVCMOS_I RESERVED – ThispinMUST be tiedLOW. 8 DCBOFF LVCMOS_I RESERVED – ThispinMUST be tiedLOW. 13 RESRVD LVCMOS_I RESERVED – ThispinMUST be tiedLOW.

23 NC NC No Connect– Make NO connection– leaveopen

LVDS SERIAL INTERFACE PINS 20 DOUT+ LVDS_O TransmitterLVDS True(+)Output.Thisoutputisintendedtobe loadedwitha 100 ohm loadto theDOUT+ pin.The interconnectshouldbe AC Coupledtothispinwitha 100 nF capacitor.

19 DOUT − LVDS_O TransmitterLVDS Inverted(-)OutputThisoutputisintendedtobe loadedwitha 100 ohm loadto

theDOUT- pin.The interconnectshouldbe AC Coupledtothispinwitha 100 nF capacitor. POWER /GROUND PINS

22 VDDDR VDD AnalogVoltageSupply,LVDS OutputPower

21 VSSDR GND AnalogGround,LVDS OutputGround

16 VDDPT0 VDD AnalogVoltagesupply,VCO Power

17 VSSPT0 GND AnalogGround,VCO Ground

14 VDDPT1 VDD AnalogVoltagesupply,PLL Power

15 VSSPT1 GND AnalogGround,PLL Ground

30 VDDT VDD DigitalVoltagesupply,Tx SerializerPower

31 VSST GND DigitalGround,Tx SerializerGround

7 VDDL VDD DigitalVoltagesupply,Tx LogicPower

6 VSSL GND DigitalGround,Tx LogicGround

42 VDDIT VDD DigitalVoltagesupply,Tx InputPower

43 VSSIT GND DigitalGround,Tx InputGround

24 VSS GND ESD Ground

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48DIN[19] 47DIN[18] 46DIN[17] 45DIN[16] 44DIN[15] 43VSS IT 42VDD IT 41DIN[14] 40DIN[13] 39DIN[12] 38DIN[11] 37DIN[10] RESRVD VDD PT1 VSS PT1 VDD PT0 VSS PT0 DEN DOUT- DOUT+ VSS DR VDD DR NC VSS 12VODSEL 11TRFB 10TCLK 9TPWDNB 8DCBOFF 7VDD L 6VSS L 5DCAOFF 4DIN[23] 3DIN[22] 2DIN[21] 1DIN[20] DIN[0] DIN[1] DIN[2] DIN[3] DIN[4] VDD T VSS T DIN[5] DIN[6] DIN[7] DIN[8] DIN[9] DS99R101

48 PIN TQFP

DS99R101,DS99R102 www.ti.com SNLS240D –MARCH 2007–REVISED APRIL 2013 DS99R101 Pin Diagram Figure17. Serializer-DS99R101 TOP VIEW DS99R102 DeserializerPin Descriptions Pin # Pin Name I/O Description LVCMOS PARALLEL INTERFACE PINS 25-28, ROUT[7:0] LVCMOS_O ReceiverParallelInterfaceData Outputs– Group 1 31-34 13-16, ROUT[15:8] LVCMOS_O ReceiverParallelInterfaceData Outputs– Group 2 21-24 3-6,9- ROUT[23:16] LVCMOS_O ReceiverParallelInterfaceData Outputs– Group 3 18 RCLK LVCMOS_O ParallelInterfaceClockOutputPin.Strobeedge setby RRFB configurationpin. CONTROL AND CONFIGURATION PINS

43 RRFB LVCMOS_I ReceiverClockEdge SelectPin

RRFB = H; ROUT LVCMOS Outputsstrobedon theRisingClockEdge. RRFB = L;ROUT LVCMOS Outputsstrobedon theFallingClockEdge.

48 REN LVCMOS_I ReceiverData Enable

REN = H; ROUT[23-0]and RCLK areEnabled(ON). REN = L;ROUT[23-0]and RCLK areDisabled(OFF),ReceiverROUT[23-0]and RCLK Outputs areinTRI-STATE, PLL stilloperationaland lockedtoTCLK.

1 RPWDNB LVCMOS_I ReceiverData Enable

REN = H; ROUT[23-0]and RCLK areEnabled(ON). REN = L;ROUT[23-0]and RCLK areDisabled(OFF),ReceiverROUT[23-0]and RCLK Outputs areinTRI-STATE, PLL stilloperationaland lockedtoTCLK.

17 LOCK LVCMOS_O LOCK indicatesthestatusofthereceiverPLL

LOCK = H; receiverPLL islocked LOCK = L;receiverPLL isunlocked,ROUT[23-0]and RCLK areTRI-STATED 2 RESRVD LVCMOS_I RES ERV ED – ThispinMUST be tiedLOW. Copyright© 2007–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:DS99R101 DS99R102

DS99R101,DS99R102 SNLS240D –MARCH 2007–REVISED APRIL 2013 www.ti.com DS99R102 DeserializerPin Descriptions(continued) Pin # Pin Name I/O Description LVDS SERIAL INTERFACE PINS

41 RIN+ LVDS_I ReceiverLVDS True(+)InputThisinputisintendedtobe terminatedwitha 100 ohm loadtothe

RIN+ pin.The interconnectshouldbe AC Coupledtothispinwitha 100 nF capacitor.

42 RIN− LVDS_I ReceiverLVDS Inverted(−)InputThisinputisintendedtobe terminatedwitha 100 ohm loadto

theRIN-pin.The interconnectshouldbe AC Coupledtothispinwitha 100 nF capacitor. POWER /GROUND PINS

39 VDDIR VDD AnalogLVDS Voltagesupply,Power

40 VSSIR GND AnalogLVDS G round

47 VDDPR0 VDD AnalogVoltagesupply,PLL Power

46 VSSPR0 GND AnalogGround,PLL Ground

45 VDDPR1 VDD AnalogVoltagesupply,PLL VCO Power

44 VSSPR1 GND AnalogGround,PLL VCO Ground

37 VDDR1 VDD DigitalVoltagesupply,LogicPower

38 VSSR1 GND DigitalGround,LogicGround

36 VDDR0 VDD DigitalVoltagesupply,LogicPower

35 VSSR0 GND DigitalGround,LogicGround

30 VDDOR1 VDD DigitalVoltagesupply,LVCMOS OutputPower

29 VSSOR1 GND DigitalGround,LVCMOS OutputGround

20 VDDOR2 VDD DigitalVoltagesupply,LVCMOS OutputPower

19 VSSOR2 GND DigitalGround,LVCMOS OutputGround

7 VDDOR3 VDD DigitalVoltagesupply,LVCMOS OutputPower

8 VSSOR3 GND DigitalGround,LVCMOS OutputGround

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ROUT[15] ROUT[14] ROUT[13] ROUT[12] LOCK RCLK VSS OR2 VDD OR2 ROUT[11] ROUT[10] ROUT[9] ROUT[8] 12ROUT[16] 11ROUT[17] 10ROUT[18] 9ROUT[19] 8VSS OR3 7VDD OR3 6ROUT[20] 5ROUT[21] 4ROUT[22] 3ROUT[23] 2RESRVD 1RPWDNB ROUT[7] ROUT[6] ROUT[5] ROUT[4] VSS OR1 VDD OR1 ROUT[3] ROUT[2] ROUT[1] ROUT[0] VSS R0 VDD R0 DS99R102 DS99R101,DS99R102 www.ti.com SNLS240D –MARCH 2007–REVISED APRIL 2013 DS99R102 Pin Diagram Figure18. Deserializer-DS99R102 TOP VIEW Copyright© 2007–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:DS99R101 DS99R102

DS99R101,DS99R102 SNLS240D –MARCH 2007–REVISED APRIL 2013 www.ti.com FUNCTIONAL DESCRIPTION The DS99R101 Serializerand DS99R102 Deserializerchipsetisan easy-to-usetransmitterand receiverpairthat sends 24-bitsofparallelLVCMOS dataovera singleserialLVDS linkfrom 72 Mbps to960 Mbps throughput. The DS99R101 transformsa 24-bitwideparallelLVCMOS dataintoa singlehighspeed LVDS serialdatastream withembedded clock.The DS99R102 receivestheLVDS serialdatastreamand convertsitback intoa 24-bit wide paralleldata and recoveredclock.The 24-bitSerializer/Deserializerchipsetisdesignedto transmitdata overshieldedtwistedpair(STP)atclockspeeds from3 MHz to40 MHz. The Deserializercan attainlockto a data stream withoutthe use of a separatereferenceclocksource.The DeserializersynchronizestotheSerializerregardlessofdatapattern,deliveringtrueautomatic“plugand lock” performance.The Deserializerrecoversthe clockand data by extractingthe embedded clockinformationand validatingdataintegrityfromtheincomingdatastreamand thendeserializesthedata.The Deserializermonitors the incomingclockinformation,determineslockstatus,and assertsthe LOCK outputhighwhen lockoccurs. Each has a power down controltoenableefficientoperationinvariousapplications. INITIALIZATIONAND LOCKING MECHANISM InitializationoftheDS99R101 and DS99R102 must be establishedbeforeeach devicesends or receivesdata. InitializationreferstosynchronizingtheSerializer’s and Deserializer’s PLL’s together.AftertheSerializerslocks totheinputclocksource,theDeserializersynchronizestotheSerializersas thesecond and finalinitialization step. Step 1:When VDD isappliedtobothSerializerand/orDeserializer,therespectiveoutputsareheldinTRI-STATE and internalcircuitryisdisabledby on-chippower-on circuitry.When VDD reachesVDD OK (2.2V)the PLL in Serializerbeginslockingto a clockinput.For the Serializer,the localclockisthe transmitclock,TCLK. The SerializeroutputsareheldinTRI-STATE whilethePLL lockstotheTCLK. AfterlockingtoTCLK, theSerializer blockisnow readytosend datapatterns.The DeserializeroutputwillremaininTRI-STATE whileitsPLL locksto theembedded clockinformationinserialdatastream.Also,theDeserializerLOCK outputwillremainlow untilits PLL lockstoincomingdataand sync-patternon theRIN± pins. Step 2: The DeserializerPLL acquireslockto a data stream withoutrequiringthe Serializerto send special patterns.The Serializerthatisgeneratingthe stream to the Deserializerwillautomaticallysend random (non- repetitive)datapatternsduringthisstepoftheInitializationState.The Deserializerwilllockontoembedded clock withinthespecifiedamount oftime.An embedded clockand datarecovery(CDR) circuitlockstotheincomingbit streamtorecoverthehigh-speedreceivebitclockand re-timeincomingdata.The CDR circuitexpectsa coded inputbitstream.InorderfortheDeserializertolocktoa random datastreamfrom theSerializer,itperformsa seriesofoperationstoidentifytherisingclockedge and validatesdataintegrity,thenlockstoit.Because this lockingprocedureisindependenton thedatapattern,totalrandom lockingdurationmay vary.At thepointwhen theDeserializer’s CDR lockstotheembedded clock,theLOCK pingoes highand validRCLK/data appearson theoutputs.Note thattheLOCK signalissynchronoustovaliddataappearingon theoutputs.The Deserializer’s LOCK pinisa convenientway toensuredataintegrityisachievedon receiverside. DATA TRANSFER Afterlockisestablished,the SerializerinputsDIN0–DIN23 are used to inputdata to the Serializer.Data is clockedintotheSerializerby theTCLK input.The edge ofTCLK used tostrobethedataisselectableviathe TRFB pin.TRFB highselectstherisingedge forclockingdataand low selectsthefallingedge.The Serializer outputs(DOUT ±)areintendedtodrivepoint-to-pointconnectionsorlimitedmulti-pointapplications. CLK1, CLK0, DCA, DCB arefouroverheadbitstransmittedalongthesingleLVDS serialdatastream.The CLK1 bitisalwayshighand theCLK0 bitisalwayslow.The CLK1 and CLK0 bitsfunctionas theembedded clockbits intheserialstream.DCB functionsas theDC Balancecontrolbit.Itdoes notrequireany pre-codingofdataon transmitside.The DC Balancebitisused tominimizetheshortand long-termDC biason thesignallines.This bitoperatesby selectivelysendingthedataeitherunmodifiedor inverted.The DCA bitisused tovalidatedata integrityinthe embedded data stream.Both DCA and DCB codingschemes are integratedand automatically performedwithinSerializerand Deserializer. The chipsetsupportsclockfrequencyrangesof3 MHz to40 MHz. Everyclockcycle,24 databitsaresentalong with4 additionaloverheadcontrolbits.Thus thelinerateis1.12Gbps maximum (84Mbps minimum).The linkis extremelyefficientat86% (24/28).Twenty five(24data+ 1 clock)plusassociatedgroundsignalsarereducedto only1 singleLVDS pairprovidinga compressionratioofbetterthen25 to1.

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DS99R101,DS99R102 www.ti.com SNLS240D –MARCH 2007–REVISED APRIL 2013 Serializeddataand clock/controlbits(24+4bits)aretransmittedfromtheserialdataoutput(DOUT ±)at28 times theTCLK frequency.For example,ifTCLK is,theserialrateis40 x 28 = 1.12Giga bitspersecond.Sinceonly 24 bitsarefrominputdata,theserial“payload”rateis24 timestheTCLK frequency.For instance,ifTCLK = 40 MHz, thepayloaddatarateis40 x 24 = 960 Mbps. TCLK isprovidedby thedatasourceand must be inthe range of 3 MHz to 40 MHz nominal.The Serializeroutputs(DOUT ±) can drivea point-to-pointconnectionas shown inFigure19.The outputstransmitdatawhen theenablepin(DEN) ishighand TPWDNB ishigh.The DEN pinmay be used toTRI-STATE theoutputswhen drivenlow. When the Deserializerchannel attainslockto the inputfrom a Serializer,itdrivesitsLOCK pin high and synchronouslydeliversvaliddataand recoveredclockon theoutput.The Deserializerlocksontotheembedded clock,uses ittogeneratemultipleinternaldatastrobes,and thendrivestherecoveredclocktotheRCLK pin. The recoveredclock(RCLK outputpin)issynchronoustothedataon theROUT[23:0]pins.WhileLOCK ishigh, dataon ROUT[23:0]isvalid.Otherwise,ROUT[23:0]isinvalid.The polarityoftheRCLK edge iscontrolledby the RRFB input.ROUT(0-23),LOCK and RCLK outputswilleach drivea maximum of8 pF loadwitha 40 MHz clock. REN controlsTRI-STATE forROUTn and theRCLK pinon theDeserializer. RESYNCHRONIZATION Ifthe Deserializerloseslock,itwillautomaticallytryto re-establishlock.For example,ifthe embedded clock edge isnotdetectedone timeinsuccession,thePLL loseslockand theLOCK pinisdrivenlow.The Deserializer thenenterstheoperatingmode where ittriestolocktoa random datastream.Itlooksfortheembedded clock edge,identifiesitand thenproceedsthroughthelockingprocess. The logicstateoftheLOCK signalindicateswhetherthedataon ROUT isvalid;when itishigh,thedataisvalid. The systemmust monitortheLOCK pintodeterminewhetherdataon theROUT isvalid. POWERDOWN The Powerdown stateisa low power sleepmode thattheSerializerand Deserializermay use toreducepower when no dataisbeingtransferred.The TPWDNB and RPWDNB are used toseteach deviceintopower down mode, whichreducessupplycurrenttotheµA range.The Serializerenterspowerdown when theTPWDNB pinis drivenlow.Inpowerdown,thePLL stopsand theoutputsgo intoTRI-STATE, disablingloadcurrentand reducing supply.To exitPowerdown, TPWDNB must be drivenhigh.When theSerializerexitsPowerdown, itsPLL must locktoTCLK beforeitisreadyfortheInitializationstate.The system must thenallowtimeforInitializationbefore datatransfercan begin.The Deserializerenterspowerdown mode when RPWDNB isdrivenlow.Inpowerdown mode, thePLL stopsand theoutputsenterTRI-STATE. To bringtheDeserializerblockoutofthepowerdown state,thesystemdrivesRPWDNB high. Both theSerializerand Deserializermust reinitializeand relockbeforedatacan be transferred.The Deserializer willinitializeand assertLOCK highwhen itislockedtotheencoded clock. TRI-STATE For theSerializer,TRI-STATE isenteredwhen theDEN orTPWDNB pinisdrivenlow.ThiswillTRI-STATE both driveroutputpins(DOUT+ and DOUT −).When DEN isdrivenhigh,theserializerwillreturntothepreviousstate as longas allothercontrolpinsremainstatic(TPWDNB, TRFB). When you drivetheREN or RPWDNB pinlow,theDeserializerentersTRI-STATE. Consequently,thereceiver outputpins(ROUT0 –ROUT23) and RCLK willenterTRI-STATE. The LOCK outputremainsactive,reflectingthe stateofthePLL. The Deserializerinputpinsarehighimpedance duringreceiverpowerdown (RPWDNB low)and power-off(VDD = 0V). AC-COUPLING AND TERMINATION The DS99R101 and DS99R102 supports AC-coupled interconnectsthrough integratedDC balanced encoding/decodingscheme. To use AC coupled connectionbetween the Serializerand Deserializer,insert externalAC couplingcapacitorsinseriesintheLVDS signalpathas illustratedin.The Deserializerinputstage isdesignedforAC-couplingby providinga built-inAC biasnetworkwhichsetstheinternalVCM to+1.2V.WithAC signalcoupling,capacitorsprovidetheac-couplingpathtothesignalinput. For the high-speedLVDS transmissions,the smallestavailablepackage shouldbe used forthe AC coupling capacitor.Thiswillhelpminimizedegradationof signalqualitydue to package parasitics.The most common used capacitorvaluefortheinterfaceis100 nF (0.1uF)capacitor. Copyright© 2007–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:DS99R101 DS99R102

DS99R101,DS99R102 SNLS240D –MARCH 2007–REVISED APRIL 2013 www.ti.com A terminationresistoracross DOUT ± is also requiredforproperoperationto be obtained.The termination resistorshouldbe equaltothedifferentialimpedance ofthemedia beingdriven.Thisshouldbe intherangeof 90 to132 Ohms. 100 Ohms isa typicalvaluecommon used withstandard100 Ohm transmissionmedia.This resistorisrequiredforcontrolofreflectionsand alsotocompletethecurrentloop.Itshouldbe placedas closeto theSerializerDOUT ± outputstominimizethestublengthfromthepins.To match withthedeferentialimpedance on thetransmissionline,theLVDS I/Oareterminatedwith100 ohm resistorson SerializerDOUT ± outputspins. PROGRESSIVE TURN –ON (PTO) DeserializerROUT[23:0] outputsare grouped intothreegroupsofeight,witheach group switchingabout0.5UI apartinphase toreduceEMI,simultaneousswitchingnoise,and systemgroundbounce.

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DS99R101,DS99R102 www.ti.com SNLS240D –MARCH 2007–REVISED APRIL 2013 APPLICATIONS INFORMATION USING THE DS99R101 AND DS99R102 The DS99R101/DS99R102 Serializer/Deserializer(SERDES) pairsends 24 bitsofparallelLVCMOS dataovera serialLVDS linkup to960 Mbps. Serializationoftheinputdataisaccomplishedusingan on-boardPLL atthe Serializerwhich embeds clockwiththe data.The Deserializerextractsthe clock/controlinformationfrom the incomingdata stream and deserializesthe data.The Deserializermonitorsthe incomingclocklinformationto determinelockstatusand willindicatelockby assertingtheLOCK outputhigh. POWER CONSIDERATIONS An allCMOS designoftheSerializerand Deserializermakes them inherentlylow power devices.Additionally, theconstantcurrentsourcenatureoftheLVDS outputsminimizetheslopeofthespeed vs.IDD curveofCMOS designs. NOISE MARGIN The Deserializernoisemarginistheamount ofinputjitter(phasenoise)thattheDeserializercan tolerateand still reliablyrecoverdata.Variousenvironmentaland systematicfactorsinclude: Serializer:TCLK jitter,VDD noise(noisebandwidthand out-of-bandnoise) Media:ISI,VCM noise Deserializer:VDD noise Fora graphicalrepresentationofnoisemargin,pleasesee Figure16. TRANSMISSION MEDIA The Serializerand Deserializercan be used in point-to-pointconfiguration,througha PCB trace,or through twistedpaircable.Ina point-to-pointconfiguration,thetransmissionmedia needs be terminatedatbothends of thetransmitterand receiverpair.InterconnectforLVDS typicallyhas a differentialimpedance of100 Ohms. Use cablesand connectorsthathave matched differentialimpedance tominimizeimpedance discontinuities.Inmost applicationsthatinvolvecables,thetransmissiondistancewillbe determinedon dataratesinvolved,acceptable biterrorrateand transmissionmedium. LIVE LINK INSERTION The Serializerand Deserializerdevicessupportlivepluggableapplications.The “Hot Inserted” operationon the serialinterfacedoes not disruptcommunicationdata on the activedata lines.The automaticreceiverlockto random data“plug& go” liveinsertioncapabilityallowstheDS99R102 toattainlocktotheactivedatastream duringa liveinsertionevent. PCB LAYOUT AND POWER SYSTEM CONSIDERATIONS Circuitboardlayoutand stack-upfortheLVDS SERDES devicesshouldbe designedtoprovidelow-noisepower feed to the device.Good layoutpracticewillalsoseparatehighfrequencyor high-levelinputsand outputsto minimizeunwanted straynoisepickup,feedbackand interference.Power system performancemay be greatly improvedby usingthindielectrics(2to4 mils)forpower /groundsandwiches.Thisarrangementprovidesplane capacitanceforthePCB power system withlow-inductanceparasitics,which has provenespeciallyeffectiveat highfrequencies,and makes thevalueand placementofexternalbypasscapacitorslesscritical.Externalbypass capacitorsshouldincludebothRF ceramicand tantalumelectrolytictypes.RF capacitorsmay use valuesinthe tantalumcapacitorsshouldbe atleast5X thepower supplyvoltagebeingused. Surfacemount capacitorsarerecommended due totheirsmallerparasitics.When usingmultiplecapacitorsper supplypin,locatethesmallervalueclosertothepin.A largebulkcapacitorisrecommend atthepointofpower entry.This is typicallyin the 50uF to 100uF range and willsmooth low frequencyswitchingnoise.Itis recommended toconnectpower and groundpinsdirectlytothepower and groundplaneswithbypass capacitors connectedtotheplanewithviaon bothends ofthecapacitor.Connectingpower or ground pinstoan external bypasscapacitorwillincreasetheinductanceofthepath. Copyright© 2007–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLinks:DS99R101 DS99R102

100: 100 nF 100 nF 100: 100 nF 100 nF DOUT- DOUT+ RIN- RIN+ DS99R101,DS99R102 SNLS240D –MARCH 2007–REVISED APRIL 2013 www.ti.com A smallbody sizeX7R chipcapacitor,such as 0603,isrecommended forexternalbypass.Itssmallbody size reducesthe parasiticinductanceof the capacitor.The user must pay attentionto the resonancefrequencyof these externalbypass capacitors,usuallyin the range of 20-30 MHz range.To provideeffectivebypassing, multiplecapacitorsare oftenused to achievelow impedance between the supplyrailsover the frequencyof interest.At highfrequency,itisalsoa common practiceto use two viasfrom power and ground pinsto the planes,reducingtheimpedance athighfrequency. Some devicesprovideseparatepower and groundpinsfordifferentportionsofthecircuit.Thisisdone toisolate switchingnoiseeffectsbetween differentsectionsof the circuit.Separateplaneson the PCB are typicallynot required.PinDescriptiontablestypicallyprovideguidanceon whichcircuitblocksareconnectedtowhichpower pinpairs.Insome cases,an externalfiltermany be used toprovidecleanpower tosensitivecircuitssuch as PLLs. Use atleasta fourlayerboardwitha power and groundplane.LocateLVCMOS (LVTTL)signalsaway fromthe LVDS linestopreventcouplingfrom theLVCMOS linestotheLVDS lines.Closely-coupleddifferentiallinesof 100 Ohms are typicallyrecommended forLVDS interconnect.The closelycoupledlineshelp to ensure that couplednoisewillappear as common-mode and thusisrejectedby thereceivers.The tightlycoupledlineswill alsoradiateless. TerminationoftheLVDS interconnectisrequired.Forpoint-to-pointapplications,terminationshouldbe locatedat both ends of the devices.Nominal valueis100 Ohms to match the line’s differentialimpedance.Place the resistoras closetothetransmitterDOUT ± outputsand receiverRIN± inputsas possibletominimizetheresulting stubbetween theterminationresistorand device. LVDS INTERCONNECT GUIDELINES See AN-1108 (SNLA008 )and AN-905 (SNLA035 )forfulldetails.

• Use 100Ω coupleddifferentialpairs
• Use theS/2S/3Sruleinspacings – S = space between thepair – 2S = space between pairs – 3S = space toLVCMOS/LVTTL signal
• Minimizethenumber ofVIA
• Use differentialconnectorswhen operatingabove 500Mbps linespeed
• Maintainbalanceofthetraces
• Minimizeskew withinthepair
• Terminateas closetotheTX outputsand RX inputsas possible Additionalgeneralguidancecan be foundintheLVDS Owner ’s Manual - availableinPDF formatfrom theTI web siteat:http://www.ti.com/ww/en/analog/interface/lvds.shtml Figure19. AC Coupled Application

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Notes: TPWDNB = System GPO DEN = High (ON) TRFB = High (Rising edge) VODSEL = Low (400mV) NC = No Connect RESRVD = Low DCAOFF = Low DCBOFF = Low GPO if used, or tie High (ON) 3.3V DS99R101 (SER) C1 C4 C2 C5 C3 C6 C1 to C3 = 0.01 PF C4 to C6 = 0.1 PF C7, C8 = 100 nF; 50WVDC, NPO or X7R R1 = 100: LVCMOS Parallel Interface Serial LVDS Interface DCAOFF VSS Open 3.3V DS99R101,DS99R102 www.ti.com SNLS240D –MARCH 2007–REVISED APRIL 2013 Figure20. DS99R101 TypicalApplicationConnection Copyright© 2007–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLinks:DS99R101 DS99R102

Notes: RPWDNB = System GPO REN = High (ON) RRFB = High (Rising edge) RESRVD = Low 3.3V DS99R102 (DES) C3 C7 C4 C8 C10 C5 C1 VDDIR VDDOR1 VSSPR0 VSSPR1 VSSR0 VSSR1 VSSIR VSSOR1 VSSOR2 VSSOR3 LOCK C2C6 C1 to C4 = 0.01 PF C5 to C8 = 0.1 PF C9, C10 = 100 nF; 50WVDC, NPO or X7R R1 = 100: Serial LVDS Interface LVCMOS Parallel Interface GPO if used, or tie High (ON) 3.3V 3.3V DS99R101,DS99R102 SNLS240D –MARCH 2007–REVISED APRIL 2013 www.ti.com Figure21. DS99R102 TypicalApplicationConnection TRUTH TABLES DS99R101 SerializerTruthTable TPWDNB DEN Tx PLL Status LVDS Outputs (Pin9) (Pin18) (Internal) (Pins19 and 20) L X X HiZ H L X HiZ H H Not Locked HiZ H H Locked SerializedData withEmbedded Clock DS99R102 DeserializerTruthTable RPWDNB REN Rx PLL Status ROUTn and RCLK LOCK (Pin1) (Pin48) (Internal) (See Pin Diagram) (Pin17) L X X HiZ HiZ H L X HiZ L = PLL Unocked; H = PLL Locked H H Not Locked HiZ L H H Locked Data and RCLK Active H

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REVISION HISTORY

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www.ti.com 7-Nov-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) DS99R101VS/NOPB Obsolete Production TQFP (PFB) | 48 - - Call TI Call TI 0 to 70 DS99R101 VS DS99R102VS/NOPB Obsolete Production TQFP (PFB) | 48 - - Call TI Call TI 0 to 70 DS99R102 VS (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

www.ti.com PACKAGE OUTLINE C 48X 0.27 0.1744X 0.5 PIN 1 ID (0.13) TYP

0.05 MIN0 -7

4X 5.5 9.2

8.8 TYP

0.75 0.45 B7.2 6.8 NOTE 3 A 7.2 6.8 NOTE 3 0.25 GAGE PLANE

1.2 MAX

(1) PLASTIC QUAD FLATPACK TQFP - 1.2 mm max heightPFB0048A PLASTIC QUAD FLATPACK 4215157/A 03/2024 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Reference JEDEC registration MS-026. 13 24 3748

0.08 C A B

0.08 A 16 DETAIL A TYPICAL SCALE 1.900

www.ti.com EXAMPLE BOARD LAYOUT

0.05 MAX

0.05 MIN

(8.5) (8.5) 44X (0.5) 48X (1.35) 48X (0.25) (R0.05) TYP TQFP - 1.2 mm max heightPFB0048A PLASTIC QUAD FLATPACK 4215157/A 03/2024 NOTES: (continued) 4. Publication IPC-7351 may have alternate designs. 5. Solder mask tolerances between and around signal pads can vary based on board fabrication site. LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SYMM SYMM 48 37 13 24 SEE DETAILS METAL SOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS EXPOSED METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL

www.ti.com EXAMPLE STENCIL DESIGN 44X (0.5) 48X (1.35) 48X (0.25) (R0.05) TYP (8.5) (8.5) TQFP - 1.2 mm max heightPFB0048A PLASTIC QUAD FLATPACK 4215157/A 03/2024 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 7. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE SCALE:8X SYMM SYMM 48 37 13 24

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