DS64BR111

Texas Instruments

Ultra Low Power 6.4 Gbps 2-Channel Repeaters with Input Equalization and Output De-Emphasis

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DS64BR111 Ultra Low Pwr 6.4 Gbps 2-Chan Repeatr w/Input Equal datasheet (Rev. C)

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Manufacturer or author: Texas Instruments, Incorporated [SNLS343,C]
PDF pages: 41

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www.ti.com SNLS343C –SEPTEMBER 2011–REVISED APRIL 2013 DS64BR111UltraLowPower6.4Gbps2-ChannelRepeaterswithInputEqualizationand OutputDe-Emphasis Check forSamples: DS64BR111 1FEATURES DESCRIPTION The DS64BR111 is an extremelylow power, high 2• Two Channel Repeaterforup to6.4Gbps performance dual-channelrepeaterfor seriallinks– DS64BR111 :1x BidirectionalLane with data ratesup to 6.4 Gbps. The DS64BR111

Low 65mW/Channel (Typical)Power pinoutis configuredas one bidirectionallane (one Consumption, withOption toPower Down transmit,one receivechannel). Unused Channels The DS64BR111 features a powerful 4-stage
Advanced SignalConditioningFeatures continuoustimelinearequalizer(CTLE) toprovidea boostofup to+25 dB at3.2GHz and open an input– Receive Equalizationup to+25 dB eye thatis completelyclosed due to inter-symbol– TransmitDe-Emphasis up to-12dB interference(ISI) induced by the interconnect – TransmitVOD Control:700 to1200 mVp-p mediums such as an FR-4 backplane or AWG-30 cables.The transmitterfeaturesa programmable– < 0.2UI ofResidualDJ at6.4Gbps outputde-emphasis driverwith up to -12 dB and• Programmable viaPin Selection,EEPROM or allowsamplitudevoltagelevelsto be selectedfromSMBus Interface 700 mVp-p to1200 mVp-p tosuitmultipleapplication
SingleSupply OperationSelectable:2.5Vor scenarios. 3.3v The programmable settingscan be appliedvia pin• Flow-ThruPinoutin4mmx4mm 24-Pin settings,SMBus (I2C) protocolor an externalLeadlessWQFN Package EEPROM. When operatingin the EEPROM mode, the configurationinformationisautomaticallyloaded• >5kV HBM ESD Rating on power up – This eliminatesthe need for an• Industrial-40to85°C OperatingTemperature externalmicroprocessororsoftwaredriver.Range Part of TI'sPowerWise familyof energy efficient devices, the DS64BR111 consumes just 65APPLICATIONS mW/channel (typical),and allowtheoptiontoturn-off• High-Speed ActiveCopper Cable Modules and unused channels.Thisultralow power consumptionFR-4 Backplane inCommunication Systems eliminatesthe need for externalheat sinks and
FC, SAS, SATA 3/6Gbps (withOOB Detection), simplifiesthermal management in active cable applications.InfiniBand,CPRI, OBSAI, RXAUI and Many Others Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsof Texas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2Alltrademarksarethepropertyoftheirrespectiveowners. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 2011–2013,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.

EQ[1:0] OUT+ OUT- 50:50: VOD SMBus LOSChannel Status and Control SD_TH TX_DIS MODE ASIC/FPGA ASIC/FPGA Interconnect Cable DS64BR111 DS64BR111 DS64BR111 SNLS343C –SEPTEMBER 2011–REVISED APRIL 2013 www.ti.com TypicalApplication Block Diagram -DetailView Of Channel (1Of 2)

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VDD_SEL VIN INB+ INB- LOS VOD_SEL / READEN# MODE / DONE# SD_TH OUTA+ OUTA- OUTB- SMBUS AND CONTROL VDD EQB1/AD2 ENSMB SCL/DEMB EQB0/AD3 SDA/DEMA VDD TX_DIS AD1/EQA1 AD0/EQA0 DS64BR111 www.ti.com SNLS343C –SEPTEMBER 2011–REVISED APRIL 2013 Pin Diagram (1) The centerDAP on thepackage bottomisthedeviceGND connection.Thispad must be connectedtoGND through multiple(minimum of4)viastoensureoptimalelectricaland thermalperformance. DS64BR111 Pin Diagram 24 lead PIN DESCRIPTIONS Pin Name Pin I/O,Type (1) Pin Description Number DifferentialHigh Speed I/O's INA+,INA-, 24,23 I,CML Invertingand non-invertingCML differentialinputstotheequalizer.An on-chip INB+,INB-, 11,12 50Ω terminationresistorconnectsINx+ toVDD and INx-toVDD when enabled. OUTA+, OUTA-, 7,8 O,CML Invertingand non-inverting50Ω driveroutputswithde-emphasis.Compatible OUTB+, OUTB-, 20,19 withAC coupledCML inputs. ControlPins ENSMB 3 I,LVCMOS Float System Management Bus (SMBus) enablepin TieHIGH = RegisterAccess,SMBus Slavemode FLOAT = SMBus MasterreadfromExternalEEPROM TieLOW = ExternalPinControlMode ENSMB = 1 (SMBUS MODE) SCL 5 I,LVCMOS ENSMB MasterorSlavemode O, Open Drain SMBUS clockinputpinisenabled.A clockinputinSlavemode. Can alsobe a clockoutputinMastermode. SDA 4 I,LVCMOS, ENSMB MasterorSlavemode O, OPEN Drain The SMBus bidirectionalSDA pinisenabled.Data inputoropen drain(pull- down only)output. (1) LVCMOS inputswithoutthe“Float”conditionsmust be driventoa logicloworhighatalltimesoroperationisnotspecified.Unlessthe "Float"levelisdesired;4-Levelinputpinsrequirea minimum 1K resistortoGND, VDD (in2.5Vmode),orVIN (in3.3Vmode).For additionalinformation,Table1 Table5 Inputedge rateforLVCMOS/FLOAT inputsmust be fasterthan50 ns from10–90% Copyright© 2011–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:DS64BR111

SNLS343C –SEPTEMBER 2011–REVISED APRIL 2013 www.ti.com PIN DESCRIPTIONS (continued) Pin Name Pin I/O,Type (1) Pin Description Number AD0-AD3 10,9,2,1 I,LVCMOS Float ENSMB MasterorSlavemode (4-Levels) SMBus SlaveAddressInputs.InSMBus mode, thesepinsaretheuserset SMBus slaveaddressinputs.Thereare16 addressessupportedby these pins. Pinsmust be tiedLOW orHIGH when used todefinethedeviceSMBus address. Note:SettingVOD_SEL = High inSMBus Mode willforcetheAddress = B0'h READEN# 17 I,LVCMOS When usingan ExternalEEPROM, a transitionfromhightolowstartstheload fromtheexternalEEPROM DONE# 18 IO,LVCMOS, EEPROM Download Status Float HIGH indicatesError/StillLoading (4-Levels) LOW indicatesdownloadcomplete.No Error. ENSMB = 0 (PINMODE) EQA0, EQA1 10,9 I,LVCMOS, Float EQA/B ,0/1controlthelevelofequalizationofeach channel.The EQA/B pins EQB0, EQB1 1,2 (4-Levels) areactiveonlywhen ENSMB isde-asserted(LOW). When ENSMB goes hightheSMBus registersprovideindependentcontrolof each lane,and theEQB0/B1 pinsareconvertedtoSMBUS AD2/AD3 inputs. DEMA, DEMB 4,5 IO,LVCMOS, DEMA/B controlsthelevelofde-emphasis.The DEMA/B pinsareonlyactive Float when ENSMB isde-asserted(LOW). Each ofthe4 A/B channelshave the (4-Levels) same levelunlesscontrolledby theSMBus controlregisters.When ENSMB goes hightheSMBus registersprovideindependentcontrolofeach laneand theDEM pinsareconvertedtoSMBUS SCL and SDA pins. TX_DIS 6 I,LVCMOS DS64BR111 High= OUTA Enabled/OUTB Disabled Low = OUTA/B Enabled VOD_SEL 17 I,LVCMOS, Float EQ Mode and VOD select. (4-Levels) High= (VOD = 1.1V/1.3V) Float= (VOD = 1.0V) 20K = (VOD = 1.2V) Low = (VOD = 700m V) Note:DS64BR111 OUTA islimitedto700mV inpinmode, see Table4 for additionalinformation. Note:SettingVOD_SEL = High inSMBus Mode willforcetheSMBus Address = B0'h VDD_SEL 16 I,InternalPull-up Enablesthe3.3Vto2.5Vinternalregulator Low = 3.3V Operation Float= 2.5V Operation MODE 18 I,LVCMOS ControlsDeviceMode ofOperation High= ContinuousTalk Float= Slow OOB 20KΩ = eSATA Mode, FastOOB, Auto Low Power on 100 uS ofinactivity.SD staysactive. Low = SAS Mode, FastOOB StatusOutput LOS 13 O, Open Drain IndicatesLoss ofSignal(DefaultisLOS on INA).Can be modifiedviaSMBus registers. LOS ThresholdInput SD_TH 14 I,LVCMOS, Float The SD_TH pincontrolsLOS thresholdsetting; (4-Levels) Assert(mV),Deassert(mV) 20K = 160 mV, 100 mV Float= 180 mV, 110 mV (Default) High= 190 mV, 130 mV Low = 210 mV, 150 mV Note:Using valueslessthan thedefaultlevelcan extend thetime requiredtodetectLOS and arenot recommended. Power

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www.ti.com SNLS343C –SEPTEMBER 2011–REVISED APRIL 2013 PIN DESCRIPTIONS (continued) Pin Name Pin I/O,Type (1) Pin Description Number VDD 21,22 Power Power supplypins 2.5Vmode connectto2.5V 3.3Vmode do notconnecttoany supplyvoltage.Shouldbe used toattach externaldecouplingtodevice.100 -200 nF recommended. Note:See APPLICATION INFORMATION foradditionalinformation. VIN 15 Power VIN = 3.3V+/-10% (inputtointernalLDO regulator) Note:Must FLOAT for2.5Voperation.See APPLICATION INFORMATION foradditionalinformation. GND DAP Power Ground pad (DAP -dieattachpad). These deviceshave limitedbuilt-inESD protection.The leadsshouldbe shortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamage totheMOS gates. ABSOLUTE MAXIMUM RATINGS (1)(2) SupplyVoltage(VDD) -0.5Vto+2.75V SupplyVoltage(VIN) -0.5Vto+4.0V LVCMOS Input/OutputVoltage -0.5Vto+4.0V CML InputVoltage -0.5Vto(VDD+0.5) CML InputCurrent -30to+30 mA JunctionTemperature 125°C StorageTemperature -40°C to+125°C ESD Rating HBM, STD -JESD22-A114F > 5 kV MM, STD -JESD22-A115-A 100 V CDM, STD -JESD22-C101-D 1250 V Package ThermalResistance θJC 3.2°C/W θJA,No Airflow,4 layerJEDEC 33.0°C/W Forsolderingspecifications: See productfolderatwww.ti.com http://www.ti.com/lit/SNOA549 (1) “AbsoluteMaximum Ratings”indicatelimitsbeyond whichdamage tothedevicemay occur,includinginoperabilityand degradationof devicereliabilityand/orperformance.Functionaloperationofthedeviceand/ornon-degradationattheAbsoluteMaximum Ratingsor otherconditionsbeyond thoseindicatedintheRecommended OperatingConditionsisnotimplied.The Recommended Operating Conditionsindicateconditionsatwhichthedeviceisfunctionaland thedeviceshouldnotbe operatedbeyond such conditions.Absolute Maximum Numbers arespecifiedfora junctiontemperaturerangeof-40°C to+125°C. Models arevalidatedtoMaximum Operating Voltagesonly. (2) IfMilitary/Aerospacespecifieddevicesarerequired,pleasecontacttheTexas InstrumentsSalesOffice/Distributorsfor availabilityand specifications. RECOMMENDED OPERATING CONDITIONS Min Typ Max Units SupplyVoltage(2.5V 2.375 2.5 2.625 V Mode) SupplyVoltage(3.3V 3.0 3.3 3.6 V Mode) AmbientTemperature -40 25 +85 °C SMBus (SDA, SCL) 3.6 V Copyright© 2011–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:DS64BR111

SNLS343C –SEPTEMBER 2011–REVISED APRIL 2013 www.ti.com

ELECTRICAL CHARACTERISTICS

Symbol Parameter Conditions Min Typ Max Units Power Supply Current IDD SupplyCurrent TX_DIS = LOW, EQ = ON 50 63 VOD_SEL = Float(1000 mV) AutoLow Power Mode 12 15 TX_DIS = LOW, MODE = 20K mA VID CHA and CHB = 0.0V VOD_SEL = Float(1000mV) TX_DIS = HIGH 25 35 LVCMOS DC Specifications VIH VoltageInputHigh 2.0 VDD V VIL VoltageInputLow GND 0.7 V VOH VoltageOutputHigh IOH = -4.0mA (1) 2.0 V VOL VoltageOutputLow IOL = 4.0mA 0.4 V IIN InputLeakage Current Vinput= 0V orVDD -15 +15 uA VDD_SEL = Float Vinput= 0V orVIN -15 +15 VDD_SEL = Low IIN-P InputLeakage Current Vinput= 0V orVDD -0.05V -160 +80 uA 4-LevelInput VDD_SEL = Float Vinput= 0V orVIN -0.05V VDD_SEL = Low LOS and ENABLE /DISABLE Timing TLOS_OFF InputIDLE toActive See (2) 0.035 uS RX_LOS responsetime TLOS_ON InputActivetoIDLE See (2) 0.4 uS RX_LOS responsetime TOFF TX DisableassertTime See (2) 0.005 uS TX_DIS = HIGH to OutputOFF TON TX DisablenegateTime See (2) 0.150 uS TX_DIS = LOW to OutputON TLP_EXIT AutoLow Power Exit See (2) 150 nS ALP toNormal Operation TLP_ENTER AutoLow Power Enter See (2) 100 uS Normal Operationto AutoLow Power CML RECEIVER INPUTS VTX SourceTransmit Defaultpower-upconditions 190 800 1600 mV Launch SignalLevel ENSMB = 0 or1 VOD_SEL = Float RL RX-IN RX returnloss SDD11 @ 4.1GHz -12 dB SDD11 @ 11.1GHz -8 SCD11 @ 11.1GHz -10 HIGH SPEED TRANSMITTER OUTPUTS (1) VOH onlyappliestotheDONE# pin;LOS, SCL, and SDA areopen-drainoutputsthathave no internalpull-upcapability.DONE# isa fullLVCMOS outputwithpull-upand pull-downcapability (2) Parameternottestedinproduction.

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www.ti.com SNLS343C –SEPTEMBER 2011–REVISED APRIL 2013 ELECTRICAL CHARACTERISTICS (continued) Symbol Parameter Conditions Min Typ Max Units VOD1 OutputVoltage OUT+ and OUT- AC coupled 500 650 800 mVp-p DifferentialSwing and terminatedby 50Ω toGND VOD_SEL = LOW (700mV setting) DE = LOW VOD2 OutputVoltage OUT+ and OUT- AC coupled 800 1000 1100 DifferentialSwing and terminatedby 50Ω toGND VOD_SEL = FLOAT (1000mV setting) DE = LOW VOD3 OutputVoltage OUT+ and OUT- AC coupled 950 1150 1350 DifferentialSwing and terminatedby 50Ω toGND VOD_SEL = 20K (1200mV setting) DE = LOW VOD_DE1 De-Emphasis Levels OUT+ and OUT- AC coupled -3 dB and terminatedby 50Ω toGND VOD_SEL = FLOAT (1000mV setting) DE = FLOAT VOD_DE2 De-Emphasis Levels OUT+ and OUT- AC coupled -6 dB and terminatedby 50Ω toGND VOD_SEL = FLOAT (1000mV setting) DE = 20K VOD_DE3 De-Emphasis Levels OUT+ and OUT- AC coupled -9 dB and terminatedby 50Ω toGND VOD_SEL = FLOAT (1000mV setting) DE = HIGH VCM-AC OutputCommon-Mode AC Common Mode Voltage 4.5 mV (RMS) Voltage DE = 0 dB,VOD <= 1000 mV VCM-DC OutputDC Common- DC Common Mode Voltage 0 1.1 1.9 V Mode Voltage VIDLE TX IDLE Output 30 mV Voltage RL TX-DIFF TX returnloss SDD22 @ 4.1GHz -13 dB SDD22 @ 11.1GHz -9 SCC22 @ 2.5GHz -22 SCC22 @ 11.1GHz -10 deltaZM TransmitterTerminationDC, IFORCE = +/-100 uA (3) 2.5 % Mismatch TR/F TransmitterRiseand 20% -80% (4) 38 Ω FallTime TPD PropagationDelay Measured at50% crossing 230 ps TCCSK ChanneltoChannel T = 25°C, VDD = 2.5V 7 ps Skew TPPSK ParttoPartChannel T = 25°C, VDD = 2.5V 20 ps Skew TDI Time totransitionto 6.5 ns validelectricalIDLE afteran activeburstin OOB signaling TID Time totransitionto 3.2 ns validactiveburstafter leavingelectricalIDLE inOOB signaling (3) Force+/-100 uA on output,measure deltaV on theOutputand calculateimpedance.MismatchisthepercentagedifferenceofOUTn+ and OUTn- impedance drivingthesame logicstate. (4) DefaultVOD used fortesting.DE = -1.5dB levelused tocompensate forfixtureattenuation. Copyright© 2011–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:DS64BR111

SNLS343C –SEPTEMBER 2011–REVISED APRIL 2013 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Symbol Parameter Conditions Min Typ Max Units TENVELOPE_DISTO ActiveOOB timing 3.3 ns RT distortion,inputactive timevs.outputactive time OUTPUT JITTER SPECIFICATIONS (5) R J Random Jitter No Media SourceAmplitude= 700 mV, PRBS15 pattern, 0.35 ps (RMS)6.4Gbps VOD = Default,EQ = minimum, DE = 0 dB D J1 DeterministicJitter 0.065 UI Equalization D JE1 ResidualDeterministic8 meter30AWG Cableon Jitter Input 10.3125Gbps Source= 700 mV, PRBS15 0.15 UI pattern EQ = 0F'h;See Figure15 D JE2 ResidualDeterministic30"FR4 on Inputs Jitter Source= 800 mV, PRBS15 0.10 UI6.4Gbps pattern EQ = 16'h;See Figure13 De-emphasis D JD1 ResidualDeterministic10”4 milstriplineFR4 on Jitter Outputs 6.4Gbps Source= 700 mV, PRBS15 0.085 UIpattern EQ = 00 (Min),DE = 010'b See Figure17 (5) Typicaljitterreportedisdeterminedby jitterdecompositionsoftwareon a DSA8200 Oscilloscope. ELECTRICAL CHARACTERISTICS — SERIAL MANAGEMENT BUS INTERFACE Over recommended operatingsupplyand temperaturerangesunlessotherspecified. Symbol Parameter Conditions Min Typ Max Units SERIAL BUS INTERFACE DC SPECIFICATIONS: (1) VIL Data,ClockInputLow Voltage 0.8 V VIH Data,ClockInputHighVoltage 2.1 3.6 V IPULLUP CurrentThroughPull-UpResistor HighPower Specification 4 mAorCurrentSource VDD NominalBus Voltage 2.375 3.6 V ILEAK-Bus InputLeakage Per Bus Segment See (2) -200 +200 µA C I CapacitanceforSDA and SCL See (2)and (3)(4) 10 pF R TERM ExternalTerminationResistance PullupVDD = 3.3V(2)(3)(5) 2000 Ω pulltoVDD = 2.5V± 5% OR 3.3V± PullupVDD = 2.5V(2)(3)(5) 1000 Ω10% SERIAL BUS INTERFACE TIMING SPECIFICATIONS FSMB Bus OperatingFrequency ENSMB = VDD (SlaveMode) 400 kHz ENSMB = FLOAT (MasterMode) 280 400 520 kHz(2) TBUF Bus FreeTime Between Stopand 1.3 µsStartCondition (1) EEPROM interfacerequires400 KHz capableEEPROM device. (2) Recommended value. (3) Recommended maximum capacitanceloadperbus segment is400pF. (4) Specifiedby Designand/orcharacterization.Parameternottestedinproduction. (5) Maximum terminationvoltageshouldbe identicaltothedevicesupplyvoltage.

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www.ti.com SNLS343C –SEPTEMBER 2011–REVISED APRIL 2013 ELECTRICAL CHARACTERISTICS — SERIAL MANAGEMENT BUS INTERFACE (continued) Over recommended operatingsupplyand temperaturerangesunlessotherspecified. Symbol Parameter Conditions Min Typ Max Units THD:STA Holdtimeafter(Repeated)Start AtIPULLUP ,Max Condition.Afterthisperiod,thefirst 0.6 µs clockisgenerated. TSU:STA Repeated StartConditionSetup 0.6 µsTime TSU:STO StopConditionSetupTime 0.6 µs THD:DAT Data HoldTime 0 ns TSU:DAT Data SetupTime 100 ns TLOW ClockLow Period 1.3 µs THIGH ClockHighPeriod See (6) 0.6 50 µs tF Clock/DataFallTime See (6) 300 ns tR Clock/DataRiseTime See (6) 300 ns tPOR Time inwhicha devicemust be See (6)and (4) 500 msoperationalafterpower-onreset SMBus common AC specificationsfordetails. Copyright© 2011–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:DS64BR111

tHD:STA tLOW tR tHD:DAT tHIGH tF tSU:DAT tSU:STA ST SP tSU:STO SCL SDA ST DS64BR111 SNLS343C –SEPTEMBER 2011–REVISED APRIL 2013 www.ti.com TIMING DIAGRAMS Figure1. CML Output TransitionTimes Figure2. PropagationDelay Timing Diagram Figure3. IdleTiming Diagram Figure4. SMBus Timing Parameters

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www.ti.com SNLS343C –SEPTEMBER 2011–REVISED APRIL 2013 FUNCTIONAL DESCRIPTION The DS64BR111 isa highperformancecircuitcapableof deliveringexcellentperformance.Carefulattention must be paidtothedetailsassociatedwithhigh-speeddesignas wellas providinga cleanpower supply.Refer to the informationbelow and Revision4 of the LVDS Owner's Manual formore detailedinformationon high speed designtipstoaddresssignalintegritydesignissues. The controlpinshave been enhanced tohave 4 differentlevelsand providea widerrange ofcontrolsettings. RefertoTable1 Table1.4-LevelControlPin Settings Pin Setting Description

0 TiepintoGND througha 1 KΩ resistor

R Tiepintogroundthrough20 KΩ resistor Float Floatthepin(noconnection)

1 TiepintoVDD througha 1 KΩ resistor

Note:4-LevelIO pinsrequirea 1K resistancetoGND or VDD/VIN. Itispossibletotiemulitple4-levelIO pins togetherwitha singleresistortoGND orVDD/VIN. When multipleIOs areconnectedinparallel,theresistanceto GND or VDD/VIN shouldbe adjustedtocompensate.For 2 pinstheoptimalresistanceis500 Ohms, 3 pins= 330 Ohms, and 4 pins= 250 Ohms. Note:For 2.5V mode thecontrolpinlogic1 levelisVDD (pins21 and 22),in3.3V mode thecontrolpinlogic1 levelisdefinedby VIN (pin15). Table2.EqualizerSettings Level EQA1/EQB1 EQA0/EQB0 EQ — 8 bits[7:0] dB Boost at3.2Ghz Suggested Media 1 0 0 0000 0000 = 0x00 3.7 FR4 < 5 inchtrace 2 0 R 0000 0001 = 0x01 6.0 FR4 5 inchtrace 3 0 Float 0000 0010 = 0x02 7.5 FR4 10 inchtrace 4 0 1 0000 0011 = 0x03 8.5 FR4 15 inchtrace

5 R 0 0000 0111 = 0x07 11 FR4 20 inchtrace

6 R R 0001 0101 = 0x15 12 FR4 25 inchtrace

7 R Float 0000 1011 = 0x0B 14 FR4 25 inchtrace

8 R 1 0000 1111 = 0x0F 15 7m 30AWG Cable

9 Float 0 0101 0101 = 0x55 15 FR4 30 inchtrace

10 Float R 0001 1111 = 0x1F 18 8m 30 AWG Cable

11 Float Float 0010 1111 = 0x2F 20 10m 30 AWG Cable

12 Float 1 0011 1111 = 0x3F 22 10m -12m, Cable

13 1 0 1010 1010 = 0xAA 23 14 1 R 0111 1111 = 0x7F 25 15 1 Float 1011 1111 = 0xBF 27 16 1 1 1111 1111 = 0xFF 28 Note:Settingsareapproximateand willchange based on PCB material,tracedimensions,and driverwaveform characteristics. Table3.De-emphasis and Output VoltageSettings Level VOD_SEL DEMA/B SMBus RegisterDEM Level SMBus RegisterVOD Level VOD (mV) DEM (dB) 1 0 0 000 000 700 0 2 0 Float 010 000 700 -3.5 3 0 R 011 000 700 -6 4 0 1 101 000 700 -9

5 Float 0 000 011 1000 0

SNLS343C –SEPTEMBER 2011–REVISED APRIL 2013 www.ti.com Table3.De-emphasis and Output VoltageSettings(continued) 6 Float Float 010 011 1000 -3.5

7 Float R 011 011 1000 -6

8 Float 1 101 011 1000 -9

9 R 0 000 101 1200 -0

10 R Float 010 101 1200 -3.5

11 R R 011 101 1200 -6

12 R 1 101 101 1200 -9

14 1 Float 001 100 1100 -1.5 15 1 R 001 110 1300 -1.5 16 1 1 010 110 1300 -3.5 Note:The DS64BR111 VOD forOUTPUT A islimitedto700 mV inpinmode (ENSMB=0). WithENSMB = 1 or FLOAT, the VOD forOUTPUT A can be adjustedwithSMBus register0x23 [4:2]as shown in the SMBus RegisterTable. Note:InSMBus Mode ifVOD_SEL isintheLogic1 state(1K resistortoVIN/VDD) theDS64BR111 AD0-AD3 pinsareinternallyforcedto0'h Table4.SignalDetectThresholdLevel SMBus REG bitSD_TH AssertLevel(Typical) De-assertLevel(Typical)[3:2]and [1:0] 0 10 210 mV 150 mV 20K toGND 01 160 mV 100 mV Float(Default) 00 180 mV 110 mV 1 11 190 mV 130 mV Note:VDD = 2.5V,25°C, and 010101 patternat6.4Gbps

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www.ti.com SNLS343C –SEPTEMBER 2011–REVISED APRIL 2013

APPLICATION INFORMATION

4-LevelInputConfigurationGuidelines The 4-levelinputpinsutilizea resistordividertohelpsetthe4 validlevels.Thereisan internal30K pull-upand a 60K pull-downconnectedto the package pin.These resistors,togetherwiththe externalresistorconnection combine toachievethedesiredvoltagelevel.Usingthe1K pull-up,1K pull-down,no connect,and 20K pull-down providetheoptimalvoltagelevelsforeach ofthefourinputstates. Table5.4-LevelInputVoltage Level Setting 3.3VMode 2.5VMode 0 01K toGND 0.1V 0.08V R 20K toGND 0.33*VIN 0.33*VDD F FLOAT 0.67*VIN 0.67*VDD 1 1K toVDD /VIN VIN -0.05V VIN -0.04V

Typical4-LevelInputThresholds – Level1 -2 = 0.2VIN orVDD – Level2 -3 = 0.5VIN orVDD – Level3 -4 = 0.8VIN orVDD Inordertominimizethestartupcurrentassociatedwiththeintegrated2.5V regulatorthe1K pull-up/pull-down resistorsare recommended. Ifseveral4 levelinputsrequirethesame setting,itispossibletocombine two or more 1K resistorsintoa singlelowervalueresistor.As an example;combiningtwo inputswitha single500Ω resistorisa good way tosave boardspace. PCB Layout Guidelines The CML inputsand outputshave been optimizedto work withinterconnectsusinga controlleddifferential impedance of 85 - 100Ω. Itis preferableto routedifferentiallinesexclusivelyon one layerof the board, particularlyfortheinputtraces.The use ofviasshouldbe avoidedifpossible.Ifviasmust be used,theyshould be used sparinglyand must be placed symmetricallyforeach side of a given differentialpair.Whenever differentialviasare used thelayoutmust alsoprovidefora low inductancepathforthereturncurrentsas well. Route thedifferentialsignalsaway from othersignalsand noisesourceson theprintedcircuitboard.See AN- 1187 (SNOA401 )foradditionalinformationon WQFN packages. Differenttransmissionlinetopologiescan be used in variouscombinationsto achievethe optimalsystem performance.Impedance discontinuitiesatviascan be minimizedor eliminatedby increasingtheswellaround each holeand providingfora low inductancereturncurrentpath.When theviastructureisassociatedwiththick backplanePCB, furtheroptimizationsuch as back drillingisoftenused toreducethedetrimentalhighfrequency effectsofstubson thesignalpath. Power Supply ConfigurationGuidelines The DS64BR111 can be configuredfor2.5V operationor 3.3V operation.The listsbelow outlinerequired connectionsforeach supplyselection. 3.3VMode ofOperation 1. TieVDD_SEL = 0 with1K resistortoGND. 3. See informationon VDD bypassbelow. 4. SDA and SCL pinsshouldconnectpull-upresistortoVIN 5. Any 4-Levelinputwhichrequiresa connectionto"Logic1"shoulduse a 1K resistortoVIN 2.5VMode ofOperation 6. VDD_SEL = Float 7. VIN = Float 8. Feed 2.5VsupplyintoVDD pins. 9. See informationon VDD bypassbelow. Copyright© 2011–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:DS64BR111

SNLS343C –SEPTEMBER 2011–REVISED APRIL 2013 www.ti.com 10. SDA and SCL pinsconnectpull-upresistortoVDD for2.5VuC SMBus IO 11. SDA and SCL pinsconnectpull-upresistortoVIN for3.3VuC SMBus IO 12. Any 4-Levelinputwhichrequiresa connectionto"Logic1"shoulduse a 1K resistortoVIN Note:The DAP (bottomsolderpad)istheGND connection. Power Supply Bypass Two approachesarerecommended toensurethattheDS64BR111 isprovidedwithan adequatepower supply. First,thesupply(VDD) and ground(GND) pinsshouldbe connectedtopower planesroutedon adjacentlayers oftheprintedcircuitboard.The layerthicknessofthedielectricshouldbe minimizedso thattheVDD and GND planes createa low inductancesupply with distributedcapacitance.Second, carefulattentionto supply bypassingthroughthe properuse of bypass capacitorsis required.A 0.1 μF bypass capacitorshould be connectedtoeach VDD pinsuch thatthecapacitorisplacedas closeas possibletothedevice.Smallerbody size capacitorscan helpfacilitatepropercomponent placement. System Management Bus (SMBus) and ConfigurationRegisters The System Management Bus interfaceiscompatibletoSMBus 2.0physicallayerspecification.ENSMB must be pulledhightoenableSMBus mode and allowaccesstotheconfigurationregisters. The DS64BR111 has AD[3:0]inputsinSMBus mode. These pinsaretheusersetSMBus slaveaddressinputs. When pulledlow the AD[3:0]= 0000'b,the devicedefaultaddress byte isB0'h.Based on the SMBus 2.0 specification,thisconfigurationresultsina 7-bitslaveaddressof1011000'b.The LSB issetto0'b(fora WRITE), thusthe 8-bitvalueis1011 0000'bor B0'h.The deviceaddressbytecan be setwiththe use of the AD[3:0] inputs. Shown intheformofan expression: SlaveAddress[7:4]= The DS64BR111 hardwareaddress(1011'b)+ AddresspinAD[3] SlaveAddress[3:1]= AddresspinsAD[2:0] SlaveAddress[0]= 0'bfora WRITE or1'bfora READ SlaveAddressExamples:

AD[3:0]= 0001'b,thedeviceslaveaddressbyteisB2'h – SlaveAddress[7:4]= 1011'b+ 0'b= 1011'borB'h – SlaveAddress[3:1]= 001'b – SlaveAddress[0]= 0'bfora WRITE
AD[3:0]= 0010'b,thedeviceslaveaddressbyteisB4'h – SlaveAddress[7:4]= 1011'b+ 0'b= 1011'borB'h – SlaveAddress[3:1]= 010'b – SlaveAddress[0]= 0'bfora WRITE
AD[3:0]= 0100'b,thedeviceslaveaddressbyteisB8'h – SlaveAddress[7:4]= 1011'b+ 0'b= 1011'borB'h – SlaveAddress[3:1]= 100'b – SlaveAddress[0]= 0'bfora WRITE
AD[3:0]= 1000'b,thedeviceslaveaddressbyteisC0'h – SlaveAddress[7:4]= 1011'b+ 1'b= 1100'borC'h – SlaveAddress[3:1]= 000'b – SlaveAddress[0]= 0'bfora WRITE TRANSFER OF DATA VIA THE SMBus Duringnormaloperationthedataon SDA must be stableduringthetimewhen SCL isHigh. TherearethreeuniquestatesfortheSMBus: START: A High-to-Lowtransitionon SDA whileSCL isHighindicatesa message START condition. STOP: A Low-to-Hightransitionon SDA whileSCL isHighindicatesa message STOP condition.

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A A 0 0S + A3 Slave Address a c k 0 1 2 3 4 5 6 7Device ID Register Address a c k S A A A 0 1 0 1 2 3 4 5 6 7 a c k Slave Address a c k Data + A3Device ID DS64BR111 www.ti.com SNLS343C –SEPTEMBER 2011–REVISED APRIL 2013 IDLE: IfSCL and SDA arebothHigh fora timeexceedingtBUF fromthelastdetectedSTOP conditionorifthey areHighfora totalexceedingthemaximum specificationfortHIGH thenthebus willtransfertotheIDLE state. SMBus TRANSACTIONS The devicesupportsWRITE and READ transactions.See RegisterDescriptiontableforregisteraddress,type (Read/Write,Read Only),defaultvalueand functioninformation. WRITING A REGISTER To writea register,thefollowingprotocolisused (seeSMBus 2.0specification). 1. The Hostdrivesa START condition,the7-bitSMBus address,and a “0”indicatinga WRITE. 2. The Device(Slave)drivestheACK bit(“0”). 3. The Hostdrivesthe8-bitRegisterAddress. 4. The Devicedrivesan ACK bit(“0”). 5. The Hostdrivethe8-bitdatabyte. 6. The Devicedrivesan ACK bit(“0”). 7. The Hostdrivesa STOP condition. The WRITE transactioniscompleted,the bus goes IDLE and communicationwithotherSMBus devicesmay now occur. READING A REGISTER To reada register,thefollowingprotocolisused (seeSMBus 2.0specification). 1. The Hostdrivesa START condition,the7-bitSMBus address,and a “0”indicatinga WRITE. 2. The Device(Slave)drivestheACK bit(“0”). 3. The Hostdrivesthe8-bitRegisterAddress. 4. The Devicedrivesan ACK bit(“0”). 5. The Hostdrivesa START condition. 6. The Hostdrivesthe7-bitSMBus Address,and a “1”indicatinga READ. 7. The Devicedrivesan ACK bit“0”. 8. The Devicedrivesthe8-bitdatavalue(registercontents). 9. The Hostdrivesa NACK bit“1”indicatingend oftheREAD transfer. 10. The Hostdrivesa STOP condition. The READ transactioniscompleted,thebus goes IDLE and communicationwithotherSMBus devicesmay now occur. Pleasesee SMBus RegisterMap Tableformore informationformore information. Figure5. TypicalSMBus WriteOperation EEPROM Modes inDS64BR111 Device The DS64BR111 devicesupportsreadingdirectlyfrom an externalEEPROM deviceby implementingSMBus Mastermode. When usingtheSMBus mastermode, theDS64BR111 willread directlyfrom specificlocationin theexternalEEPROM. When designinga systemforusingtheexternalEEPROM, theuserneeds tofollowthese specificguidelines.

SettheDS64BR111 intoSMBus MasterMode – FloatENSMB (PIN3)
The externalEEPROM deviceaddressbytemust be 0xA0'h
SettheAD[3:0]inputsforSMBus addressbyte.When theAD[3:0]= 0000'b,thedeviceaddressbyteisB0'h. Copyright© 2011–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:DS64BR111

SNLS343C –SEPTEMBER 2011–REVISED APRIL 2013 www.ti.com

Based on theSMBus 2.0specification,a devicecan have a 7-bitslaveaddressof1011 000'b.The LSB isset to0'b(fora WRITE). The bitmapping forSMBus islistedbelow: – [7:5]= ReservedBitsfromtheSMBus specification – [4:1]= UsableSMBus AddressBits – [0]= WriteBit
The DS64BR111 deviceshave AD[3:0]inputsinSMBus mode (pins1,2,9,10).These pinssetSMBus slave address.The AD[3:0]pinsdo not have any internalpullresistors.When the AD[3:0]= 0001'b,the device addressbyteisB2'h. – [7:5]= 4b'101 – [4:1]= Addressof4'b0001 – [0]= WriteBit,1'b0
The deviceaddress can be set withthe use of the AD[3:0]inputup to 16 differentaddresses.Use the example belowtoseteach oftheSMBus addresses. – AD[3:0]= 0001'b,thedeviceaddressbyteisB2'h – AD[3:0]= 0010'b,thedeviceaddressbyteisB4'h – AD[3:0]= 0011'b,thedeviceaddressbyteisB6'h – AD[3:0]= 0100'b,thedeviceaddressbyteisB8'h
The master implementationinthe DS64BR111, supportmultipledevicesreadingfrom 1 EEPROM. When tyingmultipledevicestotheSDA and SCL pins,use theseguidelines: – Use adjacentSMBus addressesforthe4 devices – Use a pull-upresistoron SDA; value= 4.7KΩ – Use a pull-upresistoron SCL: value= 4.7KΩ – Daisy-chainREADEN# (pin17)and DONE# (pin18)fromone devicetothenextdeviceinthesequence 1. TieREADEN# ofthe1stdeviceinthechain(U1)toGND 2. TieDONE# ofU1 toREADEN# ofU2 3. TieDONE# ofU2 toREADEN# ofU3 4. TieDONE# ofU3 toREADEN# ofU4 5. Optional:TieDONE# ofU4 toa LED toshow each ofthedeviceshave been loadedsuccessfully Master EEPROM Mode intheDS100BR111 Below isan example ofa 2 kbits(256 x 8-bit)EEPROM inhex formatfortheDS100BR111 device.The first3 bytesof the EEPROM always containa header common and necessaryto controlinitializationof alldevices connectedto the I2C bus.CRC enableflagto enable/disableCRC checking.There isa MAP bitto flagthe presenceof an addressmap thatspecifiesthe configurationdata startinthe EEPROM. Ifthe MAP bitisnot presenttheconfigurationdatastartaddressisderivedfromtheDS100BR111 addressand theconfigurationdata size.A bittoindicatean EEPROM size> 256 bytesisnecessarytoproperlyaddresstheEEPROM. Thereare37 bytesofdatasizeforeach DS100BR111 device.

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:1000000000002000000407002FED4002FED4002FC4 :10001000AD4002FAD400005F568005F5A8005F5AE9 :100020008005F5A800005454F100000000000000A8 :1000300000000000000000000000000000000000C0 :1000400000000000000000000000000000000000B0 :1000500000000000000000000000000000000000A0 :100060000000000000000000000000000000000090 :100070000000000000000000000000000000000080 :100080000000000000000000000000000000000070 :100090000000000000000000000000000000000060 :1000A0000000000000000000000000000000000050 :1000B0000000000000000000000000000000000040 :1000C0000000000000000000000000000000000030 :1000D0000000000000000000000000000000000020 :1000E0000000000000000000000000000000000010 :1000F0000000000000000000000000000000000000 :00000001FF CRC-8 based on 40 bytes of data in this shaded area Insert the CRC value here CRC Polynomial = 0x07 MAX EEPROM Burst = 32 DS64BR111 www.ti.com SNLS343C –SEPTEMBER 2011–REVISED APRIL 2013 Figure6. TypicalEEPROM Data Set The CRC-8 calculationisperformedon thefirst3 bytesofheader informationplusthe37 bytesofdataforthe DS64BR111 or40 bytesintotal.The resultofthiscalculationisplacedimmediatelyaftertheDS64BR111 datain theEEPROM whichends with"5454".The CRC-8 intheDS64BR111 uses a polynomial= x8 + x2 + x + 1 InSMBus mastermode theDS64BR111 readsitsinitialconfigurationfroman externalEEPROM upon power-up. Some of the pinsof the DS64BR111 performthe same functionsinSMBus master and SMBus slavemode. Once theDS64BR111 has finishedreadingitsinitialconfigurationfromtheexternalEEPROM inSMBus master mode itrevertstoSMBus slavemode and can be furtherconfiguredby an externalcontrollerovertheSMBus. The connectionto an externalSMBus master isoptionaland can be omittedforapplicationswere additional securityisdesirable.Therearetwo pinsthatprovideuniquefunctionsinSMBus mastermode.

DONE#
READEN# When the DS64BR111 is powered up in SMBus master mode, itreads itsconfigurationfrom the external EEPROM when theREADEN# pingoes low.When theDS64BR111 isfinishedreadingitsconfigurationfromthe externalEEPROM, itdrivestheDONE# pinlow.Inapplicationswhere thereismore thanone DS64BR111 on thesame SMBus, bus contentioncan resultifmore thanone DS64BR111 triestotakecontroloftheSMBus at thesame time.The READEN# and DONE# pinspreventthisbus contention.The system shouldbe designedso thattheREADEN# pinfromone DS64BR111 inthesystemisdrivenlowon power-up.ThisDS64BR111 willtake command oftheSMBus on power-upand willreaditsinitialconfigurationfromtheexternalEEPROM. When itis finishedreadingitsconfiguration,itwilldrivetheDONE# pinlow.Thispinshouldbe connectedtotheREADEN# pinofanotherDS64BR111. When thisDS64BR111 senses itsREADEN# pindrivenlow,itwilltakecommand of theSMBus and readitsinitialconfigurationfromtheexternalEEPROM, afterwhichitwillsetitsDONE# pinlow. By connectingthe DONE# pin of each DS64BR111 to the READEN# pin of the next DS64BR111, each DS64BR111 can readitsinitialconfigurationfromtheEEPROM withoutcausingbus contention. Copyright© 2011–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:DS64BR111

VDD_SEL VIN INB+ INB- LOS READEN# DONE# SD_TH INA+ INA- OUTB- SMBUS AND CONTROL VDD AD2 ENSMB SCL AD3 SDA VDD TX_DIS AD1 AD0 OUTA+ OUTA- OUTB+ VDD_SEL VIN INB+ INB- LOS READEN# DONE# SD_TH INA+ INA- OUTB- SMBUS AND CONTROL VDD AD2 ENSMB SCL AD3 SDA VDD TX_DIS AD1 AD0 OUTA+ OUTA- OUTB+ VDD_SEL VIN INB+ INB- LOS READEN# DONE# SD_TH INA+ INA- OUTB- SMBUS AND CONTROL VDD AD2 ENSMB SCL AD3 SDA VDD TX_DIS AD1 AD0 SDA SCL AD0 AD1 AD2 GND GND GND One or both of these lines should float for EEPROM larger than 256 bytes. EEPROM SDA SCL From External SMBus Master 3.3V FLOAT FLOAT FLOAT Note: Set AD[3:0] of each DS64BR111 to unique SMBus Address. GND DS64BR111 SNLS343C –SEPTEMBER 2011–REVISED APRIL 2013 www.ti.com Figure7. Typicalmulti-deviceEEPROM connectiondiagram

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www.ti.com SNLS343C –SEPTEMBER 2011–REVISED APRIL 2013 Table6.Multi-DeviceEEPROM RegisterMap Overview Addr Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 BIt0

0 CRC EN AddressMap EEPROM > Reserved COUNT[3] COUNT[2] COUNT[1] COUNT[0]

256 Bytes

Header 1 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved

2 EE Burst[7] EE Burst[6] EE Burst[5] EE Burst[4] EE Burst[3] EE Burst[2] EE Burst[1] EE Burst[0]

Device0 3 CRC[7] CRC[6] CRC[5] CRC[4] CRC[3] CRC[2] CRC[1] CRC[0] Info 4 EE AD0 [7] EE AD0 [6] EE AD0 [5] EE AD0 [4] EE AD0 [3] EE AD0 [2] EE AD0 [1] EE AD0 [0] Device1 5 CRC[7] CRC[6] CRC[5] CRC[4] CRC[3] CRC[2] CRC[1] CRC[0] Info 6 EE AD1 [7] EE AD1 [6] EE AD1 [5] EE AD1 [4] EE AD1 [3] EE AD1 [2] EE AD1 [1] EE AD1 [0] Device2 7 CRC[7] CRC[6] CRC[5] CRC[4] CRC[3] CRC[2] CRC[1] CRC[0] Info 8 EE AD2 [7] EE AD2 [6] EE AD2 [5] EE AD2 [4] EE AD2 [3] EE AD2 [2] EE AD2 [1] EE AD2 [0] Device3 9 CRC[7] CRC[6] CRC[5] CRC[4] CRC[3] CRC[2] CRC[1] CRC[0] Info 10 EE AD3 [7] EE AD3 [6] EE AD3 [5] EE AD3 [4] EE AD3 [3] EE AD3 [2] EE AD3 [1] EE AD3 [0] Device0 11 RES RES RES RES RES RES RES RES Addr 3 Device0 12 RES RES PDWN Inp PDWN OSC RES eSATA CHA eSATA CHB Ovrd TX_DIS Addr 4 Device0 46 RES RES RES RES RES RES RES RES Addr 38 Device0 47 RES RES RES RES RES RES RES RES Addr 39 Device1 48 RES RES RES RES RES RES PWDN CH B PWDN CH A Addr 3 Device1 49 RES RES PDWN Inp PDWN OSC RES eSATA CHA eSATA CHB Ovrd TX_DIS Addr 4 Device1 83 RES RES RES RES RES RES RES RES Addr 38 Device1 84 RES RES RES RES RES RES RES RES Addr 39 Device2 85 RES RES RES RES RES RES PWDN CH B PWDN CH A Addr 3 Device2 86 RES RES PDWN Inp PDWN OSC RES eSATA CHA eSATA CHB Ovrd TX_DIS Addr 4 Device2 120 RES RES RES RES RES RES RES RES Addr 38 Device2 121 RES RES RES RES RES RES RES RES Addr 39 Device3 122 RES RES RES RES RES RES PWDN CH B PWDN CH A Addr 3 Device3 123 RES RES PDWN Inp PDWN OSC RES eSATA CHA eSATA CHB Ovrd TX_DIS Addr 4 Device3 157 RES RES RES RES RES RES RES RES Addr 38 Device3 158 RES RES RES RES RES RES RES RES Addr 39

CRC EN = 1;AddressMap = 1
EEPROM > 256 Bytes= 0
COUNT[3:0] = 0011'b
Note:MultipleDS64BR111 devicesmay pointatthesame addressspace iftheyhave identicalprogramming values. Copyright© 2011–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLinks:DS64BR111

SNLS343C –SEPTEMBER 2011–REVISED APRIL 2013 www.ti.com Table7.SingleEEPROM Header + RegisterMap withDefaultValue EEPROM Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0AddressByte

0 CRC EN AddressMap EEPROM > RES COUNT[3] COUNT[2] COUNT[1] COUNT[0]Description Present 256 Bytes

Description1 RES RES RES RES RES RES RES RES Value 0 0 0 0 0 0 0 0

2 Max Max Max Max Max Max Max Max

Description EEPROM EEPROM EEPROM EEPROM EEPROM EEPROM EEPROM EEPROM Burstsize[7] Burstsize[6] Burstsize[5] Burstsize[4] Burstsize[3] Burstsize[2] Burstsize[1] Burstsize[0] Value 0 0 0 0 0 0 0 0 Description3 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Register 0x01[7] 0x01[6] 0x01[5] 0x01[4] 0x01[3] 0x01[2] 0x01 [1] 0x01 [0] Value 0 0 0 0 0 0 0 0 Description4 Ovrd_LOS LOS_Value PDWN Inp PWDN Osc Reserved eSATA eSATA Ovrd TX_DIS EnableA EnableB Register 0x02[5] 0x02[4] 0x02 [3] 0x02 [2] 0x02 [0] 0x04 [7] 0x04 [6] 0x04 [5] Value 0 0 0 0 0 0 0 0 Description5 TX_DIS CHA TX_DIS CHB Reserved EQ Stage4 EQ Stage4 Reserved Overide Reserved CHB CHA IDLE_th Register 0x04 [4] 0x04 [3] 0x04 [2] 0x04 [1] 0x04 [0] 0x06[4] 0x08 [6] 0x08 [5] Value 0 0 0 0 0 1 0 0 Description6 Ovrd_IDLE Reserved Reserved Reserved Reserved Reserved Reserved Reserved Register 0x08 [4] 0x08[3] 0x08 [2] 0x08[1] 0x08[0] 0x0B[6] 0x0B[5] 0x0B[4] Value 0 0 0 0 0 1 1 1 Description7 Reserved Reserved Reserved Reserved IdleautoA IdleselA Reserved Reserved Register 0x0B[3] 0x0B[2] 0x0B[1] 0x0B[0] 0x0E [5] 0x0E [4] 0x0E[3] 0x0E[2] Value 0 0 0 0 0 0 0 0 Description8 CHA EQ[7] CHA EQ[6] CHA EQ[5] CHA EQ[4] CHA EQ[3] CHA EQ[2] CHA EQ[1] CHA EQ[0] Register 0x0F [7] 0x0F [6] 0x0F [5] 0x0F [4] 0x0F [3] 0x0F [2] 0x0F [1] 0x0F [0] Value 0 0 1 0 1 1 1 1 Description9 A Selscp A Out Mode Reserved Reserved Reserved Reserved Reserved Reserved Register 0x10 [7] 0x10 [6] 0x10 [5] 0x10 [4] 0x10 [3] 0x10[2] 0x10[1] 0x10[0] Value 1 1 1 0 1 1 0 1 Description10 DEMA[2] DEMA[1] DEMA[0] CHA Slow IDLE thA[1] IDLE thA[0] IDLE thD[1] IDLE thD[0] Register 0x11 [2] 0x11 [1] 0x11 [0] 0x12 [7] 0x12 [3] 0x12 [2] 0x12 [1] 0x12 [0] Value 0 1 0 0 0 0 0 0 Description11 IdleautoB IdleselB Reserved Reserved CHB EQ[7] CHB EQ[6] CHB EQ[5] CHB EQ[4] Register 0x15 [5] 0x15 [4] 0x15[3] 0x15[2] 0x16 [7] 0x16 [6] 0x16 [5] 0x16 [4] Value 0 0 0 0 0 0 1 0 Description12 CHB EQ[3] CHB EQ[2] CHB EQ[1] CHB EQ[0] B Selscp B Out Mode Reserved Reserved Register 0x16 [3] 0x16 [2] 0x16 [1] 0x16 [0] 0x17 [7] 0x17 [6] 0x17 [5] 0x17 [4] Value 1 1 1 1 1 1 1 0 Description13 Reserved Reserved Reserved Reserved CHB DEM[2] CHB DEM[1] CHB DEM[0] CHB Slow Register 0x17 [3] 0x17[2] 0x17[1] 0x17[0] 0x18 [2] 0x18 [1] 0x18 [0] 0x19 [7] Value 1 1 0 1 0 1 0 0 Description14 IDLE thA[1] IDLE thA[0] IDLE thD[1] IDLE thD[0] Reserved Reserved Reserved Reserved Register 0x19 [3] 0x19 [2] 0x19 [1] 0x19 [0] Value 0 0 0 0 0 0 0 0

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www.ti.com SNLS343C –SEPTEMBER 2011–REVISED APRIL 2013 Table7.SingleEEPROM Header + RegisterMap withDefaultValue (continued) EEPROM Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0AddressByte Description15 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Register Value 0 0 1 0 1 1 1 1 Description16 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Register Value 1 0 1 0 1 1 0 1 Description17 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Register Value 0 1 0 0 0 0 0 0 Description18 Reserved A VOD[2] A VOD[1] A VOD[0] Reserved Reserved Reserved Reserved Register 0x23 [4] 0x23 [3] 0x23 [2] Value 0 0 0 0 0 0 1 0 Description19 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Register 0x25 [4] Value 1 1 1 1 1 0 1 0 Description20 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Register 0x25 [3] 0x25 [2] Value 1 1 0 1 0 1 0 0 Description21 Reserved Reserved Reserved Reserved ovrdfstidle en hiidleth en hiidleth en fstidleA A B Register 0x28 [6] 0x28 [5] 0x28 [4] 0x28 [3] Value 0 0 0 0 0 0 0 1 Description22 en fstidleB sd mgain A sd mgain B Reserved Reserved Reserved Reserved Reserved Register 0x28 [2] 0x28 [1] 0x28 [0] Value 1 0 0 0 0 0 0 0 Description23 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Register Value 0 1 0 1 1 1 1 1 Description24 Reserved Reserved Reserved Reserved B VOD[2] B VOD[1] B VOD[0] Reserved Register 0x2D [4] 0x2D 3] 0x2D [2] Value 0 1 0 1 1 0 1 0 Description25 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Register Value 1 0 0 0 0 0 0 0 Description26 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Register Value 0 0 0 0 0 1 0 1 Description27 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Register Value 1 1 1 1 0 1 0 1 Description28 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Register Value 1 0 1 0 1 0 0 0 Description29 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Register Value 0 0 0 0 0 0 0 0 Copyright© 2011–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLinks:DS64BR111

SNLS343C –SEPTEMBER 2011–REVISED APRIL 2013 www.ti.com Table7.SingleEEPROM Header + RegisterMap withDefaultValue (continued) EEPROM Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0AddressByte Description30 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Register Value 0 1 0 1 1 1 1 1 Description31 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Register Value 0 1 0 1 1 0 1 0 Description32 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Register Value 1 0 0 0 0 0 0 0 Description33 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Register Value 0 0 0 0 0 1 0 1 Description34 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Register Value 1 1 1 1 0 1 0 1 Description35 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Register Value 1 0 1 0 1 0 0 0 Description36 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Register Value 0 0 0 0 0 0 0 0 Description37 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Register Value 0 0 0 0 0 0 0 0 Description38 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Register Value 0 1 0 1 0 1 0 0 Description39 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Register Value 0 1 0 1 0 1 0 0 Below is an example of a 2 kbits(256 x 8-bit)EEPROM RegisterDump in hex formatfora multi-device DS64BR111 application. Table8.MultiDS100BR111 EEPROM Data EEPROM EEPROMAddress (Hex) CommentsAddress Data 0 00 0x43 CRC_EN = 0,AddressMap = 1,DeviceCount = 3 (Devices0,1,2,and 3) 1 01 0x00 2 02 0x08 EEPROM BurstSize 3 03 0x00 CRC notused 4 04 0x0B Device0 AddressLocation 5 05 0x00 CRC notused 6 06 0x30 Device1 AddressLocation 7 07 0x00 CRC notused 8 08 0x30 Device2 AddressLocation 9 09 0x00 CRC notused

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www.ti.com SNLS343C –SEPTEMBER 2011–REVISED APRIL 2013 Table8.MultiDS100BR111 EEPROM Data (continued) EEPROM EEPROMAddress (Hex) CommentsAddress Data 10 0A 0x0B Device3 AddressLocation 11 0B 0x00 BeginDevice0 and Device3 -AddressOffset3 12 0C 0x00 13 0D 0x04 14 0E 0x07 15 0F 0x00 16 10 0x2F DefaultEQ CHA 17 11 0xED 18 12 0x40 19 13 0x02 DefaultEQ CHB 20 14 0xFE DefaultEQ CHB 21 15 0xD4 22 16 0x00 23 17 0x2F 24 18 0xAD 25 19 0x40 26 1A 0x02 BR111 CHA VOD = 700 mV 27 1B 0xFA 28 1C 0xD4 29 1D 0x01 30 1E 0x80 31 1F 0x5F 32 20 0x56 BR111 CHB VOD = 1000 mV 33 21 0x80 34 22 0x05 35 23 0xF5 36 24 0xA8 37 25 0x00 38 26 0x5F 39 27 0x5A 40 28 0x80 41 29 0x05 42 2A 0xF5 43 2B 0xA8 44 2C 0x00 45 2D 0x00 46 2E 0x54 47 2F 0x54 End Device0 and Device3 -AddressOffset39 48 30 0x00 BeginDevice1 and Device2 -AddressOffset3 49 31 0x00 50 32 0x04 51 33 0x07 52 34 0x00 53 35 0x2F DefaultEQ CHA 54 36 0xED 55 37 0x40 56 38 0x02 DefaultEQ CHB Copyright© 2011–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 23 ProductFolderLinks:DS64BR111

SNLS343C –SEPTEMBER 2011–REVISED APRIL 2013 www.ti.com Table8.MultiDS100BR111 EEPROM Data (continued) EEPROM EEPROMAddress (Hex) CommentsAddress Data 57 39 0xFE DefaultEQ CHB 58 3A 0xD4 59 3B 0x00 60 3C 0x2F 61 3D 0xAD 62 3E 0x40 63 3F 0x02 BR111 CHA VOD = 700 mV 64 40 0xFA 65 41 0xD4 66 42 0x01 67 43 0x80 68 44 0x5F 69 45 0x56 BR111 CHB VOD = 1000 mV 70 46 0x80 71 47 0x05 72 48 0xF5 73 49 0xA8 74 4A 0x00 75 4B 0x5F 76 4C 0x5A 77 4D 0x80 78 4E 0x05 79 4F 0xF5 80 50 0xA8 81 51 0x00 82 52 0x00 83 53 0x54 84 54 0x54 End Device1 and Device2 -AddressOffset39

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www.ti.com SNLS343C –SEPTEMBER 2011–REVISED APRIL 2013 Table9.SMBus RegisterMap Register EEPROMAddress Bits Field Type Default DescriptionName Reg Bit 0x00 DeviceID 7 Reserved R/W 0x00 setbitto0 6:3 I2C Address[3:0] R [6:3]SMBus strapobservation

2 EEPROM reading R 1:EEPROM Loading

done 0:EEPROM Done Loading

1 Reserved RWS setbitto0

0 Reserved RWS setbitto0

C 0x01 Control1 7:6 IdleControl R/W 0x00 Yes Control [7]:ContinuoustalkENABLE (ChannelA) [6]:ContinuoustalkENABLE (ChannelB) [2]:LOS SEL ChannelB 5:3 Reserved R/W Setbitsto0

2 LOS Select R/W LOS MonitorSelection

1:Use LOS fromCH B 0:Use LOS fromCH A 1:0 Reserved R/W Setbitsto00'b 0x02 Control2 7 Reserved R/W 0x00 Setbitto0

6 Reserved Setbitto0

5 LOS override Yes LOS pinoverrideenable(1);

Use Normal SignalDetection(0)

4 LOS overridevalue Yes 1:Normal Operation

0:OutputLOS

3 PWDN Inputs Yes 1:PWDN

0:Normal Operation2 PWDN Oscillator Yes

1 Reserved

0 Reserved Yes Setbitto0

0x04 Control3 7:6 eSATA Mode R/W 0x00 Yes [7]ChannelA (1) Enable [6]ChannelB (1)

5 TX_DIS Override 1:OverrideUse Reg 0x04[4:3]

Enable 0:Normal Operation-uses pin

4 TX_DIS Value 1:TX Disabled

ChannelA 0:TX Enabled

3 TX_DIS Value

2 Reserved Setbitto0

1:0 EQ CONTROL [1]:ChannelB -EQ Stage4 ON/OFF [0]:ChannelA -EQ Stage4 ON/OFF 0x05 CRC 1 7:0 CRC[7:0] R/W 0x00 SlaveMode CRC Bits 0x06 CRC 2 7 DisableEEPROM R/W 0x10 DisableMasterMode EEPROM Configuration CFG 6:5 Reserved Setbitsto0

4 Reserved Yes Setbitto1

3 CRC SlaveMode [1]:CRC Disable(No CRC Check)

Disable [0]:CRC Check ENABLE Note:WithCRC checkDISABLED register updatestakeimmediateeffecton highspeed datapath.WithCRC checkENABLED register updateswillNOT takeeffectuntilcorrectCRC valueisloaded 2:1 Reserved Setbitsto0

0 CRC Enable SlaveCRC Trigger

SNLS343C –SEPTEMBER 2011–REVISED APRIL 2013 www.ti.com Table9.SMBus RegisterMap (continued) Address Register Bits Field Type Default EEPROM Description Name Reg Bit 0x07 DigitalReset 7 Reserved R/W 0x01 Setbitto0 and Control 6 ResetRegs Selfclearingresetforregisters Writinga [1]willreturnregistersettingstodefault values.

5 ResetSMBus SelfclearingresetforSMBus masterstate

4:0 Reserved Setbitsto'0001b 0x08 PinOverride 7 Reserved R/W 0x00 Setbitto0

6 OverrideIdle Yes [1]:Overrideby Channel-see Reg 0x13 and

[0]:SD_TH pincontrol

5 Reserved Yes Setbitto0

4 OverrideIDLE Yes [1]:ForceIDLE by Channel-see Reg 0x0E and

[0]:Normal Operation

3 Reserved Yes Setbitto0

2 OverrideOut Mode [1]:Enable Output Mode controlforindividual

outputs.See registerlocations0x10[6] and 0x17[6]. [0]:Disable- Outputs are kept in the normal mode of operationallowingVOD and DE adjustments.

1 OverrideDEM Yes

0x0C CH A 7 Reserved R/W 0x00 Setbitto0 Analog 6 Reserved Setbitto0Override1

5 Reserved Setbitto0

4 Reserved Setbitto0

3:0 Reserved Setbitsto0000'b.. 0x0D CH A 7:0 Reserved R/W 0x00 Setbitsto00'h. Reserved 0x0E CH A 7:6 Reserved R/W 0x00 Setbitsto00'b. IdleControl 5 IdleAuto Yes AutoIDLE valuewhen overridebitisset(reg 0x08 [4]= 1)

4 IdleSelect Yes ForceIDLE valuewhen overridebitisset(reg

0x08 [4]= 1) 3 Reserved Yes Setbitto0. 2:0 Reserved Setbitsto0. 0x0F CH A 7:0 BOOST [7:0] R/W 0x2F Yes EQ BoostDefaultto24 dB EQ Setting See EQ TableforInformation 0x10 CH A 7 Sel_scp R/W 0xED Yes 1 = ShortCircuitProtectionON Control1 0 = ShortCircuitProtectionOFF

6 Reserved Yes Setbitto1

5:3 Reserved Yes Setbitsto= 101'b 2:0 Reserved Yes Setbitsto= 101'b

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www.ti.com SNLS343C –SEPTEMBER 2011–REVISED APRIL 2013 Table9.SMBus RegisterMap (continued) Address Register Bits Field Type Default EEPROM Description Name Reg Bit 0x11 CH A 7:5 Reserved R 0x82 Setbitsto= 100'b Control2 4 Reserved R/W Setbitto0

3 Reserved Setbitto0

2:0 DEM [2:0] Yes De-Emphasis (Default= -3.5dB) 000'b= -0.0dB 001'b= -1.5dB 010'b= -3.5dB 011'b= -6.0dB 100'b= -8.0dB 101'b= -9.0dB 110'b= -10.5dB 111'b= -12.0dB 0x12 CH A 7 Slow OOB R/W 0x00 Yes Slow OOB Enable(1);Disable(0) Idle 6:4 Reserved Setbitsto000'b.Threshold 3:2 idle_thA[1:0] Yes AssertThresholds Use onlyifregister0x08 [6]= 1 00 = 180 mV (Default) 01 = 160 mV 10 = 210 mV 11= 190 mV 1:0 idle_thD[1:0] Yes De-assertThresholds Use onlyifregister0x08 [6]= 1 00 = 110 mV (Default) 01 = 100 mV 10 = 150 mV 11= 130 mV 0x13 CH B 7 Reserved R/W 0x00 Setbitto0 Analog 6 Reserved Setbitto0Override1 3:0 Reserved Setbitsto0000'b. 0x14 CH B 7:0 Reserved R/W 0x00 Setbitsto00'h. Reserved 0x15 CH B 7:6 Reserved R/W 0x00 Setbitsto00'b IdleControl 5 IdleAuto Yes AutoIDLE valuewhen overridebitisset(reg 0x08 [4]= 1) 0x08 [4]= 1) 3:2 Reserved Yes Setbitsto00'b. 1:0 Reserved Setbitsto00'b. 0x16 CH B 7:0 BOOST [7:0] R/W 0x2F Yes EQ BoostDefaultto24 dB EQ Setting See EQ TableforInformation Copyright© 2011–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 27 ProductFolderLinks:DS64BR111

SNLS343C –SEPTEMBER 2011–REVISED APRIL 2013 www.ti.com Table9.SMBus RegisterMap (continued) Address Register Bits Field Type Default EEPROM Description Name Reg Bit 0x17 CH B 7 Sel_scp R/W 0xED Yes 1 = ShortCircuitProtectionON Control1 0 = ShortCircuitProtectionOFF 5:3 Reserved Yes Setbitsto= 101'b 2:0 Reserved Setbitsto= 101'b 0x18 CH B 7:5 Reserved R 0x82 Setbitsto= 100'b Control2 4 Reserved R/W Setbitto0 2:0 DEM [2:0] Yes De-Emphasis (Default= -3.5dB) 000'b= -0.0dB 001'b= -1.5dB 010'b= -3.5dB 011'b= -6.0dB 100'b= -8.0dB 101'b= -9.0dB 110'b= -10.5dB 111'b= -12.0dB 0x19 CH B 7 Slow OOB R/W 0x00 Yes Slow OOB Enable(1);Disable(0) Idle 6:4 Reserved Setbitsto000'b.Threshold 3:2 idle_thA[1:0] Yes AssertThresholds Use onlyifregister0x08 [6]= 1 00 = 180 mV (Default) 01 = 160 mV 10 = 210 mV 11= 190 mV 1:0 idle_thD[1:0] Yes De-assertThresholds Use onlyifregister0x08 [6]= 1 00 = 110 mV (Default) 01 = 100 mV 10 = 150 mV 11= 130 mV 0x23 BR111 CH A 7:6 Reserved R/W 0x00 Setbitsto00'b. VOD 4:2 VOD_CH0[2:0] Yes DS64BR111 VOD ControlsforCH A (Default= 000'b) 000'b= 700 mV 001'b= 800 mV 010'b= 900 mV 011'b= 1000 mV 100'b= 1100 mV 101'b= 1200 mV 110'b= 1300 mV 1:0 Reserved Setbitsto00'b. 0x25 Reserved 7:5 Reserved R/W 0xAD Setbitsto101'b. 4:2 Reserved Yes Setbitsto011'b. 1:0 Reserved Setbitsto01'b. 0x28 IdleControl 7 Reserved R/W 0x00

6 OverrideFastIdle Yes

5:4 en_high_idle_th[1:0] Yes EnablehighSD thresholds [5]:CH A [4]:CH B 3:2 en_fast_idle[1:0] Yes EnableFastIDLE [3]:CH A [2]:CH B 1:0 Reserved Yes Setbitsto00'b.

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www.ti.com SNLS343C –SEPTEMBER 2011–REVISED APRIL 2013 Table9.SMBus RegisterMap (continued) Address Register Bits Field Type Default EEPROM Description Name Reg Bit 0x2D CH B VOD 7:5 Reserved R/W 0xAD Setbitsto101'b. Control 4:2 VOD_CH0[2:0] Yes VOD ControlsforCH B (Default= 011'b) 000'b= 700 mV 001'b= 800 mV 010'b= 900 mV 011'b= 1000 mV 100'b= 1100 mV 101'b= 1200 mV 110'b= 1300 mV 1:0 Reserved Setbitsto'01b 0x51 Device 7:5 Version[2:0] R 0x47 Read bits= 010'b Information 4:0 DeviceID[4:0] BR111 = '00111b Copyright© 2011–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 29 ProductFolderLinks:DS64BR111

1500OUTPUT VOLTAGE (mV) VOD SETTING SUPPLY CURRENT (mA) SUPPLY VOLTAGE (V) VOD = 700 mV Temp = 25° C 2.5V Mode 700 800 900 1000 1100 1200 1300 100 SUPPLY CURRENT (mA) OUTPUT VOLTAGE (mV) 3.3V Mode 2.5V Mode DS64BR111 SNLS343C –SEPTEMBER 2011–REVISED APRIL 2013 www.ti.com TYPICAL DC PERFORMANCE CHARACTERISTICS The followingdatawas collectedat25°C Figure8.Supply Currentvs.Output VoltageSetting Figure9.Supply Currentvs.Supply Voltage Figure10.Output Voltagevs.Output VoltageSetting

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20 GHz Bandwidth

100 Ohm Differential Stripline

www.ti.com SNLS343C –SEPTEMBER 2011–REVISED APRIL 2013 TYPICAL AC PERFORMANCE CHARACTERISTICS NO MEDIA: TotalJitter(Tj@ 1E-Device Random Jitter(Rj) DeterministicJitter(Dj) Dj Component Breakdown 12) DS100BR111 @ 340 fs 9.5ps DDJ = 7.4ps 12.3ps 10.3125Gbps DCD = 1.0ps DDPWS = 6.3ps PJ = 0.81ps Figure11.No Media;D3186 drivingdevicedirectly The followinglabsetupswere used tocollecttypicalperformancedataon FR4 and Cablemedia. Figure12.EqualizationTestSetup forFR4 EQUALIZATION RESULTS: Figure13.EqualizationPerformance with30" of4 milFR4 using EQ settting0x16 Copyright© 2011–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 31 ProductFolderLinks:DS64BR111

OscilloscopeSignal Generator FR4

100 Ohm Differential Impedance

OscilloscopeSignal Generator Cable Adapter Cable Adapter DS64BR111 SNLS343C –SEPTEMBER 2011–REVISED APRIL 2013 www.ti.com EQUALIZATION RESULTS: Figure14.EqualizationTestSetup forCables CABLE TRANSMIT and RECEIVE RESULTS: Figure15.8M 30AWG Cable Performance with700mV Launch VOD and Rx EQ setting0x0F Figure16.De-Emphasis TestSetup DE-EMPHASIS RESULTS: Figure17.De-Emphasis Performance with10" of4 milFR4 using DE settting0x02

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www.ti.com SNLS343C –SEPTEMBER 2011–REVISED APRIL 2013 DE-EMPHASIS RESULTS: Figure18.10" of4 milFR4 WithoutDe-Emphasis Copyright© 2011–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 33 ProductFolderLinks:DS64BR111

SNLS343C –SEPTEMBER 2011–REVISED APRIL 2013 www.ti.com

REVISION HISTORY

Changes from RevisionB (April2013)toRevisionC Page

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www.ti.com 31-Oct-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) DS64BR111SQ/NOPB Active Production WQFN (RTW) | 24 1000 | SMALL T&R Yes SN Level-3-260C-168 HR -40 to 85 64BR111 DS64BR111SQ/NOPB.A Active Production WQFN (RTW) | 24 1000 | SMALL T&R Yes SN Level-3-260C-168 HR -40 to 85 64BR111 DS64BR111SQE/NOPB Active Production WQFN (RTW) | 24 250 | SMALL T&R Yes SN Level-3-260C-168 HR -40 to 85 64BR111 DS64BR111SQE/NOPB.A Active Production WQFN (RTW) | 24 250 | SMALL T&R Yes SN Level-3-260C-168 HR -40 to 85 64BR111 (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 1-Aug-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 1-Aug-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DS64BR111SQ/NOPB WQFN RTW 24 1000 208.0 191.0 35.0 DS64BR111SQE/NOPB WQFN RTW 24 250 208.0 191.0 35.0 Pack Materials-Page 2

www.ti.com PACKAGE OUTLINE C 24X 0.3 0.2 24X 0.5 0.3

0.8 MAX

(0.1) TYP 0.05 0.00 20X 0.5 2.5 2X 2.5 2.6 0.1 A 4.1 3.9 B 4.1 3.9 WQFN - 0.8 mm max heightRTW0024A PLASTIC QUAD FLATPACK - NO LEAD 4222815/A 03/2016 PIN 1 INDEX AREA 0.08 C SEATING PLANE 6 13 7 12 24 19 (OPTIONAL) PIN 1 ID 0.1 C A B 0.05 C EXPOSED THERMAL PAD NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. SCALE 3.000

www.ti.com EXAMPLE BOARD LAYOUT

0.07 MIN

0.07 MAX

24X (0.25) 24X (0.6) ( ) TYP VIA 0.2 20X (0.5) (3.8) (3.8) (1.05) ( 2.6) (R ) TYP 0.05 (1.05) WQFN - 0.8 mm max heightRTW0024A PLASTIC QUAD FLATPACK - NO LEAD 4222815/A 03/2016 SYMM 7 12 1924 SYMM LAND PATTERN EXAMPLE SCALE:15X NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED METAL SOLDER MASK OPENINGSOLDER MASK DETAILS NON SOLDER MASK DEFINED (PREFERRED)

www.ti.com EXAMPLE STENCIL DESIGN 24X (0.6) 24X (0.25) 20X (0.5) (3.8) (3.8) 4X ( 1.15) (0.675) TYP (0.675) TYP (R ) TYP0.05 WQFN - 0.8 mm max heightRTW0024A PLASTIC QUAD FLATPACK - NO LEAD 4222815/A 03/2016 NOTES: (continued) 5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SYMM METAL TYP SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 25: 78% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SCALE:20X SYMM 7 12 1924

IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you fully indemnify TI and its representatives against any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale, TI’s General Quality Guidelines, or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. Unless TI explicitly designates a product as custom or customer-specified, TI products are standard, catalog, general purpose devices. TI objects to and rejects any additional or different terms you may propose. IMPORTANT NOTICE Copyright © 2025, Texas Instruments Incorporated Last updated 10/2025

Selected Specification

Texas Instruments DS64BR111 overview.

Summary

Ultra Low Power 6.4 Gbps 2-Channel Repeaters with Input Equalization and Output De-Emphasis

Description

Ultra Low Power 6.4 Gbps 2-Channel Repeaters with Input Equalization and Output De-Emphasis

Source title DS64BR111 Datasheet(PDF) - Texas Instruments

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DS64BR111 Ultra Low Pwr 6.4 Gbps 2-Chan Repeatr w/Input Equal datasheet (Rev. C)

Document overview

Technical content

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ELECTRICAL CHARACTERISTICS

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0 TiepintoGND througha 1 KΩ resistor

1 TiepintoVDD througha 1 KΩ resistor

5 R 0 0000 0111 = 0x07 11 FR4 20 inchtrace

6 R R 0001 0101 = 0x15 12 FR4 25 inchtrace

7 R Float 0000 1011 = 0x0B 14 FR4 25 inchtrace

8 R 1 0000 1111 = 0x0F 15 7m 30AWG Cable

9 Float 0 0101 0101 = 0x55 15 FR4 30 inchtrace

10 Float R 0001 1111 = 0x1F 18 8m 30 AWG Cable

11 Float Float 0010 1111 = 0x2F 20 10m 30 AWG Cable

12 Float 1 0011 1111 = 0x3F 22 10m -12m, Cable

5 Float 0 000 011 1000 0

7 Float R 011 011 1000 -6

8 Float 1 101 011 1000 -9

9 R 0 000 101 1200 -0

11 R R 011 101 1200 -6

12 R 1 101 101 1200 -9

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APPLICATION INFORMATION

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0 CRC EN AddressMap EEPROM > Reserved COUNT[3] COUNT[2] COUNT[1] COUNT[0]

256 Bytes

2 EE Burst[7] EE Burst[6] EE Burst[5] EE Burst[4] EE Burst[3] EE Burst[2] EE Burst[1] EE Burst[0]

0 CRC EN AddressMap EEPROM > RES COUNT[3] COUNT[2] COUNT[1] COUNT[0]Description Present 256 Bytes

2 Max Max Max Max Max Max Max Max

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2 EEPROM reading R 1:EEPROM Loading

1 Reserved RWS setbitto0

0 Reserved RWS setbitto0

2 LOS Select R/W LOS MonitorSelection

6 Reserved Setbitto0

5 LOS override Yes LOS pinoverrideenable(1);

4 LOS overridevalue Yes 1:Normal Operation

3 PWDN Inputs Yes 1:PWDN

1 Reserved

0 Reserved Yes Setbitto0

5 TX_DIS Override 1:OverrideUse Reg 0x04[4:3]

4 TX_DIS Value 1:TX Disabled

3 TX_DIS Value

2 Reserved Setbitto0

4 Reserved Yes Setbitto1

3 CRC SlaveMode [1]:CRC Disable(No CRC Check)

0 CRC Enable SlaveCRC Trigger

5 ResetSMBus SelfclearingresetforSMBus masterstate

6 OverrideIdle Yes [1]:Overrideby Channel-see Reg 0x13 and

5 Reserved Yes Setbitto0

4 OverrideIDLE Yes [1]:ForceIDLE by Channel-see Reg 0x0E and

3 Reserved Yes Setbitto0

2 OverrideOut Mode [1]:Enable Output Mode controlforindividual

1 OverrideDEM Yes

5 Reserved Setbitto0

4 Reserved Setbitto0

4 IdleSelect Yes ForceIDLE valuewhen overridebitisset(reg

6 Reserved Yes Setbitto1

26 SubmitDocumentationFeedback Copyright© 2011–2013,Texas InstrumentsIncorporated

3 Reserved Setbitto0

6 OverrideFastIdle Yes

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20 GHz Bandwidth

100 Ohm Differential Stripline

100 Ohm Differential Impedance

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REVISION HISTORY

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