DS42MB200

DS42MB200 Dual 4.25Gbps 2:1/1:2 CML Mux/Buffer w/Transmit Pre-Emph & Rcve Equal datasheet (Rev. G)

Document overview

• Manufacturer or author: Texas Instruments, Incorporated [SNOSAT8,G]
• PDF pages: 17

Technical content

PRE_S LO_0 ± MUX_S0 SIA_0 ± SIB_0 ± LB0A LB0B SOA_0 ± EQ EQ EQ SOB_0 ±LI_0 ± PRE_S PRE_L PRE_S LO_1 ± MUX_S1 SIA_1 ± SIB_1 ± LB1A LB1B SOA_1 ± EQ EQ EQ SOB_1 ±LI_1 ± PRE_S PRE_L Pre-emphasis Control PreL_0 PreS_1 PreS_0 PreL_1 PRE_S PRE_L VCC GND Port 0 Port 1 RSV DS42MB200 www.ti.com SNOSAT8G –JANUARY 2006–REVISED APRIL 2013 DS42MB200Dual4.25Gbps2:1/1:2CMLMux/BufferwithTransmitPre-Emphasisand ReceiveEqualization Check forSamples: DS42MB200 1FEATURES DESCRIPTION The DS42MB200 is a dual signalconditioning2:1 2• 1– 4.25Gbps FullyDifferentialData Paths multiplexerand 1:2fan-outbufferdesignedforuse in• FixedInputEqualization backplane redundancy applications. Signal

• Programmable Output Pre-emphasis conditioningfeaturesincludeinputequalizationand programmable outputpre-emphasisthatenabledata• IndependentSwitch and LineSide Pre- communicationinFR4 backplanesup to 4.25 Gbps.emphasis Controls Each inputstagehas a fixedequalizertoreduceISI• Programmable Switch-sideLoopback Mode distortionfromboardtraces.
• On-chip Terminations Alloutputdrivershave 4 selectablesteps of pre-• +3.3V Dupply emphasistocompensate fortransmissionlossesfrom
• ESD RatingHBM 6 kV longFR4 backplanesand reduce deterministicjitter. The pre-emphasis levels can be independently• Lead-lessWQFN-48 Package controlledforthe line-sideand switch-sidedrivers.(7mmx7mmx0.8mm, 0.5mm Pitch) The internalloopbackpathsfrom switch-sideinputto• –40°C to+85°C OperatingTemperature Range switch-sideoutputenableat-speedsystem testing.All receiverinputsare internallyterminatedwith100Ω APPLICATIONS differentialterminatingresistors.Alldriveroutputsare internallyterminatedwith50Ω toVCC .• Backplane Driveror Cable Driver
• Redundancy and SignalConditioning

Applications

• XAUI FunctionalBlock Diagram Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsof Texas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2Alltrademarksarethepropertyoftheirrespectiveowners. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 2006–2013,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.

LI_0+ 50 50 1.5V LI_0- Input stage +EQ M U X M U X 50501.5V 50501.5V M U X SOA_0+ SOA_0- SOB_0+ SOB_0- SIA_0+ SIA_0- SIB_0+ SIB_0- LO_0+ LO_0- 50 50 50 50 50 50 PreL_0 PreL_1 PreS_0 PreS_1 PRE_L PRE_S LB0A LB0B MUX_S0 DS42MB200 VCC VCC PRE_L PRE_S PRE_S CML driver CML driver Pre-emphasis Control CML driver Input stage +EQ Input stage +EQ LI_1+ 50 50 1.5V LI_1- Input stage +EQ M U X M U X M U X SOA_1+ SOA_1- SOB_1+ SOB_1- SIA_1+ SIA_1- SIB_1+ SIB_1- LO_1+ LO_1- 50 50 50 50 50 50 LB1A LB1B MUX_S1 VCC pins GND pins and DAP PRE_L PRE_S PRE_S CML driver CML driver CML driver Input stage +EQ Input stage +EQ PORT 0 PORT 1 VCC VCC VCC VCC 50501.5V 50501.5V DS42MB200 SNOSAT8G –JANUARY 2006–REVISED APRIL 2013 www.ti.com SimplifiedBlock Diagram

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13 14 15 16 17 18 2019 21 22 48 47 46 45 44 43 4142 40 39 VCC SOB_0- SOB_0+ GND LI_0+ LI_0- VCC LO_1+ LO_1- GND 36PreL1 WQFN-48 Top View Shown DAP = GND 12PreL0 SIA_1+ LB1A SOA_1+ SOA_1- VCC SIB_1+ SIB_1- GND SIA_1- MUX_S1 LB1B VCC SOA_0- LB0A SIA_0- SIA_0+ GND SIB_0- SIB_0+ VCC LB0B SOA_0+ VCC MUX_S0 VCC LO_0- LO_0+ GND LI_1- LI_1+ VCC SOB_1+ RSV SOB_1- PreS0 PreS1 DS42MB200 www.ti.com SNOSAT8G –JANUARY 2006–REVISED APRIL 2013 Connection Diagram Figure1. See Package Number NJU0048D PIN DESCRIPTIONS Pin Name Pin Number I/O Description LINE SIDE HIGH SPEED DIFFERENTIAL IO's LI_0+ 6 I Invertingand non-invertingdifferentialinputsofport_0atthelineside.LI_0+and LI_0− have an LI_0− 7 internal50Ω connectedtoan internalreferencevoltage.See Figure7. LO_0+ 33 O Invertingand non-invertingdifferentialoutputsofport_0atthelineside.LO_0+ and LO_0 − have an LO_0 − 34 internal50Ω connectedtoVCC . LI_1+ 30 I Invertingand non-invertingdifferentialinputsofport_1atthelineside.LI_1+and LI_1− have an LI_1− 31 internal50Ω connectedtoan internalreferencevoltage.See Figure7. LO_1+ 9 O Invertingand non-invertingdifferentialoutputsofport_1atthelineside.LO_1+ and LO_1 − have an LO_1 − 10 internal50Ω connectedtoVCC . SWITCH SIDE HIGH SPEED DIFFERENTIAL IO's SOA_0+ 46 O Invertingand non-invertingdifferentialoutputsofmux_0 attheswitch_Aside.SOA_0+ and SOA_0 − SOA_0 − 45 have an internal50Ω connectedtoVCC . SOB_0+ 4 O Invertingand non-invertingdifferentialoutputsofmux_0 attheswitch_Bside.SOB_0+ and SOB_0 − SOB_0 − 3 have an internal50Ω connectedtoVCC . SIA_0+ 40 I Invertingand non-invertingdifferentialinputstothemux_0 attheswitch_Aside.SIA_0+ and SIA_0− SIA_0− 39 have an internal50Ω connectedtoan internalreferencevoltage.See Figure7. SIB_0+ 43 I Invertingand non-invertingdifferentialinputstothemux_0 attheswitch_Bside.SIB_0+ and SIB_0− SIB_0− 42 have an internal50Ω connectedtoan internalreferencevoltage.See Figure7. SOA_1+ 22 O Invertingand non-invertingdifferentialoutputsofmux_1 attheswitch_Aside.SOA_1+ and SOA_1 − SOA_1 − 21 have an internal50Ω connectedtoVCC . SOB_1+ 28 O Invertingand non-invertingdifferentialoutputsofmux_1 attheswitch_Bside.SOB_1+ and SOB_1 − SOB_1 − 27 have an internal50Ω connectedtoVCC . Copyright© 2006–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:DS42MB200

SNOSAT8G –JANUARY 2006–REVISED APRIL 2013 www.ti.com PIN DESCRIPTIONS (continued) Pin Name Pin Number I/O Description SIA_1+ 16 I Invertingand non-invertingdifferentialinputstothemux_1 attheswitch_Aside.SIA_1+ and SIA_1− SIA_1− 15 have an internal50Ω connectedtoan internalreferencevoltage.See Figure7. SIB_1+ 19 I Invertingand non-invertingdifferentialinputstothemux_1 attheswitch_Bside.SIB_1+ and SIB_1− SIB_1− 18 have an internal50Ω connectedtoan internalreferencevoltage.See Figure7. CONTROL (3.3VLVCMOS) MUX_S0 37 I A logiclowatMUX_S0 selectsmux_0 toswitchB.MUX_S0 isinternallypulledhigh.Defaultstatefor mux_0 isswitchA. MUX_S1 13 I A logiclowatMUX_S1 selectsmux_1 toswitchB.MUX_S1 isinternallypulledhigh.Defaultstatefor mux_1 isswitchA. PREL_0 12 I PREL_0 and PREL_1 selecttheoutputpre-emphasisofthelinesidedrivers(LO_0± and LO_1 ±). PREL_1 1 PREL_0 and PREL_1 areinternallypulledhigh.See Table3 forlinesidepre-emphasislevels. PRES_0 36 I PRES_0 and PRES_1 selecttheoutputpre-emphasisoftheswitchsidedrivers(SOA_0 ±,SOB_0 ±, PRES_1 25 SOA_1 ± and SOB_1 ±).PRES_0 and PRES_1 areinternallypulledhigh.See Table4 forswitchside pre-emphasislevels. LB0A 47 I A logiclowatLB0A enablestheinternalloopbackpathfromSIA_0± toSOA_0 ±.LB0A isinternally pulledhigh. LB0B 48 I A logiclowatLB0B enablestheinternalloopbackpathfromSIB_0± toSOB_0 ±.LB0B isinternally pulledhigh. LB1A 23 I A logiclowatLB1A enablestheinternalloopbackpathfromSIA_1± toSOA_1 ±.LB1A isinternally pulledhigh. LB1B 24 I A logiclowatLB1B enablestheinternalloopbackpathfromSIB_1± toSOB_1 ±.LB1B isinternally pulledhigh. RSV 26 I Reservepintosupportfactorytesting.Thispincan be leftopen,ortiedtoGND, ortiedtoGND throughan externalpull-downresistor. POWER VCC 2,8,14,20, P VCC = 3.3V± 5%. 29,35,38, Each VCC pinshouldbe connectedtotheVCC planethrougha lowinductancepath,typicallywitha 44 vialocatedas closeas possibletothelandingpad oftheVCC pin. Itisrecommended tohave a 0.01μF or0.1μF,X7R, size-0402bypasscapacitorfromeach VCC pin togroundplane. GND 5,11,17,32, P Ground reference.Each groundpinshouldbe connectedtothegroundplanethrougha low 41 inductancepath,typicallywitha vialocatedas closeas possibletothelandingpad oftheGND pin. GND DAP P DieAttachPad (DAP) isthemetalcontactatthebottomside,locatedatthecenteroftheWQFN-48 package.Itshouldbe connectedtotheGND planewithatleast4 viatolowerthegroundimpedance and improvethethermalperformanceofthepackage. FunctionalDescription The DS42MB200 isa signalconditioning2:1multiplexerand a 1:2bufferdesignedtosupportportredundancyup to4.25Gbps. Each inputstagehas a fixedequalizerthatprovidesequalizationtocompensate about5 dB of transmissionlossfroma shortbackplanetrace(about10 inchesbackplane).The outputdriverhas pre-emphasis (driver-sideequalization)to compensate the transmissionlossof the backplanethatitisdriving.The driver conditionstheoutputsignalsuch thatthelowerfrequencyand higherfrequencypulsesreachapproximatelythe same amplitudeat the end of the backplane,and minimizethe deterministicjittercaused by the amplitude disparity.The DS42MB200 provides4 stepsofuser-selectablepre-emphasisrangingfrom0,-3,-6and –9 dB to handle differentlengthsof backplane.Figure1 shows a driverpre-emphasiswaveform. The pre-emphasis durationis200ps nominal,correspondsto0.8bit-widthat4 Gbps. The pre-emphasislevelsofswitch-sideand line-sidecan be individuallyprogrammed. The highspeed inputsareself-biasedtoabout1.5V and aredesignedforAC couplingallowingtheDS42MB200 to be directlyinsertedintothe datapathwithoutany limitation.The idealAC couplingcapacitorvalueisoften based on thelowestfrequencycomponent embedded withintheseriallink.A typicalAC couplingcapacitorvalue ranges between 100 and 1000nF, some specificationswithscrambled data may requirea largercoupling capacitorforoptimalperformance.To reduceunwanted parasiticsaroundand withintheAC couplingcapacitor,a body sizeof0402 isrecommended. Figure5 shows theAC couplingcapacitorplacementinan AC testcircuit. The inputsare compatibleto most AC couplingdifferentialsignalssuch as LVDS, LVPECL and CML. See Figure7 fordetails.

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www.ti.com SNOSAT8G –JANUARY 2006–REVISED APRIL 2013 Table1. LOGIC TABLE FOR MULTIPLEX CONTROLS MUX_S0 Mux Function 0 MUX_0 selectswitch_Binput,SIB_0±. 1 (default) MUX_0 selectswitch_Ainput,SIA_0±. MUX_S1 Mux Function 0 MUX_1 selectswitch_Binput,SIB_1±. 1 (default) MUX_1 selectswitch_Ainput,SIA_0±. Table2. LOGIC TABLE FOR LOOPBACK Controls LB0A Loopback Function 0 EnableloopbackfromSIA_0± toSOA_0 ±. 1 (default) Normal mode. Loopback disabled. LB0B Loopback Function 0 EnableloopbackfromSIB_0± toSOB_0 ±. 1 (default) Normal mode. Loopback disabled. LB1A Loopback Function 0 EnableloopbackfromSIA_1± toSOA_1 ±. 1 (default) Normal mode. Loopback disabled. LB1B Loopback Function 0 EnableloopbackfromSIB_1± toSOB_1 ±. 1 (default) Normal mode. Loopback disabled. Table3. LINE-SIDE PRE-EMPHASIS CONTROLS De-Emphasis LevelinPre-Emphasis LevelinmV PP Pre-Emphasis indB TypicalFR4 boardPreL_[1:0] mV PP(VODB) (VODPE/VODB) trace(VODPE) 0 0 1200 1200 0 10 inches 0 1 1200 850 −3 20 inches 1 0 1200 600 −6 30 inches 1 1 1200 426 −9 40 inches (default) Table4. SWITCH-SIDE PRE-EMPHASIS CONTROLS De-Emphasis LevelinPre-Emphasis LevelinmV PP Pre-Emphasis indB TypicalFR4 boardPreS_[1:0] mV PP(VODB) (VODPE/VODB) trace(VODPE) 0 0 1200 1200 0 10 inches 0 1 1200 850 −3 20 inches 1 0 1200 600 −6 30 inches 1 1 1200 426 −9 40 inches (default) Copyright© 2006–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:DS42MB200

1-bit 1 to N bits 1-bit 1 to N bits 0 dB -3 dB -6 dB -9 dB DS42MB200 SNOSAT8G –JANUARY 2006–REVISED APRIL 2013 www.ti.com Figure2. DriverPre-Emphasis DifferentialWaveform (showing all4 pre-emphasissteps) These deviceshave limitedbuilt-inESD protection.The leadsshouldbe shortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamage totheMOS gates. AbsoluteMaximum Ratings (1)(2) SupplyVoltage(VCC ) −0.3Vto4V CMOS/TTL InputVoltage −0.3Vto(VCC +0.3V) CML Input/OutputVoltage −0.3Vto(VCC +0.3V) JunctionTemperature +125°C StorageTemperature −65°C to+150°C Lead Temperature(Soldering,4 sec.) +260°C ThermalResistance,θJA 33.7°C/W ThermalResistance,θJC-top 20.7°C/W ThermalResistance,θJC-bottom 5.8°C/W ThermalResistance,ΦJB 18.2°C/W ESD RatingHBM, 1.5kΩ,100 pF 6 kV ESD RatingMachine Model 250V (1) “AbsoluteMaximum Ratings”aretheratingsbeyond whichthesafetyofthedevicecannotbe verified.They arenotmeant toimplythat thedeviceshouldbe operatedattheselimits. (2) IfMilitary/Aerospacespecifieddevicesarerequired,pleasecontacttheTexas InstrumentsSalesOffice/Distributorsforavailabilityand specifications. Recommended OperatingRatings Min Typ Max Units SupplyVoltage(VCC -GND) 3.135 3.3 3.465 V SupplyNoiseAmplitude(10Hz to2 GHz) 20 mV PP AmbientTemperature -40 85 °C Case Temperature 100 °C

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www.ti.com SNOSAT8G –JANUARY 2006–REVISED APRIL 2013 ElectricalCharacteristics Over recommended operatingsupplyand temperaturerangesunlessotherwisespecified. Symbol Parameter Conditions Min Typ (1) Max Units LVCMOS DC SPECIFICATIONS VIH HighLevelInput 2.0 VCC +0.3 VVoltage VIL Low LevelInput −0.3 0.8 VVoltage IIH HighLevelInput VIN = VCC −10 10 µACurrent IIL Low LevelInputCurrent VIN = GND 75 94 124 µA R PU Pull-HighResistance 35 kΩ RECEIVER SPECIFICATIONS VID DifferentialInput AC CoupledDifferentialSignal VoltageRange Below 1.25Gbps 100 1750 mV P-P At1.25Gbps –3.125Gbps 100 1560 mV P-P Above 3.125Gbps 100 1200 mV P-P Thisparameterisnotproductiontested. VICM Common Mode Voltage Measured atreceiverinputsreferencetoground. 1.3 VatReceiverInputs R ITD InputDifferential On-chipdifferentialterminationbetween IN+ or 84 100 116 ΩTermination IN−.(2) DRIVER SPECIFICATIONS VODB OutputDifferential R L = 100Ω ±1% VoltageSwing without PRES_1=PRES_0=0 Pre-Emphasis PREL_1=PREL_0=0 1000 1200 1400 mV P-PDriverpre-emphasisdisabled. RunningK28.7patternat4.25Gbps.(3) See Figure6 fortestcircuit. VPE OutputPre-Emphasis R L = 100Ω ±1% VoltageRatio RunningK28.7patternat4.25Gbps (3) 20*log(VODPE/VODB) PREx_[1:0]=00 0 dB PREx_[1:0]=01 −3 dB PREx_[1:0]=10 −6 dB PREx_[1:0]=11 −9 dB x=S forswitchsidepre-emphasiscontrol x=L forlinesidepre-emphasiscontrol See Figure2 on waveform. See Figure6 fortestcircuit. tPE Pre-EmphasisWidth(4) Testedat−9 dB pre-emphasislevel,PREx[1:0]=11 x=S forswitchsidepre-emphasiscontrol 125 200 250 psx=L forlinesidepre-emphasiscontrol See Figure5 on measurement condition. R OTSE OutputTermination On-chipterminationfromOUT+ orOUT − toVCC 42 50 58 Ω R OTD OutputDifferential On-chipdifferentialterminationbetween OUT+ and 100 ΩTermination OUT − ΔR OTSE Mis-MatchinOutput Mis-matchinoutputterminationsatOUT+ and 5 %TerminationResistors OUT − VOCM OutputCommon Mode 2.4 2.9 VVoltage (1) Typicalparametersmeasured atVCC = 3.3V,TA = 25°C. They areforreferencepurposesand arenotproduction-tested. (2) IN+ and IN− aregenericnames refertoone ofthemany pairsofcomplimentaryinputsoftheDS42MB200. OUT+ and OUT − are genericnames refertoone ofthemany pairsofthecomplimentaryoutputsoftheDS42MB200. DifferentialinputvoltageVID isdefined as |IN+–IN−|.DifferentialoutputvoltageVOD isdefinedas |OUT+ –OUT −|. (3) K28.7patternisa 10-bitrepeatingpatternofK28.7code group{0011111000}K28.5patternisa 20-bitrepeatingpatternof+K28.5 and −K28.5code groups{1100000101 001111 1010} (4) Specifiedby desighand characterizationusingstatisticalanalysis. Copyright© 2006–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:DS42MB200

SNOSAT8G –JANUARY 2006–REVISED APRIL 2013 www.ti.com ElectricalCharacteristics(continued) Over recommended operatingsupplyand temperaturerangesunlessotherwisespecified. Symbol Parameter Conditions Min Typ (1) Max Units POWER DISSIPATION PD Power Dissipation VDD = 3.465V Alloutputsterminatedby 100Ω ±1%. 1 WPREL_[1:0]=0,PRES_[1:0]=0 RunningPRBS 27-1patternat4.25Gbps AC CHARACTERISTICS tR DifferentialLow toHigh Measured witha clock-likepatternat100 MHz, 80 psTransitionTime between 20% and 80% ofthedifferentialoutput voltage.Pre-emphasisdisabled.tF DifferentialHightoLow Transitiontimeismeasured withfixtureas shown inTransitionTime 80 psFigure6,adjustedtoreflectthetransitiontimeatthe outputpins. tPLH DifferentialLow toHigh Measured at50% differentialvoltagefrominputto 0.5 2 nsPropagationDelay output. tPHL DifferentialHightoLow 0.5 2 nsPropagationDelay tSKP PulseSkew (5) |tPHL –tPLH | 20 ps tSKO OutputSkew (6)(5) Differenceinpropagationdelayamong datapathsin 200 psthesame device. tSKPP Part-to-PartSkew (5) Differenceinpropagationdelaybetween thesame outputfromdevicesoperatingunderidentical 500 ps condition. tSM Mux SwitchTime Measured fromVIH orVILofthemux-controlor loopbackcontrolto50% ofthevaliddifferential 1.8 6 ns output. RJ DeviceRandom See Figure6 fortestcircuit. Jitter(7)(5) Alternating-1-0pattern. Pre-emphasisdisabled. At1.25Gbps 2 psrms At4.25Gbps 2 psrms DJ DeviceDeterministic See Figure6 fortestcircuit. Jitter(8)(5) Pre-emphasisdisabled. At4.25Gbps, PRBS7 patternforDS42MB200@ – 40° to85°C 35 pspp DR MAX Maximum Data Rate(5) Testedwithalternating-1-0pattern 4.25 Gbps (5) Specifiedby desighand characterizationusingstatisticalanalysis. (6) tSKO isthemagnitudedifferenceinthepropagationdelaysamong datapathsbetween switchA and switchB ofthesame portand similardatapathsbetween port0 and port1.An example istheoutputskew among datapathsfromSIA_0± toLO_0 ±,SIB_0± to LO_0 ±,SIA_1± toLO_1 ± and SIB_1± toLO_1 ±.Anotherexample istheoutputskew among datapathsfromLI_0± toSOA_0 ±,LI_0± to SOB_0 ±,LI_1± toSOA_1 ± and LI_1± toSOB_1 ±.tSKO alsoreferstothedelayskew oftheloopbackpathsofthesame portand between similardatapathsbetween port0 and port1.An example istheoutputskew among datapathsSIA_0± toSOA_0 ±,SIB_0± to (7) Deviceoutputrandom jitterisa measurement oftherandom jittercontributionfromthedevice.Itisderivedby theequationsqrt(RJOUT RJIN 2),where RJOUT istherandom jittermeasured attheoutputofthedeviceinpsrms,RJIN istherandom jitterofthepatterngenerator drivingthedevice. (8) Deviceoutputdeterministicjitterisa measurement ofthedeterministicjittercontributionfromthedevice.Itisderivedby theequation (DJOUT –DJIN),where DJOUT isthepeak-to-peakdeterministicjittermeasured attheoutputofthedeviceinpspp,DJIN isthepeak-to- peak deterministicjitterofthepatterngeneratordrivingthedevice.

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50+-1% 50 +-1% Pattern Generator Oscilloscope or Jitter Measurement Instrument50: TLVCC GND Coax Coax 50: TL < 2" DC Block 1000 mVpp Differential OUT+ OUT- IN+ IN- R D M U X DS42MB200 EQ INPUT TLine Coax Coax DC Block DS42MB200 Test Fixture 25-inch VODPE3 1-bit 1 to N bits 1-bit 1 to N bits -9 dB 20% tPE 80% 50% VID 50% VOD tPLH tPHL IN OUT 80% 20% 80% 20% tR tF VODB DS42MB200 www.ti.com SNOSAT8G –JANUARY 2006–REVISED APRIL 2013 Timing Diagrams Figure3. DriverOutput TransitionTime Figure4. PropagationDelay from inputtooutput Figure5. Testconditionforoutputpre-emphasisduration Figure6. AC TestCircuit Copyright© 2006–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:DS42MB200

M U X 25-inch FR4 board trace Pattern Generator, 4 Gb/s 2 -1 pattern7 PE=0dB 40-inch FR4 trace 50 ps/DIV 200 mV/DIV Data eye after 25-inch FR4 trace 50 ps/DIV 200 mV/DIV 50 ps/DIV 200 mV/DIV Data eye after DS42MB200 50 ps/DIV 200 mV/DIV Data eye from pattern generator VCC 3.9k IN + EQ 180 pF IN - 1.5V DS42MB200 SNOSAT8G –JANUARY 2006–REVISED APRIL 2013 www.ti.com Figure7. ReceiverInputTerminationand BiasingCircuit APPLICATIONS INFORMATION The DS42MB200 inputequalizerprovidesequalizationto compensate about 5 dB of transmissionlossfrom a shortbackplanetransmissionline.For characterizationpurposes,a 25-inchFR4 coupledmicro-stripboardtrace isused in placeof the shortbackplanelink.The 25-inchmicrostripboard tracehas approximately5 dB of attenuationbetween 375 MHz and 1.875GHz, representingcloselythetransmissionlossoftheshortbackplane transmissionline.The 25-inchmicrostripisconnectedbetween thepatterngeneratorand thedifferentialinputsof theDS42MB200 forAC measurements. FinishedTrace Separationbetween DielectricConstantTrace Length DielectricHeightH Loss TangentWidth W Traces εR 25 inches 8.5mil 11.5mil 6 mil 3.8 0.022 Figure8. Data inputand outputeye patternswithdriversetto0 dB pre-emphasis

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ASIC or FPGA with integrated SerDes ASIC TD RD HT HR SerDes REFCLK Clock ASIC or FPGA with integrated SerDes Line Cards PHY PC R_CLK T_ CLK TD RD HT HR REFCLK R_CLK T_ CLK DS42MB200 Mux/Buf Clock Distribution OUT+ OUT- IN+ IN- DS42MB200 R DEQ M U X 25-inch FR4 board trace Pattern Generator, 4 Gb/s 2 -1 pattern7 PE = 9 dB 40-inch FR4 trace 50 ps/DIV 200 mV/DIV Data eye after 25-inch FR4 trace 50 ps/DIV 200 mV/DIV Data eye from pattern generator 50 ps/DIV 200 mV/DIV Data eye after DS42MB200 50 ps/DIV 200 mV/DIV DS42MB200 www.ti.com SNOSAT8G –JANUARY 2006–REVISED APRIL 2013 Figure9. Data inputand outputeye patternswithdriversetto9dB pre-emphasis Figure10. Applicationdiagram (showing datapaths ofport0) Copyright© 2006–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:DS42MB200

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REVISION HISTORY

Changes from RevisionF (April2013)toRevisionG Page

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www.ti.com 1-Nov-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) DS42MB200TSQ/NOPB Active Production WQFN (NJU) | 48 250 | SMALL T&R Yes SN Level-3-260C-168 HR -40 to 85 42MB200 DS42MB200TSQ/NOPB.A Active Production WQFN (NJU) | 48 250 | SMALL T&R Yes SN Level-3-260C-168 HR -40 to 85 42MB200 DS42MB200TSQ/NOPB.B Active Production WQFN (NJU) | 48 250 | SMALL T&R - Call TI Call TI -40 to 85 (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 1-Aug-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 1-Aug-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DS42MB200TSQ/NOPB WQFN NJU 48 250 208.0 191.0 35.0 Pack Materials-Page 2

www.ti.com SQA48D (Rev A)

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