DS42MB100 4.25-Gbps 2:1/1:2 CML MUX/Buffer With Transmit Pre-Emphasis and Receive Equalization datasheet (Rev. H)
Document overview
- Manufacturer or author: Texas Instruments, Incorporated [SNLS244,H]
- PDF pages: 24
Technical content
DE_S MUX LB1 EQ EQ EQ DE_S DEL _0 VCC GND RSV EQS EQL Line Side Switch Side IN0 +- IN1 +- LB0 OUT0 +- OUT1 +- DE _L DE_S DEL_1 DES_0 DES_1 -IN + OUT +- DE_L Pre-emphasis Control Product Folder Sample & Buy T echnical Documents Tools & Software Support & Community DS42MB100 SNLS244H – SEPTEMBER 2006– REVISED JANUARY 2016 DS42MB1004.25-Gbps2:1/1:2CMLMUX/Buffer WithTransmitPre-EmphasisandReceiveEqualization
1 Features 3 Description
The DS42MB100 device is a signal conditioning 2:1 1• 2:1 Multiplexer and 1:2 Buffer multiplexer and 1:2 fan-out buffer designed for use in• 0.25-Gbps to 4.25-Gbps Fully Differential Data backplane-redundancy or cable driving applications.Paths Signal conditioning features include continuous time
- Fixed Input Equalization linear equalization (CTLE) and programmable output pre-emphasis that enable data communication in FR4• Programmable Output Pre-Emphasis backplane up to 4.25 Gbps. Each input stage has a• Independent Pre-Emphasis Controls fixed equalizer to reduce ISI distortion from board
- Programmable Loopback Modes traces.
- On-Chip Terminations All output drivers have four selectable levels of pre-
- ESD Rating of 6-kV HBM emphasis to compensate for transmission losses from long FR4 backplane or cable attenuation reducing• 3.3-V Supply deterministic jitter. The pre-emphasis levels can be• Lead-Less WQFN-36 Package independently controlled for the line-side and switch-
- –40°C to +85°C Operating Temperature Range side drivers. The internal loopback paths from switch- side input to switch-side output enable at-speed 2 Applications system testing. All receiver inputs are internally terminated with 100-Ω differential terminating• Backplane Drivers or Cable Drivers resistors. All driver outputs are internally terminated• Redundancy and Signal Conditioning Applications with 50-Ω terminating resistors to VCC.
- CPRI/OBSAI Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) DS42MB100 WQFN (36) 6.00 mm × 6.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Simplified Block Diagram An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.
SNLS244H – SEPTEMBER 2006– REVISED JANUARY 2016 www.ti.com Table of Contents
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision G (April 2013) to Revision H Page
- Added Pin Configuration and Functions section, Storage Conditions table, ESD Ratings table, Thermal Information table, Parameter Measurement Information section, Feature Description section, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Changes from Revision F (April 2013) to Revision G Page
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10 11 12 13 14 15 17 16 18 36 35 34 33 32 31 2930 28 LB1 IN1+ IN1- VCC OUT1+ OUT1- GND MUX GND VCC GND GND IN+GND LB0GNDOUT+OUT-VCC VCC DEL_0 RSVGNDVCCGNDGND EQS DES_0 IN-
27 DEL_1
DAP= GND IN0- IN0+ OUT0- OUT0+ DES_1 DS42MB100 www.ti.com SNLS244H – SEPTEMBER 2006– REVISED JANUARY 2016
5 Pin Configuration and Functions
NAME NO. LINE SIDE HIGH SPEED DIFFERENTIAL I/Os IN+ 33 Inverting and non-inverting differential inputs at the line side. IN+ and IN− have an internal 50 ΩIIN− 34 connected to an internal reference voltage. See Figure 8. OUT+ 30 Inverting and non-inverting differential outputs at the line side. OUT+ and OUT− have an internalOOUT− 31 50 Ω connected to VCC. SWITCH SIDE HIGH SPEED DIFFERENTIAL I/Os IN0+ 6 Inverting and non-inverting differential inputs to the MUX at the switch side. IN0+ and IN0− haveIIN0− 7 an internal 50 Ω connected to an internal reference voltage. See Figure 8. IN1+ 25 Inverting and non-inverting differential inputs to the MUX at the switch side. IN1+ and IN1− haveIIN1− 24 an internal 50 Ω connected to an internal reference voltage. See Figure 8. OUT0+ 3 Inverting and non-inverting differential outputs at the switch side. OUT0+ and OUT0− have anOOUT0− 4 internal 50 Ω connected to VCC. OUT1+ 22 Inverting and non-inverting differential outputs at the switch side. OUT1+ and OUT1− have anOOUT1− 21 internal 50 Ω connected to VCC. CONTROL (3.3-V LVCMOS) DEL_0 18 DEL_0 and DEL_1 select the output pre-emphasis of the line side drivers (OUT±).IDEL_1 27 DEL_0 and DEL_1 are internally pulled high. DES_0 10 DES_0 and DES_1 select the output pre-emphasis of the switch side drivers (OUT0±, OUT1±).IDES_1 1 DES_0 and DES_1 are internally pulled high. A logic low enables the input equalizer on the line side. EQL is internally pulled high. Default isEQL 11 I with EQ disabled. A logic low enables the input equalizer on the switch side. EQS is internally pulled high. DefaultEQS 36 I is with EQ disabled. A logic low at LB0 enables the internal loopback path from IN0± to OUT0±. LB0 is internallyLB0 28 I pulled high. A logic low at LB1 enables the internal loopback path from IN1± to OUT1±. LB1 is internallyLB1 26 I pulled high. MUX 19 I A logic low at MUX selects IN1±. MUX is internally pulled high. Default state for MUX is IN0±. Copyright © 2006–2016, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: DS42MB100
SNLS244H – SEPTEMBER 2006– REVISED JANUARY 2016 www.ti.com Pin Functions (continued) PIN I/O DESCRIPTION NAME NO. Reserve pin to support factory testing. This pin can be left open, or tied to GND, or tied to GNDRSV 17 I through an external pull-down resistor. POWER 2, 8, 9, 12, Ground reference. Each ground pin should be connected to the ground plane through a low GND 14, 16, 20, P inductance path, typically with a via located as close as possible to the landing pad of the GND 29, 35 pin. DAP is the metal contact at the bottom side, located at the center of the WQFN package. It GND DAP P should be connected to the GND plane with at least 16 via to lower the ground impedance and improve the thermal performance of the package. VCC = 3.3 V ± 5%. Each VCC pin should be connected to the VCC plane through a low inductance path, typically with5, 13, 15,VCC P a via located as close as possible to the landing pad of the VCC pin.23, 32 It is recommended to have a 0.01 μF or 0.1 μF, X7R, size-0402 bypass capacitor from each VCC pin to ground plane.
6 Specifications
6.1 Absolute Maximum Ratings
see(1)(2) MIN MAX UNIT Supply voltage (VCC) –0.3 4 V CMOS/TTL input voltage –0.3 VCC + 0.3 V CML input/output voltage –0.3 VCC + 0.3 V Junction temperature 150 °C Lead temperature (soldering, 4 seconds) 260 °C Storage temperature, Tstg –65 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications.
6.2 ESD Ratings
Human-body model (HBM), 1.5 kΩ, 100 pF, per ANSI/ESDA/JEDEC JS- ±6000001(1) V(ESD) Electrostatic discharge VCharged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1250 Machine model ±350 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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6.3 Recommended Operating Ratings
Supply voltage (VCC – GND) 3.135 3.3 3.465 V Supply noise amplitude (10 Hz to 2 GHz) 100 mVPP Ambient temperature –40 85 °C Case temperature 100 °C
6.4 Thermal Information
THERMAL METRIC(1) NJK (WQFN) UNIT
36 PINS
RθJA Junction-to-ambient thermal resistance(2) 32.8 °C/W RθJC(top) Junction-to-case (top) thermal resistance 14.3 °C/W RθJB Junction-to-board thermal resistance 6.2 °C/W ψJT Junction-to-top characterization parameter 0.2 °C/W ψJB Junction-to-board characterization parameter 6.1 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 1.9 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. (2) Thermal resistances are based on having 16 thermal relief vias on the DAP pad under the 0 airflow condition.
6.5 Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified. PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT LVCMOS DC SPECIFICATIONS VIH High level input voltage 2 VCC + 0.3 V VIL Low level input voltage –0.3 0.8 V IIH High level input current VIN = VCC –10 10 µA IIL Low level input current VIN = GND 75 94 124 µA RPU Pull-high resistance 35 kΩ RECEIVER SPECIFICATIONS AC coupled differential Below 1.25 Gbps 100 1750 Differential input voltage signal. Between 1.25 Gbps–3.125 Gbps 100 1560VID mVP-Prange(2) This parameter is not Above 3.125 Gbps 100 1200tested at production. Common-mode voltageVICM Measured at receiver inputs reference to ground. 1.3 Vat receiver inputs Input differentialRITD On-chip differential termination between IN+ or IN−. 84 100 116 Ωtermination(3) (1) Typical parameters measured at VCC = 3.3 V, TA = 25°C, and represent most likely parametric norms at the time of product characterization. The typical specifications are not ensured. (2) This parameter is specified by design and/or characterization. It is not tested in production. (3) IN+ and IN− are generic names refer to one of the many pairs of complimentary inputs of the DS42MB100. OUT+ and OUT− are generic names refer to one of the many pairs of the complimentary outputs of the DS42MB100. Differential input voltage VID is defined as |IN+–IN−|. Differential output voltage VOD is defined as |OUT+–OUT−|. Copyright © 2006–2016, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: DS42MB100
SNLS244H – SEPTEMBER 2006– REVISED JANUARY 2016 www.ti.com Electrical Characteristics (continued) Over recommended operating supply and temperature ranges unless otherwise specified. PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT DRIVER SPECIFICATIONS RL = 100 Ω ±1% DES_1 = DES_0 = 0Output differential DEL_1 = DEL_0 = 0VODB voltage swing without 1100 1300 1500 mVP-PDriver pre-emphasis disabled.pre-emphasis(4) Running K28.7 pattern at 4.25 Gbps. See Figure 6 for test circuit. Running K28.7 pattern DEx_[1:0] = 01 –3at DEx_[1:0] = 10 –64.25 Gbps Output pre-emphasis x = S for switch side voltage ratio pre-emphasis controlVPE dB20 × log (VODPE / x = L for line side pre- VODB) emphasis control DEx_[1:0] = 11 –9See Figure 9 on waveform. See Figure 6 for test circuit. Tested at −9-dB pre-emphasis level, DEx[1:0] = 11 x = S for switch side pre-emphasis controlTPE Pre-emphasis width 125 188 250 psx = L for line side pre-emphasis control See Figure 3 on measurement condition. ROTSE Output termination(3) On-chip termination from OUT+ or OUT− to VCC 42 50 58 Ω Output differentialROTD On-chip differential termination between OUT+ and OUT− 100 Ωtermination ΔROTS Mismatch in output Mismatch in output terminations at OUT+ and OUT− 5% E termination resistors Output common modeVOCM 2.7 Vvoltage POWER DISSIPATION VDD = 3.3 V at 25°C All outputs terminated by 100 Ω ±1%.PD Power dissipation 0.45 WDEL_[1:0] = 0, DES_[1:0] = 0 Running PRBS 27– 1 pattern at 4.25 Gbps AC CHARACTERISTICS See Figure 6 for test At 0.25 Gbps 2 circuit. At 1.25 Gbps 2RJ Device random jitter(5) Alternating 1-0 pattern. psrms EQ and pre-emphasis At 4.25 Gbps 2disabled. See Figure 6 for test Between 0.25 andDevice deterministic circuit.DJ 4.25 Gbps with PRBS7 pattern for 35 psp-pjitter(6) EQ and pre-emphasis DS42MB100 at –40°C to 85°Cdisabled DR Data rate(2) Tested with alternating 1-0 pattern 0.25 4.25 Gbps (4) K28.7 pattern is a 10-bit repeating pattern of K28.7 code group {001111 1000} K28.5 pattern is a 20-bit repeating pattern of +K28.5 and −K28.5 code groups {110000 0101 001111 1010} (5) Device output random jitter is a measurement of the random jitter contribution from the device. It is derived by the equation sqrt(RJOUT 2 – RJIN 2), where RJOUT is the total random jitter measured at the output of the device in psrms, RJIN is the random jitter of the pattern generator driving the device. (6) Device output deterministic jitter is a measurement of the deterministic jitter contribution from the device. It is derived by the equation (DJOUT – DJIN), where DJOUT is the total peak-to-peak deterministic jitter measured at the output of the device in psp-p, DJIN is the peak- to-peak deterministic jitter of the pattern generator driving the device.
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6.6 Switching Characteristics
transition time at the output pins. Differential low to high propagation Measured at 50% differential voltage from inputtPLH 1 nsdelay to output. Difference in propagation delay among datatSKO Output skew(1) 100 pspaths in the same device. among data paths IN0± to OUT0± and IN1± to OUT1±. Figure 1. Driver Output Transition Time Figure 2. Propagation Delay From Input To Output
Figure 3. Test Condition For Output Pre-Emphasis Duration
6.7 Typical Characteristics
Figure 4. PRBS-7, Pre-Emphasis = 0 dB at 4 Gbps Figure 5. PRBS-7, Pre-Emphasis = –9 dB at 4 Gbps
7 Parameter Measurement Information
Figure 6. AC Test Circuit
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8 Detailed Description
8.1 Overview
8.2 Functional Block Diagram
Figure 7. Simplified Block Diagram
8.3 Feature Description
- CML Inputs and EQ
- Multiplexer and Loopback Control
- CML Drivers and Pre-Emphasis Control Copyright © 2006–2016, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Links: DS42MB100
8.3.1 CML inputs and EQ
internal receiver input termination and bias circuit. Figure 8. Receiver Input Termination and Bias Circuit AC coupling capacitor value is often based on the lowest frequency component embedded within the serial link. capacitor placement in an AC test circuit. Table 1. EQ Controls for Line and Switch Inputs 1 (default) Normal mode. Equalization disabled.
8.3.2 Multiplexer and Loopback Control
Table 2 and Table 3 provide details about how to configure the DS42MB100 multiplexer and loopback settings. Table 2. Logic Table for Multiplex Controls 0 MUX select switch input IN1±. 1 (default) MUX select switch input IN0±. Table 3. Logic Table for Loopback Controls 0 Enable loopback from IN0± to OUT0±. 1 (default) Normal mode. Loopback disabled. 0 Enable loopback from IN1± to OUT1±. 1 (default) Normal mode. Loopback disabled.
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8.3.3 CML Drivers and Pre-Emphasis Control
4.25 Gbps. The pre-emphasis levels of switch-side and line-side can be individually programmed. Figure 9. Driver Pre-Emphasis Differential Waveform (Showing All 4 Pre-Emphasis Steps) Table 4. Line-Side Pre-Emphasis Controls Table 5. Switch-Side Pre-Emphasis Controls
9 Application and Implementation
validate and test their design implementation to confirm system functionality.
9.1 Application Information
9.2 Typical Application
A typical application for the DS42MB100 is shown in Figure 10 and Figure 11. Figure 10. Network Switch System With Redundancy
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Figure 11. DS42MB100 Connection Block Diagram
9.2.1 Design Requirements
place of the short backplane link. A block diagram of this example is shown in Figure 12.
Figure 12. Block Diagram of DS42MB100 Application Example connected between the pattern generator and the differential inputs of the DS42MB100 for AC measurements. Table 6. Input Trace Parameters with similar trace width, separation, and dielectric characteristics, is placed at the DS42MB100 output. list of critical areas for consideration and study during design.
- Use 100-Ω impedance traces. Generally these are very loosely coupled to ease routing length differences.
- Place AC-coupling capacitors near to the receiver end of each channel segment to minimize reflections.
- The maximum body size for AC-coupling capacitors is 0402.
- Back-drill connector vias and signal vias to minimize stub length.
- Use reference plane vias to ensure a low inductance path for the return current.
9.2.2 Detailed Design Procedure
- The DS42MB100 should be configured to provide the correct MUX and buffer routes in order to satisfy
input from the line card is buffered to both Switch Card 0 (OUT0±) and Switch Card 1 (OUT1±).
- The DS42MB100 is designed to be placed at an offset location with respect to the overall channel
–9 dB of transmit pre-emphasis.
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9.2.3 Application Curves
measured locations can be referenced back to the labeled points provided in Figure 12.
- Point (A): Output signal of source pattern generator
- Point (B): Input to DS42MB100 after 25 inches of FR4 trace from source
- Point (C): Output of DS42MB100 driver
- Point (D): Signal after 40 inches of FR4 trace from DS42MB100 driver The source signal is a PRBS-7 pattern at 4 Gbps. For the long output traces, the eye after 40 inches of output FR4 trace is significantly improved by adding –9 dB of pre-emphasis.
Figure 14. Eye Measured at Point (B)Figure 13. Eye Measured at Point (A) Figure 15. Eye Measured at Point (C), Figure 16. Eye Measured at Point (D),
Figure 17. Eye Measured at Point (C), Figure 18. Eye Measured at Point (D),
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10 Power Supply Recommendations
Figure 11 for further details.
11 Layout
11.1 Layout Guidelines
is provided in AN-1187 Leadless Leadframe Package (LLP), SNOA401.
11.2 Layout Example
Figure 19. No Pullback WQFN, Single Row Reference Diagram Table 7. No Pullback WQFN Stencil Aperture Summary for DS42MB100
Figure 20. 36-Pin WQFN Stencil Example of Via and Opening Placement
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following: AN-1187 Leadless Leadframe Package (LLP), SNOA401
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.
12.3 Trademarks
E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Copyright © 2006–2016, Texas Instruments Incorporated Submit Documentation Feedback 19 Product Folder Links: DS42MB100
www.ti.com 10-Nov-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) DS42MB100TSQ/NOPB Active Production WQFN (NJK) | 36 250 | SMALL T&R Yes SN Level-3-260C-168 HR -40 to 85 42MB100 DS42MB100TSQ/NOPB.A Active Production WQFN (NJK) | 36 250 | SMALL T&R Yes SN Level-3-260C-168 HR -40 to 85 42MB100 (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1
PACKAGE MATERIALS INFORMATION www.ti.com 1-Aug-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION www.ti.com 1-Aug-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DS42MB100TSQ/NOPB WQFN NJK 36 250 208.0 191.0 35.0 Pack Materials-Page 2
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