DS40MB200

DS40MB200 Dual 4-Gbps 2:1/1:2 CML MUX/Buffer With Transmit Pre-Emphasis and Receive Equalization datasheet (Rev. K)

Document overview

• Manufacturer or author: Texas Instruments, Incorporated [SNLS144,K]
• PDF pages: 25

Technical content

DS40MB200 Dual 4-Gbps 2:1/1:2 CML MUX/Buffer With Transmit Pre-Emphasis and Receive Equalization

1 Features

• 1-Gbps to 4-Gbps Low Jitter Operation
• Fixed Input Equalization
• Programmable Output Pre-Emphasis
• Independent Switch and Line Side Pre-Emphasis Controls
• Programmable Switch-Side Loopback Mode
• On-Chip Terminations
• 3.3-V Supply
• ESD Rating of 6-kV HBM
• 48-leadless WQFN Package (7 mm × 7 mm)
• 0°C to +85°C Operating Temperature Range

2 Applications

• Backplane or Cable Driver
• Redundancy and Signal Conditioning Applications
• XAUI

3 Description

The DS40MB200 device is a dual signal conditioning 2:1 multiplexer (MUX) and 1:2 fan-out buffer designed for use in backplane-redundancy applications. Signal conditioning features include continuous time linear equalization (CTLE) and programmable output pre- emphasis, extending data communication in FR4 backplanes at rates up to 4 Gbps. Each input stage has a fixed equalizer to reduce intersymbol interference distortion from board traces. All output drivers have four selectable steps of pre- emphasis to compensate for transmission losses from long FR4 backplanes and reduce deterministic jitter. The pre-emphasis levels can be independently controlled for the line-side and switch-side drivers. The internal loopback paths from switch-side input to switch-side output enable at-speed system testing. All receiver inputs are internally terminated with 100- Ω differential terminating resistors. All drivers are internally terminated with 50 Ω to VCC. Device Information PART NUMBER PACKAGE(1) BODY SIZE (NOM) DS40MB200 WQFN (48) 7.00 mm × 7.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. PRE_S LO_0 ± MUX_S0 SIA_0 ± SIB_0 ± LB0A LB0B SOA_0 ± EQ EQ EQ SOB_0 ±LI_0 ± PRE_S PRE_L PRE_S LO_1 ± MUX_S1 SIA_1 ± SIB_1 ± LB1A LB1B SOA_1 ± EQ EQ EQ SOB_1 ±LI_1 ± PRE_S PRE_L Pre-emphasis Control PreL_0 PreS_1 PreS_0 PreL_1 PRE_S PRE_L VCC GND Port 0 Port 1 RSV All CML inputs and outputs must be AC coupled for optimal performance. Simplified Block Diagram DS40MB200 SNLS144K – JUNE 2005 – REVISED MARCH 2024 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

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13 Mechanical, Packaging, and Orderable

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4 Pin Configuration and Functions

13 14 15 16 17 18 2019 21 22 48 47 46 45 44 43 4142 40 39 VCC SOB_0- SOB_0+ GND LI_0+ LI_0- VCC LO_1+ LO_1- GND 36PreL1 WQFN-48 DAP = GND 12PreL0 SIA_1+ LB1A SOA_1+SOA_1- VCC SIB_1+SIB_1- GND SIA_1- MUX_S1 LB1BVCC SOA_0-LB0A SIA_0-SIA_0+GNDSIB_0-SIB_0+VCCLB0B SOA_0+ VCC MUX_S0 VCC LO_0- LO_0+ GND LI_1- LI_1+ VCC SOB_1+ RSV SOB_1- PreS0 PreS1 Figure 4-1. NJU Package 48-Pin WQFN Top View Table 4-1. Pin Functions PIN I/O(1) DESCRIPTION(2) NAME NO. LINE-SIDE HIGH-SPEED DIFFERENTIAL I/Os LI_0+ LI_0− 7 I Inverting and noninverting differential inputs of port_0 at the line side. LI_0+ and LI_0− have an internal 50 Ω connected to an internal reference voltage. See Figure 7-1. LI_1+ LI_1− 31 I Inverting and noninverting differential inputs of port_1 at the line side. LI_1+ and LI_1− have an internal 50 Ω connected to an internal reference voltage. See Figure 7-1. LO_0+ LO_0− 34 O Inverting and noninverting differential outputs of port_0 at the line side. LO_0+ and LO_0− have an internal 50 Ω connected to VCC. LO_1+ LO_1− 10 O Inverting and noninverting differential outputs of port_1 at the line side. LO_1+ and LO_1− have an internal 50 Ω connected to VCC. SWITCH-SIDE HIGH SPEED-DIFFERENTIAL I/Os SIA_0+ SIA_0− 39 I Inverting and noninverting differential inputs to the mux_0 at the switch_A side. SIA_0+ and SIA_0− have an internal 50 Ω connected to an internal reference voltage. See Figure 7-1. SIA_1+ SIA_1− 15 I Inverting and noninverting differential inputs to the mux_1 at the switch_A side. SIA_1+ and SIA_1− have an internal 50 Ω connected to an internal reference voltage. See Figure 7-1. SIB_0+ SIB_0− 42 I Inverting and noninverting differential inputs to the mux_0 at the switch_B side. SIB_0+ and SIB_0− have an internal 50 Ω connected to an internal reference voltage. See Figure 7-1. SIB_1+ SIB_1− 18 I Inverting and noninverting differential inputs to the mux_1 at the switch_B side. SIB_1+ and SIB_1− have an internal 50 Ω connected to an internal reference voltage. See Figure 7-1. SOA_0+ SOA_0− 45 O Inverting and noninverting differential outputs of mux_0 at the switch_A side. SOA_0+ and SOA_0− have an internal 50 Ω connected to VCC. SOA_1+ SOA_1− 21 O Inverting and noninverting differential outputs of mux_1 at the switch_A side. SOA_1+ and SOA_1− have an internal 50 Ω connected to VCC. SOB_0+ SOB_0− 3 O Inverting and noninverting differential outputs of mux_0 at the switch_B side. SOB_0+ and SOB_0− have an internal 50 Ω connected to VCC. SOB_1+ SOB_1− 27 O Inverting and noninverting differential outputs of mux_1 at the switch_B side. SOB_1+ and SOB_1− have an internal 50 Ω connected to VCC. www.ti.com DS40MB200 SNLS144K – JUNE 2005 – REVISED MARCH 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: DS40MB200

Table 4-1. Pin Functions (continued) PIN I/O(1) DESCRIPTION(2) NAME NO. CONTROL (3.3-V LVCMOS) LB0A 47 I A logic low at LB0A enables the internal loopback path from SIA_0± to SOA_0±. LB0A is internally pulled high. LB0B 48 I A logic low at LB0B enables the internal loopback path from SIB_0± to SOB_0±. LB0B is internally pulled high. LB1A 23 I A logic low at LB1A enables the internal loopback path from SIA_1± to SOA_1±. LB1A is internally pulled high. LB1B 24 I A logic low at LB1B enables the internal loopback path from SIB_1± to SOB_1±. LB1B is internally pulled high. MUX_S0 37 I A logic low at MUX_S0 selects mux_0 to switch B. MUX_S0 is internally pulled high. Default state for mux_0 is switch A. MUX_S1 13 I A logic low at MUX_S1 selects mux_1 to switch B. MUX_S1 is internally pulled high. Default state for mux_1 is switch A. PREL_0 PREL_1 1 I PREL_0 and PREL_1 select the output pre-emphasis of the line side drivers (LO_0± and LO_1±). PREL_0 and PREL_1 are internally pulled high. See Table 7-3 for line side pre-emphasis levels. PRES_0 PRES_1 25 I PRES_0 and PRES_1 select the output pre-emphasis of the switch side drivers (SOA_0±, SOB_0±, SOA_1± and SOB_1±). PRES_0 and PRES_1 are internally pulled high. See Table 7-4 for switch side pre-emphasis levels. RSV 26 I Reserve pin to support factory testing. This pin can be left open, or tied to GND, or tied to GND through an external pull-down resistor. POWER GND 5, 11, 17, 32, 41 P Ground reference. Each ground pin must be connected to the ground plane through a low inductance path, typically with a via located as close as possible to the landing pad of the GND pin. GND DAP P Die Attach Pad (DAP) is the metal contact at the bottom side, located at the center of the WQFN-48 package. It must be connected to the GND plane with at least 4 via to lower the ground impedance and improve the thermal performance of the package. VCC 2, 8, 14, 20, 29, 35, 38, P VCC = 3.3 V ± 5%. Each VCC pin must be connected to the VCC plane through a low inductance path, typically with a via located as close as possible to the landing pad of the VCC pin. TI recommends to have a 0.01 μF or 0.1 μF, X7R, size-0402 bypass capacitor from each VCC pin to ground plane. (1) I = Input, O = Output, P = Power (2) All CML Inputs or Outputs must be AC coupled. DS40MB200 SNLS144K – JUNE 2005 – REVISED MARCH 2024 www.ti.com

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5 Specifications

5.1 Absolute Maximum Ratings

see(1) (2) MIN MAX UNIT Supply voltage (VCC) −0.3 4 V CMOS/TTL input voltage −0.3 VCC + 0.3 V CML input/output voltage −0.3 VCC + 0.3 V Junction temperature 125 °C Lead temperature (soldering, 4 sec) 260 °C Storage temperature, Tstg −65 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) If Military/Aerospace specified devices are required, contact the TI Sales Office/Distributors for availability and specifications.

5.2 ESD Ratings

V(ESD) Electrostatic discharge Human body model (HBM), 1.5 kΩ, 100 pF, per ANSI/ESDA/JEDEC JS-001(1) ±6000 V Machine model (MM), per JEDEC specification JESD22-A115-A ±250 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

5.3 Recommended Operating Ratings

Supply voltage (VCC – GND) 3.135 3.3 3.465 V Supply noise amplitude (10 Hz to 2 GHz) 20 mVPP Ambient temperature 0 85 °C Case temperature 100 °C

5.4 Thermal Information

THERMAL METRIC(1) DS40MB200 UNITNJU (WQFN)

48 PINS

RθJA Junction-to-ambient thermal resistance 32.3 °C/W RθJC(top) Junction-to-case (top) thermal resistance 15.2 °C/W RθJB Junction-to-board thermal resistance 9 °C/W ψJT Junction-to-top characterization parameter 0.2 °C/W ψJB Junction-to-board characterization parameter 9 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 2.5 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. www.ti.com DS40MB200 SNLS144K – JUNE 2005 – REVISED MARCH 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: DS40MB200

5.5 Electrical Characteristics

over recommended operating supply and temperature ranges (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT LVCMOS DC SPECIFICATIONS VIH High level input voltage 2 VCC + 0.3 V VIL Low level input voltage −0.3 0.8 V IIH High level input current VIN = VCC −10 10 µA IIL Low level input current VIN = GND 75 94 124 µA RPU Pull-high resistance 35 kΩ RECEIVER SPECIFICATIONS VID Differential input voltage range AC-coupled differential signal. This parameter is not production tested. Below 1.25 Gbps 100 1750 mVP-PAt 1.25 Gbps–3.125 Gbps 100 1560 Above 3.125 Gbps 100 1200 VICM Common mode voltage at receiver inputs Measured at receiver inputs reference to ground. 1.3 V RITD Input differential termination On-chip differential termination between IN+ or IN−. 84 100 116 Ω DRIVER SPECIFICATIONS VODB Output differential voltage swing without pre-emphasis RL = 100 Ω ±1% PRES_1 = PRES_0 = 0 PREL_1 = PREL_0 = 0 Driver pre-emphasis disabled. Running K28.7 pattern at 4 Gbps. See AC Test Circuit for test circuit. 1000 1200 1400 mVP-P VPE Output pre-emphasis voltage ratio 20 × log (VODPE / VODB) RL = 100 Ω ±1% Running K28.7 pattern at

4 Gbps(2)

x = S for switch side pre- emphasis control x = L for line side pre-emphasis control See Driver Pre-Emphasis Differential Waveform (Showing All 4 Pre-Emphasis Steps) on waveform. See AC Test Circuit for test circuit. PREx_[1:0] = 00 0 dB PREx_[1:0] = 01 −3 PREx_[1:0] = 10 −6 PREx_[1:0] = 11 −9 tPE Pre-emphasis width(3) Tested at −9-dB pre-emphasis level, PREx[1:0] = 11 x = S for switch side pre-emphasis control x = L for line side pre-emphasis control See Test Condition for Output Pre-Emphasis Duration on measurement condition. 125 200 250 ps ROTSE Output termination On-chip termination from OUT+ or OUT− to VCC (4) 42 50 58 Ω ROTD Output differential termination On-chip differential termination between OUT+ and OUT−(4) 100 Ω Δ ROTSE Mismatch in output termination resistors Mismatch in output terminations at OUT+ and OUT−(4) 5% VOCM Output common mode voltage 2.7 V POWER DISSIPATION PD Power dissipation VDD = 3.465 V All outputs terminated by 100 Ω ±1%. PREL_[1:0] = 0, PRES_[1:0] = 0 Running PRBS 27–1 pattern at 4 Gbps 1 W DS40MB200 SNLS144K – JUNE 2005 – REVISED MARCH 2024 www.ti.com

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5.5 Electrical Characteristics (continued)

over recommended operating supply and temperature ranges (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT AC CHARACTERISTICS RJ Device random jitter(5) (3) See AC Test Circuit for test circuit. Alternating-1-0 pattern. Pre-emphasis disabled. At 1.25 Gbps 2 psrms At 4 Gbps 2 DJ Device deterministic jitter(6) (3) See AC Test Circuit for test circuit. Pre-emphasis disabled. At 4 Gbps, PRBS7 pattern 30 psp-p DRMAX Maximum data rate(3) Tested with alternating-1-0 pattern 4 Gbps (1) Typical parameters measured at VCC = 3.3 V, TA = 25°C. They are for reference purposes and are not production-tested. (2) K28.7 pattern is a 10-bit repeating pattern of K28.7 code group {001111 1000} K28.5 pattern is a 20-bit repeating pattern of +K28.5 and –K28.5 code groups {110000 0101 001111 1010} (3) Specified by design and characterization using statistical analysis. (4) IN+ and IN− are generic names refer to one of the many pairs of complementary inputs of the DS40MB200. OUT+ and OUT− are generic names refer to one of the many pairs of the complimentary outputs of the DS40MB200. Differential input voltage VID is defined as |IN+–IN−|. Differential output voltage VOD is defined as |OUT+–OUT−|. (5) Device output random jitter is a measurement of the random jitter contribution from the device. It is derived by the equation sqrt (RJOUT 2 – RJIN 2), where RJOUT is the random jitter measured at the output of the device in psrms, RJIN is the random jitter of the pattern generator driving the device. (6) Device output deterministic jitter is a measurement of the deterministic jitter contribution from the device. It is derived by the equation (DJOUT – DJIN), where DJOUT is the peak-to-peak deterministic jitter measured at the output of the device in psp-p, DJIN is the peak-to-peak deterministic jitter of the pattern generator driving the device.

5.6 Switching Characteristics

over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT tR Differential low-to-high transition time Measured with a clock-like pattern at 100 MHz, between 20% and 80% of the differential output voltage. Pre-emphasis disabled. Transition time is measured with fixture as shown in AC Test Circuit, adjusted to reflect the transition time at the output pins. 80 ps tF Differential high-to-low transition time 80 ps tPLH Differential low-to-high propagation delay Measured at 50% differential voltage from input to output. 0.5 2 ns tPHL Differential high-to-low propagation delay 0.5 2 ns tSKP Pulse skew(2) |tPHL–tPLH| 20 ps tSKO Output skew(3) (2) Difference in propagation delay among data paths in the same device. 200 ps tSKPP Part-to-part skew(2) Difference in propagation delay between the same output from devices operating under identical condition. 500 ps tSM MUX switch time Measured from VIH or VIL of the mux-control or loopback control to 50% of the valid differential output. 1.8 6 ns (1) Typical parameters measured at VCC = 3.3 V, TA = 25°C. They are for reference purposes and are not production-tested. (2) Specified by design and characterization using statistical analysis. (3) tSKO is the magnitude difference in the propagation delays among data paths between switch A and switch B of the same port and similar data paths between port 0 and port 1. An example is the output skew among data paths from SIA_0± to LO_0±, SIB_0± to LO_0±, SIA_1± to LO_1± and SIB_1± to LO_1±. Another example is the output skew among data paths from LI_0± to SOA_0±, LI_0± to SOB_0±, LI_1± to SOA_1± and LI_1± to SOB_1±. tSKO also refers to the delay skew of the loopback paths of the same port and between similar data paths between port 0 and port 1. An example is the output skew among data paths SIA_0± to SOA_0±, SIB_0± to www.ti.com DS40MB200 SNLS144K – JUNE 2005 – REVISED MARCH 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: DS40MB200

80% 20% 80% 20% tR tF VODB Figure 5-1. Driver Output Transition Time 50% VID 50% VOD tPLH tPHL IN OUT Figure 5-2. Propagation Delay From Input to Output VODPE3 1-bit 1 to N bits 1-bit 1 to N bits -9 dB 20% tPE 80% Figure 5-3. Test Condition for Output Pre-Emphasis Duration DS40MB200 SNLS144K – JUNE 2005 – REVISED MARCH 2024 www.ti.com

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5.7 Typical Characteristics

Figure 5-4. PRBS-7, Pre-Emphasis = 0 dB at 4 Gbps 50 ps/div 100 mV/div Figure 5-5. PRBS-7, Pre-Emphasis = –9 dB at 4 Gbps

6 Parameter Measurement Information

50+-1% 50 +-1% Pattern Generator Oscilloscope or Jitter Measurement Instrument50: TLVCC GND Coax Coax 50: TL < 2" DC Block 1000 mVpp Differential OUT+ OUT- IN+ IN- R D M U X DS40MB200 EQ INPUT TLine Coax Coax DC Block DS40MB200 Test Fixture 25-inch Figure 6-1. AC Test Circuit www.ti.com DS40MB200 SNLS144K – JUNE 2005 – REVISED MARCH 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: DS40MB200

7 Detailed Description

7.1 Overview

The DS40MB200 is a signal conditioning 2:1 multiplexer and 1:2 buffer designed to support port redundancy with encoded or scrambled data rates between 1 and 4 Gbps. The DS40MB200 provides fixed equalization at the receive input and pre-emphasis control on the output in order to support signal reach extension.

7.2 Functional Block Diagram

LI_0+ 50 50 1.5V LI_0- Input stage +EQ M U X M U X 50501.5V 50501.5V M U X SOA_0+ SOA_0- SOB_0+ SOB_0- SIA_0+ SIA_0- SIB_0+ SIB_0- LO_0+ LO_0- 50 50 50 50 50 50 PreL_0 PreL_1 PreS_0 PreS_1 PRE_L PRE_S LB0A LB0B MUX_S0 DS40MB200 VCC VCC PRE_L PRE_S PRE_S CML driver CML driver Pre-emphasis Control CML driver Input stage +EQ Input stage +EQ LI_1+ 50 50 1.5V LI_1- Input stage +EQ M U X M U X M U X SOA_1+ SOA_1- SOB_1+ SOB_1- SIA_1+ SIA_1- SIB_1+ SIB_1- LO_1+ LO_1- 50 50 50 50 50 50 LB1A LB1B MUX_S1 VCC pins GND pins & DAP PRE_L PRE_S PRE_S CML driver CML driver CML driver Input stage +EQ Input stage +EQ PORT 0 PORT 1 VCC VCC VCC VCC 50501.5V 50501.5V DS40MB200 SNLS144K – JUNE 2005 – REVISED MARCH 2024 www.ti.com

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7.3 Feature Description

The DS40MB200 MUX buffer consists of several key blocks:

• CML Inputs and EQ
• Multiplexer and Loopback Control
• CML Drivers and Pre-Emphasis Control

7.3.1 CML Inputs and EQ

The high-speed inputs are self-biased to about 1.3 V at IN+ and IN- and are designed for AC coupling. See Reciever Input Termination and Bias Circuit for details about the internal receiver input termination and bias circuit. VCC 3.9k IN + EQ 180 pF IN - 1.5V Figure 7-1. Receiver Input Termination and Bias Circuit The inputs are compatible to most AC coupling differential signals such as LVDS, LVPECL, and CML. The DS40MB200 is not designed to operate with data rates below 1000 Mbps or with a DC bias applied to the CML inputs or outputs. Most high-speed links are encoded for DC balance and have been defined to include AC coupling capacitors, allowing the DS40MB200 to be inserted directly into the datapath without any limitation. The ideal AC-coupling capacitor value is often based on the lowest frequency component embedded within the serial link. A typical AC-coupling capacitor value ranges between 100 and 1000 nF. Some specifications with scrambled data may require a larger capacitor for optimal performance. To reduce unwanted parasitic effects around and within the AC-coupling capacitor, a body size of 0402 is recommended. AC Test Circuit shows the AC-coupling capacitor placement in an AC test circuit. Each input stage has a fixed equalizer that provides equalization to compensate about 5 dB (at 2 GHz) of transmission loss from a short backplane trace (about 10 inches backplane).

7.3.2 Multiplexer and Loopback Control

Table 7-1 and Table 7-2 provide details about how to configure the DS40MB200 multiplexer and loopback settings. Table 7-1. Logic Table for Multiplex Controls PIN PIN VALUE MUX FUNCTION MUX_S0 0 MUX_0 select switch_B input, SIB_0±. 1 (default) MUX_0 select switch_A input, SIA_0±. MUX_S1 0 MUX_1 select switch_B input, SIB_1±. 1 (default) MUX_1 select switch_A input, SIA_0±. Table 7-2. Logic Table for Loopback Controls PIN PIN VALUE LOOPBACK FUNCTION LB0A 0 Enable loopback from SIA_0± to SOA_0±. 1 (default) Normal mode. Loopback disabled. www.ti.com DS40MB200 SNLS144K – JUNE 2005 – REVISED MARCH 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: DS40MB200

Table 7-2. Logic Table for Loopback Controls (continued) PIN PIN VALUE LOOPBACK FUNCTION LB0B 0 Enable loopback from SIB_0± to SOB_0±. 1 (default) Normal mode. Loopback disabled. LB1A 0 Enable loopback from SIA_1± to SOA_1±. 1 (default) Normal mode. Loopback disabled. LB1B 0 Enable loopback from SIB_1± to SOB_1±. 1 (default) Normal mode. Loopback disabled.

7.3.3 CML Drivers and Pre-Emphasis Control

The output driver has pre-emphasis (driver-side equalization) to compensate the transmission loss of the backplane that it is driving. The driver conditions the output signal such that the lower frequency and higher frequency pulses reach approximately the same amplitude at the end of the backplane and minimize the deterministic jitter caused by the amplitude disparity. The DS40MB200 provides four steps of user-selectable pre-emphasis ranging from 0, –3, –6 and –9 dB to handle different lengths of backplane. Figure 7-2 shows a driver pre-emphasis waveform. The pre-emphasis duration is 200 ps nominal, corresponding to 0.8 unit intervals (UI) at 4Gbps. The pre-emphasis levels of switch-side and line-side can be individually programmed. VODB VODPE3 VODPE2 VODPE1 1-bit 1 to N bits 1-bit 1 to N bits 0 dB -3 dB -6 dB -9 dB Figure 7-2. Driver Pre-Emphasis Differential Waveform (Showing All 4 Pre-Emphasis Steps) Table 7-3. Line-Side Pre-Emphasis Controls PreL_[1:0] PRE-EMPHASIS LEVEL IN mVPP (VODB) DE-EMPHASIS LEVEL IN mVPP (VODPE) PRE-EMPHASIS IN dB (VODPE/VODB) TYPICAL FR4 BOARD TRACE 0 0 1200 1200 0 10 inches 0 1 1200 850 −3 20 inches 1 0 1200 600 −6 30 inches 1 1 (default) 1200 426 −9 40 inches Table 7-4. Switch-Side Pre-Emphasis Controls PreS_[1:0] PRE-EMPHASIS LEVEL IN mVPP (VODB) DE-EMPHASIS LEVEL IN mVPP (VODPE) PRE-EMPHASIS IN dB (VODPE/VODB) TYPICAL FR4 BOARD TRACE 0 0 1200 1200 0 10 inches 0 1 1200 850 −3 20 inches 1 0 1200 600 −6 30 inches 1 1 (default) 1200 426 −9 40 inches DS40MB200 SNLS144K – JUNE 2005 – REVISED MARCH 2024 www.ti.com

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8 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information

The DS40MB200 is a 2:1 MUX and 1:2 buffer that equalizes input data up to 4 Gbps and provides transmit pre-emphasis controls to improve overall signal reach. As a MUX buffer, the DS40MB200 is ideal for designs where there is a need for port sharing or redundancy as well as on-the-fly reorganization of routes and data connections.

8.2 Typical Application

A typical application for the DS40MB200 is shown in Figure 8-1 and Figure 8-2. Passive Backplane Switch ASIC SerDes Switch Card 1 Switch Card 2 Distribution LI SOA SOB LO SIA SIB ASIC or FPGA with integrated SerDes ASIC TD RD HT HR SerDes REFCLK Clock ASIC or FPGA with integrated SerDes Line Cards PHY PC R_CLK T_ CLK TD RD HT HR REFCLK R_CLK T_ CLK DS40MB200 Mux/Buf Clock Distribution Figure 8-1. System Diagram (Showing Data Paths of Port 0) www.ti.com DS40MB200 SNLS144K – JUNE 2005 – REVISED MARCH 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: DS40MB200

LI_0+ 50 50 1.5V LI_0- Input stage +EQ M U X M U X 5050 1.5V 5050 1.5V M U X SOA_0+ SOA_0- SOB_0+ SOB_0- SIA_0+ SIA_0- SIB_0+ SIB_0- 2x0.1 PF 0402-size 2x0.1 PF 0402-size 2x0.1 PF 0402-size LO_0+ LO_0- 50 50 50 50 50 50 PreL_0 PreL_1 PreS_0 PreS_1 PRE_L PRE_S LB0A LB0B MUX_S0 To Upstream receiver From Upstream transmitter From downstream transmitter From downstream transmitter To downstream receiver To downstream receiver Control Control DS40MB200 (Showing Port0) 4x0.1 PF X7R 0402-size 4x0.01 PF X7R 0402-size VCC pinsGND pins & DAP VCC VCC VCC PRE_L PRE_S PRE_S CML driver CML driver Pre-emphasis Control 3.3V CML driver Input stage +EQ Input stage +EQ RSV Figure 8-2. DS40MB200 Connection Block Diagram (Showing Data Paths of Port 0)

8.2.1 Design Requirements

In a typical design, the DS40MB200 equalizes a short backplane trace on its input, followed by a longer trace at the DS40MB200 output. In this application example, a 25-inch FR4 coupled micro-strip board trace is used in place of the short backplane link. A block diagram of this example is shown in Figure 8-3. DS40MB200 SNLS144K – JUNE 2005 – REVISED MARCH 2024 www.ti.com

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M U X 25-inch FR4 board trace Pattern Generator, 4 Gb/s 2 -1 pattern7 Pre-Emph 40-inch FR4 trace (A) (B) (C) (D) Figure 8-3. Block Diagram of DS40MB200 Application Example The 25-inch microstrip board trace has approximately 6 dB of attenuation between 375 MHz and 1.875 GHz, representing closely the transmission loss of the short backplane transmission line. The 25-inch microstrip is connected between the pattern generator and the differential inputs of the DS40MB200 for AC measurements. Table 8-1. Input Trace Parameters TRACE LENGTH FINISHED TRACE WIDTH W SEPARATION BETWEEN TRACES DIELECTRIC HEIGHT H DIELECTRIC CONSTANT εR LOSS TANGENT 25 inches 8.5 mil 11.5 mil 6 mil 3.8 0.022 The length of the output trace may vary based on system requirements. In this example, a 40-inch FR4 trace with similar trace width, separation, and dielectric characteristics is placed at the DS40MB200 output. As with any high-speed design, there are many factors which influence the overall performance. Following is a list of critical areas for consideration and study during design.

• Use 100-Ω impedance traces. Generally, these are very loosely coupled to ease routing length differences.
• Place AC-coupling capacitors near to the receiver end of each channel segment to minimize reflections.
• The maximum body size for AC-coupling capacitors is 0402.
• Back-drill connector vias and signal vias to minimize stub length.
• Use reference plane vias to ensure a low inductance path for the return current.

8.2.2 Detailed Design Procedure

For optimal design, the DS40MB200 must be configured to route incoming data correctly as well as to provide the best signal quality. The following design procedures must be observed: 1. The DS40MB200 must be configured to provide the correct multiplexer and buffer routes in order to satisfy system requirements. In order to set the appropriate multiplexer control settings, refer to Table 7-1. To configure the buffer control settings, refer to Table 7-2. For example, consider the case where the designer wishes to route the input from Switch Card A (SIA0_0±) to the output for the line card (LO_0±). To accomplish this, set MUX_S0 = 1 (select SIA0_0±). For the other direction from line card output to switch card, set LB0A = 1 and LB0B = 1 so that the input from the line-card is buffered to both Switch Card A (SOA_0±) and Switch Card B (SOB_0±). 2. The DS40MB200 is designed to be placed at an offset location with respect to the overall channel attenuation. To optimize performance, the multiplexer buffer transmit pre-emphasis can be tuned to extend the trace length reach while also recovering a solid eye opening. To tune transmit pre-emphasis on either the line card side or switch card side, refer to Table 7-3 and Table 7-4 for recommended pre-emphasis control settings according to the length of FR4 board trace connected at the DS40MB200 output. For example, if 40 inches of FR4 trace is connected to the switch card output, set PreS_[1:0] = (1, 1) for VOD = 1200 mVpp and –9 dB of transmit pre-emphasis. www.ti.com DS40MB200 SNLS144K – JUNE 2005 – REVISED MARCH 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: DS40MB200

8.2.3 Application Curves

Figure 8-4 through Figure 8-9 show how the signal integrity varies at different places in the data path. These measured locations can be referenced back to the labeled points provided in Figure 8-3.

• Point (A): Output signal of source pattern generator
• Point (B): Input to DS40MB200 after 25 inches of FR4 trace from source
• Point (C): Output of DS40MB200 driver
• Point (D): Signal after 40 inches of FR4 trace from DS40MB200 driver The source signal is a PRBS-7 pattern at 4 Gbps. For the long output traces, the eye after 40 inches of output FR4 trace is significantly improved by adding –9 dB of pre-emphasis. 50 ps/DIV 200 mV/DIV Figure 8-4. Eye Measured at Point (A) 50 ps/DIV 200 mV/DIV Figure 8-5. Eye Measured at Point (B) 50 ps/DIV 200 mV/DIV Figure 8-6. Eye Measured at Point (C), Pre-Emph = 0 dB 50 ps/DIV 200 mV/DIV Figure 8-7. Eye Measured at Point (D), Pre-Emph = 0 dB DS40MB200 SNLS144K – JUNE 2005 – REVISED MARCH 2024 www.ti.com

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Product Folder Links: DS40MB200

9 Power Supply Recommendations

The supply (V CC) and ground (GND) pins must be connected to power planes routed on adjacent layers of the printed circuit board. The layer thickness of the dielectric must be minimized so that the V CC and GND planes create a low inductance supply with distributed capacitance. Careful attention to supply bypassing through the proper use of bypass capacitors is required. A 0.01- μF or 0.1- μF bypass capacitor must be connected to each VCC pin such that the capacitor is placed as close to the V CC pins as possible. Smaller body-size capacitors, such as 0402 body size, can help facilitate proper component placement. Refer to the V CC pin connections in Figure 8-2 for further details.

10 Layout

10.1 Layout Guidelines

Use at least a four-layer board with a power and ground plane. Closely coupled differential lines of 100 Ω are typically recommended for differential interconnect. The closely coupled lines help to ensure that coupled noise will appear as common-mode and thus will be rejected by the receivers. Information on the WQFN style package is provided in AN-1187 Leadless Leadframe Package (LLP) (SNOA401).

10.2 Layout Examples

Stencil parameters such as aperture area ratio and the fabrication process have a significant impact on paste deposition. Inspection of the stencil prior to placement of the WQFN package is highly recommended to improve board assembly yields. If the via and aperture openings are not carefully monitored, the solder may flow unevenly through the DAP. Stencil parameters for aperture opening and via locations are shown in Figure 10-1. A layout example for the DS40MB200 DAP is shown in Figure 10-2, where 16 stencil openings are used for the DAP alongside nine vias to GND. Figure 10-1. No Pullback WQFN, Single Row Reference Diagram Table 10-1. No Pullback WQFN Stencil Aperture Summary for DS40MB200 DEVICE PIN COUNT MKT DWG PCB I/O PAD SIZE (mm) PCB PITCH (mm) PCB DAP SIZE (mm) STENCIL I/O APERTURE (mm) STENCIL DAP APERTURE (mm) NUMBER OF DAP APERTURE OPENINGS GAP BETWEEN DAP APERTURE (Dim A mm) DS40MB200 SNLS144K – JUNE 2005 – REVISED MARCH 2024 www.ti.com

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Figure 10-2. 48-Pin WQFN Stencil Example of Via and Opening Placement www.ti.com DS40MB200 SNLS144K – JUNE 2005 – REVISED MARCH 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: DS40MB200

11 Device and Documentation Support

11.1 Documentation Support

11.1.1 Related Documentation

For related documentation see the following:

• AN-1187 Leadless Leadframe Package (LLP), SNOA401

11.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

11.3 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

11.4 Trademarks

TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.

11.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

11.6 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions. NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision J (January 2016) to Revision K (March 2024) Page Changes from Revision I (March 2013) to Revision J (January 2016) Page

• Added Pin Configuration and Functions section, Storage Conditions table, ESD Ratings table, Thermal Information table, Parameter Measurement Information section, Feature Description section, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. DS40MB200 SNLS144K – JUNE 2005 – REVISED MARCH 2024 www.ti.com

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Product Folder Links: DS40MB200

www.ti.com 31-Oct-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) DS40MB200SQ/NOPB Active Production WQFN (NJU) | 48 250 | SMALL T&R Yes SN Level-3-260C-168 HR 0 to 85 40MB200 DS40MB200SQ/NOPB.A Active Production WQFN (NJU) | 48 250 | SMALL T&R Yes SN Level-3-260C-168 HR 0 to 85 40MB200 (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 1-Aug-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 1-Aug-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DS40MB200SQ/NOPB WQFN NJU 48 250 208.0 191.0 35.0 Pack Materials-Page 2

www.ti.com SQA48D (Rev A)

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