DS34LV86T 3V Enhanced CMOS Quad Differential Line Receiver datasheet (Rev. D)
Document overview
- Manufacturer or author: Texas Instruments, Incorporated [SNLS115,D]
- PDF pages: 16
Technical content
www.ti.com SNLS115D –JUNE 2000–REVISED APRIL 2013 DS34LV86T3VEnhancedCMOS QuadDifferentialLineReceiver Check forSamples: DS34LV86T 1FEATURES DESCRIPTION The DS34LV86T is a high speed quad differential• Low Power CMOS Design (30mW Typical) CMOS receiverthatmeets the requirementsof both• InteroperableWith Existing5V RS-422 TIA/EIA-422-B and ITU-T V.11. The CMOSNetworks DS34LV86T featurestypicallow staticICC of 9 mA
- IndustrialTemperature Range which makes itidealforbatterypowered and power consciousapplications.The Tri-Stateenables,EN,• Meets TIA/EIA-422-B(RS-422)and ITU-TV.11 allowthe deviceto be disabledwhen not inuse toRecommendation minimize power consumption. The dual enable• 3.3VOperation scheme allowsforflexibilityin turningreceiverson
- ±7V Common Mode Range @ VID = 3V and off.
- ±10V Common Mode Range @ VID = 0.2V The receiveroutput(RO) isensuredtobe High when the inputsare leftopen. The receivercan detect• ReceiverOPEN InputFailsafeFeature signalsas low as ±200 mV over the common mode• Ensured AC Parameter: range of ±10V. The receiveroutputs (RO) are– Maximum ReceiverSkew: 4 ns compatiblewithTTL and LVCMOS levels. – TransitionTime: 10 ns
- Pin Compatible With DS34C86T
- 32 MHz Toggle Frequency
- >6.5kESD Tolerance(HBM)
- AvailableinSOIC Packaging Connection Diagram Figure1. SOIC (Top View) See Package Number D Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsof Texas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 2000–2013,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.
SNLS115D –JUNE 2000–REVISED APRIL 2013 www.ti.com TRUTH TABLE (1) Enable Inputs Output EN RI+–RI− RO L X Z H VID ≥ +0.2V H H VID ≤ −0.2V L H Open † H (1) L = LogicLow H = LogicHigh X = Irrelevant Z = Tri-State † = Open, Not Terminated These deviceshave limitedbuilt-inESD protection.The leadsshouldbe shortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamage totheMOS gates. ABSOLUTE MAXIMUM RATINGS (1)(2) SupplyVoltage(VCC ) +7V EnableInputVoltage(EN) +7V ReceiverInputVoltage (VID:RI+,RI−) ±14V ReceiverInputVoltage (VCM :RI+,RI−) ±14V ReceiverOutputVoltage(RO) −0.5VtoVCC + 0.5V ReceiverOutputCurrent(RO) ±25 mA Maximum Package Power Dissipation@ +25°C D Package 1190 mW DerateD Package 9.8mW/ °C above +25°C StorageTemperatureRange -65°C to+150°C Lead TemperatureRange Soldering(4Seconds) +260°C ESD Ratings(HBM, 1.5k,100 pF) ReceiverInputsand Enables ≥6.5kV OtherPins ≥2 kV (1) AbsoluteMaximum Ratingsarethosevaluesbeyond whichthesafetyofthedevicecannotbe ensured.They arenotmeant toimplythat thedevicesshouldbe operatedattheselimits.The tableofElectricalCharacteristicsspecifiesconditionsofdeviceoperation. (2) IfMilitary/Aerospacespecifieddevicesarerequired,pleasecontacttheTexas InstrumentsSalesOffice/Distributorsforavailabilityand specifications. RECOMMENDED OPERATING CONDITIONS Min Typ Max Units SupplyVoltage(VCC ) 3.0 3.3 3.6 V OperatingFreeAir Temperature(TA) −40 +25 +85 °C
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www.ti.com SNLS115D –JUNE 2000–REVISED APRIL 2013 ELECTRICAL CHARACTERISTICS (1)(2) Over SupplyVoltageand OperatingTemperatureranges,unlessotherwisespecified. Symbol Parameter Conditions Pin Min Typ Max Units VTH DifferentialInputThreshold VOUT = VOH orVOL RI+, −200 ±17.5 +200 mV −7V < VCM < +7V RI− VHY Hysteresis VCM = 1.5V 35 mV VIH Minimum HighLevelInputVoltage 2.0 V EN VIL Minimum Low LevelInputVoltage 0.8 V R IN InputResistance VIN = −7V,+7V 5.0 8.5 kΩ (OtherInput= GND) IIN InputCurrent VIN = +10V 0 1.1 1.8 mA (OtherInput= 0V, RI+,VIN = +3V 0 0.27 mAPower On orVCC = 0V) RI− VIN = 0.5V −0.02 mA VIN = −3V 0 −0.43 mA VIN = −10V 0 −1.26 −2.2 mA IEN VIN = 0V toVCC EN ±1 μA VOH HighLevelOutputVoltage IOH = −6 mA, VID = +1V 2.4 3 V IOH = −6 mA, VID = OPEN VOH HighLevelOutputVoltage IOH = −100 μA,VID = +1V VCC − 0.1 V IOH = −100 μA,VID = OPEN VOL Low LevelOutputVoltage IOL = +6 mA, VID = −1V 0.13 0.5 VRO IOZ OutputTri-State VIN = VCC orGND ±50 μA Leakage EN = VIL Current ISC OutputShortCircuitCurrent VO = 0V,VID ≥ |200mV| −10 −35 −70 mA See (3) ICC Power SupplyCurrent No Load,AllRI+,RI− = Open, VCC 9 15 mA EN = VCC orGND (1) Currentintodevicepinsisdefinedas positive.Currentoutofdevicepinsisdefinedas negative.Allvoltagesarereferencedtoground exceptVID. (2) Alltypicalsaregivenfor:VCC = +3.3V,TA = +25°C. (3) Shortone outputata timetoground.Do notexceed package power dissipationratings. Copyright© 2000–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:DS34LV86T
SNLS115D –JUNE 2000–REVISED APRIL 2013 www.ti.com SWITCHING CHARACTERISTICS (1)(2)(3) Over SupplyVoltageand OperatingTemperatureranges,unlessotherwisespecified. Symbol Parameter Conditions Min Typ Max Units tPHL PropagationDelayHightoLow C L = 15 pF 6 17.5 35 ns See (Figure2 andtPLH PropagationDeIayLow toHigh 6 17.8 35 nsFigure3 ) tr RiseTime (20% to80%) 4.1 10 ns tf FallTime (80% to20%) 3.3 10 ns tPHZ DisableTime C L = 50 pF 40 ns See (Figure4 andtPLZ DisableTime 40 nsFigure5) tPZH EnableTime 40 ns tPZL EnableTime 40 ns tSK1 Skew, |tPHL − tPLH |See (4) C L = 15 pF 0.3 4 ns tSK2 Skew, PintoPinSee (5) 0.6 4 ns tSK3 Skew, ParttoPartSee (6) 7 17 ns fMAX Maximum OperatingFrequency C L = 15 pF 32 MHz See (7) (1) Alltypicalsaregivenfor:VCC = +3.3V,TA = +25°C. (2) Generatorwaveform foralltestsunlessotherwisespecified:f= 1 MHz, DutyCycle= 50%, ZO = 50Ω,tr ≤ 10 ns,tf≤ 10 ns. (3) C L includesprobeand jigcapacitance. (4) tSK1 isthe|tPHL − tPLH |ofa channel. (5) tSK2 isthemaximum skew between any two channelswithina device,on eitheredge. (6) tSK3 isthedifferenceinpropagationdelaytimesbetween any channelsofany devices.Thisspecification(maximum limit)appliesto deviceswithinVCC ±0.1Vofone another,anda DeltaTA = ±5°C (betweendevices)withintheoperatingtemperaturerange.This parameterisspecifiedby designand characterization. (7) Allchannelsswitching,outputdutycyclecriteriais40%/60% measured at50% Input= 1V to2V,50% DutyCycle,tr/tf≤ 5 ns.This parameterisensuredby designand characterization. PARAMETER MEASUREMENT INFORMATION Generatorwaveform foralltestsunlessotherwisespecified:f= 1 MHz, DutyCycle= 50%, ZO = 50Ω,tr ≤ 10 ns,tf≤ 10 ns. C L includesprobeand jigcapacitance. Figure2. ReceiverPropagationDelay and TransitionTime TestCircuit
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www.ti.com SNLS115D –JUNE 2000–REVISED APRIL 2013 PARAMETER MEASUREMENT INFORMATION (continued) Generatorwaveform foralltestsunlessotherwisespecified:f= 1 MHz, DutyCycle= 50%, ZO = 50Ω,tr ≤ 10 ns,tf≤ 10 ns. C L includesprobeand jigcapacitance. Figure3. ReceiverPropagationDelay and TransitionTime Waveform Figure4. ReceiverTri-StateTestCircuit Generatorwaveform foralltestsunlessotherwisespecified:f= 1 MHz, DutyCycle= 50%, ZO = 50Ω,tr ≤ 10 ns,tf≤ 10 ns. C L includesprobeand jigcapacitance. Figure5. ReceiverTri-StateOutput Enable and DisableWaveforms Copyright© 2000–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:DS34LV86T
SNLS115D –JUNE 2000–REVISED APRIL 2013 www.ti.com TYPICAL APPLICATION INFORMATION Generalapplicationguidelinesand hintsfordifferentialdriversreceiversmay be foundinthefollowingapplication notes: AN-214 (SNLA137 ),AN-457 (SNLA148 ),AN-805 (SNOA233 ),AN-847 (SNLA031 ),AN-903 (SNLA034 ),AN-912 (SNLA036 ),AN-916 (SNLA219 ) Power DecouplingRecommendations: Bypass caps must be used on power pins.High frequencyceramic (surfacemount isrecommended) 0.1μF inparaIIelwith0.01μF atthepower supplypin.A 10 μF orgreatersolid tantalumorelectrolyticshouldbe connectedatthepower entrypointon theprintedcircuitboard. R T isoptionalalthoughhighlyrecommended toreducereflection Figure6. TypicalReceiverConnections Figure7. TypicalReceiverOutput Waveforms
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www.ti.com SNLS115D –JUNE 2000–REVISED APRIL 2013 Figure8. TypicalReceiverInputCircuit Figure9. TypicalICC vs Frequency Figure10. IIN vs VIN (Power On, Power Off) Copyright© 2000–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:DS34LV86T
SNLS115D –JUNE 2000–REVISED APRIL 2013 www.ti.com Figure11. IOL vs VOL Figure12. IOH vs VOH
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www.ti.com SNLS115D –JUNE 2000–REVISED APRIL 2013
REVISION HISTORY
Changes from RevisionC (April2013)toRevisionD Page Copyright© 2000–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:DS34LV86T
www.ti.com 31-Oct-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) DS34LV86TM/NOPB Active Production SOIC (D) | 16 48 | TUBE Yes SN Level-1-260C-UNLIM -40 to 85 DS34LV86 TM DS34LV86TM/NOPB.A Active Production SOIC (D) | 16 48 | TUBE Yes SN Level-1-260C-UNLIM -40 to 85 DS34LV86 TM DS34LV86TMX/NOPB Active Production SOIC (D) | 16 2500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 85 DS34LV86 TM DS34LV86TMX/NOPB.A Active Production SOIC (D) | 16 2500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 85 DS34LV86 TM (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1
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PACKAGE MATERIALS INFORMATION www.ti.com 10-Aug-2026 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION www.ti.com 10-Aug-2026 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DS34LV86TMX/NOPB SOIC D 16 2500 367.0 367.0 35.0 Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION www.ti.com 10-Aug-2026 TUBE L - Tube length T - Tube height W - Tube width B - Alignment groove width *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) DS34LV86TM/NOPB D SOIC 16 48 495 8 4064 3.05 DS34LV86TM/NOPB.A D SOIC 16 48 495 8 4064 3.05 Pack Materials-Page 3
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