DS32EL0124

DS32EL0124/ELX0124 125MHz-312.5MHz FPGA-Link Deserializr w/DDR LVDS Para I/F datasheet (Rev. K)

Document overview

• Manufacturer or author: Texas Instruments, Incorporated [SNLS284,K]
• PDF pages: 36

Technical content

DS32EL0124,DS32ELX0124 www.ti.com SNLS284K –MAY 2008–REVISED APRIL 2013 DS32EL0124,DS32ELX0124125MHz-312.5MHzFPGA-LinkDeserializerwithDDRLVDS ParallelInterface Check forSamples: DS32EL0124 ,DS32ELX0124 1FEATURES KEY SPECIFICATIONS 2• 5-bitDDR LVDS ParallelData Interface • 1.25to3.125Gbps SerialData Rate

• Programmable Receive Equalization • 125 to312.5MHz DDR ParallelClock
• SelectableDC-Balance Decoder • -40° to+85°C Temperature Range
• SelectableDe-Scrambler • > 8 kV ESD (HBM) Protection
• Remote Sense forAutomatic Detectionand • 0.5UI Minimum InputJitterTolerance(1.25 NegotiationofLinkStatus Gbps)
• No ExternalReceiverReferenceClock DESCRIPTIONRequired The DS32EL0124/DS32ELX0124 integratesclock• LVDS ParallelInterface and data recoverymodules for high-speedserial• Programmable LVDS Output Clock Delay communication over FR-4 printedcircuitboard
• Supports Output Data-ValidSignaling backplanes,balancedcables,and opticalfiber.This easy-to-usechipsetintegratesadvanced signaland• Supports Keep-AliveClock Output clockconditioningfunctions,withan FPGA friendly• On Chip LC VCOs interface.
• Redundant SerialInput(ELX deviceonly) The DS32EL0124/DS32ELX0124 deserializesup to• Retimed SerialOutput (ELX deviceonly) 3.125 Gbps of high speed serialdata to 5 LVDS
• ConfigurablePLL Loop Bandwidth outputswithoutthe need foran externalreference clock. With DC-balance decoding enabled, the• ConfigurableviaSMBus applicationpayloadof 2.5 Gbps isdeserializedto 4• Loss ofLock and ErrorReporting LVDS outputs.
• 48-pinWQFN Package withExposed DAP The DS32EL0124/DS32ELX01214 deserializers featurea remote sense capabilityto automaticallyAPPLICATIONS signal link status conditionsto its companion
• Imaging:Industrial,MedicalSecurity,Printers DS32EL0421/ELX0421 serializerswithoutrequiring an additionalfeedbackpath.• Displays:LED Walls,Commercial The parallelLVDS interfaceofthesedevicesreduce• Video Transport FPGA I/Opins,board tracecountand alleviatesEMI• Communication Systems issues,when compared to traditionalsingle-ended• Testand Measurement widebus interfaces.
• IndustrialBus The DS32EL0124/ELX0124 isprogrammablethrough a SMBus interfaceas wellas throughcontrolpins. Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsof Texas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2Alltrademarksarethepropertyoftheirrespectiveowners. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 2008–2013,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.

DC_B RS VDD25 N/C N/C N/C GPIO2 N/C VDD3336 VDD2535 SMB_CS34 SCK33 SDA LOCK RESET N/C VDDPLL LF_CP LF_REF VDD25 RXOUT4-48 RXOUT4+47 RXOUT3-46 RXOUT3+45 RXOUT2- RXOUT2+ RXOUT1- RXOUT1+ RXOUT0- RXOUT0+ RXCLKOUT- RXCLKOUT+ N/C 24 N/C 23 N/C 22 N/C 21 N/C N/C VDD33 RXIN0- RXIN0+ VDD33 N/C N/C

49 DAP = GND

3.125 Gbps Data Payload

5 LVDS

ControlPLL Parallel to Serial Encoder LVDS Clock LVDS Interface LVDS Interface Control SMBus Redundant Driver DS32ELX0124 Serial to Parallel LVDS Interface LVDS Interface PLL Control LVDS Clock Control SMBus DS32EL0124,DS32ELX0124 SNLS284K –MAY 2008–REVISED APRIL 2013 www.ti.com TypicalApplication Connection Diagrams Figure1. WQFN Package

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LT_EN 2 GPIO0 3 GPIO1 4 DC_B RS VDD25 N/C N/C N/C GPIO2 RX_MUX_SEL VDD3336 VDD2535 SMB_CS34 SCK33 SDA LOCK RESET N/C VDDPLL LF_CP LF_REF VDD25 RXOUT4-48 RXOUT4+47 RXOUT3-46 RXOUT3+45 RXOUT2- RXOUT2+ RXOUT1- RXOUT1+ RXOUT0- RXOUT0+ RXCLKOUT- RXCLKOUT+ N/C 24 N/C 23 TXOUT- 22 TXOUT+ 21 RXIN1- RXIN1+ VDD33 RXIN0- RXIN0+ VDD33 VOD_CTRL N/C DS32EL0124,DS32ELX0124 www.ti.com SNLS284K –MAY 2008–REVISED APRIL 2013 Figure2. WQFN Package PIN DESCRIPTIONS Pin Name Pin Number I/O,Type Description VDD33 1,15,18,36 I,VDD 3.3Vsupply VDD25 7,25,35 I,VDD 2.5Vsupply VDD_PLL 28 I,VDD 3.3Vsupply LF_CP 27 Analog Loop filtercapacitorconnection LF_REF 26 Analog Loop filtergroundreference Exposed Pad 49 GND Exposed Pad must be connectedtoGND by 9 vias. CML I/O RxIN0+ 16 I,CML Non-invertingand invertinghighspeed CML differentialinputsofthe RxIN0- 17 deserializer.These inputsareinternallyterminated. RxIN1+ 19 I,CML DS32ELX0124 only.Non-invertingand invertinghighspeed CML RxIN1- 20 differentialinputsofthedeserializer.These inputsareinternallyterminated. TxOUT+ 21 O, CML DS32ELX0124 only.Retimedserializedhighspeed output.Non-inverting TxOUT- 22 and invertingspeed CML differentialoutputsofthedeserializer.These outputsareinternallyterminated. LVDS ParallelData Bus RxCLKOUT+ 37 O, LVDS Deserializeroutputclock.RxCLKOUT+/- arethenon-invertingand inverting RxCLKOUT- 38 LVDS recoveredclockoutputpins. RxOUT[0:4]+/- 39,40,41,42,43,44,45, O, LVDS Deserializeroutputdata.RxOUT[0:4]+/-arethenon-invertingand inverting 46,47,48 LVDS deserializedoutputdatapins. Copyright© 2008–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:DS32EL0124 DS32ELX0124

DS32EL0124,DS32ELX0124 SNLS284K –MAY 2008–REVISED APRIL 2013 www.ti.com PIN DESCRIPTIONS (continued) Pin Name Pin Number I/O,Type Description ControlPins LT_EN 2 I,LVCMOS DS32ELX0124 only.When heldhigh,retimedserializedhighspeed output isenabled. RX_MUX_SEL 12 I,LVCMOS DS32ELX0124 only.RX_MUX_SEL selectstheinputofthedeserializer. 0 = RxIN0+/-selected 1 = RxIN1+/-selected VOD_CTRL 14 I,LVCMOS DS32ELX0124 only.VOD control.The deserializerloopthroughoutput amplitudecan be adjustedby connectingthispintoa pull-downresistor. The valueofthepull-downresistordeterminestheVOD. See LOOP THROUGH DRIVER LAUNCH AMPLITUDE formore details. DC_B 5 I,LVCMOS DC-balanceand Remote Sense pins.See ApplicationsInformationfor RS 6 devicebehavior. RESET 30 I,LVCMOS Resetpin.When heldlow,resetthedevice. 0 = DeviceReset 1 = Normal operation LOCK 31 O, LVCMOS Lock indicationoutput.pingoes lowwhen thedeserializerislockedtothe incomingdatastreamand beginstooutputdataand clockon RxOUT and RxCLKOUT respectively. 0 = Deserializerlocked 1 = Deserializernotlocked SMBus SCK I,SMBus 33 SMBus compatibleclock. SDA I/O,SMBus 32 SMBus compatibledataline. SMB_CS I,SMBus 34 SMBus chipselect.When heldhigh,SMBus management controlis enabled. Other GPIO0 3 I/O,LVCMOS SoftwareconfigurableIO pins. GPIO1 4 I/O,LVCMOS SoftwareconfigurableIO pins. GPIO2 11 I/O,LVCMOS SoftwareconfigurableIO pins. NC 2 ,8,9,10,12,13,14,19, Misc. No Connect,forDS32EL0124 20,21,22,23,24,29 8,9,10,13,23,24,29 Misc No Connect,forDS32ELX0124 These deviceshave limitedbuilt-inESD protection.The leadsshouldbe shortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamage totheMOS gates.

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DS32EL0124,DS32ELX0124 www.ti.com SNLS284K –MAY 2008–REVISED APRIL 2013 AbsoluteMaximum Ratings(1)(2) SupplyVoltage(VDD33 ) −0.3Vto+4V SupplyVoltage(VDD25 ) -0.3Vto+3.0V LVCMOS InputVoltage −0.3Vto(VDD33 + 0.3V) LVCMOS OutputVoltage -0.3Vto(VDD33 + 0.3V) CML Input/OutputVoltage -0.3Vto3.6V LVDS OutputVoltage -0.3Vto+3.6V JunctionTemperature +125°C StorageTemperatureRange −65°C to+150°C Lead TemperatureRange Soldering(4sec.) +260°C Package ThermalResistance θJA +25.0°C/W ESD Susceptibility HBM ≥8 kV (1) “AbsoluteMaximum Ratings”indicatelimitsbeyond whichdamage tothedevicemay occur,includinginoperabilityand degradationof devicereliabilityand/orperformance.Functionaloperationofthedeviceand/ornon-degradationattheAbsoluteMaximum Ratingsor otherconditionsbeyond thoseindicatedintheRecommended OperatingConditionsisnotimplied.The Recommended Operating Conditionsindicateconditionsatwhichthedeviceisfunctionaland thedeviceshouldnotbe operatedbeyond such conditions. (2) IfMilitary/Aerospacespecifieddevicesarerequired,pleasecontacttheTexas InstrumentsSalesOffice/Distributorsforavailabilityand specifications. Recommended OperatingConditions Min Typ Max Units SupplyVoltage(VDD33 ) 3.135 3.3 3.465 V SupplyVoltage(VDD25 ) 2.375 2.5 2.625 V SupplyNoiseAmplitudefrom10 Hz to50 MHz 100 mV P-P AmbientTemperature(TA) −40 +25 +85 °C SMBus Pull–Up ResistortoVSDD Value 1000 Ω Table1.Power Supply Characteristics Symbol Parameter Condition Min Typ Max Unit IDD25 2.5Vsupplycurrent 1.25Gbps 50 59 Loop ThroughDriverDisabled 2.5Gbps 62 73 3.125Gbps 69 79 mA 2.5Vsupplycurrent 1.25Gbps 88 99 Loop ThroughDriverEnabled 2.5Gbps 100 112 3.125Gbps 107 120 IDD33 3.3Vsupplycurrent 1.25Gbps 105 121 Loop ThroughDriverDisabled 2.5Gbps 105 121 3.125Gbps 105 121 mA 3.3Vsupplycurrent 1.25Gbps 111 127 Loop ThroughDriverEnabled 2.5Gbps 111 127 3.125Gbps 111 127 PD Power Consumption 1.25Gbps 475 560 Loop ThroughDriverDisabled 2.5Gbps 500 600 3.125Gbps 520 620 mW Power Consumption 1.25Gbps 590 690 Loop ThroughDriverEnabled 2.5Gbps 620 730 3.125Gbps 640 750 Copyright© 2008–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:DS32EL0124 DS32ELX0124

DS32EL0124,DS32ELX0124 SNLS284K –MAY 2008–REVISED APRIL 2013 www.ti.com LVCMOS ElectricalCharacteristics Over recommended operatingsupplyand temperaturerangesunlessotherwisespecified.AppliestoLT_EN, GPIO0, GPIO1, GPIO2, RX_MUX_SEL, DC_B, RESET, RS, LOCK. (1)(2)(3) Symbol Parameter Conditions Min Typ Max Units VIH HighLevelInputVoltage 2.0 VDD V VIL Low LevelInputVoltage GND 0.8 V VOH HighLevelOutputVoltage IOH = -2mA 2.7 3.2 V VOL Low LevelOutputVoltage IOL = 2mA 0.3V V VCL InputClamp Voltage ICL = −18 mA -0.9 −1.5 V IIN InputCurrent VIN = 0.4V,2.5V,orVDD33 -40 40 μA IOS OutputShortCircuitCurrent VOUT = 0V -45 mA (4) (1) The Electricaland TimingCharacteristicstableslistensuredspecificationsunderthelistedRecommended OperatingConditionsexcept as otherwisemodifiedorspecifiedby theElectricalCharacteristicsConditionsand/orNotes.Typicalspecificationsareestimationsonly and arenotensured. (2) Currentintodevicepinsisdefinedas positive.Currentoutofdevicepinsisdefinedas negative.Allvoltagesarereferencedtoground exceptVOD and ΔVOD . (3) Typicalvaluesrepresentmost likelyparametricnorms forVCC = +3.3V and TA = +25°C, and attheRecommended OperationConditions atthetimeofproductcharacterizationand arenotensured. (4) Outputshortcircuitcurrent(IOS )isspecifiedas magnitudeonly,minus signindicatesdirectiononly. SMBus ElectricalSpecifications Over recommended operatingsupplyand temperaturerangesunlessotherwisespecified.(1)(2) Symbol Parameter Conditions Min Typ Max Units VSIL Data,ClockInputLow Voltage 0.8 V VSIH Data,ClockInputHighVoltage 2.1 VSDD V VSDD NominalBus Voltage 2.375 3.465 V ISLEAKB InputLeakage Per Bus Segment SCK and SDA pins ±200 µA ISLEAKP InputLeakage Per Pin ±10 µA C SI CapacitanceforSDA and SCK 10 pF (1) The Electricaland TimingCharacteristicstableslistensuredspecificationsunderthelistedRecommended OperatingConditionsexcept as otherwisemodifiedorspecifiedby theElectricalCharacteristicsConditionsand/orNotes.Typicalspecificationsareestimationsonly and arenotensured. (2) Typicalvaluesrepresentmost likelyparametricnorms forVCC = +3.3V and TA = +25°C, and attheRecommended OperationConditions atthetimeofproductcharacterizationand arenotensured. SMBus Timing Specifications Over recommended operatingsupplyand temperaturerangesunlessotherwisespecified.(1)(2) Symbol Parameter Conditions Min Typ Max Units fSMB Bus OperatingFrequency 10 100 kHz tBUF Bus freetimebetween topand startcondition 4.7 μs tHD:STA Holdtimeafter(repeated)startcondition.Afterthis 4.0 µs period,thefirstclockisgenerated tSU:STA Repeated StartConditionSetupTime (3) 4.7 µs tHD:DAT Data HoldTime 300 ns tSU:DAT Data SetupTime (3) 250 ns tLOW ClockLow Time 4.7 µs tHIGH ClockHighTime 4.0 50 µs tSU:CS SMB_CS SetupTime (3) 30 ns (1) The Electricaland TimingCharacteristicstableslistensuredspecificationsunderthelistedRecommended OperatingConditionsexcept as otherwisemodifiedorspecifiedby theElectricalCharacteristicsConditionsand/orNotes.Typicalspecificationsareestimationsonly and arenotensured. (2) Typicalvaluesrepresentmost likelyparametricnorms forVCC = +3.3V and TA = +25°C, and attheRecommended OperationConditions atthetimeofproductcharacterizationand arenotensured. (3) Parameterisspecifiedby characterizationand isnottestedatproduction.

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DS32EL0124,DS32ELX0124 www.ti.com SNLS284K –MAY 2008–REVISED APRIL 2013 SMBus Timing Specifications(continued) Over recommended operatingsupplyand temperaturerangesunlessotherwisespecified.(1)(2) Symbol Parameter Conditions Min Typ Max Units tHS:CS SMB_CS HoldTime (3) 100 ns tPOR Time inwhichthedevicemust be operationalafter (3) 500 ms power on LVDS ElectricalSpecifications Over recommended operatingsupplyand temperaturerangesunlessotherwisespecified.(1)(2) Symbol Parameter Conditions Min Typ Max Units VOD DifferentialOutputVoltage R L = 100Ω 230 310 mV Changes inVOD between complimentaryoutput 35 mVΔVOD states VOS OffsetVoltage 1.125 1.25 1.375 V ΔVOS Change inVOS between complimentarystates 35 mV IOS OutputShortCircuitCurrent VOUT = 0V,R L = 100Ω -50 mA (3) (1) The Electricaland TimingCharacteristicstableslistensuredspecificationsunderthelistedRecommended OperatingConditionsexcept as otherwisemodifiedorspecifiedby theElectricalCharacteristicsConditionsand/orNotes.Typicalspecificationsareestimationsonly and arenotensured. (2) Typicalvaluesrepresentmost likelyparametricnorms forVCC = +3.3V and TA = +25°C, and attheRecommended OperationConditions atthetimeofproductcharacterizationand arenotensured. (3) Outputshortcircuitcurrent(IOS )isspecifiedas magnitudeonly,minus signindicatesdirectiononly. LVDS Timing Specifications Over recommended operatingsupplyand temperaturerangesunlessotherwisespecified.(1)(2) Symbol Parameter Conditions Min Typ Max Units tROTR LVDS low-to-hightransitiontime 300 ps tROTF LVDS high-to-lowtransitiontime 300 ps tROCP LVDS outputclockperiod 2T ns tRODC RxCLKOUT DutyCycle 45 50 55 % tRBIT LVDS outputbitwidth T ns tROSC RxOUT SetuptoRxCLKOUT OUT 650 800 ps tROHC RxOUT HoldtoRxCLKOUT OUT 650 800 ps tRODJ LVDS OutputDeterministicJitter RxCLKOUT 18 (3) ps RxOUT0 –4 43 (3) tRORJ LVDS OutputRandom Jitter RxCLKOUT 2.5 (3) ps RxOUT0 –4 2.5 (3) tROTJ Peak-to-PeakLVDS OutputJitter RxCLKOUT 51 (3) ps RxOUT0 –4 70 (3) (1) The Electricaland TimingCharacteristicstableslistensuredspecificationsunderthelistedRecommended OperatingConditionsexcept as otherwisemodifiedorspecifiedby theElectricalCharacteristicsConditionsand/orNotes.Typicalspecificationsareestimationsonly and arenotensured. (2) Typicalvaluesrepresentmost likelyparametricnorms forVCC = +3.3V and TA = +25°C, and attheRecommended OperationConditions atthetimeofproductcharacterizationand arenotensured. (3) Parameterisspecifiedby characterizationand isnottestedatproduction. Copyright© 2008–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:DS32EL0124 DS32ELX0124

DS32EL0124,DS32ELX0124 SNLS284K –MAY 2008–REVISED APRIL 2013 www.ti.com LVDS Timing Specifications(continued) Over recommended operatingsupplyand temperaturerangesunlessotherwisespecified.(1)(2) Symbol Parameter Conditions Min Typ Max Units tRLA DeserializerLock Time (3) 1.25Gbps 22 ms2.5Gbps 90 3.125Gbps 115 tLVSK LVDS OutputSkew LVDS DifferentialOutputSkew 20 ps between + and -pins CML InputTiming Specifications Over recommended operatingsupplyand temperaturerangesunlessotherwisespecified.(1)(2) Symbol Parameter Conditions Min Typ Max Units TOL JIT SerialInputJitterTolerance RJ = 0.18UI DJ = 0.37UI SJ increaseduntilfailure 1.25Gbps f< 10 kHz 30 f> 1 MHz 0.5 UI2.5Gbps f< 10 kHz 50 f> 1 MHz 0.3 3.125Gbps f< 10 kHz 70 f> 1 MHz 0.3 (1) The Electricaland TimingCharacteristicstableslistensuredspecificationsunderthelistedRecommended OperatingConditionsexcept as otherwisemodifiedorspecifiedby theElectricalCharacteristicsConditionsand/orNotes.Typicalspecificationsareestimationsonly and arenotensured. (2) Typicalvaluesrepresentmost likelyparametricnorms forVCC = +3.3V and TA = +25°C, and attheRecommended OperationConditions atthetimeofproductcharacterizationand arenotensured. CML InputElectricalSpecifications Over recommended operatingsupplyand temperaturerangesunlessotherwisespecified.(1)(2) Symbol Parameter Conditions Min Typ Max Units VID Differentialinputvoltage (3) 230 2200 mV VIN Singleended inputvoltage (3) 115 1100 mV IIN InputCurrent -300 50 μA R IT InputTermination 84 100 116 Ω (1) The Electricaland TimingCharacteristicstableslistensuredspecificationsunderthelistedRecommended OperatingConditionsexcept as otherwisemodifiedorspecifiedby theElectricalCharacteristicsConditionsand/orNotes.Typicalspecificationsareestimationsonly and arenotensured. (2) Typicalvaluesrepresentmost likelyparametricnorms forVCC = +3.3V and TA = +25°C, and attheRecommended OperationConditions atthetimeofproductcharacterizationand arenotensured. (3) Parameterisspecifiedby characterizationand isnottestedatproduction.

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(diff) 80% 20% tROTR 80% 20% tROTF SP tBUF tHD:STA tLOW tR tHD:DAT tHIGH tF tSU:DAT tSU:STA ST SP tSU:STO SCK SDA SMB_CS tSU:CS ST DS32EL0124,DS32ELX0124 www.ti.com SNLS284K –MAY 2008–REVISED APRIL 2013 CML Retimed Loop Through Output ElectricalSpecifications,DS32ELX0124 Only Over recommended operatingsupplyand temperaturerangesunlessotherwisespecified.(1)(2) Symbol Parameter Conditions Min Typ Max Units VLTOD Outputdifferentialvoltage VOD_CTRL resistor= 9.09kΩ 1.15 1.45 V (3) R LTOT Outputtermination 50Ω 40 50 60 Ω 75Ω 60 75 90 ΔR LTOT Mismatchinoutputterminationresistors 5 % (1) The Electricaland TimingCharacteristicstableslistensuredspecificationsunderthelistedRecommended OperatingConditionsexcept as otherwisemodifiedorspecifiedby theElectricalCharacteristicsConditionsand/orNotes.Typicalspecificationsareestimationsonly and arenotensured. (2) Typicalvaluesrepresentmost likelyparametricnorms forVCC = +3.3V and TA = +25°C, and attheRecommended OperationConditions atthetimeofproductcharacterizationand arenotensured. (3) Parameterisspecifiedby characterizationand isnottestedatproduction. CML Retimed Loop Through Output Timing Specifications,DS32ELX0124 Only Over recommended operatingsupplyand temperaturerangesunlessotherwisespecified.(1)(2) Symbol Parameter Conditions Min Typ Max Units tJIT AdditiveOutputJitter (3) 24 35 ps tOS OutputOvershoot (3) 1.5 8 % tLTR Retimedoutputdriverdifferentiallowtohigh (3) 74 105 pstransitiontime tLTF Retimedoutputdriverdifferentialhightolow (3) 74 105 pstransitiontime tLTRFMM MismatchinRise/FallTime (3) 5 15 % tLTDE Retimeddriverde-emphasiswidth 1 UI (1) The Electricaland TimingCharacteristicstableslistensuredspecificationsunderthelistedRecommended OperatingConditionsexcept as otherwisemodifiedorspecifiedby theElectricalCharacteristicsConditionsand/orNotes.Typicalspecificationsareestimationsonly and arenotensured. (2) Typicalvaluesrepresentmost likelyparametricnorms forVCC = +3.3V and TA = +25°C, and attheRecommended OperationConditions atthetimeofproductcharacterizationand arenotensured. (3) Parameterisspecifiedby characterizationand isnottestedatproduction. Timing Diagrams Figure3. SMBus Timing Parameters Figure4. LVDS Output TransitionTime Copyright© 2008–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:DS32EL0124 DS32ELX0124

Symbol N-4 Symbol N-1Symbol N-3 Symbol N-2 Symbol N Symbol N+4Symbol N+3Symbol N+2Symbol N+1Symbol N RXCLK RXIN RX[0..4] Symbol N-1 tRD RxCLKOUT RESET 3.0V RxIN LOCK tRLAPL tRLA tRPLLS RXCLK RX[4:0] Setup Hold tROCH , tROCL tROSC tROHC tROCP /2 +100 mV -100 mV DS32EL0124,DS32ELX0124 SNLS284K –MAY 2008–REVISED APRIL 2013 www.ti.com Figure5. Deserializer(LVDS Interface)Setup/Holdand High/Low Times Figure6. Reset toLock Time Figure7. DeserializerPropagationDelay

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High Speed Serial CML Input First Bit In Last Bit In Current CyclePrevious Cycle Next Cycle Output Receive Clock A0 A1 A2 A3 B0 B1 B2 B3 C0 C1 C2 C3 D0 D1 D2 D3 E0 E1 E2 E3 LVDS Data-0 LVDS Data-1 LVDS Data-2 LVDS Data-3 LVDS Data-4 DS32EL0124,DS32ELX0124 www.ti.com SNLS284K –MAY 2008–REVISED APRIL 2013 Figure8. CML toLVDS BitMap Copyright© 2008–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:DS32EL0124 DS32ELX0124

DS32EL0124,DS32ELX0124 SNLS284K –MAY 2008–REVISED APRIL 2013 www.ti.com FUNCTIONAL DESCRIPTION POWER SUPPLIES The DS32EL0124 and DS32ELX0124 have severalpower supplypins,at2.5V as wellas 3.3V.Itisimportant thatthesepinsallbe connectedand properlybypassed.Bypassingshouldconsistofparallel4.7μF and 0.1μF capacitorsas a minimum, witha 0.1μF capacitoron each power pin.A 22 μF capacitorisrequiredon the VDDPLL pinwhichisconnectedtothe3.3Vrail. These deviceshave a largecontactinthecenteron thebottomofthepackage.Thiscontactmust be connected tothesystemGND as itisthemajorgroundconnectionforthedevice. POWER UP Itisrecommended, althoughnotnecessary,tobringup the3.3Vpower supplybeforethe2.5Vsupply.Ifthe2.5V supplyispowered up first,an initialcurrentdraw ofapproximately600mA from the2.5V railmay occurbefore settlingtoitsfinalvalue.Regardlessofthesequence,bothpower railsshouldmonotonicallyramp up totheirfinal values. POWER MANAGEMENT These deviceshave two methods to reduce power consumption.To enterthe firstpower save mode, the on board hostFPGA or controllingdevicecan cease tooutputtheDDR transmitclock.To furtherreducepower,a writetothepower down registerwillputthedeviceinitslowestpower mode. RESET There arethreeways toresetthesedevices.A resetoccursautomaticallyduringpower-up.The devicecan also be resetby pullingtheRESET pinlow,withnormaloperationresumingwhen thepinisdrivenhighagain.The devicecan alsobe resetby writingtotheresetregister.Thisresetwillputalloftheregistervaluesback totheir defaultvalues,except itwillnot affectthe address registervalue ifthe SMBus defaultaddress has been changed. LVDS OUTPUTS The DS32EL0124 and DS32ELX0124 has standardLVDS outputs,compatiblewithANSI/TIA/EIA-644.Itis recommended thatthe PCB tracebetween the FPGA and the deserializeroutputbe no more than 40-inches. Longer PCB tracesmay introducesignaldegradationas wellas channelskew which couldcause serialization errors.The connectionbetween the hostand the DS32EL0124 or DS32ELX0124 shouldbe over a controlled impedance transmissionlinewithimpedance thatmatches the terminationresistor– usually100Ω. Setup and holdtimesarespecifiedintheLVDS SwitchingCharacteristicstable,however theclockdelaycan be adjustedby writingtoregister30’h. LOOP FILTER The DS32EL0124 and DSELX0124 have an internalclockdatarecoverymodule (CDR),whichisused torecover theinputserialdata.The loopfilterforthisCDR isexternal,and foroptimum results,a 30nF capacitorshouldbe connectedbetween pins26 and 27.See theTypicalInterfaceCircuit(Figure14). LOOP THROUGH DRIVER LAUNCH AMPLITUDE The launchamplitudeoftheretimedCML loopthroughdriveriscontrolledby placinga singleresistorfrom the VOD_CTRL pintoground.Use thefollowingequationtoobtainthedesiredVLTOD by selectingthecorresponding resistorvalue. R = (1400mV /VLTOD )x 9.1kΩ (1) The retimedCML loopthroughdriverlaunchamplitudecan alsobe adjustedby writingtoSMBus register49'h, bits3:1.Thisregisterismeant to assistsystem designersduringthe initialprototypedesignphase.For final production,itisrecommended thatthe appropriateresistorvaluebe selectedforthe desiredVLTOD and that register49'hbe lefttoitsdefaultvalue.

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DS32EL0124,DS32ELX0124 www.ti.com SNLS284K –MAY 2008–REVISED APRIL 2013 REMOTE SENSE The remotesense featurecan be used when a DS32EL0421 orDS32ELX0421 serializerisdirectlyconnectedto a DS32EL0124 or DS32ELX0124 deserializer.Activecomponents inthesignalpathbetween theserializerand thedeserializermay interferewiththeback channelsignalingofthedevices. When remotesense isenabled,thedeserializerwillcyclethroughfivestatestosuccessfullyestablisha linkand alignthedata.The statediagramforthedeserialiezrisshown inFigure9.The deserialzerwillremaininthelow power IDLE stateuntilitreceivesan inputsignal.Once theCDR ofthedeserializerhas lockedtotheinputclock, thedevicewillentertheLINK DETECT state.Whileinthisstate,thedeserializerwillmonitorthelinetosee ifthe serializerissendingthetrainingpattern.Whileinthisstate,thedeserializerwillperiodicallysend a linkdetect signalupstreamtonotifytheserializerthatitcan now send thetrainingpattern.When thedeserializerdetects thatdatacoming inon theserialline,itwillproceedtotheCLOCK ACQUISITION state.Whileinthisstatethe deserializerwillmonitortheincomingdataforsetperiodsoftimeinan attempttoextracttheclockfromthedata. Once, thedeserializerhas successfullyextractedtheclockthedevicewillproceedtotheLINK ACQUISITION STATE. Inthisstatethedeserializerwillperformlanealignmentbased on theexpectedtrainingpatternand then entertheNORMAL state.Ifthedeserializerisunabletosuccessfullylockor maintainlock,itwillbreakthelink sendingtheserializerback totheIDLE orLINK DETECT states. DC-BALANCE DECODER The DS32EL0124 and DS32ELX0124 have a built-inDC-balancedecodertosupportAC-coupledapplications. When enabled,theoutputsignalRxOUT4+/-, istreatedas a datavalidbit.IfRxOUT4+/- islow,thenthedata outputfromRxOUT0 -RxOUT3 has been successfullydecoded usingthe8b/10bcodingscheme. IfRxOUT4+/- ishighand theoutputsRxOUT0 - RxOUT3 are highthenan invalid8b/10bcode was received,signifyinga bit error.IfRxOUT4+/- is high and the outputsRxOUT0 - RxOUT3 are low then an idlecharacterhas been received.The defaultidlecharacterisa K28.5code.InordertoproperlyreceiveotherK codes,theymust firstbe programmed intothe deserializerviathe SMBus. The SMBus registersallowforonlya singleprogrammable character. Copyright© 2008–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:DS32EL0124 DS32ELX0124

(RS:1, DC_B:0 or RS:1, DC_B:1) Clock Recovered Link Acquired RxIN does not Exist or CDR Not Locked or Link Not Acquired Or Excessive Bit Errors CDR Locked and (RS:1, DC_B:0 or RS:1, DC_B:1) DS32EL0124,DS32ELX0124 SNLS284K –MAY 2008–REVISED APRIL 2013 www.ti.com Figure9. DeserializerStateDiagram DESCRAMBLER AND NRZI DECODER The CDR ofthedeserializerexpectsa transitiondensityof20% fora periodof200 μs.To improvethetransition densityof the data,the scramblerand NRZI encoder,which are integratedfeaturesinthe DS32EL0421 and DS32ELX0421, serializerscan be enabled.Ifthe descramblerisenabled,the serializeddata isdescrambled afterbeingrecoveredby theCDR toaccordingtothepolynomialspecifiedintheDS32EL0421 datasheet.Using thescrambler/descramblerhelpstolowerEMI emissionsby spreadingthespectrumofthedata.Scramblingalso createstransitionsfora deserializer’s CDR toproperlylockonto. The scramblerisenabledor disabledby defaultdependingon how theDC_B and RS pinsare configured.To overridethedefaultscramblersettingtwo registerwritesmust be performed.First,writetoregister22’h and set bit5 tounlockthedescramblerregister.Next writetoregister21’h and change bit5 tothedesiredvalue.Please notethatNRZI decoderhas itsown controlbitsinregisters22'hand 21'h.

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centeroftheeye diagram(i.e.0.5UI). DS32ELX0124, each inputcan have itsown independentequalizersettings. can resultinexcessivecrosstalkcoupledintoRxIN1. environment.Pleasesee theRegisterMap ,register67'hbits6:5,fordetails. Table 2. Refer to Figure9 to see how the combinationsof the RS and DC_B pinschange the linkstartup disabledthroughregisterprogramming. deserializerand viceversa.Thisfeatureisused topass linkstatusinformationbetween the2 devices. Validsignal(TXIN4±).IftheData Validinputtotheserializerislogichigh,thenSYNC charactersaretransmitted. logichighwiththeData Validoutputalsosettologichigh. low,an externaldeviceshouldtoggletheData Validinputtotheserializerperiodicallytoensureconstantlock. clockand performlanealignmentwhileskippingtheLINK ACQUISITION state.

DS32EL0124,DS32ELX0124 SNLS284K –MAY 2008–REVISED APRIL 2013 www.ti.com When both Remote Sense and DC-Balance are disabled,RS and DC_B pins set to high,the LVDS lane alignmentisnotmaintained.Inthisconfiguration,dataformattingishandledby an FPGA orexternalsource.In thismode thedeserializerlockstoincomingrandom data.To achievelockduringtheclockacquisitionphase,the incomingdata shouldhave a transitiondensityof approximately20% fora periodof 200 µs.Scramblingand NRZI encodingcan be implementedtohelpimprovethetransitiondensityofthedata.Thispinsettingalsoallows forthedevicestointerfacewithotheractivecomponents inthehighspeed signalpath. Table2. Device ConfigurationTable Remote Sense Pin (RS) DC-Balance Pin (DC_B) Configuration 0 0 Remote Sense enabled DC-Balanceenabled Data Alignment De-Scramblerand NRZI decoderdisabledby default 0 1 Remote Sense enabled DC-Balancedisabled Data Alignment De-Scramblerand NRZI decoderenabledby default 1 0 Remote Sense disabled DC-Balanceenabled Data Alignment De-Scramblerand NRZI decoderenabledby default 1 1 Remote Sense disabled DC-Balancedisabled No Data Alignment De-Scramblerand NRZI decoderdisabledby default SMBus INTERFACE The System Management Bus interfaceiscompatibletoSMBus 2.0physicallayerspecification.The use ofthe Chip Selectsignalisrequired.HoldingtheSMB_CS pinHIGH enablestheSMBus port,allowingaccesstothe configurationregisters.Holdingthe SMB_CS pinLOW disablesthe device'sSMBus, allowingcommunication fromthehosttootherslavedeviceson thebus.IntheSTANDBY state,theSystem Management Bus remains active.When communicationtootherdeviceson theSMBus isactive,theSMB_CS signalforthedeserializer must be drivenLOW. The address byte for allDS32EL0124 and DS32ELX0124 devices is B0'h. Based on the SMBus 2.0 specification,thesedeviceshave a 7-bitslaveaddressof1011000'b.The LSB issetto0'b(fora WRITE), thus the8-bitvalueis1011 0000'borB0'h. The SCK and SDA pinsare 3.3V LVCMOS signalingand includehigh-Zinternalpullup resistors.Externallow impedance pullup resistorsmaybe requireddependingupon SMBus loadingand speed.Note,thesepinsarenot 5V tolerant. TransferofData viatheSMBus Duringnormaloperationthedataon SDA must be stableduringthetimewhen SCK isHIGH. TherearethreeuniquestatesfortheSMBus: START A HIGH toLOW transitionon SDA whileSCK isHIGH indicatesa message START condition. STOP A LOW toHIGH transitionon SDA whileSCK isHIGH indicatesa message STOP condition. IDLE IfSCK and SDA arebothHIGH fora timeexceedingtBUF fromthelastdetectedSTOP conditionoriftheyareHIGH fora total exceedingthemaximum specificationfortHIGH thenthebus willtransfertotheIDLE state. SMBus Transactions The devicessupportWRITE and READ transactions.See RegisterMap forregisteraddress,type(Read/Write, Read Only),defaultvalueand functioninformation. Writingtoa Register The devicessupportWRITE and READ transactions.See RegisterMap forregisteraddress,type(Read/Write, Read Only),defaultvalueand functioninformation.

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DS32EL0124,DS32ELX0124 www.ti.com SNLS284K –MAY 2008–REVISED APRIL 2013 1. The Host(Master)selectsthedeviceby drivingitsSMBus ChipSelect(SMB_CS) signalHIGH. 2. The Hostdrivesa START condition,the7-bitSMBus address,and a “0”indicatinga WRITE. 3. The Device(Slave)drivestheACK bit(“0”). 4. The Hostdrivesthe8-bitRegisterAddress. 5. The Devicedrivesan ACK bit(“0”). 6. The Hostdrivethe8-bitdatabyte. 7. The Devicedrivesan ACK bit(“0”). 8. The Hostdrivesa STOP condition. 9. The Hostde-selectsthedeviceby drivingitsSMBus CS signalLow. The WRITE transactioniscompleted,the bus goes IDLE and communicationwithotherSMBus devicesmay now occur. Reading a Register To reada register,thefollowingprotocolisused (seeSMBus 2.0specification). 1. The Host(Master)selectsthedeviceby drivingitsSMBus ChipSelect(SMB_CS) signalHIGH. 2. The Hostdrivesa START condition,the7-bitSMBus address,and a “0”indicatinga WRITE. 3. The Device(Slave)drivestheACK bit(“0”). 4. The Hostdrivesthe8-bitRegisterAddress. 5. The Devicedrivesan ACK bit(“0”). 6. The Hostdrivesa START condition. 7. The Hostdrivesthe7-bitSMBus Address,and a “1”indicatinga READ. 8. The Devicedrivesan ACK bit“0”. 9. The Devicedrivesthe8-bitdatavalue(registercontents). 10. The Hostdrivesa NACK bit“1”indicatingend oftheREAD transfer. 11. The Hostdrivesa STOP condition. 12. The Hostde-selectsthedeviceby drivingitsSMBus CS signalLow. The READ transactioniscompleted,thebus goes IDLE and communicationwithotherSMBus devicesmay now occur. SMBus Configurations Many differentconfigurationsof the SMBus are possibleand depend upon the specificrequirementsof the applications.Severalpossibleapplicationsaredescribed. Configuration1 The deserializerSMB_CS may be tiedHigh (alwaysenabled)sinceitisthe onlydeviceon the SMBus. See Figure10. Configuration2 SincethemultipleSER deviceshave thesame address,theuse oftheindividualSMB_CS signalsisrequired. To communicate witha specificdevice,itsSMB_CS isdrivenHigh toselectthedevice.Afterthetransactionis complete,itsSMB_CS isdrivenLow todisableitsSMB interface.Otherdeviceson thebus may now be selected withtheirrespectivechipselectsignalsand communicatedwith.See Figure11. Configuration3 The addressingfieldislimitedto 7-bitsby the SMBus protocol.Thus itispossiblethatmultipledevicesmay sharethesame 7-bitaddress.An optionalfeatureintheSMBus 2.0specificationsupportsan AddressResolution Protocol(ARP).Thisoptionalfeatureisnotsupportedby theDS32EL0124/DS32ELX0124 devices.Solutionsfor thisinclude:theuse oftheindependentSMB_CS signals,independentSMBus segments,orothermeans. Copyright© 2008–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:DS32EL0124 DS32ELX0124

SMB_CS SMBus Device SCK SDA SMB_CS SMBus Device SCK SDA SMB_CS SMBus Device 3V3 3V3 3V3 FPGA Host LVCMOS GPIO SMBus Interface 3V3 SCK SDA SMB_CS SMBus Device SCK SDA SMB_CS SMBus Device SCK SDA SMB_CS SMBus Device FPGA Host LVCMOS GPIO SMBus Interface 3V3 SCK SDA SMB_CS SMBus Device 3V3 DS32EL0124,DS32ELX0124 SNLS284K –MAY 2008–REVISED APRIL 2013 www.ti.com Figure10. SMBus Configuration1 Figure11. SMBus Configuration2 Figure12. SMBus Configuration3

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(RS, DC_B) NRZ Decoder Descrambler Lane Alignment Logic DC Balance Decoder Total Propagation Delay Data Flow 1, 1 0, 0 0, 1 1, 0 2 clocks 2 clocks 2 clocks 2 clocks 1 clock 1 clock 1 clock (bypassed) 1 clock 1 clock 1 clock (bypassed) 3 clocks 3 clocks 3 clocks 3 clocks 1 clock 1 clock 3-4 clocks 3-4 clocks 3-4 clocks 3-4 clocks 9-10 clocks 11-12 clocks 10-11 clocks LVDS InterfaceCML Interface 10-11 clocks DS32EL0124,DS32ELX0124 www.ti.com SNLS284K –MAY 2008–REVISED APRIL 2013 PROPAGATION DELAY Once thedeserializerislocked,theamount oftimeittakesfora signaltotravelfromthehighspeed CML serial inputthroughthe deviceand out viathe DDR LVDS interfaceisdefinedto be the propagationdelay.The propagationdelaythroughtheDS32EL0124/DS32ELX0124 due totheanalogcircuitryisconsiderednegligible compared tothetimedelaycaused by thedigitalcomponents.The informationpresentedinthissectionallows system designersto predictthe propagationdelay throughthe devicein terms of clockcycleswhich are proportionaltothehighspeed seriallinerate. Each clockcycleshown inFigure13 isdefinedtobe 1/20th ofthehighspeed serialbitrate.For example,ata seriallinerateof3.125Gbps theclockfrequencyofeach delaycyclewould be 156.25MHz. Note,thisisnotthe same frequencyas theLVDS outputs,which would be 312.5MHz fora seriallinerateof3.125Gbps. Dashed linesinFigure13 indicatethatthefeatureisdisabledby defaultinthatmode and thereforeadd no more timeto thetotalpropagationdelay.Inthelastrow,bypassed indicatesthatthedataissampled even thoughthefeature isdisabledby default.The samplingofthedataresultsinan added amount ofpropagationdelayas specifiedin thebox. Figure13. DeserializerPropagationDelay PROPAGATION DELAY FOR RETIMED LOOP THROUGH DRIVER — DS32ELX0124 ONLY Ifthe loopthroughdriverisenabledinthe DS32ELX0124, the propagationdelaycan alsobe definedas the amount oftimeittakesa signaltopass fromthehighspeed CML serialinputtotheretimedloopthroughdriver output.Thistimedelayismeasured inCDR clockcycles.The CDR clockfrequencyisequaltohighspeed serial linerateorone highspeed serialbitwidth.For example,ifthehighspeed seriallinerateis3.125Gbps, thenthe CDR clockfrequencyis3.125GHz. The propagationdelayfromthehighspeed inputtotheloopthroughdriver outputis1 CDR clock. ApplicationsInformation GPIO PINS The GPIO pinscan be usefultoolswhen debuggingor evaluatingthesystem.For specificGPIO configurations and functionsrefertoregisters2,3,4,5 and 6 inthedeviceregistermap. GPIO pinsare commonly used when thereare multipledeserializerson thesame SMBus. Inordertoprogram individualsettingsintoeach serializer,theywilleach need to have a uniqueSMBus address.To reprogram multipledeserializerson a singleSMBus, configurethefirstdeserializersuch thattheSMBus linesareconnected to the FPGA or host controller.The CS pin of the second serializershould be tiedto GPIO0 of the first deserializer,withtheCS pinofthenextdeseriazliertiedtoGPIO0 ofitsprecedingdeserializer.By holdingallof theGPIO0 pinslow,thefirstdeserializer’s addressmay now be reprogrammed by writingtoregister0.The first deserializer’s GPIO pincan now be assertedand thesecond deserializer’s addressmay now be reprogrammed. Copyright© 2008–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLinks:DS32EL0124 DS32ELX0124

DS32EL0124,DS32ELX0124 SNLS284K –MAY 2008–REVISED APRIL 2013 www.ti.com HIGH SPEED COMMUNICATION MEDIA Using the deserializer’s integratedequalizerblocksin combinationwiththe DS32EL0421 or DS32ELX0421 ’s integratedde-emphasisblockallowsdatatobe transmittedacrossa varietyofmedia athighspeeds.Factors thatcan limitdeviceperformanceincludeexcessiveinputclockjitter,noisypower rails,EMI from nearbynoisy components and poor layouttechniques.Althoughmany cablescontainwiresof similargauge and shielding, performancecan varygreatlydependingon thequalityoftheconnector. The DS32ELX0124 alsohas a programmable de-emphasisblockon itsretimedloopthroughoutputTxOUT+/-. The de-emphasissettingfortheloopthroughdriverisprogrammed throughtheSMBus. REDUNDANCY APPLICATIONS The DS32ELX0124 has two highspeed CML serialinputs.SMBus registercontrolallowsthe hostdeviceto monitorforerrorsor linklosson the activeinputchannel.Thisenablesthe hostdevice,usuallyan FPGA, to switchtothesecondaryinputifproblemsoccurwiththeprimaryinput. LINK AGGREGATION MultipleDS32EL0421/DS32ELX0421 serializersand D32EL0124/DS32ELX0124 deserializerscan be aggregatedtogetherifan applicationrequiresa datathroughputofmore than3.125Gbps. By utilizingthedata validsignalofeach device,thesystem can be properlydeskewed toallowfora singlecable,such as CAT-6, DVI-D,orHDMI, tocarrydatapayloadsbeyond 3.125Gbps. Linkaggregationconfigurationscan alsobe implementedinapplicationswhich requirelongercablelengths.In thesetypeofapplicationsthedatarateofeach serializerand deserializerchipsetcan be reduced,such thatthe applications'netdatathroughputisstillthesame. Sinceeach highspeed channelisnow operatingata fraction oftheoriginaldatarate,thelossoverthecableisreduced,allowingforgreaterlengthsofcabletobe used inthe system. For more informationregardinglinkaggregationpleasesee ApplicationNote 1887,ExpandingthePayloadwith TI'sFPGA-Link DS32ELX0421 and DS32ELX0124 Serializerand Deserializer. REACH EXTENSION The DS32ELX0124 deserializercontainsa retimedloopthroughCML serialoutput.The loopthroughdriveralso has programmablede-emphasismaking thisdevicecapableofreachextensionapplications. DAISY CHAINING The loopthroughdriveroftheDS32ELX0124 deserializercan be used tostringtogetherdeserializersina daisy chainconfiguration.This allowsa singledata source such as a DS32EL0421 serializerto communicate to multiplereceivingsystems. LAYOUT GUIDELINES Itisimportanttofollowgood layoutpracticesforhighspeed devices.The lengthofLVDS inputtracesshouldnot exceed 40 inches.InnoisyenvironmentstheLVDS tracesmay need tobe shortertopreventdatacorruptiondue toEMI. Noisycomponents shouldnotbe placednexttotheLVDS or CML traces.The LVDS and CML traces must have a controlleddifferentialimpedance of100Ω.Do notplaceterminationresistorsattheCML inputsor output,the DS32EL0124 and DS32ELX0124 have internalterminationresistors.Itisrecommended to avoid usingvias.Each pairofviascreatesan impedance mismatch inthetransmissionlineand resultinreflections, which can greatlylowerthemaximum distanceofthehighspeed datalink.Ifviasare required,theyshouldbe placedsymmetricallyon each sideofthedifferentialpair.For more tipsand detailedsuggestionsregardinghigh speed boardlayoutprinciples,pleaseconsulttheLVDS Owner ’s Manual.

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SMB_CS GPIO2 FPGA Host 0.1 PF 0.1 PF 2.5V 3.3V VDDPLL LF_REF LF_CP 30 nF GPIO0 GPIO1 22 PF 3.3V RXIN0 RXIN1 GND VCC25 VCC33 VOD_CTRL 9.1 k: 1, 15, 18, 28, 36 7, 25, 3549 TXOUT+ TXOUT- 21 22 DC_B RS 5 6 3.3V 3.3V 0.1 PF 0.1 PF RESET LOCK RXOUT3 + - 46 RXOUT2 + - 44 RXOUT1 + - 42 RXOUT0 + - 40 RXCLKOUT + - 38 DS32EL0124,DS32ELX0124 www.ti.com SNLS284K –MAY 2008–REVISED APRIL 2013 Figure14. TypicalInterfaceCircuit Copyright© 2008–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLinks:DS32EL0124 DS32ELX0124

DS32EL0124,DS32ELX0124 SNLS284K –MAY 2008–REVISED APRIL 2013 www.ti.com TypicalPerformance Characteristics The eye diagramsshown belowillustratethetypicalperformanceoftheDS32ELX0124/DS32EL0124 configuredwithRS = 0, DC_B = 0,fortheconditionslistedbeloweach figure.The PRBS-15 datawas generatedby a lowcostFPGA, whichused an LMK03000C togeneratethevariousclockfrequencies.The datawas thensenttoa DS32ELX0421 configuredwithRS = 0, DC_B = 0,whichtransmittedthedataacrossthespecifiedcabletypeand lengthatthespecifieddatarate.The signal conditioningsettingsused foreach measurement arealsolistedbelowthefigures. Figure15.LVDS RxCLKOUT Output Figure16.LVDS RxOUT0 Output (1.25Gbps, 40m CAT-5e, 0x000 DS32ELX0124 EQ setting, (1.25Gbps, 40m CAT-5e, 0x000 DS32ELX0124 EQ setting, 0x10 DS32EL0421 De-Emphasis setting) 0x10 DS32EL0421 De-Emphasis setting) Figure17.LVDS RxCLKOUT Output Figure18.LVDS RxOUT0 Output (3.125Gbps, 20m CAT-6 SCTP, 0x001 DS32ELX0124 EQ (3.125Gbps, 20m CAT-6 SCTP, 0x001 DS32ELX0124 EQ setting,0x10 DS32EL0421 De-Emphasis setting) setting,0x10 DS32EL0421 De-Emphasis setting)

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DS32EL0124,DS32ELX0124 www.ti.com SNLS284K –MAY 2008–REVISED APRIL 2013 TypicalPerformance Characteristics(continued) The eye diagramsshown belowillustratethetypicalperformanceoftheDS32ELX0124/DS32EL0124 configuredwithRS = 0, DC_B = 0,fortheconditionslistedbeloweach figure.The PRBS-15 datawas generatedby a lowcostFPGA, whichused an LMK03000C togeneratethevariousclockfrequencies.The datawas thensenttoa DS32ELX0421 configuredwithRS = 0, DC_B = 0,whichtransmittedthedataacrossthespecifiedcabletypeand lengthatthespecifieddatarate.The signal conditioningsettingsused foreach measurement arealsolistedbelowthefigures. Figure19.Retimed Loop Through Output Figure20.Retimed Loop Through Output (1.25Gbps, 40m CAT-5e, 0x000 DS32ELX0124 EQ setting, (3.125Gbps, 20m CAT-6 SCTP, 0x001 DS32ELX0124 EQ 0x10 DS32EL0421 De-Emphasis setting) setting,0x10 DS32EL0421 De-Emphasis setting) Copyright© 2008–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 23 ProductFolderLinks:DS32EL0124 DS32ELX0124

DS32EL0124,DS32ELX0124 SNLS284K –MAY 2008–REVISED APRIL 2013 www.ti.com RegisterMap The registerinformationforthedeserializerisshown inthetablebelow.Some registershave been omittedor marked as reserved;theseare forinternaltestingand shouldnot be writtento.Some registerbitsrequirean overridebittobe setbeforetheycan be writtento. Addr (Hex) Name Bits Field R/W Default Description

00 DeviceID 7:1 SMBus Address R/W 58'h Some systemswilluse all8 bitsas thedevice

ID.Thiswillshiftthevaluefrom58’h toB0’h

0 Reserved 0

01 Reset 7:1 Reserved 0

0 SoftwareReset R/W 0 Resetthedevice.Does notaffectdeviceID.

02 GPIO0 Config 7:4 GPIO0 Mode R/W 0 0000:GP Out

0001:SignalDetectRxIN0 0010:BIST Status AllOthers:Reserved 3:2 GPIO0 R Enable R/W 01'b 00:Pullup/Pulldowndisabled 01:PulldownEnabled 10:PullupEnabled 11:Reserved

1 InputEnable R/W 0 0:Inputbufferdisabled

1:Inputbufferenabled

0 OutputEnable R/W 1'b 0:OutputTri-State™

1:Outputenabled

03 GPIO1 Config 7:4 GPIO1 Mode R/W 0 0000:Power On Reset

0001:GP Out 0010:SignalDetectRxIN1 0011:CDR Lock AllOthers:Reserved 3:2 GPIO1 R Enable R/W 01'b 00:Pullup/Pulldowndisabled 01:PulldownEnabled 10:PullupEnabled 11:Reserved 1:Inputbufferenabled

0 OutputEnable R/W 1 0:OutputTri-State™

1:Outputenabled

04 GPIO2 Config 7:4 GPIO2 Mode R/W 0 0000:GP Out

0001:Alwayson ClockOut 0010:LVDS Tx CLK 0011:CDR CLK AllOthers:Reserved 3:2 GPIO2 R Enable R/W 01'b 00:Pullup/Pulldowndisabled 01:PulldownEnabled 10:PullupEnabled 11:Reserved 1:Inputbufferenabled 1:Outputenabled

05 GP In 7:3 Reserved

2 GP In2 R 0 Inputvalueon GPIO2

1 GP In1 R 0 Inputvalueon GPIO1

0 GP In0 R 0 Inputvalueon GPIO0

06 GP Out 7:3 Reserved 0

2 GP Out 2 R/W 0 Outputvalueon GPIO2

1 GP Out 1 R/W 0 Outputvalueon GPIO1

0 GP Out 0 R/W 0 Outputvalueon GPIO0

07 — 1F Reserved

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DS32EL0124,DS32ELX0124 www.ti.com SNLS284K –MAY 2008–REVISED APRIL 2013 Addr (Hex) Name Bits Field R/W Default Description

20 DeviceConfig 7 LVDS AlwaysOn Clock R/W 0 1:Disable

0 0:When notlockedswitchtoAlwaysOn Clock 6:3 Reserved 0

2 ReverseData Order R/W 0 0:Normal

1:Reverseoutputdataorder

1 ResetChannel R/W 0 Resetinputhighspeed channel

0 DigitalPower Down R/W 0 Power down parallel,seria-to-parallell,and

21 DeviceConfig 7 Reserved 0

1 6 NRZI Decode Enable R/W 0 EnableNRZI decodingofincomingdata; requiresan overridebit

5 DescrambleEnable R/W 0 Enabledthedescrambler,requiresan

4 Rx Mux R/W 0 RX_MUX_SEL controlregister.requiresan overridebit 3 Decode Bypass R/W 0 Bypass DC Balancedecoder.requiresan overridebit 2 TrainingSequence R/W 0 Enabletrainingsequence.requiresan Enable overridebit 1:0 DeviceConfiguartion R/W 0 MSB: Remote Sense enable,activelow LSB: DC balanceencoderenable,activelow requiresan overridebit

22 DeviceConfig 7 Reserved 0

Override 6 NRZ Override R/W 0 Unlockbit6 ofregister21'h

5 DescrambleOverride R/W 0 Unlockbit5 ofregister21'h

4 Rx Mux Override R/W 0 Unlockbit4 ofregister21'h

3 Reserved 0

2 Decode Bypass Override R/W 0 Unlockbit3 ofregister21'h

1 TraningOverride R/W 0 Unlockbit2 ofregister21'h

0 DeviceConfigOverride R/W 0 Unlockbits1 and 0 ofregister21'h

23 — 26 Reserved 27 LVDS Per 7 LVDS VOD High R/W 0 0:LVDS VOD normaloperation.Settingused Channel inElectricalCharacteristicsTable Enable 1:IncreasesVOD .Allowsforlongertracesto be driven,butconsume more power

6 LVDS Control R/W 0 1:AllowSMBus tocontrolLVDS perchannel

5 RxCLKOUT Enable R/W 0 EnablesRxCLKOUT outputdriver

4 RxOUT4 Enable R/W 0 EnablesRxOUT4 outputdriver

3 RxOUT3 Enable R/W 0 EnablesRxOUT3 outputdriver

2 RxOUT2 Enable R/W 0 EnablesRxOUT2 outputdriver

1 RxOUT1 Enable R/W 0 EnablesRxOUT1 outputdriver

0 RxOUT0 Enable R/W 0 EnablesRxOUT0 outputdriver

28 LVDS Config 7 Reserved 0

6 LVDS Reset R/W 0 ResetsLVDS block

5 LVDS ClockRate R/W 1 0:RxCLKOUT isDDR/2

1:RxCLKOUT isDDR

4 LVDS ClockInvert R/W 0 InvertsthepolarityoftheRxCLKOUT signal

3:2 LVDS ClockDelay R/W 10'b 00:160 ps 11:-80ps 80 ps stepsize 1:0 Reserved 0 29 — 2A Reserved Copyright© 2008–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 25 ProductFolderLinks:DS32EL0124 DS32ELX0124

DS32EL0124,DS32ELX0124 SNLS284K –MAY 2008–REVISED APRIL 2013 www.ti.com Addr (Hex) Name Bits Field R/W Default Description 2B EventConfig 7:4 Reserved 0 3 EventCount Select R/W 0 0:SelectCDR EventCounterforreading. Eventsincludelossofsignaldetectorlossof CDR lock. 1:SelectData EventCounterforreading

2 ResetCDR ErrorCount R/W 0 ResetsCDR eventcount

1 ResetLinkErrorCount R/W 0 Resetdataeventcount

0 EnableCount R/W 0 Enableeventcoutners

2D ErrorMonitor 7:5 Reserved 0

4 AccumulateErrorEnable R/W 0 1:Enablecountingaccumulationoferrors

3 8b/10bErrordisable R/W 0 1:Disables8b/10bdecode errorsfrombeing countedorflaggedon LOCK pin

2 ClearEventCounter R/W 0 1:clearserrorsinboththecurrentand

previousstateofteherrorscount

1 SelectErrorCount R/W 0 0:Number oferrorsincurrentrun

1:Number oferrorswithintheselectedtiming window

0 Normal ErrorDisable R/W 0 1:DisableexitingNORMAL statewhen the

number oferrorsexceedstheerrorthreshold 2E Error 7:0 ErrorThreshold R/W 10'h Errorthresholdabove whichpartstops Threshold transmittionofdata— LSB LSBs 2F Error 7:0 ErrorThreshold R/W 0 Errorthresholdabove whichpartstops Threshold transmittionofdata— MSB MSBs 30 — 3A Reserved 3B Data Rate 7 Reserved 0 6:4 FrequencyRange R 111'b 001:Reserved 010:1 — 1.3Gbps 011:1.2— 1.8Gbps 100:1.5— 2.1Gbps 101:1.9— 2.7Gbps 110:2.4— 3.2Gbps 111:No Lock 3:2 BIST Status R 0 00:BIST passed 01:BIST failedtocapturePREAMBLE 10:BIST patternmode failed 11:BIST datasequence failed 1 BIST Done R 0 BIST patterndone.Setwhen notusing repeat.

0 BIST AllignDone R 0 Alignmentofincomingdatadone

3D EventStatus 7:0 EventCount R 0 Count oferrorsthatcaused a lossoflink 3E ErrorStatus 7:0 Data ErrorCount R 0 Number oferrorsindata— LSB LSBs 3F ErrorsStatus 7:0 Data ErrorCount R 0 Number oferrorsindata— MSB MSBs 40 — 49 Reserved

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DS32EL0124,DS32ELX0124 www.ti.com SNLS284K –MAY 2008–REVISED APRIL 2013 Addr (Hex) Name Bits Field R/W Default Description

49 Loop Through 7:5 Reserved 0

DriverConfig 4 TerminationSelect R/W 1 0:75Ω 1:50 Ω 3:1 OutputAmplitudeAdjust R/W 011'b 000:Level7 001:Level8 (Highestoutput) 010:Level5 011:Level6 (Normaloutput) 100:Level4 101:Level3 110:Level2 111:Level1 (Lowestoutput)

60 EQ Attenuator 7:4 Reserved 0

3 Attenuator0 Override R/W 0 OverridesattenuationcontrolinEQ 0

2 Attenuator1 Override R/W 0 OverridesattenuationcontrolinEQ 1

1 Attenuator0 Enable R/W 0 1:enablesattenuatorforforEQ 0.Requiresbit 3 tobe set 0 Attenuator1 Enable R/W 0 EnablesattenuatoforEQ 1.Requiresbit2 to be set.r 61 EQ Boost 7:5 EQ 0 BoostControl 0 SetsEQ levelforRxIN0.Requiresoverridebit Control 000:Off x10:Low (or110) x01:Mid (or101) x11:High(or111) 4:2 EQ 1 BoostControl 0 SetsEQ levelforRxIN1.Requiresoverridebit 000:Off x10:Low (or110) x01:Mid (or101) x11:High(or111) 1:0 Reserved 0

62 Reserved

63 EQ Override 7 Reserved 1

5 EQ 0 Enable R/W 1 1:EnablesEQ forRxIN0

4 EQ 1 Enable R/W 0 1:EnablesEQ forRxIN1

3:0 Reserved 0 64 — 66 Reserved

67 LT De- 7 Reserved 0

Emphasis 6:5 De-Emphasis Setting 0 00:OffControl 01:Low 10:Med 11:Max 4:0 Reserved 0 Copyright© 2008–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 27 ProductFolderLinks:DS32EL0124 DS32ELX0124

DS32EL0124,DS32ELX0124 SNLS284K –MAY 2008–REVISED APRIL 2013 www.ti.com

REVISION HISTORY

Changes from RevisionJ (April2013)toRevisionK Page

28 SubmitDocumentationFeedback Copyright© 2008–2013,Texas InstrumentsIncorporated

ProductFolderLinks:DS32EL0124 DS32ELX0124

www.ti.com 1-Nov-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) DS32EL0124SQ/NOPB Active Production WQFN (RHS) | 48 1000 | SMALL T&R Yes SN Level-3-260C-168 HR -40 to 85 32EL0124 DS32EL0124SQ/NOPB.A Active Production WQFN (RHS) | 48 1000 | SMALL T&R Yes SN Level-3-260C-168 HR -40 to 85 32EL0124 DS32EL0124SQE/NOPB Active Production WQFN (RHS) | 48 250 | SMALL T&R Yes SN Level-3-260C-168 HR -40 to 85 32EL0124 DS32EL0124SQE/NOPB.A Active Production WQFN (RHS) | 48 250 | SMALL T&R Yes SN Level-3-260C-168 HR -40 to 85 32EL0124 DS32EL0124SQX/NOPB Active Production WQFN (RHS) | 48 2500 | LARGE T&R Yes SN Level-3-260C-168 HR -40 to 85 32EL0124 DS32EL0124SQX/NOPB.A Active Production WQFN (RHS) | 48 2500 | LARGE T&R Yes SN Level-3-260C-168 HR -40 to 85 32EL0124 DS32ELX0124SQE/NO.A Active Production WQFN (RHS) | 48 250 | SMALL T&R Yes SN Level-3-260C-168 HR -40 to 85 32ELX0124 DS32ELX0124SQE/NO.B Active Production WQFN (RHS) | 48 250 | SMALL T&R - Call TI Call TI -40 to 85 DS32ELX0124SQE/NOPB Active Production WQFN (RHS) | 48 250 | SMALL T&R Yes SN Level-3-260C-168 HR -40 to 85 32ELX0124 DS32ELX0124SQX/NO.A Active Production WQFN (RHS) | 48 2500 | LARGE T&R Yes SN Level-3-260C-168 HR -40 to 85 32ELX0124 DS32ELX0124SQX/NOPB Active Production WQFN (RHS) | 48 2500 | LARGE T&R Yes SN Level-3-260C-168 HR -40 to 85 32ELX0124 (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Addendum-Page 1

www.ti.com 1-Nov-2025 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 1-Aug-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 1-Aug-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DS32EL0124SQ/NOPB WQFN RHS 48 1000 356.0 356.0 36.0 DS32EL0124SQE/NOPB WQFN RHS 48 250 208.0 191.0 35.0 DS32EL0124SQX/NOPB WQFN RHS 48 2500 356.0 356.0 36.0 DS32ELX0124SQE/NOPB WQFN RHS 48 250 208.0 191.0 35.0 DS32ELX0124SQX/NOPB WQFN RHS 48 2500 356.0 356.0 36.0 Pack Materials-Page 2

www.ti.com PACKAGE OUTLINE C SEE TERMINAL DETAIL 48X 0.30 0.18 5.1 0.1 48X 0.5 0.3 0.8 0.7 (A) TYP 0.05 0.00 44X 0.5 5.5 2X 5.5 A 7.15 6.85 B 7.15 6.85 0.30 0.18 0.5 0.3 (0.2) WQFN - 0.8 mm max heightRHS0048A PLASTIC QUAD FLATPACK - NO LEAD 4214990/B 04/2018 DIM A OPT 1 OPT 2 (0.1) (0.2) PIN 1 INDEX AREA 0.08 C SEATING PLANE 12 25 13 24 48 37 (OPTIONAL) PIN 1 ID 0.1 C A B 0.05 EXPOSED THERMAL PAD

49 SYMM

NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. SCALE 1.800 DETAIL OPTIONAL TERMINAL TYPICAL

www.ti.com EXAMPLE BOARD LAYOUT

0.07 MIN

0.07 MAX

48X (0.25) 48X (0.6) ( 0.2) TYP VIA 44X (0.5) (6.8) (6.8) (1.25) TYP ( 5.1) (R0.05) TYP (1.25) TYP (1.05) TYP (1.05) TYP WQFN - 0.8 mm max heightRHS0048A PLASTIC QUAD FLATPACK - NO LEAD 4214990/B 04/2018 SYMM 13 24 3748 SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:12X NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL METAL EDGE SOLDER MASK OPENING SOLDER MASK DETAILS NON SOLDER MASK DEFINED (PREFERRED) EXPOSED METAL

www.ti.com EXAMPLE STENCIL DESIGN 48X (0.6) 48X (0.25) 44X (0.5) (6.8) (6.8) 16X ( 1.05) (0.625) TYP (R0.05) TYP (1.25) TYP (1.25) TYP (0.625) TYP WQFN - 0.8 mm max heightRHS0048A PLASTIC QUAD FLATPACK - NO LEAD 4214990/B 04/2018 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SYMM METAL TYP SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 49 68% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SCALE:15X SYMM 13 24 3748

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