DS15BR400

DS15BR400/DS15BR401 4-Channel LVDS Buffer/Repeater with Pre-Emphasis datasheet (Rev. G)

Document overview

• Manufacturer or author: Texas Instruments, Incorporated [SNLS224,G]
• PDF pages: 23

Technical content

DS15BR400,DS15BR401 www.ti.com SNLS224G –AUGUST 2006–REVISED APRIL 2013 DS15BR400/DS15BR4014-ChannelLVDSBuffer/RepeaterwithPre-Emphasis Check forSamples: DS15BR400 ,DS15BR401 1FEATURES DESCRIPTION The DS15BR400/DS15BR401 arefourchannelLVDS 2• DC to2 Gbps Low Jitter,High Noise Immunity, buffer/repeaterscapable of data ratesof up to 2Low Power Operation Gbps. High speed datapathsand flow-throughpinout• 6 dB ofPre-emphasis DrivesLossy minimize internaldevice jitterand simplifyboard Backplanes and Cables layout,while pre-emphasis overcomes ISI jitter effectsfrom lossy backplanes and cables.The• LVDS/CML/LVPECL Compatible Input,LVDS differentialinputsinterfaceto LVDS, and Bus LVDSOutput signalssuch as those on TI's10-,16-,and 18- bit• On-chip 100 Ω outputtermination,optional100 Bus LVDS SerDes, as wellas CML and LVPECL.Ω InputTermination The differentialinputsand outputsoftheDS15BR400

• 15 kV ESD Protectionon LVDS Inputsand are internallyterminatedwith 100Ω resistorsto Outputs improveperformanceand minimizeboardspace.The DS15BR401 does not have input termination• Single3.3VSupply resistors.The repeaterfunctionis especiallyuseful• Industrial-40to+85°C Temperature Range forboostingsignalsforlongerdistancetransmission
• Space Saving WQFN-32 or TQFP-48 Packages overlossycablesand backplanes. The DS15BR400/DS15BR401 are powered from aAPPLICATIONS single3.3V supplyand consume 578 mW (typ).They
• Cable ExtensionApplications operate over the full-40°C to +85°C industrial temperaturerange and are availableinspace saving• SignalRepeatingand Buffering WQFN-32 and TQFP-48 packages.• DigitalRouters TypicalApplication Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsof Texas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2Alltrademarksarethepropertyoftheirrespectiveowners. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 2006–2013,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.

25 3626 33 3428 3529 3027 31 32 12 111 4 3 9 28 710 6 5 21 22 23 2418 201917 DAP (GND) OUT0+ OUT0- OUT1+ OUT1- OUT2+ OUT2- OUT3+ OUT3- IN0+ IN0- IN1+ IN1- IN2+ IN2- IN3+ IN3- PWDNVDD VDD GND VDD VDD PEM N/C 8 7 6 5 4 3 2 1 N/C N/C N/C VDD N/C N/C N/C VDD PEM PWDN OUT1+ OUT1-IN1- IN1+ OUT0+ OUT0-IN0- IN0+ OUT2+ OUT2-IN2- IN2+ Pre-emphasis and Control OUT3+ OUT3-IN3- IN3+ PEM PWDN OUT1+ OUT1-IN1- IN1+ OUT0+ OUT0-IN0- IN0+ OUT2+ OUT2-IN2- IN2+ Pre-emphasis and Control OUT3+ OUT3-IN3- IN3+ DS15BR400,DS15BR401 SNLS224G –AUGUST 2006–REVISED APRIL 2013 www.ti.com Block and Connection Diagrams Figure1.DS15BR400 Block Diagram Figure2.DS15BR401 Block Diagram Figure3.TQFP Pinout-Top View Figure4.WQFN Pinout-Top View PIN DESCRIPTIONS Pin TQFP Pin WQFN Pin I/O,Type DescriptionName Number Number DIFFERENTIAL INPUTS IN0+ 13 9 I,LVDS Channel0 invertingand non-invertingdifferentialinputs. IN0− 14 10 IN1+ 15 11 I,LVDS Channel1 invertingand non-invertingdifferentialinputs. IN1− 16 12 IN2+ 19 13 I,LVDS Channel2 invertingand non-invertingdifferentialinputs. IN2− 20 14 IN3+ 21 15 I,LVDS Channel3 invertingand non-invertingdifferentialinputs. IN3− 22 16

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DS15BR400,DS15BR401 www.ti.com SNLS224G –AUGUST 2006–REVISED APRIL 2013 PIN DESCRIPTIONS (continued) Pin TQFP Pin WQFN Pin I/O,Type DescriptionName Number Number DIFFERENTIAL OUTPUTS OUT0+ 48 32 O, LVDS Channel0 invertingand non-invertingdifferentialoutputs.(1) OUT0 − 47 31 OUT1+ 46 30 O, LVDS Channel1 invertingand non-invertingdifferentialoutputs.(1) OUT1 − 45 29 OUT2+ 42 28 O, LVDS Channel2 invertingand non-invertingdifferentialoutputs.(1) OUT2 − 41 27 OUT3+ 40 26 O, LVDS Channel3 invertingand non-invertingdifferentialoutputs.(1) OUT3- 39 25 DIGITAL CONTROL INTERFACE PWDN 12 8 I,LVTTL A logiclowatPWDN activatesthehardwarepower down mode (allchannels). PEM 2 2 I,LVTTL Pre-emphasisControlInput(affectsallChannels) POWER VDD 3,4,5,7,10, 3,4,6,7,20, I,Power VDD = 3.3V,±10% 11,28,29,32, 21 GND 8,9,17,18,23, 5 (2) I,Ground Ground referenceforLVDS and CMOS circuitry.FortheWQFN package,the 24,37,38,43, DAP isused as theprimaryGND connectiontothedeviceinadditiontothepin 44 numbers listed.The DAP istheexposed metalcontactatthebottomofthe WQFN-32 package.Itshouldbe connectedtothegroundplanewithatleast4 viasforoptimalAC and thermalperformance. N/C 1,6,25,26,27, 1,17, No Connect 36 24 (1) The LVDS outputsdo notsupporta multidrop(BLVDS) environment.The LVDS outputcharacteristicsoftheDS15BR400 and DS15BR401 areoptimizedforpoint-to-pointbackplaneand cableapplications. (2) Note thatfortheWQFN package theGND isconnectedthrutheDAP on theback sideoftheWQFN package inadditiontotheactual pinnumbers listed. These deviceshave limitedbuilt-inESD protection.The leadsshouldbe shortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamage totheMOS gates. Copyright© 2006–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:DS15BR400 DS15BR401

DS15BR400,DS15BR401 SNLS224G –AUGUST 2006–REVISED APRIL 2013 www.ti.com AbsoluteMaximum Ratings(1) SupplyVoltage(VDD ) −0.3Vto+4.0V CMOS InputVoltage −0.3Vto(VDD +0.3V) LVDS ReceiverInputVoltage −0.3Vto(VDD +0.3V) LVDS DriverOutputVoltage −0.3Vto(VDD +0.3V) LVDS OutputShortCircuitCurrent +40 mA JunctionTemperature +150°C StorageTemperature −65°C to+150°C Lead Temperature(Solder,4sec) 260°C Max Pkg Power Capacity@ 25°C TQFP 1.64W WQFN 4.16W ThermalResistance(θJA) TQFP 76°C/W WQFN 30°C/W Package Deratingabove +25°C TQFP 13.2mW/°C WQFN 33.3mW/°C ESD LastPassingVoltage HBM, 1.5kΩ,100pF 8 kV LVDS pinstoGND only 15 kV EIAJ,0Ω,200pF 250V Charged DeviceModel 1000V (1) Absolutemaximum ratingsarethosevaluesbeyond whichdamage tothedevicemay occur.The databookspecificationsshouldbe met, withoutexception,toensurethatthesystemdesignisreliableoveritspower supply,temperature,and output/inputloadingvariables.TI does notrecommend operationofproductsoutsideofrecommended operationconditions. Recommended OperatingConditions SupplyVoltage(VDD ) 3.0Vto3.6V InputVoltage(VI) (1) 0V toVDD OutputVoltage(VO ) 0V toVDD OperatingTemperature(TA) Industrial −40°C to+85°C (1) VID max < 2.4V ElectricalCharacteristics Over recommended operatingsupplyand temperaturerangesunlessotherspecified. TypSymbol Parameter Conditions Min Max Units(1) LVCMOS DC SPECIFICATIONS (PWDN, PEM) VIH HighLevelInputVoltage 2.0 VDD V VIL Low LevelInputVoltage GND 0.8 V IIH HighLevelInputCurrent VIN = VDD = 3.6V(PWDN pin) −10 +10 µA IIHR HighLevelInputCurrent VIN = VDD = 3.6V(PEM pin) 40 200 µA IIL Low LevelInputCurrent VIN = VSS ,VDD = 3.6V −10 +10 µA C IN1 LVCMOS InputCapacitance Any DigitalInputPintoVSS 5.5 pF VCL InputClamp Voltage ICL = −18 mA, VDD = 0V −1.5 −0.8 V (1) Typicalparametersaremeasured atVDD = 3.3V,TA = 25°C. They areforreferencepurposes,and arenotproduction-tested.

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DS15BR400,DS15BR401 www.ti.com SNLS224G –AUGUST 2006–REVISED APRIL 2013 ElectricalCharacteristics(continued) Over recommended operatingsupplyand temperaturerangesunlessotherspecified. TypSymbol Parameter Conditions Min Max Units(1) LVDS INPUT DC SPECIFICATIONS (INn±) VTH DifferentialInputHigh VCM = 0.8Vto3.55V, 0 100 mVThreshold(2) VDD = 3.6V VTL DifferentialInputLow VCM = 0.8Vto3.55V, −100 0 mVThreshold(2) VDD = 3.6V VID DifferentialInputVoltage VCM = 0.8Vto3.55V,VDD = 3.6V 100 2400 mV VCMR Common Mode VoltageRange VID = 150 mV, VDD = 3.6V 0.05 3.55 V C IN2 LVDS InputCapacitance IN+ orIN− toVSS 3.0 pF IIN InputCurrent VIN = 3.6V,VDD = 3.6V −10 +10 µA VIN = 0V,VDD = 3.6V −10 +10 µA LVDS OUTPUT DC SPECIFICATIONS (OUTn ±) VOD DifferentialOutputVoltage, R L = 100Ω externalresistorbetween OUT+ and OUT − 250 360 500 mV0% Pre-emphasis(2) Figure5 ΔVOD Change inVOD between −35 35 mVComplementaryStates VOS OffsetVoltage(3) 1.05 1.18 1.475 V ΔVOS Change inVOS between −35 35 mVComplementaryStates C OUT LVDS OutputCapacitance OUT+ orOUT − toVSS 2.5 pF IOS OutputShortCircuitCurrent OUT+ orOUT − ShorttoGND −21 −40 mA OUT+ orOUT − ShorttoVDD 6 40 mA SUPPLY CURRENT (Static) ICC SupplyCurrent Allinputsand outputsenabledand active,terminatedwith 175 215 mAdifferentialloadof100Ω between OUT+ and OUT-. PEM = L ICCZ SupplyCurrent-Power Down PWDN = L,PEM = L 20 200 µAMode SWITCHING CHARACTERISTICS — LVDS OUTPUTS tLHT DifferentialLow toHigh Use an alternating1 and 0 patternat200 Mbps, measure 170 250 psTransitionTime (4) between 20% and 80% ofVOD . Figure6 ,Figure8tHLT DifferentialHightoLow 170 250 psTransitionTime (4) tPLHD DifferentialLow toHigh Use an alternating1 and 0 patternat200 Mbps, measure at 1.0 2.0 nsPropagationDelay 50% VOD between inputtooutput. Figure6 ,Figure7tPHLD DifferentialHightoLow 1.0 2.0 nsPropagationDelay tSKD1 PulseSkew (4) |tPLHD –tPHLD | 10 60 ps tSKCC OutputChanneltoChannel Differenceinpropagationdelay(tPLHD ortPHLD )among all 25 75 psSkew (4) outputchannels. tSKP ParttoPartSkew (4) Common edge,partsatsame temp and VCC 550 ps (2) DifferentialoutputvoltageVOD isdefinedas ABS(OUT+ –OUT −).DifferentialinputvoltageVID isdefinedas ABS(IN+–IN−). (3) OutputoffsetvoltageVOS isdefinedas theaverageoftheLVDS single-endedoutputvoltagesatlogichighand logiclowstates. (4) Not productiontested.Ensuredby a statisticalanalysison a sample basisatthetimeofcharacterization. Copyright© 2006–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:DS15BR400 DS15BR401

DS15BR400,DS15BR401 SNLS224G –AUGUST 2006–REVISED APRIL 2013 www.ti.com ElectricalCharacteristics(continued) Over recommended operatingsupplyand temperaturerangesunlessotherspecified. TypSymbol Parameter Conditions Min Max Units(1) tJIT Jitter(0% Pre-emphasis) RJ -Alternating1 and 0 at750 MHz (6) 0.5 1.5 ps (5) DJ -K28.5Pattern,1.5Gbps (7) 14 30 ps TJ -PRBS 223-1Pattern,1.5Gbps (8) 14 31 ps tON LVDS OutputEnableTime Time fromPWDN toOUT ± change fromTRI-STATE toactive. 20 µsFigure9,Figure10 tOFF LVDS OutputDisableTime Time fromPWDN toOUT ± change fromactivetoTRI-STATE. 12 nsFigure9,Figure10 (5) Jitterisnotproductiontested,butensuredthroughcharacterizationon a sample basis. (6) Random Jitter,orRJ,ismeasured RMS witha histogramincluding1500 histogramwindow hits.Stimulusand fixtureJitterhas been subtracted.The inputvoltage= VID = 500 mV, inputcommon mode voltage= VICM = 1.2V,50% dutycycleat750 MHz, tr = tf= 50 ps (20% to80%). (7) DeterministicJitter,orDJ,isa peak topeak value.Stimulusand fixturejitterhas been subtracted.The inputvoltage= VID = 500 mV, streamsof(00111110101100000101). (8) TotalJitter,orTJ,ismeasured peak topeak witha histogramincluding3500 window hits.Stimulusand fixtureJitterhas been subtracted.The inputvoltage= VID = 500 mV, inputcommon mode voltage= VICM = 1.2V,223-1PRBS patternat1.5Gbps, tr = tf= 50 ps (20% to80%). DC TestCircuits Figure5. DifferentialDriverDC TestCircuit AC TestCircuitsand Timing Diagrams Figure6. DifferentialDriverAC TestCircuit Figure7. PropagationDelay Timing Diagram

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50: Pulse Generator PWDN 1/4 DS15BR400 R L/ 2 R L/ 2 1.2V Power Supply DS15BR400,DS15BR401 www.ti.com SNLS224G –AUGUST 2006–REVISED APRIL 2013 Figure8. LVDS Output TransitionTimes Figure9. Enable/DisableTime TestCircuit Figure10. Enable/DisableTime Diagram Copyright© 2006–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:DS15BR400 DS15BR401

DS15BR400,DS15BR401 SNLS224G –AUGUST 2006–REVISED APRIL 2013 www.ti.com

APPLICATION INFORMATION

The DS15BR400 has integratedterminationresistorson both the inputand outputs.The inputshave a 100Ω resistoracrossthedifferentialpair,placingthereceiverterminationas closeas possibletotheinputstageofthe device.The LVDS outputsalsocontainan integrated100Ω ohm terminationresistor,thisresistorisused to minimizethe outputreturnlossand does not takethe placeof the 100 ohm terminationat the inputsto the receivingdevice.The integratedterminationsimprove signalintegrityand decrease the externalcomponent countresultinginspace savings.The DS15BR401 has 100Ω outputterminationsonly. OUTPUT CHARACTERISTICS The outputcharacteristicsof the DS15BRB400/DS15BR401 have been optimizedforpoint-to-pointbackplane and cableapplications,and arenotintendedformultipointormultidropsignaling. POWERDOWN MODE The PWDN inputactivatesa hardwarepowerdown mode. When thepowerdown mode isactive(PWDN=L), all inputand outputbuffersand internalbiascircuitryare powered off.When exitingpowerdown mode, thereisa delayassociatedwithturningon bandgap referencesand input/outputbuffercircuitsas indicatedintheLVDS OutputSwitchingCharacteristics. Upon assertingthepower down function(PWDN = Low),and ifthePre-emphasisfeatureisenable,itispossible forthe driveroutputto sourcecurrentfora shortamount of timeliftingthe outputcommon mode to VDD . To preventthisoccurrence,a load dischargepulldown path can be used on eitheroutput(1 kΩ to ground recommended). Alternately,a commonly deployed externalfailsafenetwork willalso providethispath (see INPUT FAILSAFE BIASING).The occurrenceofthisisapplicationdependant,and parametersthatwilleffectif thisisofconcerninclude:AC coupling,use ofthepowerdown feature,presenceofthedischargepath,presence ofthefailsafebiasing,theusage ofthepre-emphasisfeature,and inputcharacteristicsofthedownstream LVDS Receiver. PRE-EMPHASIS Pre-emphasisdramaticallyreducesISIjitterfromlongorlossytransmissionmedia.One pinisused toselectthe pre-emphasislevelforalloutputs,offoron.The pre-emphasisboostisapproximately6 dB at750 MHz. Table1.Pre-emphasis ControlSelectionTable PEM Pre-Emphasis

0 Off

FailsafebiasingoftheLVDS linkshouldbe consideredifthedownstream ReceiverisON and enabledwhen the sourceisinTRI-STATE, powered off,or removed.Thiswillseta validknown inputstatetotheactivereceiver. Thisisaccomplishedby usinga pullup resistortoVDD on the‘plus’line,and a pulldown resistortoGND on the ‘minus’line.Resistorvaluesareinthe750 Ohm toseveralkΩ range.The exactvaluedepends upon thedesired common mode biaspoint,terminationresistor(s)and desiredinputdifferentialvoltagesetting.Please referto applicationnoteAN-1194 “FailsafeBiasingofLVDS interfaces” (SNLA051 ) formore informationand a general discussion. DECOUPLING Each power orgroundleadoftheDS15BR400 shouldbe connectedtothePCB througha low inductancepath. For bestresults,one or more viasare used toconnecta power or ground pintothenearbyplane.Ideally,via placementisimmediatelyadjacenttothepintoavoidaddingtraceinductance.Placingpower planeclosertothe topoftheboardreduceseffectivevialengthand itsassociatedinductance.

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150-250: 100: Differential T-Line LVDS Receiver IN+ IN- 100: LVPECL Driver 150-250: OUT+ OUT- 50:50: VCC CML3.3V or CML2.5V Driver 100: Differential T-Line DS15BR400 Receiver IN+ IN- 100: OUT+ OUT- DS15BR400 Receiver IN+ IN- 100: Differential T-Line 100: LVDS Driver DS15BR400,DS15BR401 www.ti.com SNLS224G –AUGUST 2006–REVISED APRIL 2013 Bypass capacitorsshouldbe placedcloseto VDD pins.Small physicalsizecapacitors,such as 0402, X7R, surfacemount capacitorsshouldbe used tominimizebody inductanceofcapacitors.Each bypass capacitoris connectedto the power and ground planethroughviastangentto the pads of the capacitor.An X7R surface mount capacitorofsize0402 has about0.5nH ofbody inductance.At frequenciesabove 30 MHz or so,X7R capacitorsbehave as low impedance inductors.To extendtheoperatingfrequencyrangetoa few hundredMHz, an arrayofdifferentcapacitorvalueslike100 pF,1 nF,0.03µF,and 0.1µF arecommonly used inparallel.The most effectivebypasscapacitorcan be builtusingsandwichedlayersofpower and groundata separationof2–3 mils.Witha 2 milFR4 dielectric,thereisapproximately500 pF persquareinchofPCB. The centerdap oftheWQFN package housingtheDS15BR400 shouldbe connectedtoa groundplanethrough an array of vias.The via array reduces the effectiveinductanceto ground and enhances the thermal performanceoftheWQFN package. INPUT INTERFACING The DS15BR400 and DS15BR401 acceptdifferentialsignalsand allowsimpleAC or DC coupling.With a wide common mode range,theDS15BR400 and DS15BR401 can be DC-coupledwithallcommon differentialdrivers (i.e.LVPECL, LVDS, CML). The followingthreefiguresillustratetypicalDC-coupled interfaceto common differentialdrivers.Note thatthe DS15BR400 inputsare internallyterminatedwitha 100Ω resistorwhilethe DS15BR401 inputsarenot,thereforethelatterrequiresexternalinputtermination. Figure11. TypicalLVDS DriverDC-Coupled InterfacetoDS15BR400 Input Figure12. TypicalCML DriverDC-Coupled InterfacetoDS15BR400 Input Figure13. TypicalLVPECL DriverDC-Coupled InterfacetoDS15BR400 Input Copyright© 2006–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:DS15BR400 DS15BR401

100: 100: Differential T-Line Differential Receiver DS15BR400 Driver 100: DS15BR400,DS15BR401 SNLS224G –AUGUST 2006–REVISED APRIL 2013 www.ti.com OUTPUT INTERFACING The DS15BR400 and DS15BR401 outputsignalsthatarecomplianttotheLVDS standard.Theiroutputscan be DC-coupledtomost common differentialreceivers.Figure14 illustratestypicalDC-coupledinterfacetocommon differentialreceiversand assumes thatthe receivershave high impedance inputs.While most differential receivershave a common mode inputrangethatcan accomodate LVDS compliantsignals,itisrecommended to checkrespectivereceiver'sdatasheetpriortoimplementingthesuggestedinterfaceimplementation. Figure14. TypicalDS15BR400 Output DC-Coupled Interfacetoan LVDS, CML or LVPECL Receiver

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0.5 1.0 1.5 2.0 2.5 CABLE LENGTH (m) DATA RATE (Gbps) VCC = 3.3V NRZ PRBS-23 Jitter = 0.5 UI TA = 25° C CAT5e PEM ON PEM OFF 1 10 20 30 40 0.5 1.0 1.5 2.0 2.5 CABLE LENGTH (m) DATA RATE (Gbps) VCC = 3.3V NRZ PRBS-23 Jitter = 0.25 UI TA = 25 ° C CAT5e PEM ON PEM OFF VCC = 3.3V VID = 500 mV VCM = 1.2V NRZ PRBS-23 TA = 25° C TOTAL JITTER (ps) DATA RATE (Gbps) 300 250 200 150 100 VCC = 3.3V VID = 500 mV VCM = 1.2V NRZ PRBS-23 TA =25° C POWER SUPPLY CURRENT (mA) DATA RATE (Gbps) -40 -20 0 20 40 60 80 100 VCC = 3.3V VID = 500 mV VCM = 1.2V NRZ PRBS-23

1.5 Gbps

TEMPERATURE (° C) TOTAL JITTER (ps) DS15BR400,DS15BR401 www.ti.com SNLS224G –AUGUST 2006–REVISED APRIL 2013 TypicalPerformance Characteristics Power Supply Currentvs.Data Rate TotalJittervs.Ambient Temperature Figure15. Figure16. TotalJittervs.Data Rate Data Rate vs.Cable Length (0.25UI Criteria) Figure17. Figure18.(1) Data Rate vs.Cable Length (0.5UI Criteria) Figure19. (1) (1) Data presentedinthisgraphwas collectedusingtheDS15BR400EVK, a pairofRJ-45 toSMA adapterboardsand variouslength Belden1700a cables.The maximum dataratewas determinedbased on totaljitter(0.25UI criteria)measured afterthecable.The total jitterwas a peak topeak valuemeasured witha histogramincluding3000 window hits. Copyright© 2006–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:DS15BR400 DS15BR401

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REVISION HISTORY

Changes from RevisionF (April2013)toRevisionG Page

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www.ti.com 1-Nov-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) DS15BR400TSQ/NOPB Active Production WQFN (RTV) | 32 1000 | SMALL T&R Yes SN Level-3-260C-168 HR -40 to 85 5R400SQ DS15BR400TSQ/NOPB.A Active Production WQFN (RTV) | 32 1000 | SMALL T&R Yes SN Level-3-260C-168 HR -40 to 85 5R400SQ DS15BR400TVS/NOPB Active Production TQFP (PFB) | 48 250 | JEDEC TRAY (10+1) Yes SN Level-3-260C-168 HR -40 to 85 DS15BR 400TVS DS15BR400TVS/NOPB.A Active Production TQFP (PFB) | 48 250 | JEDEC TRAY (10+1) Yes SN Level-3-260C-168 HR -40 to 85 DS15BR 400TVS DS15BR400TVS/NOPB.B Active Production TQFP (PFB) | 48 250 | JEDEC TRAY (10+1) - Call TI Call TI -40 to 85 DS15BR400TVSX/NOPB Active Production TQFP (PFB) | 48 1000 | LARGE T&R Yes SN Level-3-260C-168 HR -40 to 85 DS15BR 400TVS DS15BR400TVSX/NOPB.A Active Production TQFP (PFB) | 48 1000 | LARGE T&R Yes SN Level-3-260C-168 HR -40 to 85 DS15BR 400TVS DS15BR400TVSX/NOPB.B Active Production TQFP (PFB) | 48 1000 | LARGE T&R - Call TI Call TI -40 to 85 DS15BR401TSQ/NOPB Active Production WQFN (RTV) | 32 1000 | SMALL T&R Yes SN Level-3-260C-168 HR -40 to 85 5R401SQ DS15BR401TSQ/NOPB.A Active Production WQFN (RTV) | 32 1000 | SMALL T&R Yes SN Level-3-260C-168 HR -40 to 85 5R401SQ DS15BR401TVS/NOPB Active Production TQFP (PFB) | 48 250 | JEDEC TRAY (10+1) Yes SN Level-3-260C-168 HR -40 to 85 DS15BR 401TVS DS15BR401TVS/NOPB.A Active Production TQFP (PFB) | 48 250 | JEDEC TRAY (10+1) Yes SN Level-3-260C-168 HR -40 to 85 DS15BR 401TVS DS15BR401TVSX/NOPB Active Production TQFP (PFB) | 48 1000 | LARGE T&R Yes SN Level-3-260C-168 HR -40 to 85 DS15BR 401TVS DS15BR401TVSX/NOPB.A Active Production TQFP (PFB) | 48 1000 | LARGE T&R Yes SN Level-3-260C-168 HR -40 to 85 DS15BR 401TVS DS15BR401TVSX/NOPB.B Active Production TQFP (PFB) | 48 1000 | LARGE T&R - Call TI Call TI -40 to 85 (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. Addendum-Page 1

www.ti.com 1-Nov-2025 (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 3-Aug-2026 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 3-Aug-2026 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DS15BR400TSQ/NOPB WQFN RTV 32 1000 208.0 191.0 35.0 DS15BR400TVSX/NOPB TQFP PFB 48 1000 356.0 356.0 36.0 DS15BR401TSQ/NOPB WQFN RTV 32 1000 208.0 191.0 35.0 DS15BR401TVSX/NOPB TQFP PFB 48 1000 356.0 356.0 36.0 Pack Materials-Page 2

www.ti.com PACKAGE OUTLINE C 48X 0.27 0.1744X 0.5 PIN 1 ID (0.13) TYP

0.05 MIN0 -7

4X 5.5 9.2

8.8 TYP

0.75 0.45 B7.2 6.8 NOTE 3 A 7.2 6.8 NOTE 3 0.25 GAGE PLANE

1.2 MAX

(1) PLASTIC QUAD FLATPACK TQFP - 1.2 mm max heightPFB0048A PLASTIC QUAD FLATPACK 4215157/A 03/2024 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Reference JEDEC registration MS-026. 13 24 3748

0.08 C A B

0.08 A 16 DETAIL A TYPICAL SCALE 1.900

www.ti.com EXAMPLE BOARD LAYOUT

0.05 MAX

0.05 MIN

(8.5) (8.5) 44X (0.5) 48X (1.35) 48X (0.25) (R0.05) TYP TQFP - 1.2 mm max heightPFB0048A PLASTIC QUAD FLATPACK 4215157/A 03/2024 NOTES: (continued) 4. Publication IPC-7351 may have alternate designs. 5. Solder mask tolerances between and around signal pads can vary based on board fabrication site. LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SYMM SYMM 48 37 13 24 SEE DETAILS METAL SOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS EXPOSED METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL

www.ti.com EXAMPLE STENCIL DESIGN 44X (0.5) 48X (1.35) 48X (0.25) (R0.05) TYP (8.5) (8.5) TQFP - 1.2 mm max heightPFB0048A PLASTIC QUAD FLATPACK 4215157/A 03/2024 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 7. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE SCALE:8X SYMM SYMM 48 37 13 24

www.ti.com PACKAGE OUTLINE C 5.15 4.85 5.15 4.85 0.8 0.7 0.05 0.00 2X 3.5 28X 0.5 2X 3.5 32X 0.5 0.3 32X 0.30 0.18 3.1 0.1 (0.1) TYP WQFN - 0.8 mm max heightRTV0032A PLASTIC QUAD FLATPACK - NO LEAD 4224386/B 04/2019 0.08 C

0.1 C A B

0.05 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. PIN 1 INDEX AREA SEATING PLANE PIN 1 ID SYMMEXPOSED THERMAL PAD SYMM 9 16 2532 SCALE 2.500 AB

www.ti.com EXAMPLE BOARD LAYOUT 28X (0.5) (1.3) (1.3) (R0.05) TYP

0.07 MAX

0.07 MIN

32X (0.6) 32X (0.24) (4.8) (4.8) (3.1) (3.1) ( 0.2) TYP VIA WQFN - 0.8 mm max heightRTV0032A PLASTIC QUAD FLATPACK - NO LEAD 4224386/B 04/2019 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. SYMM SYMM SEE SOLDER MASK DETAIL LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 15X 9 16 2532 METAL EDGE SOLDER MASK OPENING EXPOSED METAL METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METAL NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED SOLDER MASK DETAILS

www.ti.com EXAMPLE STENCIL DESIGN 32X (0.6) 32X (0.24) 28X (0.5) (4.8) (4.8) (0.775) TYP (0.775) TYP 4X (1.35) 4X (1.35) (R0.05) TYP WQFN - 0.8 mm max heightRTV0032A PLASTIC QUAD FLATPACK - NO LEAD 4224386/B 04/2019 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SOLDER PASTE EXAMPLE BASED ON 0.125 MM THICK STENCIL SCALE: 20X EXPOSED PAD 33 76% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SYMM SYMM 9 16 2532

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