DS110DF111

DS110DF111 Low-Power, Multirate, 2-Channel Retimer datasheet (Rev. A)

Document overview

• Manufacturer or author: Texas Instruments, Incorporated [SNLS461,A]
• PDF pages: 55

Technical content

OUTA_P OUTA_N INB_P INB_N SCL ADDR0/LOCK SDA INA_P INA_N OUTB_P OUTB_N 100nF 100nF

25 MHz

3.3V 0.22/c1dF (2x) REFCLK_IN EN_SMB GND 1k/c3a 1k/c3a1k/c3a 1k/c3a 2k/c3a2k/c3a ADDR1/VODB/DONE# VODA/READ_EN 100nF 100nF 3.3V TX_DIS 1k/c3a 22nFLPF_REF_A LPF_CP_A 22nFLPF_REF_B LPF_CP_B DAP VIN 1/c1dF 3.3V GND Product Folder Sample & Buy T echnical Documents Tools & Software Support & Community DS110DF111 SNLS461A –MAY 2013–REVISED JUNE 2015 DS110DF111Low-Power,Multirate,2-ChannelRetimer

1 Features 3 Description

The DS110DF111 is a dual-channel (1-lane 1• Pin-Compatible Retimer Family bidirectional) retimer with integrated signal– DS110DF111 With DFE: 8.5 to 11.3 Gbps conditioning. The DS110DF111 includes an input – DS125DF111 With DFE: 9.8 to 12.5 Gbps Continuous-Time Linear Equalizer (CTLE), clock and data recovery (CDR), and transmit driver on each• Adaptive CTLE Up to 34 dB Boost at 5.65 GHz channel.• Self-Tuning 5-Tap DFE The DS110DF111 with its on-chip Decision Feedback• Raw Equalized and Retimed Data Loopback Equalizer (DFE) can enhance the reach and• Adjustable Transmit VOD: 600 to 1300 mVp-p robustness of long, lossy, cross-talk-impaired high

• Settable TX De-Emphasis Driver 0 to –12 dB speed serial links to achieve BER < 1x10-15. For less- demanding applications and interconnects, the DFE• Low Power Consumption: 200 mW/Channel can be switched off and achieve the same BER• Locks to Half, Quarter, and Eighth Data Rates for performance. The DS125DF111 and DS110DF111Legacy Support devices are pin-compatible.
• On-Chip Eye Monitor (EOM), PRBS Generator Each channel of the DS110DF111 independently• Input Signal Detection, CDR Lock locks to serial data at data rates from 8.5 to 11.3Detection/Indicator Gbps or to any supported subrate of these data rates.
• Single 3.3-V or 2.5-V ±5% Power Supply This simplifies system design and lowers overall cost.
• SMBus, EEPROM, or Pin-Based Configuration Programmable transmit de-emphasis driver offers
• 4.0-mm × 4.0-mm, 24-Pin QFN Package precise settings to meet the SFF-8431 output eye template. The fully adaptive receive equalization• Operating Temp Range: –40°C to 85°C (CTLE and DFE) enables longer distance transmission in lossy copper interconnect and2 Applications backplanes with multiple connectors. The CDR
• Front Port Optical Interconnects function is ideal for use in front port parallel optical module applications to reset the jitter budget and• SFF-8431 retime high-speed serial data.• 10G/1G Ethernet
• CPRI Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) DS110DF111 WQFN (24) 4.0 mm × 4.0 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. Simplified Schematic An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

SNLS461A –MAY 2013–REVISED JUNE 2015 www.ti.com Table of Contents

4 Revision History

Changes from Original (May 2013) to Revision A Page

• Added Pin Configuration and Functions section, Handling Rating table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information

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Product Folder Links: DS110DF111

LOS/INT# LPF_CP_BLPF_REF_BREFCLK_IN OUTA+ OUTA- OUTB- VDD LPF_CP_AENSMB 1256 3 SCL/DEMB LPF_REF_ASDA/DEMA VDD TX_DIS/LBK VODA/READEN# ADDR1/VODB/DONE# TOP VIEW DS110DF111 DAP = GND 4 mm x 4 mm, 0.5 mm pitch DS110DF111 www.ti.com SNLS461A –MAY 2013–REVISED JUNE 2015

5 Pin Configuration and Functions

HIGH SPEED DIFFERENTIAL I/OS Inverting and noninverting CML-compatible differential outputs.OUTA± 7, 8 O, CML Outputs require AC coupling Inverting and noninverting CML-compatible differential outputs.OUTB± 20, 19 O, CML Outputs require AC coupling Inverting and noninverting CML-compatible differential inputs. An on-chip

100 Ohm terminating resistor connects INA+ to INA-

INA± 24, 23 I, CML Inputs require AC coupling. TI recommends 100 nF capacitors. Note that for SFP+ applications, AC coupling is included as part of the SFP+ module. Inverting and noninverting CML-compatible differential inputs. An on-chip

100 Ohm terminating resistor connects INB+ to INB-

INB± 11, 12 I, CML Inputs require AC coupling. TI recommends 100 nF capacitors. Note that for SFP+ applications, AC coupling is included as part of the SFP+ module. LOOP FILTER CONNECTION PIN Loop filter connection, place a 22 nF capacitor in series betweenLPF_CP_A, LPF_REF_A 2, 1 I/O, analog LPF_CP_A and LPF_REF_A Loop filter connection, place a 22 nF capacitor in series betweenLPF_CP_B, LPF_REF_B 17, 18 I/O, analog LPF_CP_B and LPF_REF_B Reference Clock I/O REFCLK_IN 14 I, LVCMOS 25 MHz ±100 ppm clock from external Oscillator Copyright © 2013–2015, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: DS110DF111

SNLS461A –MAY 2013–REVISED JUNE 2015 www.ti.com Pin Functions (continued) PIN TYPE DESCRIPTION NAME NUMBER INDICATOR PINS Goes high when CDR lock is attained on the corresponding channel.LOCK 16 O, LVCMOS Note that this terminal is shared with strap input functions read at startup Output is driven LOW when a valid signal is present on CH A. Output is released when signal on CH A is lost (LOS). This output can beLOS/INT# 13 O, OD redefined as an INT# signal which will be driven LOW if the EOM check returns a value below the HEO/VEO interrupt threshold(1) SMBus MODE PINS System Management Bus (SMBus) enable terminal HIGH = Register Access, SMBus Slave modeENSMB 3 I, 4-Level FLOAT = SMBus Master read from External EEPROM LOW = External Pin Control Mode Data Input / Open Drain OutputI, SMBusSDA 4 External pull-up resistor is required. Terminal is 3.3 V LVCMOSO, OD tolerant(2) Clock input in SMBus slave mode. Can also be an open drain output inI, SMBusSCL 5 SMBus master modeO, OD Pin is 3.3 V LVCMOS Tolerant(2) Disable the OUTB transmitter HIGH = OUTA Enabled/OUTB Disabled TX_DIS 6 I, 4-Level FLOAT = Reserved 20K to GND = Reserved LOW = OUTA/OUTB Enabled (normal operation) This pin sets the SMBus address for the retimer. ADDR0 16 I, LVCMOS This pin is a strap input. The state is read on power-up to set the SMBus address in SMBus control mode(2) This pin sets the SMBus address for the retimer in SMBus Slave Mode. ADDR1/DONE# 10 IO, LVCMOS Goes low to indicate that the SMBus master EEPROM read has been completed in SMBus Master Mode(2) Initiates SMBus master EEPROM read. When multiple DS110DS111 are connected to a single EEPROM, the READEN# input can be daisyREADEN# 9 I, 4-Level chained to the DONE# output. In SMBus Slave Mode, pull low to Logic 0 proper register operation(2) PIN CONTROL (ENSMB = LOW)(3) DEMA 4 I, 4-Level Set CHA output de-emphasis level in pin control mode(2) DEMB 5 I, 4-Level Set CHB output de-emphasis level in pin control mode(2) HIGH = INA goes to OUTA, INB goes to OUTB FLOAT = INB goes to OUTA and OUTBLBK 6 I, 4-Level 20K to GND = INA goes to OUTA and OUTB LOW = INA goes to OUTB, INB goes to OUTA(2) VODA 9 I, 4-Level Set CHA output launch amplitude in pin control mode(2) VODB 10 I, 4-Level Set CHB output launch amplitude in pin control mode(2) POWER VDD = 2.5 V ±5% VDD 21, 22 Power 3.3 V Mode Operation: VDD Supply Output = 2.5 V ±5% 2.5 V Mode Operation: VDD Supply Input = 2.5 V ±5% Regulator Input with Integrated Supply Mode Control VIN 15 Power 3.3 V Mode Operation: VIN Supply Input = 3.3 V ±10% 2.5 V Mode Operation: VIN Supply Input = 2.5 V ±5% Ground reference The exposed pad at the center of the package must be connected toDAP PAD Power ground plane of the board with at least 4 vias to lower the ground impedance and improve the thermal performance of the package (1) The LOS/INT# pin is an open drain output which requires external pull-up resistor to 3.3 V to achieve a HIGH level. (2) This terminal is shared with other functions. (3) When in pin control mode the DS110DF111 device operates at 1.25 and 10.3125 Gbps and has limited VOD and De-Emphasis control.

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Product Folder Links: DS110DF111

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6 Specifications

6.1 Absolute Maximum Ratings(1)

Supply Voltage (VDD) –0.5 +2.75 V Supply Voltage (VIN) –0.5 +4.0 V LVCMOS Input/Output Voltage –0.5 +4.0 V 4-Level Input Voltage (2.5 V mode) –0.5 +2.75 V 4-Level Input Voltage (3.3 V mode) –0.5 4.0 V SMBus Input/Output Voltage –0.5 4.0 V CML Input Voltage –0.5 VDD + 0.5 V CML Input Current –30 +30 mA Storage Temperature Tstg –40 +125 °C (1) For soldering specifications, see product folder at www.ti.com

6.2 ESD Ratings

HBM, STD - JESD22-A114F(2) ±2500 V ESD Rating(1) CDM, STD - JESD22-C101-D(3) ±1000 V (1) Electrostatic discharge (ESD) to measure device sensitivity and immunity to damage caused by assembly line electrostatic discharges in to the device. (2) Level listed above is the passing level per ANSI, ESDA, and JEDEC JS-001. JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (3) Level listed above is the passing level per EIA-JEDEC JESD22-C101. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

2.5 V Mode 2.375 2.5 2.625 Supply Voltage V 3.3 V Mode 3.0 3.3 3.6 Ambient Temperature –40 25 +85 °C SMBus (SDA, SCL) 3.0 3.3 3.6 V

6.4 Thermal Information

THERMAL METRIC(1) WQFN (RTW) UNIT

24 PINS

θJA Junction-to-ambient thermal resistance 35.0 °C/W RθJC(top) Junction-to-case (top) thermal resistance 34.0 °C/W RθJB Junction-to-board thermal resistance 13.4 °C/W ψJT Junction-to-top characterization parameter 0.3 °C/W ψJB Junction-to-board characterization parameter 13.4 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 3.3 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. Copyright © 2013–2015, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: DS110DF111

SNLS461A –MAY 2013–REVISED JUNE 2015 www.ti.com

6.5 Electrical Characteristics

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT R_baud Input baud rate Full Rate: DS110DF111 8.5 11.3 Gbps Slave Mode Clock Rate 100 400 FSDC SMBus Clock Rate kHz Master Mode Clock Rate 280 400 520 REFCLK Clock Rate ± 100 ppm 25.0 MHz POWER SUPPLY CURRENT

11.3 Gbps : DS110DF111 170 mA

11.3 Gbps : DS110DF111 150 mADFE DisabledCurrent ConsumptionIDD Maximum Transient Supply Current(Whole Device) Default Settings: CHA and CHB 235 300 mAvalid input signal detected CHA and CHB acquiring LOCK

50 Hz to 100 Hz 100 mVp-p

NTps Supply Noise Tolerance 100 Hz to 10 MHz 40 mVp-p 10 MHz to 5.0 GHz 10 mVp-p LVCMOS (LBK, READEN#, DONE#, LOCK) VIH High level input voltage 2.5 V or 3.3 V Supply Modes 1.7 VIN V VIL Low level input voltage 2.5 V or 3.3 V Supply Modes 0.7 VOH High level output voltage IOH = –3 mA 2.0 VIN V VOL Low level output voltage IOL = 3 mA 0.4 IIN Input leakage current VINPUT = GND or VIN –15 +15 μA 4-LEVEL INPUTS (ENSMB, DEMA, DEMB, TX_DIS, VODA, VODB) IIN-R Input leakage current VINPUT = GND or VIN –160 +80 μA OPEN DRAIN (LOS/INT#) VOL Low level output voltage IOL = 3 mA 0.4 V SIGNAL DETECT Signal Detect: Default level to assertSDH 20 mVp-pON Threshold Level Signal Detect, 10.3125 Gbps Signal Detect: Default level to de-assertSDL 15 mVp-pOFF Threshold Level Signal Detect, 10.3125 Gbps CML RX INPUTS R_Rd DC Input differential Resistance 100 Ω SDD11 10 MHz –19 RLRX-IN Input Return-Loss SDD11 2.0 GHz –14 dB SDD11 6.0 - 11.1 GHz –8 VRX- Source Transmit Signal Level 600 1600 mVp-p LAUNCH CML TX OUTPUTS T_VDIFF0 Output differential voltage Default setting, PRBS31 400 550 675 mVp-p Maximum setting, PRBS31T_VDIFF7 Output differential voltage 1000 1250 mVp-pRequires SMBus Control Maximum setting, VOD and DE VOD_DE De-emphasis Level Requires SMBus Control –12 dB Input: 10.3125Gbps, 64T pattern T_Rd DC Output Differential Resistance 100 Ω Full Slew Rate TR/TF Output Rise/Fall Time 20% - 80% 36 ps Input: 10.3125 Gbps, 8T Pattern Limited Slew Rate (Reg 0x18) TRS/TFS Output Rise/Fall Time 20% - 80% 50 ps Input: 10.3125 Gbps, 8T Pattern

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www.ti.com SNLS461A –MAY 2013–REVISED JUNE 2015 Electrical Characteristics (continued) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SDD22 10 MHz - 2 GHz –19 TSDD22 Output differential mode return loss SDD22 5.5GHz –15 dB SDD22 11.1GHz –11 TPD Propagation Delay Retimed Data 10.3125 Gbps 350 ps TPD-RAW Propagation Delay Raw Data 200 ps TRANSMIT JITTER SPECS (1) TTJ Total Jitter (1E-12) PRBS7, 10.3125 Gbps 7.5 ps TRJ Random Jitter PRBS7, 10.3125 Gbps 0.33 ps (RMS) TDJ Deterministic Jitter PRBS7, 10.3125 Gbps 3.6 ps CLOCK AND DATA RECOVERY BWP LL PLL Bandwidth –3 dB Measured at 10.3125 Gbps 5 MHz Jitter per SFF-8431 Appendix D.11JTOL Total jitter tolerance > 0.70 UICombination of Dj, Pj, and Rj TLOCK1 CDR Lock Time Standards Based(2) 10 - 30 ms Lock Temperature RangeTEMPLOCK CDR Lock 125 °C–40°C to 85°C operating range SERIAL BUS INTERFACE CHARACTERISTICS(3) Data, Clock Input Low VoltageVIL 0.8 V(SDA / SCL) Data, Clock Input High VoltageVIH 2.1 3.6 V(SDA / SCL) VHY Input Hystersis >50 mV VOL Output Low Voltage SDA or SCL, IOL = 1.25 mA 0 0.36 V SDA or SCL, VINPUT = VIN, VDD,IIN Input Current –15 +15 μAGND TR SDA Rise Time, Read Operation SDA, RPU = 10K, Cb < 400 pF 430 ns TF SDA Fall Time, Read Operation SDA, RPU = 10K, Cb < 400 pF 20 ns TSU;DAT Setup Time, Read Operation 560 ns THD;DAT Hold Time, Read Operation 615 ns TSP Input Filter 50 ns CIN Input Capacitance SDA or SCL < 5 pF RECOMMENDED TIMING FOR THE SERIAL BUS INTERFACE FSCL SCL Clock Frequency 400 kHz TLOW SCL Low Period 1300 ns THIGH SCL High Period 600 ns THD;STA Hold Time, Start Operation 600 ns TSU;STA Setup Time, Start Operation 600 ns THD;DAT Data Hold Time 0 900 ns TSU;DAT Data Set Up Time 100 ns TSU;STO Set Up Time, Stop Condition 600 ns Bus Free TimeTBUF 1300 nsBetween Stop - Start TF SCL and SDA, Fall Time 300 ns TR SCL and SDA, Rise Time 1000 ns (1) Rj and Dj Jitter decomposition as reported by TEK DSA8200 Sampling scope using a 80E09 Electrical sampling module, 80A06 Pattern trigger, and 82A04 Phase Reference Module. (2) The typical LOCK time can vary based on data-rate, input channel, and specific DS110DF111 settings. (3) EEPROM interface requires 520 kHz capable (1 MHz Recommended) EEPROM device. Copyright © 2013–2015, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: DS110DF111

Figure 1. Output Edge Rate Figure 2. Propagation Delay Figure 3. SMBus Timing Diagram

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6.6 Typical Characteristics

Figure 5. Output Eye Diagram 10.3125 GbpsFigure 4. De-Emphasis Gain vs. Frequency

7 Detailed Description

7.1 Overview

an independent Voltage-Controlled Oscillator (VCO) and Phase-Locked Loop (PLL) which produce a clean clock.

7.2 Functional Block Diagram

Figure 6. DS110DF111 Data Path Block Diagram

7.3 Feature Description

7.3.1 Device Data Path Operation

The data path operation of the DS110DF111 is shown Figure 6. The functional sections are as follows.

• Input Channel Equalization
• Clock and Data Recovery
• PRBS Pattern Generator
• Datapath Multiplexer and Output Driver
• Reference Clock
• Control Pins
• Eye Opening Monitor

7.3.1.1 Input Channel Equalization

high-speed broadband signals propagating through the transmission medium.

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www.ti.com SNLS461A –MAY 2013–REVISED JUNE 2015 Feature Description (continued) To make configuration of these settings easier, the DS110DF111 is designed to determine the correct settings for the CTLE autonomously by automatically adapting these equalizations to the input transmission medium. The automatic adaptation takes place when a signal is first detected at the input to the DS110DF111, immediately after the DS110DF111 acquires phase lock. The automatic adaptation is also triggered whenever the CDR circuitry is reset. The DS110DF111 uses its internal eye monitor to generate a figure of merit for the adaptation. The DS110DF111 adjusts its CTLE boost settings in a systematic way to optimize this figure of merit. When 8b/10b encoding is used and the input channels has more than 15 dB of loss, the CTLE table and or adaption algorithm needs to be modified so as to prevent CTLE mal-adaption. This scenario occurs when the CTLE boost is insufficient at lower settings to cause regeneration of the high-frequency content of the K28.5 pattern. As boost is increased, the adaption Figure of Merit (FOM) temporarily observes eye closure as the EQ boost begins to restore the high-frequency content. If the FOM does not improve within the look-beyond counter depth, the CTLE will settle at a lower boost, which is insufficient to equalize the signal and provide good BER. The 5-tap DFE discriminates against input noise and random jitter as well as against crosstalk at the input to the DS110DF111. The DFE tap weights and polarities are adaptive and operate in conjunction with the CTLE to achieve an acceptable BER with more severe channel impairments.

7.3.1.2 Clock And Data Recovery

The DS110DF111 performs its clock and data recovery function by detecting the bit transitions in the incoming data stream and locking its internal VCO to the clock represented by the mean arrival times of these bit transitions. This process produces a recovered clock with greatly reduced jitter at jitter frequencies outside the bandwidth of the CDR Phase-Locked Loop (PLL). This is the primary benefit of using the DS110DF111 in a system. It significantly reduces the jitter present in the data stream, in effect resetting the jitter budget for the system.

7.3.1.3 PRBS Pattern Generator

Each channel in the DS110DF111 can be configured to generate and output its own pseudo random bit sequence (PRBS). The DS110DF111 pattern generators support the following PRBS sequences:

• PRBS-9, 29 - 1
• PRBS-31, 231 - 1

7.3.1.4 Datapath Multiplexer and Output Driver

The DS110DF111 datapath multiplexer is used to control which internal signal will be presented to the output driver block. Inputs to this multiplexer include raw equalized data without clock recovery, retimed data, PRBS patterns, and Loopback data from the other datapath. The DS110DF111 output driver is used to control specific signal characteristics to enhance transmission quality. The output driver is used to control the following signal features

• Amplitude
• De-Emphasis
• Edge Rate
• Polarity The DS110DF111 is commonly used in applications where lossy transmission media exist both at the input and the output of the DS110DF111. The CTLE compensates for lossy transmission media at the input to the DS110DF111. The output de-emphasis compensates for the lossy transmission medium at the output of the DS110DF111. When there is a transition in the output data stream, the output differential voltage reaches its configured maximum value within the configured rise/fall time of the output driver. Following this, the differential voltage rapidly falls off until it reaches the configured VOD level minus the configured de-emphasis level. This accentuates the high-frequency components of the output driver signal at the expense of the low frequency components. The pre-distorted DS110DF111 output signal, with high-frequency components emphasized relative to its low frequency components, exhibits less inter-symbol interference after traveling down a dispersive transmission medium than an undistorted output signal. Copyright © 2013–2015, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Links: DS110DF111

An idealized transmit waveform with analog de-emphasis applied is shown in Figure 7. Figure 7. Idealized De-Emphasis Waveform The output driver is capable of driving variable output voltages with variable amounts of analog de-emphasis. is responsible for configuring these parameters. They can be set for each channel independently.

7.3.1.5 Reference Clock

DS110DF111 does not include a crystal driver, so a stand-alone external oscillator is required. VIN level used on the DS110DF111.

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7.3.1.6 Control Pins

settings when ENSMB=0. There is an internal 30K pull-up and a 60K pull-down connected to the package pin. These resistors, together with the external resistor connection combine to achieve the desired voltage level. Table 1. 4-Level Inputs resistor is a good way to save board space.

7.3.1.6.1 Pin Mode Limitation

7.3.1.7 Eye Opening Monitor

1. Horizontal Eye Opening (HEO) and Vertical Eye Opening (VEO) measurement

• HEO [UI] = ch reg 0x27 ÷ 64
• VEO [mV] = ch reg 0x28 x 3.125 A full eye diagram capture can be performed when the CDR is locked. The eye diagram is constructed within a 64 x 64 array, where each cell in the matrix consists of an 16-bit word. Users can manually adjust the vertical scaling of the EOM or allow the state machine to control the scaling which is the default option. The horizontal scaling controlled by the state machine and is always directly proportional to the data rate. When a full eye diagram plot is captured, the retimer will shift out 4 16-bit words of junk data that should be discarded followed by 4096 16-bit words that make up the 64 x 64 eye plot. The first actual word of the eye plot from the retimer is for (X, Y) position (0,0). Each time the eye plot data is read out the voltage position is incremented. Once the voltage position has incremented to position 63, the next read will cause the voltage position to reset to 0 and the phase position to increment. This process will continue until the entire 64 x 64 matrix is read out. Figure 8 shows the EOM read out sequence overlaid on top of a simple eye opening plot. In this plot any hits are shown in green. This type of plot is helpful for quickly visualizing the HEO and VEO. Users can apply different algorithms to the output data to plot density or color gradients to the output data. Copyright © 2013–2015, Texas Instruments Incorporated Submit Documentation Feedback 13 Product Folder Links: DS110DF111

Figure 8. EOM Full Eye Capture Readout Table 2. Eye Opening Monitor Vertical Range Settings

• Multi-byte reads can be used such that data is repeatedly latched out from channel register 0x25.
• Or single byte reads. With single byte reads, the MSB are located in register 0x25 and the LSB are located in register 0x26. In this mode, the device must be addressed each time a new byte is read.

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Table 3. Eye Opening Monitor Full Eye Capture Instructions

7.4 Device Functional Modes

be programmed using external pin control, a SMBus controller, or through an EEPROM configuration load. Table 4. ENSMB Control Description

7.4.1 Control Pin Mode

settings when ENSMB=0. There is an internal 30K pull-up and a 60K pull-down connected to the package pin. These resistors, together with the external resistor connection combine to achieve the desired voltage level. Table 5. 4-Level Inputs resistor is a good way to save board space.

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7.4.2 SMBus Master Mode and SMBus Slave Mode

In SMBus master mode the DS110DF111 reads its initial configuration from an external EEPROM upon powerup. The serial EEPROM must support a minimum frequency of 520 KHz. Once the DS110DF111 has finished reading its initial configuration from the external EEPROM in SMBus master mode it reverts to SMBus slave mode and can be further configured by an external controller over the SMBus. Two device pins initiate reading the configuration from the external EEPROM and indicate when the configuration read is complete.

• DONE#
• READEN# These pins are meant to work together. When the DS110DF111 is powered up in SMBus master mode, it reads its configuration from the external EEPROM. This is triggered when the READEN# pin goes low. When the DS110DF111 is finished reading its configuration from the external EEPROM, it drives its DONE# pin low. In this mode, as the name suggests, the DS110DF111 acts as an SMBus master during the time it is reading its configuration from the external EEPROM. After the DS110DF111 has finished reading its configuration from the EEPROM, it releases control of the SMBus and becomes a SMBus slave. In applications where there is more than one DS110DF111 on the same SMBus, bus contention can result if more than one DS110DF111 tries to take command of the SMBus as the SMBus master at the same time. The READEN# and DONE# pins prevent this bus contention. In a system where the DS110DF111s are meant to operate in SMBus master mode, the READEN# pin of one retimer should be wired to the DONE# pin of the next. The system should be designed so that the READEN# pin of one (and only one) of the DS110DF111s in the system is driven low on power-up. This DS110DF111 will take command of the SMBus on power-up and will read its initial configuration from the external EEPROM. When it is finished reading its configuration, it will set its DONE# pin low. This pin should be connected to the READEN# pin of another DS110DF111. When this DS110DF111 senses its READEN# pin driven low, it will take command of the SMBus and read its initial configuration from the external EEPROM, after which it will set its DONE# pin low. By connecting the DONE# pin of each DS110DF111 to the READEN# pin of the next DS110DF111, each DS110DF111 can read its initial configuration from the EEPROM without causing bus contention. For SMBus slave mode, the READEN# pin must be tied LOW. Do not leave it Floating or tie it HIGH.

7.5 Programming

7.5.1 SMBus Interface

7.5.1.1 Address Lines

In either SMBus mode the DS110DF111 must be assigned a SMBus address. A unique address should be assigned to each device on the SMBus. The SMBus address is latched into the DS110DF111 on power-up. The address is read in from the state of the ADR[1:0] lines upon power-up. A floating address line input will be interpreted as a logic 0. The DS110DF111 can be configured with any of 4 SMBus addresses. The SMBus addressing scheme uses the least significant bit of the SMBus address as the Write/Read_N address bit. When an SMBus device is addressed for writing, this bit is set to 0; for reading, to 1. Table 6 shows the write address setting for the DS110DF111versus the values latched in on the address line at power-up.

7.5.1.2 Device Configuration in SMBus Slave Mode

The configurable settings of the DS110DF111 may be set independently for each channel at any time after power up using the SMBus. A register write is accomplished when the controller sends a START condition on the SMBus followed by the Write address of the DS110DF111 to be configured. See Table 6 for the mapping of the address lines to the SMBus Write addresses. After sending the Write address of the DS110DF111, the controller sends the register address byte followed by the register data byte. The DS110DF111 acknowledges each byte written to the controller according to the data link protocol of the SMBus Version 2.0 Specification. See this specification for additional information on the operation of the SMBus. There are two types of device registers in the DS110DF111. These are the control/shared registers and the channel registers. The control/shared registers control or allow observation of settings which affect the operation of all channels of the DS110DF111. They are also used to select which channel of the device is to be the target channel for reads from and writes to the channel registers.

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www.ti.com SNLS461A –MAY 2013–REVISED JUNE 2015 Programming (continued) The channel registers are used to set all the configuration settings of the DS110DF111. They provide independent control for each channel of the DS110DF111 for all the settable device characteristics. Any registers not described in the tables that follow should be treated as reserved. The user should not try to write new values to these registers. The user-accessible registers described in the tables that follow provide a complete capability for customizing the operation of the DS110DF111 on a channel-by-channel basis.

7.5.1.3 Bit Fields in the Register Set

Many of the registers in the DS110DF111 are divided into bit fields. This allows a single register to serve multiple purposes, which may be unrelated. Often configuring the DS110DF111 requires writing a bit field that makes up only part of a register value while leaving the remainder of the register value unchanged.

7.5.1.4 Writing to and Reading From the Control/Shared Registers

Any write operation targeting register 0xff writes to the control/shared register 0xff. This is the only register in the DS110DF111 with an address of 0xff. Bit 2 of register 0xff is used to select either the control/shared register set or a channel register set. If bit 2 of register 0xff is cleared (written with a 0), then all subsequent read and write operations over the SMBus are directed to the control/shared register set. This situation persists until bit 2 of register 0xff is set (written with a 1). There is a register with address 0x00 in the control/shared register set, and there is also a register with address 0x00 in each channel register set. If you read the value in register 0x00 when bit 2 of register 0xff is cleared to 0, then the value returned by the DS110DF111 is the value in register 0x00 of the control/shared register set. If you read the value in register 0x00 when bit 2 of register 0xff is set to 1, then the value returned by the DS110DF111 is the value in register 0x00 of the selected channel register set. The channel register set is selected by bits 1:0 of register 0xff. If bit 3 of register 0xff is set to 1 and bit 2 of register 0xff is also set to 1, then any write operation to any register address will write all the channel register sets in the DS110DF111 simultaneously. This situation will persist until either bit 3 of register 0xff or bit 2 of register 0xff is cleared. Note that when you write to register 0xff, independent of the current settings in register 0xff, the write operation ALWAYS targets the control/shared register 0xff. This channel select register, register 0xff, is unique in this regard. Table 7 shows the control/shared register set. Copyright © 2013–2015, Texas Instruments Incorporated Submit Documentation Feedback 17 Product Folder Links: DS110DF111

Table 6. SMBus Write Address Assignment(1) (1) A floating ADDR[1:0] terminal at power-up will be interpreted as a logic 0. Table 7. Control and Shared Register Space

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7.5.1.5 SMBus Strap Observation

to a SMBus Write address of 0x30.

7.5.1.6 Interrupt Channel Flag Bits

The operation of these bits is described in the section on interrupt handling later in this data sheet.

7.5.1.7 Control/Shared Register Reset

so it is cleared after it is written and the control/shared registers are reset to their factory default values.

7.5.1.8 Device Revision and Device ID

device with appropriate settings depending upon the device variant and revision. Table 8. Channel Select Register Values Mapped to Register Set Target

7.5.1.9 Channel Select Register

channel register sets only when bit 2 of register 0xff is set.

SNLS461A –MAY 2013–REVISED JUNE 2015 www.ti.com Bit 2 of register 0xff is the universal channel register enable. This bit must be set in order for any channel register reads and writes to occur. If this bit is set, then read operations from or write operations to register 0x00, for example, target channel register 0x00 for the selected channel rather than the control/shared register 0x00. In order to access the control/shared registers again, bit 2 of register 0xff should be cleared. Then the control/shared registers can again be accessed using the SMBus. Write operations to register 0xff always target the register with address 0xff in the control/shared register set. There is no other register, and specifically, no channel register, with address 0xff. The contents of the channel select register, register 0xff, cannot be read back over the SMBus. Read operations on this register will always yield an invalid result. All eight bits of this register should always be set to the desired values whenever this register is written. Always write 0x0 to the four most significant bits of register 0xff. The register set target selected by each valid value written to the channel select register is shown in Table 8.

7.5.1.10 Resetting Individual Channels of the Retimer

Register 0x00, bit 2, and register 0x0a, bits 3:2 Bit 2 of channel register 0x00 is used to reset all the registers for the corresponding channel to their factory default settings. This bit is self-clearing. Writing this bit will clear any register changes you have made in the DS110DF111 since it was powered-up. To reset just the CDR state machine without resetting the register values, which will re-initiate the lock and adaptation sequence for a particular channel, use channel register 0x0a. Set bit 3 of this register to enable the reset override, then set bit 2 to force the CDR state machine into reset. These bits can be set in the same operation. When bit 2 is subsequently cleared, the CDR state machine will resume normal operation. If a signal is present at the input to the selected channel, the DS110DF111 will attempt to lock to it and will adapt its CTLE and its DFE according to the currently configured adapt mode for the selected channel. The adapt mode is configured by channel register 0x31, bits 6:5.

7.5.1.11 Rate and Subrate Setting

Each channel of the DS110DF111 will, by default operate at 10.3125 Gbps and 1.25 Gbps. The device can be configured to operate at other VCO frequencies between 8.5 GHz and 11.3 GHz using the RATE (Reg: 0x2F bits [7:6]) and SUBRATE (Reg: 0x2F bits [5:4]) registers. The DS110DF111 is designed to lock to signals conforming to several different data transmission standards. These standards may define a single data rate or multiple data rates. The rate and subrate settings of the DS110DF111 may be used to select a data transmission standard to which the input signal is expected to conform. The DS110DF111 searches each data rate applicable to the selected standard to find a valid signal to which it then phase locks.

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Product Folder Links: DS110DF111

Table 9. Rate/Subrate VCO and Data Rate Information (1) The default datarates are Group 0 = 1.25 Gbps and Group 1 = 10.3125 Gbps. The DS110DF111 is designed to lock to signals conforming to several different data transmission standards. datarates within these enabled VCO divide ratios starting with divide by 8 and working up to divide by 1. 0x64) need to be reprogrammed. Table 10. Group 0 VCO Frequency Programming Registers Table 11. Group 1 VCO Frequency Programming Registers Table 12. Programming Values for Common Data Rates the Group 0/1 VCO programming registers.

Table 13. Group 0 VCO Programming Equations function for manual programming. Integer Value only, maximum value = 15. Convert to Hex for register. Table 14. Group 1 VCO Programming Equations function for manual programming. Integer Value only, maximum value = 15. Convert to Hex for register.

7.5.1.12 Overriding the CTLE Boost Setting

The current CTLE setting applied to the high-speed analog input can always be readback from register 0x52. the CTLE value from register 0x03 is being used. to a minimal CTLE value, writing register 0x3A = 00’h is recommended.

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Table 15. Default Output Status Description Table 16. Output Multiplexer Override Settings,

7.5.1.13 Overriding the Output Multiplexer

By default, the DS110DF111 output for each channel will be as shown in Table 15 and Table 16. override value. The values of this three-bit field and the corresponding meanings of each are shown in Table 16. Table 17. Divider Ratio Map

7.5.1.14 Overriding the VCO Divider Selection

current Rate/Subrate setting.

7.5.1.15 Using the Internal Eye Opening Monitor

queried through the SMBus by a system controller.

SNLS461A –MAY 2013–REVISED JUNE 2015 www.ti.com The eye opening monitor produces error hit counts for settable phase and voltage offsets of the comparator in the retimer. This is similar to the way many Bit Error Rate Test Sets measure eye opening. At each phase and amplitude offset setting, the eye opening monitor determines the nominal bit value (“0” or “1”) using its primary comparator. This is the bit value that is resynchronized to the recovered clock and presented at the output of the DS110DF111. The eye opening monitor also determines the bit value detected by the offset comparator. This information yields an eye contour. Here's how this works. If the offset comparator is offset in voltage by an amount larger than the vertical eye opening, for example, then the offset comparator will always decide that the current bit has a bit value of “0”. When the bit is really a “1”, as determined by the primary comparator, this is considered a bit error. The number of bit errors is counted for a settable interval at each setting of the offset phase and voltage of the offset comparator. These error counts can be read from registers 0x25 and 0x26 for sequential phase and voltage offsets. These error counts for all phase and voltage offsets form a 64 X 64 point array. A surface or contour plot of the error hit count versus phase and voltage offset produces an eye diagram, which can be plotted by external software. The eye opening monitor works in two modes. In the first, only the horizontal and vertical eye openings are measured. The eye opening monitor first sweeps its variable-phase clock through one unit interval with the comparison voltage set to the mid-point of the signal. This determines the mid-point of the horizontal eye opening. The eye opening monitor then sets its variable phase clock to the mid-point of the horizontal eye opening and sweeps its comparison voltage. These two measurements determine the horizontal and vertical eye openings. The horizontal eye opening value is read from register 0x27 and the vertical eye opening from register 0x28. Both values are single byte values. The measurement of horizontal and vertical eye opening is very fast. The speed of this measurement makes it useful for determining the adaptation figure of merit. In normal operation, the HEO and VEO are automatically measured periodically to determine whether the DS110DF111 is still in lock. Reading registers 0x27 and 0x28 will yield the most-recently measured HEO and VEO values. In normal operation, the eye monitor circuitry is powered down most of the time to save power. When the eye is to be measured under external control, it must first be enabled by writing a 0 to bit 5 of register 0x11. The default value of this bit is 1, which powers down the eye monitor except when it is powered-up periodically by the CDR state machine and used to test CDR lock. The eye monitor must be powered up to measure the eye under external SMBus control. Bits 7:6 of register 0x11 are also used during eye monitor operation to set the EOM voltage range. This is described below. A single write to register 0x11 can set both bit 5 and bits 7:6 in one operation. Register 0x3e, bit 7, enables horizontal and vertical eye opening measurements as part of the lock validation sequence. When this bit is set, the CDR state machine periodically uses the eye monitor circuitry to measure the horizontal and vertical eye opening. If the eye openings are too small, according to the pre-determined thresholds in register 0x6a, then the CDR state machine declares lock loss and begins the lock acquisition process again. For SMBus acquisition of the internal eye, this lock monitoring function must be disabled. Prior to overriding the EOM by writing a 1 to bit 0 of register 0x24, disable the lock monitoring function by writing a 0 to bit 7 of register 0x3e. Once the eye has been acquired, you can reinstate HEO and VEO lock monitoring by once again writing a 1 to bit 7 of register 0x3e. Under external SMBus control, the eye opening monitor can be programmed to sweep through all its 64 states of phase and voltage offset autonomously. This mode is initiated by setting register 0x24, bit 7, the fast_eom mode bit. Register 0x11, bits 7:6 and bit 5, Register 0x22, bit 7, Register 0x24, bit 7 and bit 0, Register 0x25, Register 0x26, Register 0x27, Register 0x28, Register 0x2a and Register 0x3e, bit 7 Register 0x22, bit 7, the eom_ov bit, should be cleared in this mode. When the fast_eom bit is set, the eye opening monitor operation is initiated by setting bit 0 of register 0x24, which is self-clearing. As soon as this bit is set, the eye opening monitor begins to acquire eye data. The results of the eye opening monitor error counter are stored in register 0x25 and 0x26. In this mode the eye opening monitor results can be obtained by repeated multi-byte reads from register 0x25. It is not necessary to read from register 0x26 for a multi-byte read. As soon as the eight most significant bits are read from register 0x25, the eight least significant bits for the current setting are loaded into register 0x25 and they can be read immediately. As soon as the read of the eight most significant

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Product Folder Links: DS110DF111

ranges are shown in Table 18. Table 18. EOM Voltage Range vs Reg 0x11 [7:6] be outside the vertical voltage range of the eye measurement. To summarize, the procedure for reading the eye monitor data from the DS110DF111is shown below.

1. Select the DS110DF111 channel to be used for the eye monitor measurement by writing the channel select

already selected, this step may be skipped.

1. Select the eye monitor voltage range by setting bits 7:6 of register 0x11 according to the values in Table 18.

to capture the entire vertical eye extent.

1. Power up the eye monitor circuitry by clearing bit 5 of register 0x11. Normally the eye monitor circuitry is

setting bits 7:6 of register 0x11 as desired can be combined into a single register write if desired.

1. Clear bit 7 of register 0x22. This is the eye monitor override bit. It is cleared by default, so you may not need
2. Set bit 7 of register 0x24. This is the fast eye monitor enable bit.
3. Set bit 1 of register 0x24. This initiates the automatic fast eye monitor measurement. This bit can be set at

the same time a bit 7 of register 0x24 if desired.

SNLS461A –MAY 2013–REVISED JUNE 2015 www.ti.com 7. Read the data array from the DS110DF111. This can be accomplished in two ways. – If you are using multi-byte reads, address the DS110DF111 to read from register 0x25. Continue to read from this register without addressing the device again until you have read all the data desired. The read operation can be interrupted by addressing the device again and then resumed by reading once again from register 0x25. – If you are not using multi-byte reads, then read the MSB for each phase and amplitude offset setting from register 0x25 and the LSB for each setting from register 0x26. In this mode, you address the device each time you want to read a new byte. 8. In either mode, the first four bytes do not contain valid data. These should be discarded. 9. Continue reading eye monitor data until you have read the entire 64X64 array. 10. Clear bit 7 of register 0x24. This disables fast eye monitor mode. 11. Set bit 5 of register 0x11. This will return control of the eye monitor circuitry to the CDR state machine. 12. Set bit 7 of register 0x3e. This re-enables the HEO and VEO lock monitoring.

7.5.1.16 Overriding the DFE Tap Weights and Polarities

Register 0x11, bits 3:0, Register 0x12, bit 7 and bits 4:0, Register 0x15, bit 7, Register 0x1e, bit 3, Register 0x20, Register 0x21, Register 0x23, bit 6, Register 0x24, bit 2, Register 0x2f, bit 0, and Registers 0x71–0x75 For the DS110DF111 the DFE tap weights and polarities are normally set automatically by the adaptation procedure. These values can be overridden by the user if desired. Prior to overriding the DFE tap weights and polarities, the dfe_ov bit, bit 6 of register 0x23, should be set. This bit is set by default. In order for the DFE tap weights and polarities to be applied to the input signal, bit 3 of register 0x1e, the dfe_PD bit, which powers down the DFE, should be cleared. This bit is cleared by default. It is not necessary to change the default settings of these registers, but verify that they are set as described. It is necessary to set bit 7 of register 0x15 to manually set the DFE tap weights. This bit is cleared by default. Bits 4:0 of register 0x12 set the five-bit weight for DFE tap 1. The first DFE tap has a five-bit setting, while the other taps are set using four bits. Often the first DFE tap has the largest effect in improving the bit error rate of the system, which is why this tap has a five-bit weight setting. The polarity of the tap weight for tap 1 is set using bit 7 of the same register, register 0x12. The polarity is set to 0 by default, which corresponds to a negative algebraic sign for the tap. The other four taps are set using four-bit fields in registers 0x20 and 0x21. The polarities of these taps are set by bits 3:0 in register 0x11. These tap polarities are all set to 0 by default. As is the case for the CTLE settings, if changing the DFE tap weights or polarities causes the DS110DF111 to lose lock, it may readapt its CTLE in order to reacquire lock. If this occurs, the CTLE settings may appear to change spontaneously when the DFE tap weights are changed. The mechanism is the same as that described above for the CTLE boost settings. When the DS110DF111 is set to adapt mode 2 or 3 using bits 6:5 of register 0x31, it will automatically adapt its DFE whenever its CDR state machine is reset. This occurs when the user manually resets the CDR state machine using bits 3:2 of register 0x0a, or when a signal is first presented at the input to the channel when the channel is in an unlocked state. Regardless of the adapt mode, DFE adaptation can be initiated under SMBus control. Because the DFE tap weight registers are used by the DFE state machine during adaptation, they may be reset prior to adaptation, which can cause the adaptation to fail. The DFE tap observation registers can be used to prevent this. Prior to initiating DFE adaptation under SMBus control, write the starting values of the DFE tap settings into the DFE tap weight registers, registers 0x11, 0x12, 0x20, and 0x21. The values can be read from the observation registers, registers 0x71 through 0x75. For each DFE tap, read the current value in the observation register. Both the polarities and the tap weights are contained in the observation registers. For each DFE tap, write the current tap polarity and tap weight into the DFE tap register. Once all these values have been written, DFE adaptation can be initiated and it will proceed normally. If the DS110DF111 fails to find a set of DFE tap weights producing a better adaptation figure of merit than the starting tap weights, the starting tap weights will be retained and used.

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Product Folder Links: DS110DF111

7.5.1.17 Enabling Slow Rise/Fall Time on the Output Driver

Setting bit 2 of register 0x18 will adjust the output driver circuitry to increase the rise and fall times of the signal.

7.5.1.18 Using the PRBS Generator

Table 19. Programming Sequence 1: (Requires Valid and Locked Input Data Pattern)

1. To select PRBS31 instead of PRBS9, change Register Data 0x30 = 0x02 with mask of 0x03 in Step 6.
2. To only select Channel A, change Register Data 0xFF = 0x04 in Step 1.
3. To only select Channel B, change Register Data 0xFF = 0x05 in Step 1.
4. It has been noted in product testing that some pattern analyzers use an alternate PRBS9 polarity.

Table 20. Programming Sequence 2: (Free-Running VCO @ ~10.3 Gbps, No Input Data Required)

1. To select PRBS31 instead of PRBS9, change Register Data 0x30 = 0x0A in Step 13.
2. To achieve a higher data-rate in Step 6 decrease VCO cap count value.
3. To achieve a lower data-rate in Step 6 increase the VCO cap count value.
4. To only select Channel A, change Register Data 0xFF = 0x04 in Step 1.
5. To only select Channel B, change Register Data 0xFF = 0x05 in Step 1.
6. With a free running VCO the actual output frequency will change with temperature and voltage. BERT is not

7.5.1.19 Inverting the Output Polarity

necessary, for the purposes of trace routing, for example, to invert the normal polarities of the data signals. in system design and board layout.

7.5.1.20 Overriding the Figure of Merit Adaption

usually provides optimum bit error rate performance for most transmission channels.

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Table 21. DS110DF111 Adaption Algorithm Settings, Register 0x31 Bits 6:5 taken directly from register 0x3A. Table 22. Figure of Merit Type Settings

• HEO is horizontal eye opening
• VEO is vertical eye opening
• FOM is the figure of merit
• the factors a, b, and c are set using registers 0x6b, 0x6c, and 0x6d respectively (1) In order to use the configurable figure of merit, the enable bits must be set. To use the configurable figure of merit for the CTLE adaptation, set bit 7 of register 0x6e. To use the configurable figure of merit for the DFE adaptation, set bit 6 of register 0x6e. The same scaling factors are used for both CTLE and DFE adaptation when the configurable figure of merit is enabled.

7.5.1.21 Setting the Rate and Subrate for Lock Acquisition

7:6 are RATE<1:0>, and bits 5:4 are SUBRATE<1:0>.

7.5.1.22 Setting the Adaption/Lock Mode

There are four adaptation modes available in the DS110DF111.

• Mode 0: The user is responsible for setting the CTLE and DFE (for the DS110DF111) values. This mode is used if the transmission channel response is fixed.
• Mode 1: Only the CTLE is adapted to equalize the transmission channel. The DFE is enabled , but the tap weights are all set to 0. This mode is primarily used for smoothly-varying high-loss transmission channels such as cables and simple PCB traces.
• Mode 2: In this mode, both the CTLE and the DFE are adapted to compensate for additional loss, reflections, and crosstalk in the input transmission channel. The maximum DFE tap weights can be constrained using register 0x34, bits 3:0, and register 0x35, bits 4:0.
• Mode 3: In this mode, both the CTLE and DFE are adapted as in mode 2. However, in mode 3, more Copyright © 2013–2015, Texas Instruments Incorporated Submit Documentation Feedback 29 Product Folder Links: DS110DF111

SNLS461A –MAY 2013–REVISED JUNE 2015 www.ti.com emphasis is placed on the DFE setting. This mode may give better results for high crosstalk transmission channels. Bits 6:5 of register 0x31 determine the adaptation mode to be used. The mapping of these register bits to the adaptation algorithm is shown in. By default the DS110DF111 requires that the equalized internal eye exhibit horizontal and vertical eye openings greater than a pre-set minimum in order to declare a successful lock. The minimum values are set in register 0x6a. The DS110DF111 continuously monitors the horizontal and vertical eye openings while it is in lock. If the eye opening falls below the threshold set in register 0x6a, the DS110DF111 will declare a loss of lock. The continuous monitoring of the horizontal and vertical eye openings may be disabled by clearing bit 7 of register 0x3e.

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Product Folder Links: DS110DF111

7.5.1.23 Initiating Adaption

selected using bits 6:5 in register 0x31, the DS110DF111 will also try to adapt its CTLE and DFE.

7.5.1.24 Overriding the CTLE Settings used for CTLE Adaption

settings to their defaults. So will power-cycling the DS110DF111. Table 23. CTLE Settings for Adaption, Register 0x40-0x4F

Table 24. VOD Settings

7.5.1.25 Setting the Output Differential Voltage

7.5.1.26 Setting the Output De-Emphasis Setting

emphasis values come from register 0x15, bits 2:0 and register 0x15, bit 6, which is the de-emphasis range bit. The available driver de-emphasis settings and the mapping to these bits are shown in Table 25. Table 25. De-Emphasis Settings

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www.ti.com SNLS461A –MAY 2013–REVISED JUNE 2015

7.5.1.27 CTLE Setting for Divide by 4 and Divide by 8 VCO Ranges

Register 0x3a, bits 7:0 In the DS110DF111 the default CTLE setting for lower speed signals is taken directly from register 0x3a and is not automatically adapted. For short, low loss input channels this value may need to be decreased from the default (A5'h) CTLE setting. Copyright © 2013–2015, Texas Instruments Incorporated Submit Documentation Feedback 33 Product Folder Links: DS110DF111

7.6 Register Maps

7.6.1 Reading to and Writing From the Channel Registers

to register 0xff. As noted, there is only one register with an address of 0xff, the channel select register. Table 26. Channel Register Definition Register 0x2D[3] is high. Read-back value5:4 00 Y R/W going to analog in Channel Register 0x52.

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Table 26. Channel Register Definition (continued) Use in conjunction with 0x1E[4] and 0x30[3] to0x0D 00 5 0 Y R/W start PRBS. Note: This bit must be set high last.

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preclude lower CTLE settings.

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determined by Reg_0x69[3:0]. 0x52 00 7:0 00’h N R CTLE Boost setting readback register. 7 0 Signal Detect observation bit. 6 0 EQ Limiting (CTLE Stage 3[2]) observation bit.

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HEO/VEO interval while monitoring lock.

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8 Applications and Implementation

validate and test their design implementation to confirm system functionality.

8.1 Application Information

The DS110DF111 is a 2 channel retimer that support many different data rates and application spaces.

8.2 Typical Application

short, low-loss channels this value should be adjusted as indicated in the Channel Register Table. Figure 9. Typical Application

8.2.1 Design Requirements

This section lists some critical areas for high speed printed circuit board design consideration and study.

• Utilize 100-Ω differential impedance traces.
• Back-drill connector vias and signal vias to minimize stub length.
• Use reference plane vias to ensure a low inductance path for the return current.
• Place AC-Coupling capacitors for the transmitter links near the receiver for that channel.
• The maximum body size for AC-coupling capacitors is 0402. Copyright © 2013–2015, Texas Instruments Incorporated Submit Documentation Feedback 43 Product Folder Links: DS110DF111

8.2.2 Detailed Design Procedure

• Select a reference clock frequency and routing scheme.
• Plan out channel connectivity. Be sure to note any desired polarity inversion routing in the board schematics.
• Ensure that each device has a unique SMBus address if the control bus is shared with other devices or components.
• Use the IBIS-AMI model for simple channel simulations before PCB layout is complete. Initialization Sequence: Channel Register Configurations repeated for all desired channels:
• CDR reset
• Adapt Mode Configuration
• Data rate selection
• Output driver VOD and De-Emphasis Optional Interrupt enable
• CDR reset release

8.2.3 Application Curves

8.2.3.1 SFF-8431 Testing

Testing for Receiver Jitter Tolerance based on SFF-8431 section D11.

• Datarate: 10.3125 Gbps
• PRBS15 Pattern
• Output Amplitude: 700 mV
• Periodic Jitter: 70 mUI at 20 MHz
• ISI Jitter: 10" 4-mil FR4 differential microstrip + Limiting Amplifier
• Random Jitter noise source: Agilent 346B The SFF-8431 specification combines deterministic, random, and periodic jitter components. The combination of these jitter components has been measured and calibrated to ensure adequate levels of individual jitter components and total jitter.

Figure 10. SFF-8431 Input Jitter Tolerance Profile Figure 11. SFF-8431 Output Jitter Eye Mask

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9 Power Supply Recommendations

Figure 12. DS110DF111 Power Supply and Regulator Connections

10 Layout

10.1 Layout Guidelines

The typical layout example Figure 13 highlights good high-speed layout techniques.

1. Maintain differential pair symmetry to minimize any signal conversion to common mode.
2. Isolate Tx - Rx differential pairs with a minimum of 5x inter-pair to intra-pair spacing ratio.
3. Decoupling should be placed as close as possible to the DS110DF111
4. Use differential vias which incorporate reference plane current returns and relief to minimize impedance
5. Use a back-drill technique to minimize via stubs.
6. Keep Loop Filter capacitors as close as possible to the DS110DF111.

10.2 Layout Example

Figure 13. DS110DF111 Typical Layout

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11 Device and Documentation Support

11.1 Documentation Support

11.1.1 Related Documentation

11.2 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.

11.3 Trademarks

E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.

11.4 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

11.5 Glossary

SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical packaging and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Copyright © 2013–2015, Texas Instruments Incorporated Submit Documentation Feedback 47 Product Folder Links: DS110DF111

www.ti.com 10-Nov-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) DS110DF111SQ/NOPB Active Production WQFN (RTW) | 24 1000 | LARGE T&R Yes SN Level-3-260C-168 HR -40 to 85 1D111B3 DS110DF111SQ/NOPB.A Active Production WQFN (RTW) | 24 1000 | LARGE T&R Yes SN Level-3-260C-168 HR -40 to 85 1D111B3 DS110DF111SQ/NOPB.B Active Production WQFN (RTW) | 24 1000 | LARGE T&R Yes SN Level-3-260C-168 HR -40 to 85 1D111B3 DS110DF111SQE/NOPB Active Production WQFN (RTW) | 24 250 | SMALL T&R Yes SN Level-3-260C-168 HR -40 to 85 1D111B3 DS110DF111SQE/NOPB.A Active Production WQFN (RTW) | 24 250 | SMALL T&R Yes SN Level-3-260C-168 HR -40 to 85 1D111B3 DS110DF111SQE/NOPB.B Active Production WQFN (RTW) | 24 250 | SMALL T&R Yes SN Level-3-260C-168 HR -40 to 85 1D111B3 (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

www.ti.com 10-Nov-2025 Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 1-Aug-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 1-Aug-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DS110DF111SQ/NOPB WQFN RTW 24 1000 208.0 191.0 35.0 DS110DF111SQE/NOPB WQFN RTW 24 250 208.0 191.0 35.0 Pack Materials-Page 2

www.ti.com PACKAGE OUTLINE C 24X 0.3 0.2 24X 0.5 0.3

0.8 MAX

(0.1) TYP 0.05 0.00 20X 0.5 2.5 2X 2.5 2.6 0.1 A 4.1 3.9 B 4.1 3.9 WQFN - 0.8 mm max heightRTW0024A PLASTIC QUAD FLATPACK - NO LEAD 4222815/A 03/2016 PIN 1 INDEX AREA 0.08 C SEATING PLANE 6 13 7 12 24 19 (OPTIONAL) PIN 1 ID 0.1 C A B 0.05 C EXPOSED THERMAL PAD NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. SCALE 3.000

www.ti.com EXAMPLE BOARD LAYOUT

0.07 MIN

0.07 MAX

24X (0.25) 24X (0.6) ( ) TYP VIA 0.2 20X (0.5) (3.8) (3.8) (1.05) ( 2.6) (R ) TYP 0.05 (1.05) WQFN - 0.8 mm max heightRTW0024A PLASTIC QUAD FLATPACK - NO LEAD 4222815/A 03/2016 SYMM 7 12 1924 SYMM LAND PATTERN EXAMPLE SCALE:15X NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED METAL SOLDER MASK OPENINGSOLDER MASK DETAILS NON SOLDER MASK DEFINED (PREFERRED)

www.ti.com EXAMPLE STENCIL DESIGN 24X (0.6) 24X (0.25) 20X (0.5) (3.8) (3.8) 4X ( 1.15) (0.675) TYP (0.675) TYP (R ) TYP0.05 WQFN - 0.8 mm max heightRTW0024A PLASTIC QUAD FLATPACK - NO LEAD 4222815/A 03/2016 NOTES: (continued) 5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SYMM METAL TYP SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 25: 78% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SCALE:20X SYMM 7 12 1924

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