DS100DF410

Texas Instruments

Low Power 10GbE Quad Channel Retimer

Manufacturer variants: 1

Selected specification: Texas Instruments

Documents: 4

Request Quote Download Datasheet Read online HTML view

Compare manufacturer specifications More from Texas Instruments Browse D parts

Manufacturer Specifications

Compare DS100DF410 variants.

Select a manufacturer to view its specifications, local PDF, and searchable HTML text.

1 manufacturers / 4 documents

Manufacturer	Series	Package	Documents	Available	Select specification
Texas Instruments	-	-	4	PDF HTML	Viewing

Online Datasheet

Read the Texas Instruments document online.

DS100DF410 Low Power 10GbE Quad Channel Retimer datasheet (Rev. B)

Document overview

Manufacturer or author: Texas Instruments, Incorporated [SNLS399,B]
PDF pages: 59

Technical content

SFP+(SFF8431) QSFP DS100DF410 10GbE Product Folder Sample & Buy T echnical Documents Tools & Software Support & Community DS100DF410 SNLS399B – JANUARY 2012–REVISED JANUARY 2015 DS100DF410LowPower10GbEQuadChannelRetimer

1 Features 3 Description

The DS100DF410 is four channel retimers with 1• Each Channel Independently Locks to 10.3125 integrated signal conditioning. Each channel canGbps independently lock to 10.3125 Gbps data rate to• Lock Operation (typically under 15 ms) support 10GbE. The device includes a fully adaptive

Low Latency (~300 ps) Continuous-Time Linear Equalizer (CTLE), Clock and Data Recovery (CDR) and transmit De-Emphasis• Adaptive Equalization up to 34 dB Boost at 5 GHz (DE) driver. The DS100DF410 also includes a self• Adjustable Transmit VOD: 600 to 1300 mVp-p calibrating 5-tap Decision Feedback Equalizer (DFE)
Adjustable Transmit De-emphasis to –12 dB to enable data transmission over long, lossy and crosstalk-impaired highspeed serial links to achieve• Typical Power Dissipation (EQ+DFE+CDR+DE): BER < 1×10-15.180 mW/channel
Programmable Output Polarity Inversion The programmable settings can be applied easily using the SMBus (I2C) interface, or they can be• Input Signal Detection, CDR Lock loaded via an external EEPROM. An on-chip eyeDetection/Indicator monitor and a PRBS generator allow real-time• On-chip Eye Monitor (EOM), PRBS Generator measurement of high-speed serial data for system
Single 2.5 V ±5% Power Supply bring-up or field tuning. Flow-through pinout and single power supply make the DS100DF410 easy to• SMBus/EEPROM Configuration Modes use.• Operating Temperature Range of –40°C to 85°C
WQFN 48-Pin, 7 mm x 7 mm Package Device Information(1)
Easy Pin Compatible Upgrade Between Repeater PART NUMBER PACKAGE BODY SIZE (NOM) and Retimers DS100DF410SQ WQFN (48) 7.00 mm × 7.00 mm – DS100RT410 (EQ+CDR+DE): 10.3125 Gbps (1) For all available packages, see the orderable addendum at the end of the data sheet.– DS100DF410 (EQ+DFE+CDR+DE): 10.3125 Gbps Typical Application Diagram– DS110RT410 (EQ+CDR+DE): 8.5–11.3 Gbps – DS110DF410 (EQ+DFE+CDR+DE): 8.5–11.3 Gbps – DS125RT410 (EQ+CDR+DE): 9.8–12.5 Gbps – DS125DF410 (EQ+DFE+CDR+DE): 9.8–12.5 Gbps – DS100BR410 (EQ+DE): Up to 10.3125 Gbps

2 Applications

Front Port SFF 8431 (SFP+) Optical and Direct Attach Copper
Backplane Reach Extension, Data Retimer
Ethernet: 10GbE, 1GbE For other data rates and data transmission protocols, other pin-compatible devices in the retimer family can be used. An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

SNLS399B – JANUARY 2012– REVISED JANUARY 2015 www.ti.com Table of Contents

4 Revision History

Changes from Revision A (February 2013) to Revision B Page

Changed ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation

2 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated

Product Folder Links: DS100DF410

32 TXN1

DAP = GND LP F_CP_3 LP F_REF_3 VDD LOCK_3ADDR_3 SDC SDA REFCLK_IN EN_SMB LOCK_2/ADDR_2 GND LP F_REF_2 LP F_CP_2 7 mm x 7 mm, 0.5 mm pitch LP F_REF_1 LP F_CP_1 GND LOCK_1/ADDR_1 ALL_DONE REFCLK_OUT INT READ_EN LOCK_0/ADDR_0 VDD LP F_REF_0 LP F_CP_0 DS100DF410 www.ti.com SNLS399B – JANUARY 2012– REVISED JANUARY 2015

5 Pin Configuration and Functions

48 Pins

TYPE(1) DESCRIPTION NAME NUMBER HIGH-SPEED DIFFERENTIAL I/O RXP0 1 I, CML Inverting and non-inverting CML-compatible differential inputs to the equalizer. Nominal RXN0 2 differential input impedance = 100Ω. Must be AC coupled. RXP1 4 I, CML Inverting and non-inverting CML-compatible differential inputs to the equalizer. Nominal RXN1 5 differential input impedance = 100Ω. Must be AC coupled. RXP2 8 I, CML Inverting and non-inverting CML-compatible differential inputs to the equalizer. Nominal RXN2 9 differential input impedance = 100Ω. Must be AC coupled. RXP3 11 I, CML Inverting and non-inverting CML-compatible differential inputs to the equalizer. Nominal RXN3 12 differential input impedance = 100Ω. Must be AC coupled. TXP0 36 O, CML Inverting and non-inverting CML-compatible differential outputs from the driver. TXN0 35 Nominal differential output impedance = 100Ω. Must be AC coupled. TXP1 33 O, CML Inverting and non-inverting CML-compatible differential outputs from the driver. TXN1 32 Nominal differential output impedance = 100Ω. Must be AC coupled. TXP2 29 O, CML Inverting and non-inverting CML-compatible differential outputs from the driver. TXN2 28 Nominal differential output impedance = 100Ω. Must be AC coupled. TXP3 26 O, CML Inverting and non-inverting CML-compatible differential outputs from the driver. TXN3 25 Nominal differential output impedance = 100Ω. Must be AC coupled. (1) Notes: I = Input, O = Output and 2.5V LVCMOS pins are 2.5 V levels only. Only SMBus pins SDA and SDC and INT pin are 3.3 V tolerant. These three pins are open-drain and require external pull-up resistors. Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: DS100DF410

SNLS399B – JANUARY 2012– REVISED JANUARY 2015 www.ti.com Pin Functions (continued) PIN TYPE(1) DESCRIPTION NAME NUMBER LOOP FILTER CONNECTION PINS LPF_CP_0 47 I/O, analog Loop filter connection LPF_REF_0 48 Place a 22 nF ± 10% Capacitor between LPF_CP_0 and LPF_REF_0 LPF_CP_1 38 I/O, analog Loop filter connection LPF_REF_1 37 Place a 22 nF ± 10% Capacitor between LPF_CP_1 and LPF_REF_1 LPF_CP_2 23 I/O, analog Loop filter connection LPF_REF_2 24 Place a 22 nF ± 10% Capacitor between LPF_CP_2 and LPF_REF_2 LPF_CP_3 14 I/O, analog Loop filter connection LPF_REF_3 13 Place a 22 nF ± 10% Capacitor between LPF_CP_3 and LPF_REF_3 REFERENCE CLOCK I/O REFCLK_IN 19 I, 2.5V analog Input is 2.5 V, 25 MHz ± 100 ppm reference clock from external oscillator No stringent phase noise requirement REFCLK_OUT 42 O, 2.5V analog Output is 2.5 V, buffered replica of reference clock input for connecting multiple DS100DF410s on a board LOCK INDICATOR PINS LOCK_0 45 O, 2.5V LVCMOS Output is 2.5 V, the pin is high when CDR lock is attained on the corresponding LOCK_1 40 channel LOCK_2 21 Note that these pins are shared with SMBus address strap input functions read at LOCK_3 16 startup. SMBus MASTER MODE PINS ALL_DONE 41 O, 2.5V LVCMOS Output is 2.5 V, the pin goes low to indicate that the SMBus master EEPROM read has been completed. READ_EN 44 I, 2.5V LVCMOS Input is 2.5 V, a transition from high to low starts the load from the external EEPROM. The READ_EN pin must be tied low when in SMBus slave mode INTERRUPT OUTPUT INT 43 O, 3.3V Used to signal horizontal or vertical eye opening out of tolerance, loss of signal detect, LVCMOS, Open or CDR unlock Drain External 2KΩ to 5KΩ pull-up resistor is required. Pin is 3.3 V LVCMOS tolerant. SERIAL MANAGEMENT BUS (SMBus) INTERFACE EN_SMB 20 I, 2.5V analog Input is 2.5 V, selects SMBus master mode or SMBus slave mode EN_SMB = High for slave mode EN_SMB = Float for master mode Tie READ_EN pin low for SMBus slave mode. See Table 1 SDA 18 I/O, 3.3V Data Input / Open Drain Output LVCMOS, Open External 2KΩ to 5KΩ pull-up resistor is required. Drain Pin is 3.3 V LVCMOS tolerant. SDC 17 I/O, 3.3V Clock Input / Open Drain Clock Output LVCMOS, Open External 2KΩ to 5KΩ pull-up resistor is required. Drain Pin is 3.3 V LVCMOS tolerant. ADDR_0 45 I, 2.5V LVCMOS Input is 2.5 V, the ADDR_[3:0] pins set the SMBus address for the retimer. ADDR_1 40 These pins are strap inputs. Their state is read on power-up to set the SMBus address ADDR_2 21 in SMBus control mode. ADDR_3 16 High = 1KΩ to VDD, Low = 1KΩ to GND Note that these pins are shared with the lock indicator functions. See Table 2 POWER VDD 3, 6, 7, Power VDD = 2.5 V ± 5%10, 15, 46 GND 22, 27, Power 30, 31, Ground reference. 34, 39 DAP PAD Power Ground reference. The exposed pad at the center of the package must be connected to ground plane of the board with at least 4 vias to lower the ground impedance and improve the thermal performance of the package.

4 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated

Product Folder Links: DS100DF410

www.ti.com SNLS399B – JANUARY 2012– REVISED JANUARY 2015

6 Specifications

6.1 Absolute Maximum Ratings (1)

over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT Supply Voltage (VDD) –0.5 2.75 V 2.5 I/O Voltage (LVCMOS and Analog) –0.5 2.75 V 3.3 LVCMOS I/O Voltage (SDA, SDC, INT) –0.5 4.0 V Signal Input Voltage (RXPn, RXNn) –0.5 2.75 V Signal Output Voltage (TXPn, TXNn) –0.5 2.75 V Junction Temperature 150 °C Storage Temperature, Tstg –65 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

Human Body Model (HBM), per ANSI/ESDA/JEDEC JS-001, all ±6000pins(1) V(ESD) ESD Rating Machine Model (MM), STD - JESD22-A115-A(2) ±250 V Charged Device Model (CDM), per JEDEC specification JESD22- ±1250C101, all pins(3) (1) JEDEC document JEP155 states that 6000-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V MM allows safe manufacturing with a standard ESD control process. (3) JEDEC document JEP157 states that 1250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT Supply Voltage (VDD to GND) 2.375 2.5 2.625 V Ambient Temperature -40 25 +85 °C

6.4 Thermal Information(1)

THERMAL METRIC(2) WQFN UNIT RθJA Junction-to-ambient thermal resistance 26.1 °C/W (1) No airflow, 4-layer JEDEC, 9 thermal vias (2) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: DS100DF410

SNLS399B – JANUARY 2012– REVISED JANUARY 2015 www.ti.com

6.5 Electrical Characteristics

Over recommended operating supply and temperature ranges with default register settings unless otherwise specified. (1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER Average Power Consumption(2) 720 mW PD Power supply consumption Max Transient Power Supply Current (3) 500 610 mA

50 Hz to 100 Hz 100 mVP-P

NTPS Supply noise tolerance (4) 100 Hz to 10 MHz 40 mVP-P 10 MHz to 5.0 GHz 10 mVP-P 2.5V LVCMOS DC SPECIFICATIONS VIH High level input voltage 1.75 VDD V High level (ADDR[3:0] pins) 2.28 VDD V Low level input voltage GND 0.7 V VIL Low level input voltage (ADDR[3:0] VGND 0.335pins) VOH High level output voltage IOH = -3mA 2.0 V VOL Low level output voltage IOL = 3mA 0.4 V VIN = VDD 10 μA IIN Input leakage current VIN = GND –10 μA IIH Input high current (EN_SMB pin) VIN = VDD 55 μA IIL Input low current (EN_SMB pin) VIN = GND –110 μA

3.3 V LVCMOS DC SPECIFICATIONS (SDA, SDC, INT)

VIH High level input voltage VDD = 2.5 V 1.75 3.6 V VIL Low level input voltage VDD = 2.5 V GND 0.7 V VOL Low level output voltage IPULLUP = 3mA 0.4 V IIH Input high current VIN = 3.6 V, VDD = 2.5 V 20 40 μA IIL Input low current VIN = GND, VDD = 2.5 V –10 10 μA Slave Mode 10 400 kHz fSDC SMBus clock rate Master Mode(5) 400 kHz DATA BIT RATES 10.3125 Gbps Ethernet 10.1 10.6 Gbps RB Bit rate range 1.25 Gbps Ethernet 1.2 1.3 Gbps SIGNAL DETECT Default differential input signal level to assert signal detect,SDH Signal detect ON threshold level 70 mVp-p

10.3125 Gbps, PRBS-31

Default differential input signal level to de- assert signal detect,SDL Signal detect OFF threshold level 10 mVp-p (1) Typical values represent most likely parametric norms at VDD = 2.5V, TA = 25°C, and at the Recommended Operation Conditions at the time of product characterization. (2) VDD= 2.5V, TA = 25°C. All four channels active and locked. DFE powered-up and enabled. (3) Maximum power supply current during lock acquisition. All four channels active, all four channels unlocked, all registers at default settings. (4) Allowed supply noise (mVP-P sine wave) under typical conditions. (5) EEPROM device used for Master mode programming must support fSDC greater than 400kHz.

6 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated

Product Folder Links: DS100DF410

www.ti.com SNLS399B – JANUARY 2012– REVISED JANUARY 2015 Electrical Characteristics (continued) Over recommended operating supply and temperature ranges with default register settings unless otherwise specified. (1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT RECEIVER INPUTS (RXPn, RXNn) VTX2, min See (5) 600 mVP-P VTX2, max 1000 mVP-PMinimum source transmit launch signal level (IN, diff)VTX1, max See (6) 1200 mVP-P VTX0, max See (7) 1600 mVP-P Maximum differential input returnLRI 100 MHz – 6 GHz(8) -15 dBloss - |SDD11| ZD Differential input impedance 100 MHz – 6 GHz 100 Ω ZS Single-ended input impedance 100 MHz – 6 GHz 50 Ω DRIVER OUTPUTS (TXPn, TXNn) Differential measurement with OUT+ and OUT- terminated by 50Ω to GND, AC-Coupled, SMBus register VOD controlVOD0 Differential output voltage 400 675 mVP-P(Register 0x2d bits 2:0) set to 0, minimum VOD De-emphasis control set to minimum (0 dB) Differential measurement with OUT+ and OUT- terminated by 50Ω to GND, AC-Coupled SMBus register VOD controlVOD7 Differential output voltage 1000 mVP-P(Register 0x2d bits 2:0) set to 7, maximum VOD De-emphasis control set to minimum (0 dB) Differential measurement with OUT+ and OUT- terminated by 50Ω to GND, AC-Coupled Set by SMBus register control VOD_DE De-emphasis level (9) to maximum de-emphasis setting -12 dB Relative to the nominal 0 dB de-emphasis level set at the minimum de-emphasis setting Transition time control = Full Slew Rate 39 psTransition time (rise and falltR, tF times)(9) (10) Transition time control = Limited Slew Rate 50 ps Maximum differential output returnLRO 100 MHz – 6 GHz (8) –15 dBloss - |SDD22| tDP Propagation delay Retimed data(11) 300 ps Measured at VOD = 1000 mVP-P, de-TDE De-emphasis pulse duration(12) 75 psemphasis setting = -12 dB (6) Differential signal amplitude at the transmitter output providing < 1x10-12 bit error rate. Measured at 10.3125 Gbps with a PRBS-31 data pattern. Input transmission channel is 40-inch long FR-4 stripline, 4-mil trace width. (7) Differential signal amplitude at the transmitter output providing < 1x10-12 bit error rate. Measured at 10.3125 Gbps with a PRBS-31 data pattern. No input transmission channel. (8) Measured with 10 MHz clock pattern output. (9) Measured with clock-like {11111 00000} pattern. (10) Slew rate is controlled by SMBus register settings. (11) Typical at 10.3125 Gbps bit rate. (12) De-emphasis pulse width varies with VOD and de-emphasis settings. Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: DS100DF410

(13) Typical with no output de-emphasis, minimum output transmission channel.

6.6 Typical Characteristics

Figure 1. Typical VOD vs VDD Figure 2. Typical VOD vs Temperature

8 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated

7 Detailed Description

7.1 Overview

Sequence (PRBS) pattern generator that can be used for debug purposes. master to configure itself from an EEPROM. The sections below describe the functionality of the various circuits and features within the DS100DF410.

7.2 Functional Block Diagram

Figure 3. DS100DF410 Data Path Block Diagram: One of Four Channels

7.3 Feature Description

7.3.1 Device Data Path Operation

diagram of Figure 3. The functional sections are as follows.

Signal Detect
CTLE
DFE
CDR
Differential Output Driver

7.3.2 Signal Detect

manually force channels to be disabled.

7.3.3 CTLE

different shape for the EQ transfer function (boost curve).

7.3.4 DFE

selected adapt mode. The DFE can be manually configured to specified tap polarities and tap weights.

7.3.5 Clock and Data Recovery

7.3.6 Output Driver

The output driver is capable of driving variable output voltages with variable amounts of analog de-emphasis. is responsible for configuring these parameters. They can be set for each channel independently. An idealized transmit waveform with analog de-emphasis applied is shown in Figure 4. Figure 4. Idealized De-Emphasis Waveform

10 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated

www.ti.com SNLS399B – JANUARY 2012– REVISED JANUARY 2015 Feature Description (continued)

7.3.7 CTLE Boost Setting

The CTLE is a four-stage amplifier with an adjustable, quasi-high-pass transfer function on each stage. The overall frequency response of the CTLE is set by adjusting the boost of each stage independently. Each stage of the CTLE can be set to one of four boost settings. The amount of high-frequency boost supplied by each stage generally increases with increasing boost settings. The CTLE can also be configured to adapt automatically to provide the optimum boost level for its input signal. Automatic adaptation of the CTLE only is the default mode of operation for the DS100DF410.

7.3.8 DFE Tap Weight and Polarity Setting

The DS100DF410 includes a five-tap decision-feedback equalizer (DFE) which operates on the signal at the output of the CTLE. When the tap weights and polarities are properly set, the DFE approximates a matched filter for the input transmission channel frequency response as modified by the CTLE frequency response. The CTLE and the DFE work together to compensate for the input transmission channel response. The DFE discriminates against input noise and random jitter as well as against crosstalk at the input to the DS100DF410. When the DFE tap weights and polarities are properly set the DS100DF410 CDR operates at an acceptable BER with more severe channel impairments than can be compensated with the CTLE alone. It is possible to automatically or manually set the tap weights and polarities in the DS100DF410. Determining the correct tap weights manually is difficult and time-consuming. The DS100DF410 automatically adapts the DFE tap weights and polarities in normal operation. This automatic adaptation provides superior BER performance for noisy channels and channels subject to crosstalk aggressors. The DFE is powered down by default. In order for the DFE tap weights and polarities to be applied to the input signal, bit 3 of register 0x1e, the dfe_PD bit, should be set to 0 to power up the DFE. Also the adapt mode setting in register 0x31, bits[6:5] should be set to 2b'10 or 2b'11 so the device can automatically adapt the CTLE and DFE.

7.3.9 Driver Output Voltage

The differential output voltage of the DS100DF410 can be configured from a nominal setting of 600 mV peak-to- peak differential to a nominal setting of 1.3 V peak-to-peak differential, depending upon the application. The driver output voltage as set is the typical peak-to-peak differential output voltage with no de-emphasis enabled.

7.3.10 Driver Output De-Emphasis

The output de-emphasis level of the DS100DF410 can be configured from a nominal setting of 0 dB to a nominal setting of -12 dB depending upon the application. Larger absolute values of the de-emphasis setting provide more pre-distortion of the output driver waveform, accentuating the high-frequency components of the output driver waveform relative to the low-frequency components. Greater values of de-emphasis can compensate for greater dispersion in the transmission media at the output of the DS100DF410. The output de-emphasis level as set is the typical value to which the output signal will settle following the de-emphasis pulse interval in dB relative to the output VOD.

7.3.11 Driver Output Rise/Fall Time

In some applications, a longer rise/fall time for the output signal is desired. This can reduce electromagnetic interference (EMI) generated by fast switching waveforms. This is necessary in some applications for regulatory compliance. In others, it can reduce the crosstalk in the system. The DS100DF410 can be configured to operate with a nominal rise/fall time corresponding to the maximum slew rate of the output drivers into the load capacitance. Alternatively, the DS100DF410 can be configured to operate with a slightly greater rise/fall time if desired. For the typical specifications on rise/fall time, see Electrical Characteristics. Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Links: DS100DF410

SNLS399B – JANUARY 2012– REVISED JANUARY 2015 www.ti.com Feature Description (continued)

7.3.12 Ref_mode 0 Mode (Reference Clock Not Required)

The DS100DF410 can be used without using a reference clock and the input REFCLK_IN pin can be open. When register 0x36, bits [5:4] are set to 2’b00, the device operates without using a reference clock at 10.3125 Gbps mode. For 1GbE applications, it is required to bypass the CDR by setting the override bit 5 of register 0x09 to 1, and set the data mux bits [7:5] to 3'b000 of register 0x1E.

7.3.13 Ref_mode 3 Mode (Reference Clock Required)

When using ref_mode 3, the device uses an external 25 MHz clock. This mode of operation is set in register 0x36 bits [5:4] = 2'b11 and is the default setting. In ref_mode 3, the external reference clock is used to aid initial phase lock, and to determine when its VCO is properly phase-locked. An external oscillator should be used to generate a 2.5V, 25 MHz reference signal which is connected to the DS100DF410 on the reference clock input pin (pin 19). The DS100DF410 does not include a crystal oscillator circuit, so a stand-alone external oscillator is required. The reference clock speeds up the initial phase lock acquisition. The DS100DF410 is set to phase lock to a known data rate, or a constrained set of known data rates, and the digital circuitry in the DS100DF410 pre- configures the VCO frequency. This enables the DS100DF410 phase-lock to the incoming signal very quickly. The reference clock is used to calibrate the VCO coarse tuning. However, the reference clock is not synchronous to the data stream, and the quality of the reference clock does not affect the jitter on the output retimed data. The retimed data clock for each channel is synchronous to the VCO internal to that channel of the DS100DF410. The phase noise of the reference clock is not critical. Any commercially-available 25 MHz oscillator can provide an acceptable reference clock. The reference clock can be daisy-chained from one retimer to another so that only one reference oscillator is required in a system.

7.3.14 False Lock Detector Setting

The register 0x2F, bit 1 is set to 1 by default, which disables the false lock detector. This bit must be set to 0 to enable the false lock detector function.

7.3.15 Reference Clock In

REFCLK_IN pin 19 is for reference clock input. A 25 MHz oscillator should be connected to pin 19. See Electrical Characteristics for the requirements on the 25 MHz clock. The frequency of the reference clock should always be 25 MHz no matter what data rate or mode of operation is used.

7.3.16 Reference Clock Out

REFCLK_OUT pin 42 is the reference clock output pin. The DS100DF410 drives a buffered replica of the 25 MHz reference clock input on this output pin. If there are multiple DS100DF410 in the system, the REFCLK_OUT pin can be directly connected to the REFCLK_IN pin of another DS100DF410 in a daisy chain connection. The other option is to connect the external 25 MHz oscillator to a clock fanout buffer to distribute the 25 MHz clock to each DS100DF410, which ensures there is a reference clock for the DS100DF410.

7.3.17 Daisy Chain of REFCLK_OUT to REFCLK_IN

When daisy chaining the device REFCLK_OUT to the REFCLK_IN of another device, the trace connection should be less than 1.5 inches (about 5pF trace capacitance) and it is possible to cascade up to 9 devices. While in other systems with longer interconnecting trace or more capacitive loading, the daisy chain of multiple devices should be reduced. In a system which requires longer daisy chain, it is recommended to place an inverted gate after the 6th devices. The pre-distorted duty cycle from the inverter allows longer daisy chain. A better approach is to break the long daisy chain into shorter chains, each driven by a buffer version of the clock distribution and with each chain kept to a maximum of 6 cascade devices. As an example, if there are 12 devices in the system, the daisy chain connections can be divided into two groups of 6 devices and PCB trace length for the reference clock output to input connection. Should be 1.5 inch or less.

12 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated

Product Folder Links: DS100DF410

7.3.18 INT

DS100DF410s can be wired together and connected to an external controller. interrupt. This can then be read out by the controller over the SMBus.

7.3.19 LOCK_3, LOCK_2, LOCK_1, and LOCK_0

their lock indication function. it can be connected to other circuitry which can interpret the lock status of the channel.

7.4 Device Functional Modes

The DS100DF410 can be configured using two different methods.

SMBus Master Configuration Mode
SMBus Slave Configuration Mode The configuration mode is selected by the state of the EN_SMB pin (pin 20) when the DS100DF410 is powered- up. This pin should be either left floating or tied to the device VDD through an optional 1kΩ resistor. The effect of each of these settings is shown in Table 1.

Table 1. SMBus Enable Settings

7.4.1 SMBus Master Mode and SMBus Slave Mode

up. A description of the operation of this mode appears in a separate application note. Some of the pins of the DS100DF410 perform the same functions in SMBus master and SMBus slave mode. mode it reverts to SMBus slave mode and can be further configured by an external controller over the SMBus.

ALL_DONE
READ_EN Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback 13 Product Folder Links: DS100DF410

SNLS399B – JANUARY 2012– REVISED JANUARY 2015 www.ti.com These pins are meant to work together. When the DS100DF410 is powered up in SMBus master mode, it reads its configuration from the external EEPROM. This is triggered when the READ_EN pin goes low. When the DS100DF410 is finished reading its configuration from the external EEPROM, it drives its ALL_DONE pin low. In this mode, as the name suggests, the DS100DF410 acts as an SMBus master during the time it is reading its configuration from the external EEPROM. After the DS100DF410 has finished reading its configuration from the EEPROM, it releases control of the SMBus and becomes a SMBus slave. In applications where there is more than one DS100DF410 on the same SMBus, bus contention can result if more than one DS100DF410 tries to take command of the SMBus as the SMBus master at the same time. The READ_EN and ALL_DONE pins prevent this bus contention. In a system where the DS100DF410s are meant to operate in SMBus master mode, the READ_EN pin of one retimer should be wired to the ALL_DONE pin of the next. The system should be designed so that the READ_EN pin of one (and only one) of the DS100DF410s in the system is driven low on power-up. This DS100DF410 will take command of the SMBus on power-up and will read its initial configuration from the external EEPROM. When it is finished reading its configuration, it will set its ALL_DONE pin low. This pin should be connected to the READ_EN pin of another DS100DF410. When this DS100DF410 senses its READ_EN pin driven low, it will take command of the SMBus and read its initial configuration from the external EEPROM, after which it will set its ALL_DONE pin low. By connecting the ALL_DONE pin of each DS100DF410 to the READ_EN pin of the next DS100DF410, each DS100DF410 can read its initial configuration from the EEPROM without causing bus contention. For SMBus slave mode, the READ_EN pin must be tied low. Do not leave it floating or tie it high. A connection diagram showing several DS100DF410s along with an external EEPROM and an external SMBus master is shown in Figure 5. The SMBus master must be prevented from trying to take control of the SMBus until the DS100DF410s have finished reading their initial configurations from the EEPROM.

14 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated

Product Folder Links: DS100DF410

Figure 5. Connection Diagram for Multiple DS100DF410s in SMBus Master Mode The DS100DF410 reads its SMBus address upon power-up from the SMBus address lines.

7.4.2 Address Lines <ADDR_[3:0]>

address must be assigned to each device on the SMBus. lines are input pins on power-up.

DS100DF410 versus the values latched in on the address lines at power-up. read by the slave, or a read operation, in which the slave will output data to the SMBus to be read by the master. corresponding to each set of address line values. access the DS100DF410s over the SMBus. Table 2. DS100DF410 SMBus Write Address Assignment pins of the SMBus interface, Serial Data (SDA) and Serial Data Clock (SDC).

7.4.3 SDA and SDC

provide reliable SMBus operation. an description of its operation, see http://smbus.org/specs/.

16 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated

www.ti.com SNLS399B – JANUARY 2012– REVISED JANUARY 2015

7.5 Programming

7.5.1 SMBus Strap Observation

Register 0x00, bits 7:4 and register 0x06, bits 3:0 In order to communicate with the DS100DF410 over the SMBus, it is necessary for the SMBus controller to know the address of the DS100DF410 . The address strap observation bits in control/shared register 0x00 are primarily useful as a test of SMBus operation. There is no way to get the DS100DF410 to tell you what its SMBus address is unless you already know what it is. In order to use the address strap observation bits of control/shared register 0x00, it is necessary first to set the diagnostic test control bits of control/shared register 0x06. This four-bit field should be written with a value of 0xa. When this value is written to bits 3:0 of control/shared register 0x06, then the value of the SMBus address straps can be read in register 0x00, bits 7:4. The value read will be the same as the value present on the ADDR3:ADDR0 lines when the DS100DF410 was powered up. For example, if a value of 0x1 is read from control/shared register 0x00, bits 7:4, then at power-up the ADDR0 line was set to 1 and the other address lines, ADDR3:ADDR1, were all set to 0. The DS100DF410 is set to an SMBus Write address of 0x32.

7.5.2 Device Revision and Device ID

Control/shared register 0x01 contains the device revision and device ID. The device revision shown in Table 12 is the current revision for the DS100DF410. The device ID will be different for the different devices in the retimer family. The value shown in "For the DS100DF410, Register 0x01, bits 4:0 = 0x10" is the correct value for the DS100DF410. This register is useful because it can be interrogated by software to determine the device variant and revision installed in a particular system. The software might then configure the device with appropriate settings depending upon the device variant and revision.

7.5.3 Control/Shared Register Reset

Register 0x04, bit 6 Register 0x04, bit 6, clears all the control/shared registers back to their factory defaults. This bit is self-clearing, so it is cleared after it is written and the control/shared registers are reset to their factory default values.

7.5.4 Interrupt Channel Flag Bits

Register 0x05, bits 3:0 The operation of these bits is described in the section on interrupt handling later in this data sheet.

7.5.5 SMBus Master Mode Control Bits

Register 0x04, bits 5 and 4 and register 0x05, bits 7 and 4 Register 0x04, bit 5, can be used to reset the SMBus master mode. This bit should not be set if the DS100DF410 is in SMBus slave mode. This is an undefined condition. When this bit is set, if the EN_SMB pin is floating (meaning that the DS100DF410 is in SMBus master mode), then the DS100DF410 will read the contents of the external EEPROM when the READ_EN pin is pulled low. This bit is not self-clearing, so it should be cleared after it is set. When the DS100DF410 EN_SMB pin is floating (meaning that the DS100DF410 is in SMBus master mode), it will read from its external EEPROM when its READ_EN pin goes low. After the EEPROM read operation is complete, register 0x05, bit 4 will be set. Alternatively, the DS100DF410 will read from its external EEPROM when triggered by register 0x04, bit 4, as described below. When register 0x04, bit 4, is set, the DS100DF410 reads its configuration from an external EEPROM over the SMBus immediately. When this bit is set, the DS100DF410 does not wait until the READ_EN pin is pulled low to read from the EEPROM. This EEPROM read occurs whether the DS100DF410 is in SMBus master mode or not. If the read from the EEPROM is not successful, for example because there is no EEPROM present, then the DS100DF410 may hang up and a power-up reset may be necessary to return it to proper operation. You should only set this bit if you know that the EEPROM is present and properly configured. Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback 17 Product Folder Links: DS100DF410

SNLS399B – JANUARY 2012– REVISED JANUARY 2015 www.ti.com Programming (continued) If the EEPROM read has already completed, then setting register 0x04, bit 4, will not have any effect. To cause the DS100DF410 to read from the EEPROM again it is necessary to set bit 5 of register 0x04, resetting the SMBus master mode. If the DS100DF410 is not in SMBus master mode, do not set this bit. After setting this bit, it should be cleared before further SMBus operations. After SMBus master mode has been reset, the EEPROM read may be initiated either by pulling the READ_EN pin low or by then setting register 0x04, bit 4. Register 0x05, bit 7, disables SMBus master mode. This prevents the DS100DF410 from trying to take command of the SMBus to read from the external EEPROM. Obviously this bit will have no effect if the EEPROM read has already taken place. It also has no effect if an EEPROM read is currently in progress. The only situations in which disabling EEPROM master mode read is valid are (1) when the DS100DF410 is in SMBus master mode, but the READ_EN pin has not yet gone low, and (2) when register 0x04, bit 5, has been used to reset SMBus master mode but the EEPROM read operation has not yet occurred. Do not set this bit and bit 4 of register 0x04 simultaneously. This is an undefined condition and can cause the DS100DF410 to hang up.

7.5.6 Resetting Individual Channels of the Retimer

Register 0x00, bit 2, and register 0x0a, bits 3:2 Bit 2 of channel register 0x00 are used to reset all the registers for the corresponding channel to their factory default settings. This bit is self-clearing. Writing this bit will clear any register changes you have made in the DS100DF410 since it was powered-up. To reset just the CDR state machine without resetting the register values, which will re-initiate the lock and adaptation sequence for a particular channel, use channel register 0x0a. Set bit 3 of this register to enable the reset override, then set bit 2 to force the CDR state machine into reset. These bits can be set in the same operation. When bit 2 is subsequently cleared, the CDR state machine will resume normal operation. If a signal is present at the input to the selected channel, the DS100DF410 will attempt to lock to it and will adapt its CTLE and its DFE according to the currently configured adapt mode for the selected channel. The adapt mode is configured by channel register 0x31, bits 6:5.

7.5.7 Interrupt Status

Control/Shared Register 0x05, bits 3:0, Register 0x01, bits 4 and 0, Register 0x30, bit 4, Register 0x32, and Register 0x36, bit 6 Each channel of the DS100DF410 will generate an interrupt under several different conditions. The DS100DF410 will always generate an interrupt when it loses CDR lock or when a signal is no longer detected at its input. If the HEO/VEO interrupt is enabled by setting bit 6 of register 0x36, then the retimer will generate an interrupt when the horizontal or vertical eye opening falls below the preset values even if the retimer remains locked. When one of these interrupt conditions occurs, the retimer alerts the system controller via hardware and provides additional details via register reads over the SMBus. First, the open-drain interrupt line INT is pulled low. This indicates that one or more of the channels of the retimer has generated an interrupt. The interrupt lines from multiple retimers can be wire-ANDed together so that if any retimer generates an interrupt the system controller can be notified using a single interrupt input. if the interrupt has occurred because the horizontal or vertical eye opening has dropped below the pre-set threshold, which is set in channel register 0x32, then bit 4 of register 0x30 will go high. This indicates that the source of the interrupt was the HEO or VEO. If the interrupt has occurred because the CDR has fallen out of lock, or because the signal is no longer detected at the input, then bit 4 and/or bit 0 of register 0x01 will go high, indicating the cause of the interrupt. In either case, the control/shared register set will indicate which channel caused the interrupt. This is read from bits 3:0 of control/shared register 0x05. When an interrupt is detected by the controller on the interrupt input, the controller should take the following steps to determine the cause of the interrupt and clear it. 1. The controller detects the interrupt by detecting that the INT line has been pulled low by one of the retimers to which it is connected.

18 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated

Product Folder Links: DS100DF410

www.ti.com SNLS399B – JANUARY 2012– REVISED JANUARY 2015 Programming (continued) 2. The controller reads control/shared register 0x05 from all the DS100DF410s connected to the INT line. For at least one of these devices, at least one of the bits 3:0 will be set in this register. 3. For each device with a bit set in bits 3:0 of control/shared register 0x05, the controller determines which channel or channels produced an interrupt. Refer to Table 12 for a mapping of the bits in this bit field to the channel producing the interrupt. 4. When the controller detects that one of the retimers has a 1 in one of the four LSBs of this register, the controller selects the channel register set for that channel of that retimer by writing to the channel select register, 0xff, as previously described. 5. For each channel that generated an interrupt, the controller reads channel register 0x01. If bit 4 of this register is set, then the interrupt was caused by a loss of CDR lock. If bit 0 is set, then the interrupt was caused by a loss of signal. it is possible that both bits 0 and 4 could be set. Reading this register will clear these bits. 6. Optionally, for each channel that generated an interrupt, the controller reads channel register 0x30. If bit 4 of this register is set, then the interrupt was caused by HEO and/or VEO falling out of the configured range. This interrupt will only occur if bit 6 of channel register 0x36 is set, enabling the HEO/VEO interrupt. Reading register 0x30 will clear this interrupt bit. 7. Once the controller has determined what condition caused the interrupt, the controller can then take the appropriate action. For example, the controller might reset the CDR to cause the retimer to re-adapt to the incoming signal. If there is no longer an incoming signal (indicated by a loss of signal interrupt, bit 0 of channel register 0x01), then the controller might alert an operator or change the channel configuration. This is system dependent. 8. Reading the interrupt status registers will clear the interrupt. if this does not cause the interrupt input to go high, then another device on the same input has generated an interrupt. The controller can address the next device using the procedure above. 9. Once all the interrupt registers for all channels for all DS100DF410s that generated interrupts have been read, clearing all the interrupt indications, the INT line should go high again. This indicates that all the existing interrupt conditions have been serviced. The channel registers referred to above, registers 0x01, 0x30, 0x32, and 0x36, are described in the channel registers table, Table 14.

7.5.8 Overriding the CTLE Boost Setting

Register 0x03, Register 0x13, bit 2, and Register 0x3a To override the CTLE boost settings, register 0x03 is used. This register contains the currently-applied CTLE boost settings. The boost values can be overridden by using the two-bit fields in this register as shown in the table. The final stage of the CTLE has an additional control bit which sets it to a limiting mode. For some channels, this additional setting improves the bit error rate performance. This bit is bit 2 of register 0x13. If the DS100DF410 loses lock because of a change in the CTLE settings, the DS100DF410 will initiate its lock and adaptation sequence again. Thus, if you write new CTLE boost values to register 0x03 and 0x13 which cause the DS100DF410 to drop out of lock, the DS100DF410 may, in the process of reacquiring the CDR lock, reset the CTLE settings to different values than those you set in register 0x03 and 0x13. If this behavior is not understood, it can appear that the DS100DF410 did not accept the values you wrote to the CTLE boost registers. What's really happening, however, is that the lock and adaptation sequence is overriding the CTLE values you wrote to the CTLE boost registers. This will not happen unless the DS100DF410 drops out of lock. If the adapt mode is set to 0 (bits 6:5 of channel register 0x31), then the CTLE boost values will not be overridden, but the DS100DF410 may still lose lock. If this happens, the DS100DF410 will attempt to reacquire lock. if the reference mode is set correctly, and if the rate/subrate code is set to permit it, the DS100DF410 will begin searching for CDR lock at the highest allowable VCO divider ratio – that is, at the lowest configured bit rate. At this lowest bit rate, the CTLE boost settings used will come not from the values in register 0x03, and Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback 19 Product Folder Links: DS100DF410

CTLE boost settings can be difficult to understand. To manually override the CTLE boost under all conditions, perform the following steps.

Set the DS100DF410 channel adapt mode to 0 by writing 0x0 to bits 6:5 of channel register 0x31.
Set the desired CTLE boost setting in register 0x3a. If the DS100DF410 loses lock and attempts to lock to a

lower data rate, it will use this CTLE boost setting.

Set the desired CTLE boost setting in register 0x03. This may cause the DS100DF410 to lose lock.
If desired, set the CTLE stage 3 limiting bit, bit 2 of register 0x13.

DS100DF410 will try to reacquire lock, but it will not change the CTLE boost settings in order to do so.

7.5.9 Overriding the VCO CAP DAC Values

override bit (bit 7 of register 0x09) is cleared.

7.5.10 Overriding the Output Multiplexer

By default, the DS100DF410 output for each channel will be as shown in Table 3. Table 3. Default Output Status Description This default behavior can be modified by register writes. corresponding meanings of each are shown in Table 4.

20 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated

Table 4. Output Multiplexer Override Settings register 0x1e, bits 7:5, even when the retimer is locked. output may saturate to a static 1 or 0. settings and it will vary from part to part and over temperature. with the input signal, but the bit stream output will be determined by the PRBS generator selection. system. The clock frequency will be approximately 10 MHz, but this will vary from part to part. PRBS generator, if it is enabled, will be synchronous to the input signal. signal, replacing the data content of the input signal with the internally-generated PRBS sequence.

7.5.11 Overriding the VCO Divider Selection

Table 5. Divider Ratio Mapping to Register 0x18, Bits 6:4 should not be overridden except in this case.

7.5.12 Using the PRBS Generator

operation are described in the paragraphs that follow. sequence of register writes will enable the internal PRBS generator.

22 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated

www.ti.com SNLS399B – JANUARY 2012– REVISED JANUARY 2015 First write a 1 to bit 3 of register 0x09, then 0x0 to bits 1:0 of register 0x1b. This disables the charge pump for the phase-locked loop. Next write a 1 to bit 2 of register 0x09. This enables the VCO divider override. Then set the VCO divider ratio by writing to register 0x18 as shown in Table 5. For an output frequency of approximately 10.3125 GHz, set the divider ratio to 1 by writing 0x0 to bits 6:4 of register 0x18. Do not clear bit 3 when you write a 1 to bit 2 of register 0x09. Now write a 1 to bit 7 of register 0x09. This enables the VCO CAP DAC override. Write the desired VCO cap count to register 0x08, bits 4:0. The mapping of VCO frequencies to cap count will vary somewhat from part to part. The VCO cap count should be set to 0x0c to yield an output VCO frequency of approximately 10.3125 GHz. Do not clear bits 3 and 2 when you write a 1 to bit 7 of register 0x09. Now write a 1 to bit 6 of register 0x09. This enables the VCO LPF DAC which can generate a VCO control voltage internally to the DS100DF410. Once the LPF DAC is enabled, write the desired value of the LPF DAC output in register 0x1f, bits 4:0. For an output VCO frequency of approximately 10.3125 GHz, set the LPF DAC setting to 0x12. Do not clear the remaining bits of register 0x09 when you write a 1 to bit 6. Now, as above, enable the PRBS generator and set it to the desired bit sequence, then select the output to be the PRBS generator by setting the output multiplexer. Notice that when this entire sequence has been completed, bits 7:2 of register 0x09 will all be set. The default value of register 0x09 is 0x00, so you can clear all the overrides when you are ready to return to normal operation by writing 0x00 to register 0x09. The VCO frequency in free-run will vary somewhat from part to part. In order to determine exact values of the CAP DAC and LPF DAC settings, it will be necessary to directly measure the VCO frequency using some sort of frequency-measurement device such as a frequency counter or a spectrum analyzer. When the VCO is set to free-run mode as above, you can select the VCO I-clock (in-phase clock) to be the output as shown in Table 4. You can measure the frequency of the VCO I-clock while adjusting the CAP DAC and LPF DAC values until the VCO I-clock frequency is acceptable for your application. Then you can once again select the PRBS generator as the output using the output multiplexer selection field.

7.5.13 Using the Internal Eye Opening Monitor

Register 0x11, bits 7:6 and bit 5, Register 0x22, bit 7, Register 0x24, bit 7 and bit 0, Register 0x25, Register 0x26, Register 0x27, Register 0x28, and Register 0x2a The DS100DF410 includes an internal eye opening monitor. The eye opening monitor is used by the retimer to compute a figure of merit for automatic adaptation of the CTLE and the DFE. It can also be controlled and queried through the SMBus by a system controller. The eye opening monitor produces error hit counts for settable phase and voltage offsets of the comparator in the retimer. This is similar to the way many Bit Error Rate Test Sets measure eye opening. At each phase and amplitude offset setting, the eye opening monitor determines the nominal bit value (“0” or “1”) using its primary comparator. This is the bit value that is resynchronized to the recovered clock and presented at the output of the DS100DF410. The eye opening monitor also determines the bit value detected by the offset comparator. This information yields an eye contour. Here's how this works. If the offset comparator is offset in voltage by an amount larger than the vertical eye opening, for example, then the offset comparator will always decide that the current bit has a bit value of “0”. When the bit is really a “1”, as determined by the primary comparator, this is considered a bit error. The number of bit errors is counted for a settable interval at each setting of the offset phase and voltage of the offset comparator. These error counts can be read from registers 0x25 and 0x26 for sequential phase and voltage offsets. These error counts for each phase and voltage offsets form a 64 X 64 point array. A surface or contour plot of the error hit count versus phase and voltage offset produces an eye diagram, which can be plotted by external software. The eye opening monitor works in two modes. In the first, only the horizontal and vertical eye openings are measured. The eye opening monitor first sweeps its variable-phase clock through one unit interval with the comparison voltage set to the mid point of the signal. This determines the midpoint of the horizontal eye opening. The eye opening monitor then sets its variable phase clock to the midpoint of the horizontal eye opening and sweeps its comparison voltage. These two measurements determine the horizontal and vertical eye openings. The horizontal eye opening value is read from register 0x27 and the vertical eye opening from register 0x28. Both values are single byte values. Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback 23 Product Folder Links: DS100DF410

SNLS399B – JANUARY 2012– REVISED JANUARY 2015 www.ti.com The measurement of horizontal and vertical eye opening is very fast. The speed of this measurement makes it useful for determining the adaptation figure of merit. In normal operation, the HEO and VEO are automatically measured periodically to determine whether the DS100DF410 is still in lock. Reading registers 0x27 and 0x28 will yield the most-recently measured HEO and VEO values. In normal operation, the eye monitor circuitry is powered down most of the time to save power. When the eye is to be measured under external control, it must first be enabled by writing a 0 to bit 5 of register 0x11. The default value of this bit is 1, which powers down the eye monitor except when it is powered-up periodically by the CDR state machine and used to test CDR lock. The eye monitor must be powered up to measure the eye under external SMBus control. Bits 7:6 of register 0x11 are also used during eye monitor operation to set the EOM voltage range. This is described below. A single write to register 0x11 can set both bit 5 and bits 7:6 in one operation. Register 0x3e, bit 7, enables horizontal and vertical eye opening measurements as part of the lock validation sequence. When this bit is set, the CDR state machine periodically uses the eye monitor circuitry to measure the horizontal and vertical eye opening. If the eye openings are too small, according to the pre-determined thresholds in register 0x6a, then the CDR state machine declares lock loss and begins the lock acquisition process again. For SMBus acquisition of the internal eye, this lock monitoring function must be disabled. Prior to overriding the EOM by writing a 1 to bit 0 of register 0x24, disable the lock monitoring function by writing a 0 to bit 7 of register 0x3e. Once the eye has been acquired, you can reinstate HEO and VEO lock monitoring by once again writing a 1 to bit 7 of register 0x3e. Under external SMBus control, the eye opening monitor can be programmed to sweep through all its 64 states of phase and voltage offset autonomously. This mode is initiated by setting register 0x24, bit 7, the fast_eom mode bit. Register 0x22, bit 7, the eom_ov bit, should be cleared in this mode. When the fast_eom bit is set, the eye opening monitor operation is initiated by setting bit 0 of register 0x24, which is self-clearing. As soon as this bit is set, the eye opening monitor begins to acquire eye data. The results of the eye opening monitor error counter are stored in register 0x25 and 0x26. In this mode the eye opening monitor results can be obtained by repeated multi-byte reads from register 0x25. It is not necessary to read from register 0x26 for a multi-byte read. As soon as the eight most significant bits are read from register 0x25, the eight least significant bits for the current setting are loaded into register 0x25 and they can be read immediately. As soon as the read of the eight most significant bits has been initiated, the DS100DF410 sets its phase and voltage offsets to the next setting and starts its error counter again. The result of this is that the data from the eye opening monitor is available as quickly as it can be read over the SMBus with no further register writes required. The external controller just reads the data from the DS100DF410 over the SMBus as fast as it can. When all the data has been read, the DS100DF410 clears the eom_start bit. If multi-byte reads are not used, meaning that the device is addressed each time a byte is read from it, then it is necessary to read register 0x25 to get the MSB (the eight most significant bits) and register 0x26 to get the LSB (the eight least significant bits) of the current eye monitor measurement. Again, as soon as the read of the MSB has been initiated, the DS100DF410 sets its phase and voltage offsets to the next setting and starts its error counter again. In this mode both registers 0x25 and 0x26 must be read in order to get the eye monitor data. The eye monitor data for the next set of phase and voltage offsets will not be loaded into registers 0x25 and 0x26 until both registers have been read for the current set of phase and voltage offsets. In all eye opening monitor modes, the amount of time during which the eye opening monitor accumulates eye opening data can be set by the value of register 0x2a. In general, the greater this value the longer the accumulation time. When this value is set to its maximum possible value of 0xff, the maximum number of samples acquired at each phase and amplitude offset is approximately 218. Even with this setting, the eye opening monitor values can be read from the SMBus with no delay. The eye opening monitor operation is sufficiently fast that the SMBus read operation cannot outrun it. The eye opening is measured at the input to the data comparator. At this point in the data path, a significant amount of gain has been applied to the signal by the CTLE. In many cases, the vertical eye opening as measured by the EOM will be on the order of 400 to 500 mV peak-to-peak. The secondary comparator, which is used to measure the eye opening, has an adjustable voltage range from ±100 mV to ±400 mV. The EOM voltage range is normally set by the CDR state machine during lock and adaptation, but the range can be overridden by setting bit 6 to 0 of register 0x2C, so the voltage range can scale with the values in register 0x11, bits [7:6]. The values of this code and the corresponding EOM voltage ranges are shown in Table 6.

24 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated

Product Folder Links: DS100DF410

Table 6. EOM Voltage Range vs. Bits 7:6 of Register 0x11 be outside the vertical voltage range of the eye measurement.

7.5.14 Overriding the DFE Tap Weights and Polarities

procedure. These values can be overridden by the user if desired. the DFE is powered down by default. the system, which is why this tap has a five-bit weight setting. 0 by default, which corresponds to a negative algebraic sign for the tap. bits 3:0 in register 0x11. These tap polarities are all set to 0 by default. above for the CTLE boost settings. channel is in an unlocked state. which can cause the adaptation to fail. The DFE tap observation registers can be used to prevent this.

7.5.15 Enabling Slow Rise/Fall Time on the Output Driver

Setting bit 2 of register 0x18 will adjust the output driver circuitry to increase the rise and fall times of the signal.

7.5.16 Inverting the Output Polarity

necessary, for the purposes of trace routing, for example, to invert the normal polarities of the data signals. in system design and board layout.

7.5.17 Overriding the Figure of Merit for Adaptation

optimum bit error rate performance for most transmission channels. figure of merit type is shown in Table 7. Table 7. Figure of Merit Type Setting of merit is structured as shown in Equation 1.

26 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated

factors a, b, and c are set using registers 0x6b, 0x6c, and 0x6d respectively. used for both CTLE and DFE adaptation when the configurable figure of merit is enabled.

7.5.18 Setting the Rate and Subrate for Lock Acquisition

be calibrated are set using channel register 0x2f. Bits 7:6 are RATE<1:0>, and bits 5:4 are SUBRATE<1:0>.

7.5.19 Setting the Adaptation/Lock Mode

There are four adaptation modes available in the DS100DF410.

Mode 0: The user is responsible for setting the CTLE and DFE values. this mode is used if the transmission channel response is fixed.
Mode 1: Only the CTLE is adapted to equalize the transmission channel. The DFE is enabled but the tap weights are all set to 0. This mode is primarily used for smoothly-varying high-loss transmission channels such as cables and simple PCB traces.
Mode 2: In this mode, both the CTLE and the DFE are adapted to compensate for additional loss, reflections, and crosstalk in the input transmission channel. – The maximum DFE tap weights can be constrained using register 0x34, bits 3:0, and register 0x35, bits 4:0 as shown in Table 14.
Mode 3: In this mode, both the CTLE and DFE are adapted as in mode 2. However, in mode 3, more emphasis is placed on the DFE setting. This mode may give better results for high crosstalk transmission channels. Bits 6:5 of register 0x31 determine the adaptation mode to be used. The mapping of these register bits to the adaptation algorithm is shown in Table 14.

Table 8. DS100DF410 Adaptation Algorithm Settings opening falls below the threshold set in register 0x6a, the DS100DF410 will declare a loss of lock.

7.5.20 Initiating Adaptation

selected using bits 6:5 in register 0x31, the DS100DF410 will also try to adapt its CTLE and its DFE.

SNLS399B – JANUARY 2012– REVISED JANUARY 2015 www.ti.com Adaptation can also be initiated by the user. CTLE adaptation can be initiated by setting and then clearing register 0x2f, bit 0. DFE adaptation can be initiated by setting and then clearing bit 2 of register 0x24.

7.5.21 Setting the Reference Enable Mode

Register 0x36, bits 5:4 Register 0x36, bits 5:4, are the ref_mode<1:0> bits. These bits should be set to a value of 2'b11. Note that this is not the default. The reference mode must be set prior to using the DS100DF410. A 25 MHz reference clock signal must be provided on the reference in pin (pin 19). The use of the reference clock in the DS100DF410 is explained below. First, the reference clock allows the DS100DF410 to calibrate its VCO frequency at power-up and upon reset. This enables the DS100DF410 to determine the optimum coarse VCO tuning setting a-priori, which makes phase lock much faster. The DS100DF410 is not required to tune through the available coarse VCO tuning settings as it tries to acquire lock to an input signal. It can select the correct setting immediately. Second, if the DS100DF410 loses lock for some reason and the VCO drifts from its phase-locked frequency, the DS1010DF410 can detect this very quickly using the reference clock. Detecting an out-of-lock condition quickly allows the DS100DF410 to raise an interrupt indicating that it has lost lock quickly, which the system controller can then service to correct the problem quickly. Finally, some data signals with large jitter spurs in their frequency spectra can cause the DS1100DF410 to false lock. This occurs when the data pattern exhibits strong discrete frequency components in its frequency spectrum, or when the data pattern has a lot of periodic jitter imposed on it. If you look at such a signal in the frequency domain using a spectrum analyzer, it will clearly show “spurs” close in to the fundamental data rate frequency. These spurs can cause the DS100DF410 to false lock. Using the 25 MHz reference clock, the DS100DF410 can detect when it is locked to a jitter spur. When this happens, the DS100DF410 will re-initiate the adaptation and lock sequence until it locks to the correct data rate. This provides immunity to false lock conditions. The reference clock mode is set by a two-bit field, register 0x36, bits 5:4. This field should always be set to a value of 3 or 2'b11.

7.5.22 Overriding the CTLE Settings Used for CTLE Adaptation

Register 0x2c, bits 3:0, Register 0x2f, bit 3, Register 0x39, bits 4:0, and Registers 0x50-0x5f The CTLE adaptation algorithm operates by setting the CTLE boost stage controls to a set of pre-determined boost settings, each of which provides progressively more high-frequency boost. At each stage in the adaptation process, the DS100DF410 attempts to phase lock to the equalized signal. If the phase lock succeeds, the DS100DF410 measures the horizontal and vertical eye openings using the internal eye monitor circuit. The DS100DF410 computes a figure of merit for the eye opening and compares it to the previous best value of the figure of merit. While the figure of merit continues to improve, the DS100DF410 continues to try additional values of the CTLE boost setting until the figure of merit ceases to improve and begins to degrade. When the figure of merit starts to degrade, the DS100DF410 still continues to try additional CTLE settings for a pre-determined trial count called the “look-beyond” count, and if no improvement in the figure of merit results, it resets the CTLE boost values to those that produced the best figure of merit. The resulting CTLE boost values are then stored in register 0x03. The “look-beyond” count is configured by the value in register 0x2c, bits 3:0. The value is 0x2 by default. The set of boost values used as candidate values during CTLE adaptation are stored as bit fields in registers 0x40-0x5f. The default values for these settings are shown in Table 9. These values may be overridden by setting the corresponding register values over the SMBus. If these values are overridden, then the next time the CTLE adaptation is performed the set of CTLE boost values stored in these registers will be used for the adaptation. Resetting the channel registers by setting bit 2 of channel register 0x00 will reset the CTLE boost settings to their defaults. So will power-cycling the DS100DF410.

28 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated

Product Folder Links: DS100DF410

Table 9. CTLE Settings for Adaptation

7.5.23 Setting the Output Differential Voltage

settings and the corresponding values of this bit field are shown in Table 10.

Table 10. VOD Settings

7.5.24 Setting the Output De-emphasis Setting

bit 6, which is the de-emphasis range bit. The available driver de-emphasis settings and the mapping to these bits are shown in Table 11. Table 11. Driver De-Emphasis Settings

7.6 Register Maps

7.6.1 Register Information

channel for reads from and writes to the channel registers. independent control for each channel of the DS100DF410 for all the settable device characteristics. complete capability for customizing the operation of the DS100DF410 on a channel-by-channel basis.

7.6.2 Bit Fields in the Register Set

purposes, which may be unrelated. register, it is not necessary to read in the current value of the register first. however, the procedure described above should be used.

7.6.3 Writing to and Reading from the Control/Shared Registers

DS100DF410 with an address of 0xff. directed to the control/shared register set. This situation persists until bit 2 of register 0xff is set (written with a 1). register 0xff. This channel select register, register 0xff, is unique in this regard. Table 12. Control/Shared Registers

Table 12. Control/Shared Registers (continued) 6 0 RWSC N RST_SMB_REGS 1: Resets share registers. Self-clearing. 3 0 RW N WRITE_ALL_CH Selects All Channels for Register Write. See Table 3. Register Read from One Channel. 1:0 0 RW N SEL_CH_SMB Selects Target Channel for Register Reads and Writes.

7.6.4 Channel Select Register

channel register sets only when bit 2 of register 0xff is set. channel register, with address 0xff. selected by each valid value written to the channel select register is shown in Table 13.

Table 13. Channel Select Register Values Mapped to Register Set Target

7.6.5 Reading to and Writing from the Channel Registers

write to register 0xff. As noted, there is only one register with an address of 0xff, the channel select register. Table 14. Channel Registers 4 0 R N CDR_LOCK_LOSS_INT 1: indicates loss of CDR lock after having acquired it. 0 0 R N SIG_DET_LOSS_INT Loss of signal indicator. Bit is set once signal is acquired and then lost.

Table 14. Channel Registers (continued)

configured to be a linear stage. channel. Should not be set if bit 6 is set. channel. Should not be set if bit 7 is set. 5 0 RW Y EQ_REFA_SEL1 Controls the signal detect assert levels. 3 0 RW Y EQ_REFD_SEL1 Controls the signal detect de-assert levels. 6 1 RW Y PDIQ_SEL_DIV2 These bits will force the divider setting if 0x09[2] is set. All other values are reserved.

All other values are reserved.

automatically incremented through a 64 x 64 matrix. 2 0 RW N DFE_ADAPT 1: Manually start DFE adaption, self-clearing. enabled with channel register 0x23[7].

3 0 RW Y DFE_ADAPT_COUNTER3 DFE look-beyond count.

index to the [31:0] array of EQ settings. interrupt. Each threshold bit represents 8 counts of HEO6 0 RW Y HEO_INT_THRESH2 or VEO. and VEO required for CTLE adaption, before starting6 0 RW Y HEO_THRESH2 DFE adaption. This can be a max of 15.

after 100ms after signal detect goes low. these registers, with a max value of +3, for a total of 4. which DFE taps 2-5 are able to adapt with each2 1 RW Y DFE_MAX_TAP2_5[2] subsequent adaptation. Same used for both polarities. 5 0 RW N GET_PPM_ERROR Get ppm error from ppm_count - clears when done.

3E 7 1 RW Y HEO_VEO_LOCKMON_EN Enable HEO/VEO lock monitoring.

check for group 0. Must also program channel register6 0 RW Y GRP0_OV_DLTA2 0x67[7]. check for group 1. Must also program channel register2 0 RW Y GRP1_OV_DLTA2 0x67[6]. 4 0 RW N CTLE_ADPT_FRC_EN This feature is reserved for future use.

0 0 RW N GET_HV_ST_FRC_EN This feature is reserved for future use.

8 Application and Implementation

validate and test their design implementation to confirm system functionality.

8.1 Application Information

CTLE boost setting
DFE tap weight and polarity setting
Driver output voltage
Driver output de-emphasis
Driver output rise/fall time Configuration of the DS100DF410 is accomplished by writing the appropriate values into various device registers over the SMBus. This can either be done while the device is operating or upon initial power-up. When the DS100DF410 is operating it behaves like an SMBus slave device, and its register contents can be read or written over the SMBus. Optionally, when the DS100DF410 first powers up, it can behave like an SMBus master and read its register contents autonomously from an external EEPROM.

8.2 Typical Application

Figure 6. Typical Application Diagram

8.2.1 Design Requirements

This section lists some critical areas for high speed printed circuit board design consideration and study.

Utilize 100-Ω differential impedance traces.
Back-drill connector vias and signal vias to minimize stub length.
Use reference plane vias to ensure a low inductance path for the return current.
Place AC-Coupling capacitors for the transmitter links near the receiver for that channel.
The maximum body size for AC-coupling capacitors is 0402.

8.2.2 Detailed Design Procedure

Maximum power draw for PCB regulator selection. For this calculation use the maximum transient power supply current specified in the datasheet. The lock time for each channel is typically very short, so this power calculation should not be used for the thermal simulations of the PCB.
Maximum operational power for thermal calculations. For this calculation use the Average Power Consumption number in the datasheet.
Select a reference clock frequency and routing scheme.
Plan out channel connectivity. Be sure to note any desired polarity inversion routing in the board schematics.
Ensure that each device has a unique SMBus address if the control bus is shared with other devices or components.
Use the IBIS-AMI model for simple channel simulations before PCB layout is complete.

8.2.3 Application Curves

of 600mVp-p and de-emphasis setting of -2dB. to evaluate the driver, which consists of 0xFF00. Figure 7. Typical Application Transmit Eye Diagram, Figure 8. Transmit Equalization Example, 10.3125Gbps

10.3125 Gbps

2.5 V1 µF

9 Power Supply Recommendations

Figure 9. Example Power Connection

10 Layout

10.1 Layout Guidelines

10.2 Layout Example

To minimize the effects of crosstalk, a 5:1 ratio or greater should be maintained between inter-pair spacing. reduce the detrimental high frequency effects of stubs on the signal path.

Figure 10. Different Transmission Line Topologies

www.ti.com SNLS399B – JANUARY 2012– REVISED JANUARY 2015

11 Device and Documentation Support

11.1 Trademarks

All trademarks are the property of their respective owners.

11.2 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

11.3 Glossary

SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback 51 Product Folder Links: DS100DF410

www.ti.com 10-Nov-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) DS100DF410SQ/NOPB Active Production WQFN (RHS) | 48 1000 | LARGE T&R Yes SN Level-3-260C-168 HR -40 to 85 100DF410 DS100DF410SQ/NOPB.A Active Production WQFN (RHS) | 48 1000 | LARGE T&R Yes SN Level-3-260C-168 HR -40 to 85 100DF410 DS100DF410SQ/NOPB.B Active Production WQFN (RHS) | 48 1000 | LARGE T&R Yes SN Level-3-260C-168 HR -40 to 85 100DF410 DS100DF410SQE/NOPB Active Production WQFN (RHS) | 48 250 | SMALL T&R Yes SN Level-3-260C-168 HR -40 to 85 100DF410 DS100DF410SQE/NOPB.A Active Production WQFN (RHS) | 48 250 | SMALL T&R Yes SN Level-3-260C-168 HR -40 to 85 100DF410 DS100DF410SQE/NOPB.B Active Production WQFN (RHS) | 48 250 | SMALL T&R Yes SN Level-3-260C-168 HR -40 to 85 100DF410 (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

www.ti.com 10-Nov-2025 Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 1-Aug-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 1-Aug-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DS100DF410SQ/NOPB WQFN RHS 48 1000 356.0 356.0 36.0 DS100DF410SQE/NOPB WQFN RHS 48 250 208.0 191.0 35.0 Pack Materials-Page 2

www.ti.com PACKAGE OUTLINE C SEE TERMINAL DETAIL 48X 0.30 0.18 5.1 0.1 48X 0.5 0.3 0.8 0.7 (A) TYP 0.05 0.00 44X 0.5 5.5 2X 5.5 A 7.15 6.85 B 7.15 6.85 0.30 0.18 0.5 0.3 (0.2) WQFN - 0.8 mm max heightRHS0048A PLASTIC QUAD FLATPACK - NO LEAD 4214990/B 04/2018 DIM A OPT 1 OPT 2 (0.1) (0.2) PIN 1 INDEX AREA 0.08 C SEATING PLANE 12 25 13 24 48 37 (OPTIONAL) PIN 1 ID 0.1 C A B 0.05 EXPOSED THERMAL PAD

49 SYMM

NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. SCALE 1.800 DETAIL OPTIONAL TERMINAL TYPICAL

www.ti.com EXAMPLE BOARD LAYOUT

0.07 MIN

0.07 MAX

48X (0.25) 48X (0.6) ( 0.2) TYP VIA 44X (0.5) (6.8) (6.8) (1.25) TYP ( 5.1) (R0.05) TYP (1.25) TYP (1.05) TYP (1.05) TYP WQFN - 0.8 mm max heightRHS0048A PLASTIC QUAD FLATPACK - NO LEAD 4214990/B 04/2018 SYMM 13 24 3748 SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:12X NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL METAL EDGE SOLDER MASK OPENING SOLDER MASK DETAILS NON SOLDER MASK DEFINED (PREFERRED) EXPOSED METAL

www.ti.com EXAMPLE STENCIL DESIGN 48X (0.6) 48X (0.25) 44X (0.5) (6.8) (6.8) 16X ( 1.05) (0.625) TYP (R0.05) TYP (1.25) TYP (1.25) TYP (0.625) TYP WQFN - 0.8 mm max heightRHS0048A PLASTIC QUAD FLATPACK - NO LEAD 4214990/B 04/2018 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SYMM METAL TYP SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 49 68% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SCALE:15X SYMM 13 24 3748

IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you fully indemnify TI and its representatives against any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale, TI’s General Quality Guidelines, or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. Unless TI explicitly designates a product as custom or customer-specified, TI products are standard, catalog, general purpose devices. TI objects to and rejects any additional or different terms you may propose. IMPORTANT NOTICE Copyright © 2025, Texas Instruments Incorporated Last updated 10/2025

Selected Specification

Texas Instruments DS100DF410 overview.

Summary

Low Power 10GbE Quad Channel Retimer

Description

Low Power 10GbE Quad Channel Retimer

Source title DS100DF410 Datasheet(PDF) - Texas Instruments

Related Parts

More parts from the same family.

Browse manufacturer