DRV5013-Q1 Automotive, Digital-Latch Hall Effect Sensor datasheet (Rev. I)
Document overview
- Manufacturer or author: Texas Instruments, Incorporated [SLIS162,I]
- PDF pages: 33
Technical content
DRV5013-Q1 Automotive, Digital-Latch Hall Effect Sensor
1 Features
- AEC-Q100 qualified for automotive applications: – DRV5013xxQ grade 1: TA = –40°C to 125°C (see Device Nomenclature) – DRV5013xxE grade 0: TA = –40°C to 150°C (see Device Nomenclature)
- Digital bipolar-latch Hall sensor
- Superior temperature stability – BOP ±10% over temperature
- Multiple sensitivity options (BOP / BRP) – ±1.3 mT (FA, see Device Nomenclature) – ±2.7 mT (AD, see Device Nomenclature) – ±6 mT (AG, see Device Nomenclature) – ±12 mT (BC, see Device Nomenclature)
- Supports a wide voltage range – 2.7 V to 38 V – No external regulator required
- Open-drain output (30-mA sink)
- Fast 35-µs power-on time
- Small package and footprint – Surface mount 3-pin SOT-23 (DBZ)
- 2.92 mm × 2.37 mm – Through-hole 3-pin TO-92 (LPG)
- 4.00 mm × 3.15 mm
- Protection features: – Reverse supply protection (up to –22 V) – Supports up to 40-V load dump – Output short-circuit protection – Output current limitation – OUT short to battery protection
2 Applications
- Power tools
- Flow meters
- Valve and solenoid status
- Brushless dc motors
- Proximity sensing
- Tachometers
3 Description
The DRV5013-Q1 device is a chopper-stabilized Hall effect sensor that offers a magnetic sensing solution with superior sensitivity stability over temperature and integrated protection features. The magnetic field is indicated through a digital bipolar latch output. The IC has an open-drain output stage with 30-mA current sink capability. A wide operating voltage range from 2.7 V to 38 V with reverse polarity protection up to –22 V makes the device suitable for a wide range of automotive applications. Internal protection functions are provided for reverse supply conditions, load dump, and output short circuit or overcurrent. Package Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) DRV5013-Q1 SOT-23 (3) 2.92 mm × 1.30 mm TO-92 (3) 4.00 mm × 3.15 mm (1) For all available packages, see the package option addendum at the end of the data sheet. B (mT) OUT BOP (South) BRP (North) BOF Bhys Output State Device Packages DRV5013-Q1 SLIS162I – DECEMBER 2014 – REVISED FEBRUARY 2023 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.
10 Mechanical, Packaging, and Orderable
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision H (August 2018) to Revision I (February 2023) Page
- Moved the Power Supply Recommendations and Layout sections to the Application and Implementation Changes from Revision G (October 2017) to Revision H (August 2018) Page Changes from Revision F (September 2016) to Revision G (October 2017) Page Changes from Revision E (August 2016) to Revision F (September 2016) Page Changes from Revision D (June 2016) to Revision E (August 2016) Page Changes from Revision C (May 2016) to Revision D (June 2016) Page Changes from Revision B (February 2016) to Revision C (May 2016) Page Changes from Revision A (December 2015) to Revision B (February 2016) Page DRV5013-Q1 SLIS162I – DECEMBER 2014 – REVISED FEBRUARY 2023 www.ti.com
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Changes from Revision * (December 2014) to Revision A (June 2015) Page
- Removed table notes regarding testing for the operating junction temperature in Absolute Maximum Ratings .
5 Pin Configuration and Functions
For additional configuration information, see Device Markings and Mechanical, Packaging, and Orderable Information. GND OUT
1 VCC
Figure 5-1. DBZ Package 3-Pin SOT-23 Top View 1 2 3 VCC GND OUT Figure 5-2. LPG Package 3-Pin TO-92 Top View Table 5-1. Pin Functions PIN TYPE DESCRIPTION NAME DBZ LPG GND 3 2 Ground Ground pin OUT 2 3 Output Hall sensor open-drain output. The open drain requires a resistor pullup. VCC 1 1 Power 2.7 V to 38 V power supply. Bypass this pin to the GND pin with a 0.01-µF (minimum) ceramic capacitor rated for VCC. www.ti.com DRV5013-Q1 SLIS162I – DECEMBER 2014 – REVISED FEBRUARY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: DRV5013-Q1
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT Power supply voltage VCC –22(2) 40 V Voltage ramp rate (VCC), VCC < 5 V Unlimited V/µs Voltage ramp rate (VCC), VCC > 5 V 0 2 Output pin voltage –0.5 40 V Output pin reverse current during reverse supply condition 0 100 mA Magnetic flux density, BMAX Unlimited Operating junction temperature, TJ Q, see Figure 9-1 –40 150 E, see Figure 9-1 –40 175 Storage temperature, Tstg –65 150 °C (1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime. (2) Specified by design. Only tested to –20 V.
6.2 ESD Ratings
V(ESD) Electrostatic discharge Human-body model (HBM), per AEC Q100-002(1) HBM ESD classification level 2 ±2500 V Charged-device model (CDM), per AEC Q100-011 Device HBM ESD classification level C4B ±500 (1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VCC Power supply voltage 2.7 38 V VO Output pin voltage (OUT) 0 38 V ISINK Output pin current sink (OUT)(1) 0 30 mA TA Operating ambient temperature Q, see Figure 9-1 –40 125 E, see Figure 9-1 –40 150 (1) Power dissipation and thermal limits must be observed.
6.4 Thermal Information
THERMAL METRIC(1) DRV5013-Q1 UNITDBZ (SOT-23) LPG (TO-92)
3 PINS 3 PINS
RθJA Junction-to-ambient thermal resistance 333.2 180 °C/W RθJC(top) Junction-to-case (top) thermal resistance 99.9 98.6 °C/W RθJB Junction-to-board thermal resistance 66.9 154.9 °C/W ψJT Junction-to-top characterization parameter 4.9 40 °C/W ψJB Junction-to-board characterization parameter 65.2 154.9 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. DRV5013-Q1 SLIS162I – DECEMBER 2014 – REVISED FEBRUARY 2023 www.ti.com
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6.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLIES (VCC) VCC VCC operating voltage 2.7 38 V ICC Operating supply current VCC = 2.7 V to 38 V, TA = 25°C 2.7 mA VCC = 2.7 V to 38 V, TA = TA, MAX (1) 3 3.5 ton Power-on time AD, AG, BC versions 35 50 µs FA version 35 70 OPEN-DRAIN OUTPUT (OUT) rDS(on) FET on-resistance VCC = 3.3 V, IO = 10 mA, TA = 25°C 22 Ω VCC = 3.3 V, IO = 10 mA, TA = 125 (1) 36 50 Ilkg(off) Off-state leakage current Output Hi-Z 1 µA PROTECTION CIRCUITS VCCR Reverse supply voltage –22 V IOCP Overcurrent protection level OUT shorted VCC 15 30 45 mA (1) TA, MAX is 125°C for Q Grade 1 devices and 150°C for E Grade 0 devices (see Figure 9-1).
6.6 Switching Characteristics
over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OPEN-DRAIN OUTPUT (OUT) td Output delay time B = BRP – 10 mT to BOP + 10 mT in 1 µs 13 25 µs tr Output rise time (10% to 90%) R1 = 1 kΩ, CO = 50 pF, VCC = 3.3 V 200 ns tf Output fall time (90% to 10%) R1 = 1 kΩ, CO = 50 pF, VCC = 3.3 V 31 ns www.ti.com DRV5013-Q1 SLIS162I – DECEMBER 2014 – REVISED FEBRUARY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: DRV5013-Q1
6.7 Magnetic Characteristics
over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT(1) ƒBW Bandwidth(2) 20 30 kHz DRV5013FA: ±1.3 mT BOP Operate point; see Figure 7-2 –0.6 1.3 3.4 mT BRP Release point; see Figure 7-2 –3.4 –1.3 0.6 mT Bhys Hysteresis; Bhys = (BOP – BRP) 1.2 2.6 mT BO Magnetic offset; BO = (BOP + BRP) / 2 –1.5 0 1.5 mT DRV5013AD: ±2.7 mT BOP Operate point; see Figure 7-2 1 2.7 5 mT BRP Release point; see Figure 7-2 –5 –2.7 –1 mT Bhys Hysteresis; Bhys = (BOP – BRP) 5.4 mT BO Magnetic offset; BO = (BOP + BRP) / 2 –1.5 0 1.5 mT DRV5013AG: ±6 mT BOP Operate point; see Figure 7-2 3 6 9 mT BRP Release point; see Figure 7-2 –9 –6 –3 mT Bhys Hysteresis; Bhys = (BOP – BRP) 12 mT BO Magnetic offset; BO = (BOP + BRP) / 2 –1.5 0 1.5 mT DRV5013BC: ±12 mT BOP Operate point; see Figure 7-2 6 12 18 mT BRP Release point; see Figure 7-2 –18 –12 –6 mT Bhys Hysteresis; Bhys = (BOP – BRP) 24 mT BO Magnetic offset; BO = (BOP + BRP) / 2 –1.5 0 1.5 mT (1) 1 mT = 10 Gauss. (2) Bandwidth describes the fastest changing magnetic field that can be detected and translated to the output. DRV5013-Q1 SLIS162I – DECEMBER 2014 – REVISED FEBRUARY 2023 www.ti.com
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6.8 Typical Characteristics
Supply Voltage (V) Supply Current (mA) 0 10 20 30 40 2.5 3.5 D009 TA ±& TA = 25°C TA = 75°C TA = 125°C TA = 150°C Figure 6-1. ICC vs VCC Ambient Temperature (°C) Supply Current (mA) -50 -25 0 25 50 75 100 125 150 2.5 3.5 D010 VCC = 3.3 V VCC = 13.2 V VCC = 38 V Figure 6-2. ICC vs Temperature Supply Voltage (V) Magnetic Field Operate Point BOP (mT) 0 10 20 30 40 D001 DRV5013AD DRV5013AG DRV5013BC TA = 25°C Figure 6-3. BOP vs VCC Ambient Temperature (°C) Magnetic Field Operate Point BOP (mT) -50 -25 0 25 50 75 100 125 150 D002 DRV5013AD DRV5013AG DRV5013BC VCC = 3.3 V Figure 6-4. BOP vs Temperature Supply Voltage (V) Magnetic Field Release Point BRP (mT) 0 10 20 30 40 -14 -12 -10 D003 DRV5013AD DRV5013AG DRV5013BC TA = 25°C Figure 6-5. BRP vs VCC Ambient Temperature (°C) Magnetic Field Operate Point BRP (mT) -50 -25 0 25 50 75 100 125 150 -14 -12 -10 D004 DRV5013AD DRV5013AG DRV5013BC VCC = 3.3 V Figure 6-6. BRP vs Temperature www.ti.com DRV5013-Q1 SLIS162I – DECEMBER 2014 – REVISED FEBRUARY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: DRV5013-Q1
6.8 Typical Characteristics (continued)
Supply Voltage (V) Hysteresis (mT) 0 10 20 30 40 D007 DRV5013AD DRV5013AG DRV5013BC TA = 25°C Figure 6-7. Hysteresis vs VCC Ambient Temperature (°C) Hysteresis (mT) -50 -25 0 25 50 75 100 125 150 D008 DRV5013AD DRV5013AG DRV5013BC VCC = 3.3 V Figure 6-8. Hysteresis vs Temperature Supply Voltage (V) Offset (mT) 0 10 20 30 40 -0.25 -0.125 0.125 0.25 D005 DRV5013AD DRV5013AG DRV5013BC TA = 25°C Figure 6-9. Offset vs VCC Ambient Temperature (°C) Offset (mT) -50 -25 0 25 50 75 100 125 150 -0.25 -0.125 0.125 0.25 D006 DRV5013AD DRV5013AG DRV5013BC VCC = 3.3 V Figure 6-10. Offset vs Temperature DRV5013-Q1 SLIS162I – DECEMBER 2014 – REVISED FEBRUARY 2023 www.ti.com
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7 Detailed Description
7.1 Overview
The DRV5013-Q1 device is a chopper-stabilized Hall sensor with a digital latched output for magnetic sensing applications. The DRV5013-Q1 device can be powered with a supply voltage between 2.7 V and 38 V, and continuously survives continuous –22 V reverse-battery conditions. The DRV5013-Q1 device does not operate when –22 V to 2.4 V is applied to the VCC pin (with respect to the GND pin). In addition, the device can withstand voltages up to 40 V for transient durations. The field polarity is defined as follows: a south pole near the marked side of the package is a positive magnetic field. A north pole near the marked side of the package is a negative magnetic field. The output state is dependent on the magnetic field perpendicular to the package. A south pole near the marked side of the package causes the output to pull low (operate point, B OP), and a north pole near the marked side of the package causes the output to release (release point, B RP). Hysteresis is included in between the operate point and the release point therefore magnetic-field noise does not accidentally trip the output. An external pullup resistor is required on the OUT pin. The OUT pin can be pulled up to V CC, or to a different voltage supply. This allows for easier interfacing with controller circuits.
7.2 Functional Block Diagram
2.7 V to 38 V
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7.3 Feature Description
7.3.1 Field Direction Definition
Figure 7-1 shows the positive magnetic field defined as a south pole near the marked side of the package. 1 2 3 S N B > 0 mT S N B < 0 mT S N B > 0 mT S N B < 0 mT (Bottom view) SOT-23 (DBZ) TO-92 (LPG) 1 2 3 N = North pole, S = South pole Figure 7-1. Field Direction Definition
7.3.2 Device Output
If the device is powered on with a magnetic field strength between B RP and B OP, then the device output is indeterminate and can either be Hi-Z or Low. If the field strength is greater than B OP, then the output is pulled low. If the field strength is less than BRP, then the output is released. B (mT) OUT BOP (South)BRP (North) BOF Bhys Figure 7-2. DRV5013-Q1 — BOP > 0 DRV5013-Q1 SLIS162I – DECEMBER 2014 – REVISED FEBRUARY 2023 www.ti.com
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7.3.3 Power-On Time
After applying VCC to the DRV5013-Q1 device, ton must elapse before the OUT pin is valid. During the power-up sequence, the output is Hi-Z. A pulse as shown in Figure 7-3 and Figure 7-4 occurs at the end of t on. This pulse can allow the host processor to determine when the DRV5013-Q1 output is valid after start-up. In Case 1 (Figure 7-3) and Case 2 (Figure 7-4), the output is defined assuming a constant magnetic field B > BOP and B < BRP. VCC BOP BRP t (s) B (mT) t (s) t (s) OUT Valid Output ton Figure 7-3. Case 1: Power On When B > BOP VCC BOP BRP t (s) B (mT) t (s) OUT t (s) Valid Output ton Figure 7-4. Case 2: Power On When B < BRP If the device is powered on with the magnetic field strength B RP < B < B OP, then the device output is indeterminate and can either be Hi-Z or pulled low. During the power-up sequence, the output is held Hi-Z www.ti.com DRV5013-Q1 SLIS162I – DECEMBER 2014 – REVISED FEBRUARY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: DRV5013-Q1
until ton has elapsed. At the end of t on, a pulse is given on the OUT pin to indicate that t on has elapsed. After ton, if the magnetic field changes such that B OP < B, the output is released. Case 3 ( Figure 7-5) and Case 4 ( Figure 7-6) show examples of this behavior. VCC BOP BRP t (s) B (mT) t (s) t (s) OUT Valid Output tdton Figure 7-5. Case 3: Power On When BRP < B < BOP, Followed by B > BOP VCC BOP BRP t (s) B (mT) t (s) t (s) OUT Valid Output tdton Figure 7-6. Case 4: Power On When BRP < B < BOP, Followed by B < BRP
7.3.4 Output Stage
Figure 7-7 shows the DRV5013-Q1 open-drain NMOS output structure, rated to sink up to 30 mA of current. For proper operation, use Equation 1 to calculate the value of pullup resistor R1. DRV5013-Q1 SLIS162I – DECEMBER 2014 – REVISED FEBRUARY 2023 www.ti.com
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ref refV max V minR 1 30 mA 100 µAd d (1) The size of R1 is a tradeoff between the OUT rise time and the current when OUT is pulled low. A lower current is generally better, however faster transitions and bandwidth require a smaller resistor for faster switching. In addition, make sure that the value of R1 > 500 Ω so that the output driver can pull the OUT pin close to GND. Note Vref is not restricted to V CC. The allowable voltage range of this pin is specified in the Absolute Maximum Ratings. Gate Drive OCP OUT GND Vref ISINK Figure 7-7. NMOS Open-Drain Output Select a value for C2 based on the system bandwidth specifications as shown in Equation 2. BW 1 ¦
2 R 1 C2u S u u
(2) Most applications do not require this C2 filtering capacitor. www.ti.com DRV5013-Q1 SLIS162I – DECEMBER 2014 – REVISED FEBRUARY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: DRV5013-Q1
7.3.5 Protection Circuits
The DRV5013-Q1 device is fully protected against overcurrent and reverse-supply conditions. Table 7-1 lists a summary of the protection circuits. Table 7-1. Protection Circuit Summary FAULT CONDITION DEVICE DESCRIPTION RECOVERY FET overload (OCP) ISINK ≥ IOCP Operating Output current is clamped to IOCP IO < IOCP Load dump 38 V < VCC < 40 V Operating Device will operate for a transient duration VCC ≤ 38 V Reverse supply –22 V < VCC < 0 V Disabled Device will survive this condition VCC ≥ 2.7 V
7.3.5.1 Overcurrent Protection (OCP)
An analog current-limit circuit limits the current through the FET. The driver current is clamped to I OCP. During this clamping, the rDS(on) of the output FET is increased from the nominal value.
7.3.5.2 Load Dump Protection
The DRV5013-Q1 device operates at DC V CC conditions up to 38 V nominally, and can additionally withstand VCC = 40 V. No current-limiting series resistor is required for this protection.
7.3.5.3 Reverse Supply Protection
The DRV5013-Q1 device is protected in the event that the VCC pin and the GND pin are reversed (up to –22 V). Note In a reverse supply condition, the OUT pin reverse-current must not exceed the ratings specified in the Absolute Maximum Ratings.
7.4 Device Functional Modes
The DRV5013-Q1 device is active only when VCC is between 2.7 V and 38 V. When a reverse supply condition exists, the device is inactive. With regard to some industry standards that require analyzing every possible output from a device, an internal clock is unlikely to couple to the output. DRV5013-Q1 SLIS162I – DECEMBER 2014 – REVISED FEBRUARY 2023 www.ti.com
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8 Application and Implementation
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.
8.1 Application Information
The DRV5013-Q1 device is used in magnetic-field sensing applications.
8.2 Typical Applications
8.2.1 Standard Circuit
0.01 µF (minimum) OUT VCC 10 k 680 pF (Optional) VCC Figure 8-1. Typical Application Circuit
8.2.1.1 Design Requirements
For this design example, use the parameters listed in Table 8-1 as the input parameters. Table 8-1. Design Parameters DESIGN PARAMETER REFERENCE EXAMPLE VALUE Supply voltage VCC 3.2 to 3.4 V System bandwidth ƒBW 10 kHz
8.2.1.2 Detailed Design Procedure
Table 8-2. External Components COMPONENT PIN 1 PIN 2 RECOMMENDED C1 VCC GND A 0.01-µF (minimum) ceramic capacitor rated for VCC C2 OUT GND Optional: Place a ceramic capacitor to GND R1 OUT REF(1) Requires a resistor pullup (1) REF is not a pin on the DRV5013-Q1 device, but a REF supply-voltage pullup is required for the OUT pin; the OUT pin may be pulled up to VCC. www.ti.com DRV5013-Q1 SLIS162I – DECEMBER 2014 – REVISED FEBRUARY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: DRV5013-Q1
8.2.1.2.1 Configuration Example
ref refV max V minR 1 30 mA 100 µAd d (3) For this design example, use Equation 4 to calculate the allowable range of R1. 3.4 V 3.2 VR130 mA 100 µAd d (4) Therefore: 113 Ω ≤ R1 ≤ 32 kΩ (5) After finding the allowable range of R1 (Equation 5), select a value between 500 Ω and 32 kΩ for R1. Assuming a system bandwidth of 10 kHz, use Equation 6 to calculate the value of C2. BW 1 ¦ (6) For this design example, use Equation 7 to calculate the value of C2. 12 10 kHz 2 R 1 C2u S u u (7) An R1 value of 10 kΩ and a C2 value less than 820 pF satisfy the requirement for a 10-kHz system bandwidth. A selection of R1 = 10 kΩ and C2 = 680 pF would cause a low-pass filter with a corner frequency of 23.4 kHz.
8.2.1.3 Application Curves
R1 = 10 kΩ pull-up No C2 Figure 8-2. 10-kHz Switching Magnetic Field OUT R1 = 10-kΩ pull-up C2 = 680 pF Figure 8-3. 10-kHz Switching Magnetic Field DRV5013-Q1 SLIS162I – DECEMBER 2014 – REVISED FEBRUARY 2023 www.ti.com
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Frequency (Hz) Magnitude (dB) 100 1000 10000 100000 -14 -12 -10 D011 R1 = 10-kΩ pull-up C2 = 680 pF Figure 8-4. Low-Pass Filtering
8.2.2 Alternative Two-Wire Application
For systems that require minimal wire count, the device output can be connected to V CC through a resistor, and the total supplied current can be sensed near the controller. OUT VCC GND 3 2 1 Controller Current sense Figure 8-5. 2-Wire Application Current can be sensed using a shunt resistor or other circuitry.
8.2.2.1 Design Requirements
Table 8-3 lists the related design parameters. Table 8-3. Design Parameters DESIGN PARAMETER REFERENCE EXAMPLE VALUE Supply voltage VCC 12 V OUT resistor R1 1 kΩ Bypass capacitor C1 0.1 µF Current when B < BRP IRELEASE About 3 mA Current when B > BOP IOPERATE About 15 mA www.ti.com DRV5013-Q1 SLIS162I – DECEMBER 2014 – REVISED FEBRUARY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: DRV5013-Q1
8.2.2.2 Detailed Design Procedure
When the open-drain output of the device is high-impedance, current through the path equals the I CC of the device (approximately 3 mA). When the output pulls low, a parallel current path is added, equal to V CC / (R1 + r DS(on)). Using 12 V and 1 k Ω, the parallel current is approximately 12 mA, making the total current approximately 15 mA. The local bypass capacitor C1 should be at least 0.1 µF, and a larger value if there is high inductance in the power line interconnect.
8.3 Power Supply Recommendations
The DRV5013-Q1 device is designed to operate from an input voltage supply (VM) range between 2.7 V and 38 V. A 0.01-µF (minimum) ceramic capacitor rated for V CC must be placed as close to the DRV5013-Q1 device as possible. Larger values of the bypass capacitor may be needed to attenuate any significant high-frequency ripple and noise components generated by the power source. TI recommends limiting the supply voltage variation to less than 50 mVPP.
8.4 Layout
8.4.1 Layout Guidelines
The bypass capacitor should be placed near the DRV5013-Q1 device for efficient power delivery with minimal inductance. The external pullup resistor should be placed near the microcontroller input to provide the most stable voltage at the input; alternatively, an integrated pullup resistor within the GPIO of the microcontroller can be used. Generally, using PCB copper planes underneath the DRV5013-Q1 device has no effect on magnetic flux, and does not interfere with device performance. This is because copper is not a ferromagnetic material. However, If nearby system components contain iron or nickel, they may redirect magnetic flux in unpredictable ways.
8.4.2 Layout Example
Figure 8-6. DRV5013-Q1 Layout Example DRV5013-Q1 SLIS162I – DECEMBER 2014 – REVISED FEBRUARY 2023 www.ti.com
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9 Device and Documentation Support
9.1 Device Support
9.1.1 Device Nomenclature
Figure 9-1 shows a legend for reading the complete device name for and DRV5013-Q1 device. (DBZ)(AD)DRV5013 Prefix DRV5013: Digital latch Hall sensor (Q) (R) (Q1) AEC-Q100 Q1: Automotive qualification Blank: Non-auto Package DBZ: 3-pin SOT-23 LPG: 3-pin TO-92 Temperature Range Q: ±40 to 125°C E: ±40 to 150°C BOP/BRP FA: 1.3/±1.3 mT AD: 2.7/±2.7 mT AG: 6/±6 mT BC: 12/±12 mT Tape and Reel R: 3000 pcs/reel T: 250 pcs/reel M: 3000 pcs/box (ammo) Blank: 1000 pcs/bag (bulk) Figure 9-1. Device Nomenclature
9.1.2 Device Markings
Figure 9-2. SOT-23 (DBZ) Package (Bottom view) 1 2 3 Marked Side Front Marked Side 1 2 3 Figure 9-3. TO-92 (LPG) Package
9.2 Receiving Notification of Documentation Updates
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9.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.
9.4 Trademarks
TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.
9.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
9.6 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
10 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. DRV5013-Q1 SLIS162I – DECEMBER 2014 – REVISED FEBRUARY 2023 www.ti.com
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www.ti.com 7-Oct-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) DRV5013ADEDBZJQ1 Active Production SOT-23 (DBZ) | 3 10000 | JUMBO T&R Yes NIPDAUAG | SN Level-1-260C-UNLIM -40 to 150 (+NJAD, NJAD) DRV5013ADEDBZJQ1.A Active Production SOT-23 (DBZ) | 3 10000 | JUMBO T&R Yes SN Level-1-260C-UNLIM -40 to 150 (+NJAD, NJAD) DRV5013ADEDBZRQ1 Active Production SOT-23 (DBZ) | 3 3000 | LARGE T&R Yes NIPDAUAG | SN Level-1-260C-UNLIM -40 to 150 (+NJAD, NJAD) DRV5013ADEDBZRQ1.A Active Production SOT-23 (DBZ) | 3 3000 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 150 (+NJAD, NJAD) DRV5013ADEDBZTQ1 Obsolete Production SOT-23 (DBZ) | 3 - - Call TI Call TI -40 to 150 +NJAD DRV5013ADELPGMQ1 Active Production TO-92 (LPG) | 3 3000 | AMMO Yes SN N/A for Pkg Type -40 to 150 +NJAD DRV5013ADELPGMQ1.A Active Production TO-92 (LPG) | 3 3000 | AMMO Yes SN N/A for Pkg Type -40 to 150 +NJAD DRV5013ADELPGQ1 Active Production TO-92 (LPG) | 3 1000 | BULK Yes SN N/A for Pkg Type -40 to 150 +NJAD DRV5013ADELPGQ1.A Active Production TO-92 (LPG) | 3 1000 | BULK Yes SN N/A for Pkg Type -40 to 150 +NJAD DRV5013ADQDBZRQ1 Active Production SOT-23 (DBZ) | 3 3000 | LARGE T&R Yes NIPDAUAG | SN Level-1-260C-UNLIM -40 to 125 (+NKAD, NKAD) DRV5013ADQDBZRQ1.A Active Production SOT-23 (DBZ) | 3 3000 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 (+NKAD, NKAD) DRV5013ADQDBZTQ1 Obsolete Production SOT-23 (DBZ) | 3 - - Call TI Call TI -40 to 125 +NKAD DRV5013ADQLPGMQ1 Active Production TO-92 (LPG) | 3 3000 | AMMO Yes SN N/A for Pkg Type -40 to 125 +NKAD DRV5013ADQLPGMQ1.A Active Production TO-92 (LPG) | 3 3000 | AMMO Yes SN N/A for Pkg Type -40 to 125 +NKAD DRV5013ADQLPGQ1 Active Production TO-92 (LPG) | 3 1000 | BULK Yes SN N/A for Pkg Type -40 to 125 +NKAD DRV5013ADQLPGQ1.A Active Production TO-92 (LPG) | 3 1000 | BULK Yes SN N/A for Pkg Type -40 to 125 +NKAD DRV5013AGEDBZRQ1 Active Production SOT-23 (DBZ) | 3 3000 | LARGE T&R Yes NIPDAUAG | SN Level-1-260C-UNLIM -40 to 150 (+NJAG, NJAG) DRV5013AGEDBZRQ1.A Active Production SOT-23 (DBZ) | 3 3000 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 150 (+NJAG, NJAG) DRV5013AGEDBZTQ1 Obsolete Production SOT-23 (DBZ) | 3 - - Call TI Call TI -40 to 150 +NJAG DRV5013AGELPGMQ1 Active Production TO-92 (LPG) | 3 3000 | AMMO Yes SN N/A for Pkg Type -40 to 150 +NJAG DRV5013AGELPGMQ1.A Active Production TO-92 (LPG) | 3 3000 | AMMO Yes SN N/A for Pkg Type -40 to 150 +NJAG DRV5013AGELPGQ1 Active Production TO-92 (LPG) | 3 1000 | BULK Yes SN N/A for Pkg Type -40 to 150 +NJAG DRV5013AGELPGQ1.A Active Production TO-92 (LPG) | 3 1000 | BULK Yes SN N/A for Pkg Type -40 to 150 +NJAG DRV5013AGQDBZRQ1 Active Production SOT-23 (DBZ) | 3 3000 | LARGE T&R Yes NIPDAUAG | SN Level-1-260C-UNLIM -40 to 125 (+NKAG, NKAG) DRV5013AGQDBZRQ1.A Active Production SOT-23 (DBZ) | 3 3000 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 (+NKAG, NKAG) DRV5013AGQDBZTQ1 Obsolete Production SOT-23 (DBZ) | 3 - - Call TI Call TI -40 to 125 +NKAG DRV5013AGQLPGMQ1 Active Production TO-92 (LPG) | 3 3000 | AMMO Yes SN N/A for Pkg Type -40 to 125 +NKAG DRV5013AGQLPGMQ1.A Active Production TO-92 (LPG) | 3 3000 | AMMO Yes SN N/A for Pkg Type -40 to 125 +NKAG DRV5013AGQLPGQ1 Active Production TO-92 (LPG) | 3 1000 | BULK Yes SN N/A for Pkg Type -40 to 125 +NKAG Addendum-Page 1
www.ti.com 7-Oct-2025 Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) DRV5013AGQLPGQ1.A Active Production TO-92 (LPG) | 3 1000 | BULK Yes SN N/A for Pkg Type -40 to 125 +NKAG DRV5013BCEDBZRQ1 Active Production SOT-23 (DBZ) | 3 3000 | LARGE T&R Yes NIPDAUAG | SN Level-1-260C-UNLIM -40 to 150 (+NJBC, NJBC) DRV5013BCEDBZRQ1.A Active Production SOT-23 (DBZ) | 3 3000 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 150 (+NJBC, NJBC) DRV5013BCEDBZTQ1 Obsolete Production SOT-23 (DBZ) | 3 - - Call TI Call TI -40 to 150 +NJBC DRV5013BCELPGMQ1 Active Production TO-92 (LPG) | 3 3000 | AMMO Yes SN N/A for Pkg Type -40 to 150 +NJBC DRV5013BCELPGMQ1.A Active Production TO-92 (LPG) | 3 3000 | AMMO Yes SN N/A for Pkg Type -40 to 150 +NJBC DRV5013BCELPGQ1 Active Production TO-92 (LPG) | 3 1000 | BULK Yes SN N/A for Pkg Type -40 to 150 +NJBC DRV5013BCELPGQ1.A Active Production TO-92 (LPG) | 3 1000 | BULK Yes SN N/A for Pkg Type -40 to 150 +NJBC DRV5013BCQDBZRQ1 Active Production SOT-23 (DBZ) | 3 3000 | LARGE T&R Yes NIPDAUAG | SN Level-1-260C-UNLIM -40 to 125 (+NKBC, NKBC) DRV5013BCQDBZRQ1.A Active Production SOT-23 (DBZ) | 3 3000 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 (+NKBC, NKBC) DRV5013BCQDBZTQ1 Obsolete Production SOT-23 (DBZ) | 3 - - Call TI Call TI -40 to 125 +NKBC DRV5013BCQLPGMQ1 Active Production TO-92 (LPG) | 3 3000 | AMMO Yes SN N/A for Pkg Type -40 to 125 +NKBC DRV5013BCQLPGMQ1.A Active Production TO-92 (LPG) | 3 3000 | AMMO Yes SN N/A for Pkg Type -40 to 125 +NKBC DRV5013BCQLPGQ1 Active Production TO-92 (LPG) | 3 1000 | BULK Yes SN N/A for Pkg Type -40 to 125 +NKBC DRV5013BCQLPGQ1.A Active Production TO-92 (LPG) | 3 1000 | BULK Yes SN N/A for Pkg Type -40 to 125 +NKBC DRV5013FAEDBZRQ1 Active Production SOT-23 (DBZ) | 3 3000 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 150 +NJFA DRV5013FAEDBZRQ1.A Active Production SOT-23 (DBZ) | 3 3000 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 150 +NJFA (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. Addendum-Page 2
www.ti.com 7-Oct-2025 (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF DRV5013-Q1 :
- Catalog : DRV5013 NOTE: Qualified Version Definitions:
- Catalog - TI's standard catalog product Addendum-Page 3
PACKAGE MATERIALS INFORMATION www.ti.com 15-Jul-2026 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION www.ti.com 15-Jul-2026 Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION www.ti.com 15-Jul-2026 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DRV5013ADEDBZJQ1 SOT-23 DBZ 3 10000 367.0 367.0 35.0 DRV5013ADEDBZJQ1 SOT-23 DBZ 3 10000 346.0 346.0 29.0 DRV5013ADEDBZRQ1 SOT-23 DBZ 3 3000 210.0 185.0 35.0 DRV5013ADEDBZRQ1 SOT-23 DBZ 3 3000 180.0 180.0 18.0 DRV5013ADEDBZRQ1 SOT-23 DBZ 3 3000 202.0 201.0 28.0 DRV5013ADQDBZRQ1 SOT-23 DBZ 3 3000 180.0 180.0 18.0 DRV5013ADQDBZRQ1 SOT-23 DBZ 3 3000 202.0 201.0 28.0 DRV5013ADQDBZRQ1 SOT-23 DBZ 3 3000 210.0 185.0 35.0 DRV5013AGEDBZRQ1 SOT-23 DBZ 3 3000 210.0 185.0 35.0 DRV5013AGEDBZRQ1 SOT-23 DBZ 3 3000 202.0 201.0 28.0 DRV5013AGQDBZRQ1 SOT-23 DBZ 3 3000 210.0 185.0 35.0 DRV5013AGQDBZRQ1 SOT-23 DBZ 3 3000 202.0 201.0 28.0 DRV5013BCEDBZRQ1 SOT-23 DBZ 3 3000 210.0 185.0 35.0 DRV5013BCEDBZRQ1 SOT-23 DBZ 3 3000 202.0 201.0 28.0 DRV5013BCQDBZRQ1 SOT-23 DBZ 3 3000 210.0 185.0 35.0 DRV5013BCQDBZRQ1 SOT-23 DBZ 3 3000 202.0 201.0 28.0 DRV5013FAEDBZRQ1 SOT-23 DBZ 3 3000 210.0 185.0 35.0 DRV5013FAEDBZRQ1 SOT-23 DBZ 3 3000 202.0 201.0 28.0 Pack Materials-Page 3
www.ti.com PACKAGE OUTLINE C 0.20
0.08 TYP
0.25 2.64 2.10
1.12 MAX
0.10
0.01 TYP
3X 0.5 0.3 0.6
0.2 TYP
1.9 0.95 0 -8 TYP 4X 0 -15 4X 4 -15 A 3.04 2.80 B1.4 1.2 (0.95) (0.15) (0.125) SOT-23 - 1.12 mm max heightDBZ0003A SMALL OUTLINE TRANSISTOR 4214838/F 08/2024 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Reference JEDEC registration TO-236, except minimum foot length. 4. Support pin may differ or may not be present. 5. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.25mm per side
0.2 C A B
0.1 C SCALE 4.000
www.ti.com EXAMPLE BOARD LAYOUT
0.07 MAX
0.07 MIN
3X (1.3) 3X (0.6) (2.1) 2X (0.95) (R0.05) TYP 4214838/F 08/2024 SOT-23 - 1.12 mm max heightDBZ0003A SMALL OUTLINE TRANSISTOR NOTES: (continued) 5. Publication IPC-7351 may have alternate designs. 6. Solder mask tolerances between and around signal pads can vary based on board fabrication site. SYMM LAND PATTERN EXAMPLE SCALE:15X PKG SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED METALSOLDER MASK OPENING NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DETAILS
www.ti.com EXAMPLE STENCIL DESIGN (2.1) 2X(0.95) 3X (1.3) 3X (0.6) (R0.05) TYP SOT-23 - 1.12 mm max heightDBZ0003A SMALL OUTLINE TRANSISTOR 4214838/F 08/2024 NOTES: (continued) 7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 8. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 THICK STENCIL SCALE:15X SYMM PKG
www.ti.com PACKAGE OUTLINE 4.1 3.9 15.5 15.1 3X 0.48 0.35 2X 1.27 0.05 3.25 3.05 3X 0.51 0.36 3X 0.55 0.40 2X (45 ) 0.86 0.66 1.62 1.42 2.64 2.44 2.68 2.28 5.05 MAX (0.5425) 3X (0.8) 4221343/C 01/2018 TO-92 - 5.05 mm max heightLPG0003A TRANSISTOR OUTLINE NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 1 3 1 2 3 SCALE 1.300
www.ti.com EXAMPLE BOARD LAYOUT TYP ALL AROUND
0.05 MAX
TYP(1.07) (1.7) (1.27) (2.54) 2X (1.7) 3X ( 0.75) VIA 4221343/C 01/2018 TO-92 - 5.05 mm max heightLPG0003A TRANSISTOR OUTLINE LAND PATTERN EXAMPLE NON-SOLDER MASK DEFINED SCALE:20X METAL TYP OPENING SOLDER MASK 1 32 METAL2X SOLDER MASK OPENING
www.ti.com TAPE SPECIFICATIONS 0 1 0 1 12.9 12.5 6.55 6.15 13.0 12.4
2.5 MIN
6.5 5.5 3.8-4.2 TYP 9.5 8.5 19.0 17.5
1 MAX21
0.45 0.35 0.25 0.15 TO-92 - 5.05 mm max heightLPG0003A TRANSISTOR OUTLINE 4221343/C 01/2018
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