DM9161A ETC1
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Technical content
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
1 Preliminary
Version: DM9161A-DS-P04 Jan.19,2005 DAVICOM Semiconductor, Inc. DM9161A 10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver DATA SHEET Prel i mi nary Versi on: DM9161A- DS- P04 J an. 19, 2005
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver Preliminary 2 Version: DM9161A-DS-P04 Jan.19, 2005 Table of Contents
5.8 Pin Maps of Normal MII, Reduced MII, and 10Base-T GPSI
6.1 LED Functional Description……………………..12
7.2.9 Management Interface – Read Frame
8.5 Auto-negotiation Advertisement Register (ANAR)
8.6 Auto-negotiation Link Partner Ability Register (ANLPAR) - 0528
8.7 Auto-negotiation Expansion Register (ANER)
8.9 DAVICOM Specified Configuration and Status Register
8.12 DAVICOM Specified Receive Error Counter Register (RECR) -
8.13 DAVICOM Specified Disconnect Counter Register (DISCR) -
8.14 DAVICOM Hardware Reset Latch State
- DC and AC Electrical Characteristics
9.4 AC Electrical Characteristics & Timing
9.4.11 MII 10Base-T Nibble Transmit Timing
9.4.13 MII 10Base-T Receive Nibble Timing
9.4.14 Auto-negotiation and Fast Link Pulse Timing Parameters41
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
3 Preliminary
Version: DM9161A-DS-P04 Jan. 19, 2005 1. General Description The DM9161A is a physical layer, single-chip, and low power transceiver for 100BASE-TX and 10BASE-T operations. On the media side, it provides a direct interface either to Unshielded Twisted Pair Category 5 Cable (UTP5) for 100BASE-TX Fast Ethernet, or UTP5/UTP3 Cable for 10BASE-T Ethernet. Through the Media Independent Interface (MII), the DM9161A connects to the Medium Access Control (MAC) layer, ensuring a high inter operability from different vendors. TheDM9161A uses a low power and high performance advanced CMOS process. It contains the entire physical layer functions of 100BASE-TX as defined by IEEE802.3u, including the Physical Coding Sublayer (PCS), Physical Medium Attachment (PMA), Twisted Pair Physical Medium Dependent Sublayer (TP-PMD), 10BASE-TX Encoder/Decoder (ENC/DEC), and Twisted Pair Media Access Unit (TPMAU). The DM9161A provides a strong support for the auto-negotiation function, utilizing automatic media speed and protocol selection. Furthermore, due to the built-in wave shaping filter, the DM9161A needs no external filter to transport signals to the media in 100BASE-TX or 10BASE-T Ethernet operation. 2. Features Fully comply with IEEE 802.3 / IEEE 802.3u 10Base-T/ 100Base-TX, ANSI X3T12 TP-PMD 1995 standard Support MDI/MDI-X auto crossover function (Auto-MDI) Support Auto-Negotiation function, compliant with IEEE 802.3u Fully integrated Physical layer transceiver On-chip filtering with direct interface to magnetic transformer Selectable repeater or node mode Selectable MII or RMII (Reduced MII) mode for 100Base-TX and 10Base-TX. Selectable MII or GPSI (7-Wired) mode for 10Base-T Selectable full-duplex or half-duplex operation MII management interface with maskable interrupt output capability Provide Loopback mode for easy system diagnostics LED status outputs indicate Link/ Activity, Speed10/100 and Full-duplex/Collision. Support Dual-LED optional control Single low power Supply of 3.3V with an advanced CMOS technology Very Low Power consumption modes:
- Power Reduced mode (cable detection)
- Power Down mode
- Selectable TX drivers for 1:1 or 1.25:1 transformers for additional power reduction. 1: 1 transformers only when Auto MDIX Enable . Compatible with 3.3V and 5.0V tolerant I/Os 48-pin LQFP
Version: DM9161A-DS-P04 Jan.19, 2005 3. Block Diagram MII Signals MII Interface/ Control 4B/5B Encoder 4B/5B Decoder Register Code- group Alignment Descrambler Serial to Parallel NRZI to NRZ RX CRM MLT-3 to NRZI Adaptive EQ Digital Logic Scrambler Parallel to Serial NRZ to NRZI NRZI to MLT-3 MLT-3 Driver Rise/Fall Time CTL TX CGM LED Driver Collision Detection Carrier Sense Auto- Negotiation 10BASE-T Module RX TX 125M CLK 25M CLK LED1-4# 25M OSCI RXI+/- RXI+/- 10TXD+/- 100TXD+/- AutoMDIX
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Version: DM9161A-DS-P04 Jan.19,2005 4. Pin Configuration: AVDDR AVDDT RX+ TX- RX- AGND AGND TX+ AVDDR PWRDWN LED0/OP0 LED1/OP1 RXDV/TESTMODE RXER/RXD[4]/RPTR DISMDIX DVDD RESET# XT2 XT1 DGND NC AGND BGRESG BGRES TXD[1] LED2/OP2 CABLESTS/LINKSTS DGND TXER/TXD[4] TXD[3] TXD[2] TXEN TXCLK/ISOLATE DVDD TXD[0] MDC MDIO RXD[0]/PHYAD[0] RXD[2]/PHYAD[2] RXD[3]/PHYAD[3] RXD[1]/PHYAD[1] DVDD LEDMODE MDINTR# RXCLK/10BTSER DGND CRS/PHYAD[4] COL/RMII DM9161A 5. Pin Description
Version: DM9161A-DS-P04 Jan.19, 2005 I: Input, O: Output, LI: Latch input when power-up/reset, Z: Tri-State output, U: Pulled high D: Pulled low
5.1 Normal MII Interface, 21 pins
Pin No. Pin Name I/O
Description
TXER/TXD [4] I Transmit Error/The Fifth TXD Data Bit In 100Mbps mode, when the signal indicates active high and TXEN is active, the HALT symbol substitutes the actual data nibble. In 10Mbps, the input is ignored In bypass mode (bypass BP4B5B), TXER becomes the TXD [4] pin, the fifth TXD data bit of the 5B symbol 20,19,18,17 TXD [0:3] I Transmit Data 4-bit nibble data inputs (synchronous to the TXCLK) when in 10/100Mbps nibble mode. In 10Mbps GPSI (7-Wired) mode, the TXD [0] pin is used as the serial data input pin, and TXD [1:3] are ignored. TXEN I Transmit Enable Active high indicates the presence of valid nibble data on the TXD [0:3] for both 100Mbps and 10Mbps nibble modes. In 10Mbps GPSI (7-Wired) mode, active high indicates the presence of valid 10Mbps data on TXD [0]. TXCLK/ ISOLATE LI (D) Transmit Clock The transmitting clock provides the timing reference for the transfer of the TXEN, TXD, and TXER. TXCLK is provided by the PHY 25MHz in 100Mbps nibble mode, 2.5MHz in 10Mbps nibble mode, 10MHz in 10Mbps GPSI (7-Wired) mode ISOLATE Setting: (When power up reset, latch input) 0: Reg 0.10 will be initialized to “0”. (Ref.to 8.1 Basic Control Register) 1: Reg 0.10 will be initialized to “1”. MDC I Management Data Clock Synchronous clock for the MDIO management data. This clock is provided by management entity, and it is up to 2.5MHz MDIO I/O Management Data I/O Bi-directional management data which may be provided by the station management entity or the PHY 29,28,27,26 RXD[0:3] /PHYAD[0:3] LI (D) Receive Data Output 4-bit nibble data outputs (synchronous to RXCLK) when in 10/100Mbps MII mode In 10Mbps GPSI (7-Wired) mode, the RXD [0] pin is used as the serial data output pin, and the RXD [1:3] are ignored PHY address [0:3] (power up reset latch input) PHY address sensing input pins MDINTR IO, LI (D) Status Interrupt Output: Whenever there is a status change (link, speed, duplex depend on interrupt register [21] ) The interrupt output assert low when pull up. Asserted high when pull down.
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Version: DM9161A-DS-P04 Jan.19,2005 RXCLK /10BTSER LI (U) Receive Clock The received clock provides the timing reference for the transfer of the RXDV, RXD, and RXER. RXCLK is provided by PHY. The PHY may recover the RXCLK reference from the received data or it may derive the RXCLK reference from a nominal clock 25MHz in 100Mbps MII mode, 2.5MHz in 10Mbps MII mode, 10MHz in 10Mbps GPSI (7-Wired) mode 10BTSER only support for 10M mode; (power up reset latch input) 0 = GPSI (7-Wired) mode in 10M mode 1 = MII mode in 10M mode CRS /PHYAD[4] LI (D) Carrier Sense Detect/ PHYAD[4] Asserted high to indicate the presence of carrier due to receive or transmit activities in half-duplex mode of 10BASE-T or 100BASE-TX. In repeater mode or full-duplex mode, this signal is asserted high to indicate the presence of carrier due to receive activity only This pin is also used as PHYAD [4] (power up reset latch input) PHY address sensing input pin COL /RMII LI (D) Collision Detection Asserted high to indicate the detection of the collision conditions in half-duplex mode of 10Mbps and 100Mbps. In full-duplex mode, this signal is always logical 0 Reduced MII enable: This pin is also used to select Normal MII or Reduced MII. (power up reset latch input) 0= Normal MII (default) 1= Reduced MII This pin is always pulled low except used as reduced MII RXDV /TESTMODE LI (D) Receive Data Valid Asserted high to indicate that the valid data is presented on the RXD [0:3] Test mode control pin (power up reset latch input) 0 = normal operation (default) 1 = enable test mode RXER/RXD[4] /RPTR LI (D) Receive Data Error/The Fifth RXD Data Bit of the 5B Symbol Asserted high to indicate that an invalid symbol has been detected In decoder bypass mode (bypass BP4B5B), RXER becomes RXD [4], the fifth RXD data bit of the 5B symbol This pin is also used to select Repeater or Node mode. (power up reset latch input) 0 = Node Mode (default) 1 = Repeater Mode LEDMODE I LED MODE Select Reference LED function description 0: support Dual-LED 1: Normal LED RESET# I Reset Active low input that initializes the DM9161A.
Version: DM9161A-DS-P04 Jan.19, 2005
5.2 Media Interface, 4 pins
Pin No. Pin Name I/O 3,4 RX+ RX- I Differential Receive Pair Differential data is received from the media 7,8 TX+ TX- O Differential Transmit Pair/PECL Transmit Pair Differential data is transmitted to the media in TP mode
5.3 LED Interface, 3 pins
Pin No. Pin Name I/O /OP0 LI (U) LED Driver output 0 OP0: (power up reset latch input) This pin is used to control the forced or advertised operating mode of the DM9161A according to the Table A. The value is latched into the DM9161A registers at power-up/reset LED1 /OP1 LI (U) LED Driver output 1 OP1: (power up reset latch input) This pin is used to control the forced or advertised operating mode of the DM9161A according to the Table A. The value is latched into the DM9161A registers at power-up/reset LED2 /OP2 LI (U) LED Driver output 2 OP2: (power up reset latch input) This pin is used to control the forced or advertised operating mode of the DM9161A according to the Table A. The value is latched into the DM9161A registers at power-up/reset
5.4 Mode, 3 pins
Pin No. Pin Name I/O I Power Down Control Asserted high to force the DM9161A into power down mode. When in power down mode, most of the DM9161A circuit block’s power is turned off, only the MII management interface (MDC, MDIO) logic is available (the PHY should respond to management transactions and should not generate spurious signals on the MII)). To leave power down mode, the DM9161A needs the hardware or software reset with the PWRDWN pin low CABLESTS /LINKSTS LI (D) Cable Status or Link Status This pin is used to indicate the status of the cable connection when power up reset latch low (Default) 0 = Without cable connection 1 = With cable connection This pin is used to indicate the status of the Link connection when power up reset latch high 0 = With link 1 = Without link DISMDIX I (D) Auto MDIX Control 1: Disable auto mode 0: Enable auto MDI/MDIX mode
5.5 Bias and Clock, 4 pins
Version: DM9161A-DS-P04 Jan.19, 2005 Pin No. Pin Name I/O P Bandgap Ground BGRES O Bandgap Voltage Reference Resistor 6.8K ohm +/- 1% XT2 I/O Crystal Output; REF_CLK input for RMII mode XT1 I Crystal Input
5.6 Power, 12 pins
Pin No. Pin Name I/O 1,2 AVDDR P Analog Receive Power output AVDDT P Analog Transmit Power output AGND P Analog Receive Ground AGND P Analog Transmit Ground AGND P Analog Substrate Ground 23,30,41 DVDD P Digital Power 15,33,44 DGND P Digital Ground
5.7 Table A (Media Type Seclection)
Auto-negotiation Enables All Capabilities
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Version: DM9161A-DS-P04 Jan.19,2005
5.8 Pin Maps of Normal MII, Reduced MII, and 10Base-T GPSI (7-Wired) Mode
10Base-T GPSI (7-Wired) Mode TXD [0:1] TXD [0:1] TXD [0] ; TXD [1] = NC TXD [2:3] NC NC TXEN TXEN TXEN TXER/TXD [4] NC NC TXCLK NC TXCLK RXD [0:1] RXD [0:1] RXD [0] ; RXD [1] = NC RXD[2:3] NC NC RXER/RXD[4]/RPTR/NODE RPTR/NODE RPTR/NODE RXDV CRS DV NC RXCLK NC RXCLK COL NC COL CRS (PHYADR [2:4]) (BP4B5B) NC CRS MDC MDC MDC MDIO MDIO MDIO RESET# RESET# RESET# XT1 (25 MHz) XT2 (REF_CLK 50MHz) XT1 (25 MHz)
Version: DM9161A-DS-P04 Jan.19, 2005 6.LED Configuration LEDs flash once per 500ms after power-on reset or software reset by writing PHY register. All LED pins are dual function pins, which can be configured as either active high or low by pulling them low or high accordingly. If the pin is pulled high, the LED is active low after reset. Likewise, if the pin is pulled low, the LED is active high. DVDD DM9161A
510 Ohm
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Version: DM9161A-DS-P04 Jan.19,2005
6.1 LED Function Description
LK_ACT TX_RX_ACT Active depend on strap value2 CABLESTS CABLESTS(High active) LINK(low active) Note1 & Note2: FDX:Active status indicate the full-duplex mode. SPEED: Active status indicate the 100Mbps mode. LK-ACT: Active status indicate the good link for 100Mbps and 100Mbps operations.It's flash when transnitting or receiving data. For Dual-LED. LEDMODE = 0 Pin14, Pulldown Pin_14 pullup LinkFail 100M 10M Pin Link Act Link Act Lo Lo LoHi Hi HiLo Same Previous define Lo Hi Lo Same Previous define FDX1 FDX1 FDX1 FDX_COL, collision flash out CABLESTS(High active) LINK(low active) 1 : When Half mode LED is blank. The collision status can flash output by change register 16.5, set to High. 2 Application reference 6.1.0 TX-RX-ACT:Active flash when transmitting and receiving data. CABLESTS:Active status indicate the cable connection. LINK:Active status indicate the good link 10Mbps or 100Mbps operation. 16.1.1 Dual-LED application circuit. 7. Functional Description The DM9161A Fast Ethernet single chip transceiver, providing the functionality as specified in IEEE 802.3u, PAD PAD
Version: DM9161A-DS-P04 Jan.19, 2005 integrates a complete 100Base-TX module and a complete 10Base-T module. The DM9161A provides a Media Independent Interface (MII) as defined in the IEEE 802.3u standard (Clause 22). The DM9161A performs all PCS (Physical Coding Sublayer), PMA (Physical Media Access), TP-PMD (Twisted Pair Physical Medium Dependent) sublayer, 10Base-T Encoder/Decoder, and Twisted Pair Media Access Unit (TPMAU) functions. Figure 7-1 shows the major functional blocks implemented in the DM9161A. MII Interface MII Interface 100Base-TX Transmitter 100Base-TX Transmitter 100Base-TX Receiver 100Base-TX Receiver 10Base-T Tranceiver 10Base-T Tranceiver Carrier Sense Carrier Sense Collision Detection Collision Detection Auto Negotiation Auto Negotiation MII Serial Management Interface MII Serial Management Interface Auto MDIX Auto MDIX Figure 7-1
7.1 MII Interface
The DM 9161A provides a Media Independent Interface (MII) as defined in the IEEE 802.3u standard (Clause 22). The purpose of the MII interface is to provide a simple, easy to implement connection between the MAC Reconciliation layer and the PHY. The MII is designed to make the differences between various media transparent to the MAC sublayer. The MII consists of a nibble wide receive data bus, a nibble wide transmit data bus, and control signals to facilitate data transfers between the PHY and the Reconciliation layer. TXD (transmit data) is a nibble (4 bits) of data that are driven by the reconciliation sublayer synchronously with respect to TXCLK. For each TXCLK period, which TXEN is asserted, TXD (3:0) are accepted for transmission by the PHY. TXCLK (transmit clock) output to the MAC reconciliation sublayer is a continuous clock that provides the timing reference for the transfer of the TXEN, TXD, and TXER signals. TXEN (transmit enable) input from the MAC reconciliation sublayer indicates that nibbles are being presented on the MII for transmission on the physical medium.
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Version: DM9161A-DS-P04 Jan.19,2005 MII Interface (continued) TXER (transmit coding error) transitions are synchronously with respect to TXCLK. If TXER is asserted for one or more clock periods, and TXEN is asserted, the PHY will emit one or more symbols that are not part of the valid data delimiter set somewhere in the frame being transmitted. RXD (receive data) is a nibble (4 bits) of data that are sampled by the reconciliation sublayer synchronously with respect to RXCLK. For each RXCLK period which RXDV is asserted, RXD (3:0) are transferred from the PHY to the MAC reconciliation sublayer. RXCLK (receive clock) output to the MAC reconciliation sublayer is a continuous clock that provides the timing reference for the transfer of the RXDV, RXD, and RXER signals. RXDV (receive data valid) input from the PHY indicates that the PHY is presenting recovered and decoded nibbles to the MAC reconciliation sublayer. To interpret a receive frame correctly by the reconciliation sublayer, RXDV must encompass the frame, starting no later than the Start-of-Frame delimiter and excluding any End-Stream delimiter. RXER (receive error) transitions are synchronously with respect to RXCLK. RXER will be asserted for 1 or more clock periods to indicate to the reconciliation sublayer that an error was detected somewhere in the frame being transmitted from the PHY to the reconciliation sublayer. CRS (carrier sense) is asserted by the PHY when either the transmit or receive medium is non-idle, and de-asserted by the PHY when the transmit and receive medium are idle. Figure 7-2 depicts the behavior of CRS during 10Base-T and 100Base-TX transmission. TXD Preamble SFD Data EFD Preamble SFD Data ESD J/K SSD T/R 10Base-T 100Base-TX TXD CRS CRS IDLE IDLE Figure 7-2
Version: DM9161A-DS-P04 Jan.19, 2005 7.2 100Base-TX Operation The 100Base-TX transmitter receives 4-bit nibble data clocked in at 25MHz at the MII, and outputs a scrambled 5-bit encoded MLT-3 signal to the media at 100Mbps. The on-chip clock circuit converts the 25MHz clock into a 125MHz clock for internal use. The IEEE 802.3u specification defines the Media Independent Interface. The interface specification defines a dedicated receive data bus and a dedicated transmit data bus. These two busses include various controls and signal indications that facilitate data transfers between the DM9161A and the Reconciliation layer. 7.2.1 100Base-TX Transmit The 100Base-TX transmitter consists of the functional blocks shown in figure 7-3. The 100Base-TX transmit section converts 4-bit synchronous data provided by the MII to a scrambled MLT-3 125, a million symbols per second serial data stream. MII Signals MII Interface/ Control 4B/5B Encoder 4B/5B Decoder Register Code- group Alignment Descrambler Serial to Parallel NRZI to NRZ RX CRM MLT-3 to NRZI Adaptive EQ Digital Logic Scrambler Parallel to Serial NRZ to NRZI NRZI to MLT-3 MLT-3 Driver Rise/Fall Time CTL TX CGM LED Driver Collision Detection Carrier Sense Auto- Negotiation 10BASE-T Module RX TX 125M CLK 25M CLK LED1-4# 25M OSCI RXI+/- RXI+/- 10TXD+/- 100TXD+/- AutoMDIX Figure 7-3
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Version: DM9161A-DS-P04 Jan.19,2005 The block diagram in figure 7-3 provides an overview of the functional blocks contained in the transmit section. The transmitter section contains the following functional blocks: - 4B5B Encoder - Scrambler - Parallel to Serial Converter - NRZ to NRZI Encoder - NRZI to MLT-3 - MLT-3 Driver 7.2.1.1 4B5B Encoder The 4B5B encoder converts 4-bit (4B) nibble data generated by the MAC Reconciliation Layer into a 5-bit (5B) code group for transmission, see reference Table 7-1. This conversion is required for control and packet data to be combined in code groups. The 4B5B encoder substitutes the first 8 bits of the MAC preamble with a J/K code group pair (11000 10001) upon transmit. The 4B5B encoder continues to replace subsequent preamble and data nibbles with corresponding 5B code-groups. At the end of the transmit packet, upon the deassertion of the Transmit Enable signal from the MAC Reconciliation layer, the 4B5B encoder injects the T/R code group pair (01101 00111) indicating end of frame. After the T/R code group pair, the 4B5B encoder continuously injects IDLEs into the transmit data stream until Transmit Enable is asserted and the next transmit packet is detected. The DM9161A includes a Bypass 4B5B conversion option within the 100Base-TX Transmitter for support of applications like 100 Mbps repeaters, which do not require 4B5B conversion.
7.2.1.2 Scrambler
The scrambler is required to control the radiated emissions (EMI) by spreading the transmit energy across the frequency spectrum at the media connector and on the twisted pair cable in 100Base-TX operation. By scrambling the data, the total energy presented to the cable is randomly distributed over a wide frequency range. Without the scrambler, energy levels on the cable could peak beyond FCC limitations at frequencies related to repeated 5B sequences like continuous transmission of IDLE symbols. The scrambler output is combined with the NRZ 5B data from the code group encoder via an XOR logic function. The result is a scrambled data stream with sufficient randomization to decrease radiated emissions at critical frequencies.
7.2.1.3 Parallel to Serial Converter
The Parallel to Serial Converter receives parallel 5B scrambled data from the scrambler and serializes it (converts it from a parallel to a serial data stream). The serialized data stream is then presented to the NRZ to NRZI encoder block
7.2.1.4 NRZ to NRZI Encoder
Since the transmit data stream has been scrambled and serialized, the data must be NRZI encoded for compatibility with the TP-PMD standard for 100Base-TX transmission over Category-5 unshielded twisted pair cable.
7.2.1.5 MLT-3 Converter
The MLT-3 conversion is accomplished by converting the data stream output from the NRZI encoder into two binary data streams with alternately phased logic one events.
7.2.1.6 MLT-3 Driver
The two binary data streams, created at the MLT-3 converter, are fed to the twisted pair output driver, which converts these streams to current sources and alternately drives either side of the transmit transformer’s primary winding, resulting in a minimal current MLT-3 signal. Refer to figure 7-4 for the block diagram of the MLT-3 converter.
Version: DM9161A-DS-P04 Jan.19, 2005 7.2.1.7 4B5B Code Group Symbol Meaning 4B code 3210 5B Code 43210 Data 0 0000 11110 Data 1 0001 01001 Data 2 0010 10100 Data 3 0011 10101 Data 4 0100 01010 Data 5 0101 01011 Data 6 0110 01110 Data 7 0111 01111 Data 8 1000 10010 Data 9 1001 10011 A Data A 1010 10110 B Data B 1011 10111 C Data C 1100 11010 D Data D 1101 11011 E Data E 1110 11100 F Data F 1111 11101 I Idle undefined 11111 J SFD (1) 0101 11000 K SFD (2) 0101 10001 T ESD (1) undefined 01101 R ESD (2) undefined 00111 H Error undefined 00100 V Invalid undefined 00000 V Invalid undefined 00001 V Invalid undefined 00010 V Invalid undefined 00011 V Invalid undefined 00101 V Invalid undefined 00110 V Invalid undefined 01000 V Invalid undefined 01100 V Invalid undefined 10000 V Invalid undefined 11001 Table 7-1
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Version: DM9161A-DS-P04 Jan.19,2005 Figure 7-4 7.2.2 100Base-TX Receiver The 100Base-TX receiver contains several function blocks that convert the scrambled 125Mb/s serial data to synchronous 4-bit nibble data, which is then provided to the MII. The receive section contains the following functional blocks: - Signal Detect - Adaptive Equalizer - MLT-3 to NRZI Decoder - Clock Recovery Module - NRZI to NRZ Decoder - Serial to Parallel - Descrambler - Code Group Alignment - 4B5B Decoder
7.2.2.1 Signal Detect
The signal detect function meets the specifications mandated by the ANSI XT12 TP-PMD 100Base-TX Standards for both voltage thresholds and timing parameters.
7.2.2.2 Adaptive Equalizer
When transmitting data at high speeds over copper twisted pair cable, attenuation based on frequency becomes a concern. In high speed twisted pair signaling, the frequency content of the transmitted signal can vary greatly during normal operation based on the randomness of the scrambled data stream. This variation in signal attenuation caused by frequency variations must be compensated for to ensure the integrity of the received data. In order to ensure quality transmission when employing MLT-3 encoding, the compensation must be able to adapt to various cable lengths and cable types depending on the installed environment. The selection of long cable lengths for a given implementation requires significant compensation, which will be over-kill in a situation that includes shorter, less attenuating cable lengths. Conversely, the selection of short or intermediate cable lengths requiring less compensation will cause serious under-compensation for longer length cables. Therefore, the compensation or equalization must be adaptive to ensure proper conditioning of the received signal independent of the cable length.
7.2.2.3 MLT-3 to NRZI Decoder
The DM9161A decodes the MLT-3 information from the Digital Adaptive Equalizer into NRZI data. The relation between NRZI and MLT-3 data is shown in figure 7-4.
7.2.2.4 Clock Recovery Module
The Clock Recovery Module accepts NRZI data from the MLT-3 to NRZI decoder. The Clock Recovery Module locks D CK Q Q Binary In Common driver Binary minus Binary plus MLT-3 MLT-3 Binary In
Version: DM9161A-DS-P04 Jan.19, 2005 onto the data stream and extracts the 125MHz reference clock. The extracted and synchronized clock and data are presented to the NRZI to NRZ Decoder.
7.2.2.5 NRZI to NRZ
The transmit data stream is required to be NRZI encoded in for compatibility with the TP-PMD standard for 100Base-TX transmission over Category-5 unshielded twisted pair cable. This conversion process must be reversed on the receive end. The NRZI to NRZ decoder, receives the NRZI data stream from the Clock Recovery Module and converts it to a NRZ data stream to be presented to the Serial to Parallel conversion block.
7.2.2.6 Serial to Parallel
The Serial to Parallel Converter receives a serial data stream from the NRZI to NRZ converter, and converts the data stream to parallel data to be presented to the descrambler.
7.2.2.7 Descrambler
Because the scrambling process requires to control the radiated emissions of transmit data streams, the receiver must descramble the receive data streams. The descrambler receives scrambled parallel data streams from the Serial to Parallel converter, descrambles the data streams, and presents the data streams to the Code Group alignment block.
7.2.2.8 Code Group Alignment
The Code Group Alignment block receives un-aligned 5B data from the descrambler and converts it into 5B code group data. Code Group Alignment occurs after the J/K is detected, and subsequent data is aligned on a fixed boundary. 7.2.2.9 4B5B Decoder The 4B5B Decoder functions as a look-up table that translates incoming 5B code groups into 4B (Nibble) data. When receiving a frame, the first 2 5-bit code groups received are the start-of-frame delimiter (J/K symbols). The J/K symbol pair is stripped and two nibbles of preamble pattern are substituted. The last two code groups are the end-of-frame delimiter (T/R symbols). The T/R symbol pair is also stripped from the nibble presented to the Reconciliation layer. 7.2.3 10Base-T Operation The 10Base-T transceiver is IEEE 802.3u compliant. When the DM9161A is operating in 10Base-T mode, the coding scheme is Manchester. Data processed for transmit is presented to the MII interface in nibble format, converted to a serial bit stream, then Manchester encoded. When receiving, the Manchester encoded bit stream is decoded and converted into nibble format for presentation to the MII interface.
7.2.4 Collision Detection
For half-duplex operation, a collision is detected when the transmit and receive channels are active simultaneously. When a collision has been detected, it will be reported by the COL signal on the MII interface. Collision detection is disabled in Full Duplex operation.
7.2.5 Carrier Sense
Carrier Sense (CRS) is asserted in half-duplex operation during transmission or reception of data. During full-duplex mode, CRS is asserted only during receive operations.
7.2.6 Auto-Negotiation
The objective of Auto-negotiation is to provide a means to exchange information between segment linked devices and to automatically configure both devices to take maximum advantage of their abilities. It is important to note that Auto-negotiation does not test the link segment characteristics. The Auto-Negotiation function provides a means for a device to advertise supported modes of operation to a remote link partner, acknowledge the receipt and understanding of common modes of operation, and to reject un-shared modes of operation. This allows devices on both ends of a segment to establish a link at the best common mode of operation. If more than one common mode exists between the two devices, a mechanism is provided to allow the devices to resolve to a single mode of operation using a predetermined priority resolution function.
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Version: DM9161A-DS-P04 Jan.19,2005 Auto-Negotiation (continued) Auto-negotiation also provides a parallel detection function for devices that do not support the Auto-negotiation feature. During Parallel detection there is no exchange of configuration information, instead, the receive signal is examined. If it is discovered that the signal matches a technology, supported by the receiving device, a connection will be automatically established using that technology. This allows devices, which do not support Auto-negotiation but support a common mode of operation, to establish a link.
7.2.7 MII Serial Management
The MII serial management interface consists of a data interface, basic register set, and a serial management interface to the register set. Through this interface it is possible to control and configure multiple PHY devices, get status and error information, and determine the type and capabilities of the attached PHY device(s). The DM9161A management functions correspond to MII specification for IEEE 802.3u-1995 (Clause 22) for registers 0 through 6 with vendor-specific registers 16,17, 18, 21, 22, 23 and 24. In read/write operation, the management data frame is 64-bits long and starts with 32 contiguous logic one bits (preamble) synchronization clock cycles on MDC. The Start of Frame Delimiter (SFD) is indicated by a <01> pattern followed by the operation code (OP):<10> indicates Read operation and <01> indicates Write operation. For read operation, a 2-bit turnaround (TA) filing between Register Address field and Data field is provided for MDIO to avoid contention. Following the turnaround time, 16-bit data is read from or written onto management registers.
7.2.8 Serial Management Interface
The serial control interface uses a simple two-wired serial interface to obtain and control the status of the physical layer through the MII interface. The serial control interface consists of MDC (Management Data Clock), and MDI/O (Management Data Input/Output) signals. The MDIO pin is bi-directional and may be shared by up to 32 devices.
7.2.9 Management Interface - Read Frame Structure
32 "1"s Z Idle Preamble SFD Op Code PHY Address Register Address Turn Around Data Idle Read Write MDC MDIO Read D15 D14
7.2.10 Management Interface - Write Frame Structure
32 "1"s D15 D14 Idle Preamble SFD Op Code PHY Address Register Address Turn Around Data Idle Write MDC MDIO Write Figure 7-5
Version: DM9161A-DS-P04 Jan.19, 2005
7.2.11 Power Reduced Mode
The Signal detect circuit is always turned on to monitor whether there is any signal on the media. In case of cable disconnection,, DM9161A will automatically turn off the power and enter the Power Reduced mode, regardless of its operation mode being N-way auto-negotiation or forced mode. While in the Power Reduced mode, the transmit circuit will continue sending out fast link pulse with minimum power consumption. If a valid signal is detected from the media, which might be N-way fast link pulse, 10Base-T normal link pules, or 100Base-TX MLT3 signals, the device wakes up and resumes normal operation mode. Automatic reduced power down mode can be disabled by writing Zero to Reg.16.4.
7.2.12 Power Down Mode
Power Down mode is entered by setting Reg.0.11 to ONE or pulling PWRDWN pin high, which disables all transmit and receive functions, and MII interface functions except the MDC/MDIO management interface.
7.2.13 Reduced Transmit Power Mode
Additional transmit power reduction can be gained by designing with 1.25:1 turns ration magnetic on its TX side and using a 8.5KΩ resistor on BGRES and BGRESG pins, and the TX+/TX- pulled high resistors being changed from 50Ω to 78Ω . This configuration could reduce about 20% of transmit power.
7.3 Auto MDIX Functional Description
The DM9161A supports the automatic detect cable connection type, MDI/MDIX (straight through/cross over). A manual configuration by register bit for MDI or MDIX is still accepted. When set to automatic, the polarity of MDI/MDIX controlled timing is generated by a 16-bits LFSR. The switching cycle time is located from 200ms to 420ms. The polarity control is always switch until detect received signal. After selected MDI or MDIX, the Pin 39 is used to enable Auto MDIX function. Pull pin 39 low will enable it, and pull pin 39 high will disable it. Specified config Register 20 bit 4 (20, 4) is used by programmer to disable Auto MDIX function. Write register 20 bit 4 to “ 1 “ will disable Auto MDIX function. Its default value is “ 0 “. When the register 20 bit 4 (20, 4) is set to “ 1 “, the register 20 bit 5(20, 5) is used to select straight through or cross over mode, “ 0 “ is for straight through, and “ 1 “ is for cross over. RX + /- from DM9161A RX+/- to RJ45 TX + /- from DM9161A TX+/- to RJ45 This feature is able to detect the required cable connection type.( straight through or crossed over ) and make correction automatically 8. MII Register Description
23 Preliminary
Version: DM9161A-DS-P04 Jan.19,2005 AD D Name Reset Loop back Speed select Auto-N Enable Power Down Isolate Restart Auto-N Full Duplex Coll. Test Reserved
00 CONTROL
000_0000 Cap. TX FDX Cap. TX HDX Cap.
10 FDX
Cap.
10 HDX
Cap. Reserved Pream. Supr. Auto-N Compl. Remote Fault Auto-N Cap. Link Status Jabber Detect Extd Cap. STATUS 0000 PHYID1 PHYID2 Model No. Version No. 01010 0000 04 Auto-Neg. Advertise Next Page FLP Rcv Ack Remote Fault Reserved FC Adv Adv TX FDX Adv TX HDX Adv Advertised Protocol Selector Field Link Part. Ability LP Next Page LP Ack LP RF Reserved LP FC LP LP TX FDX LP TX HDX LP Link Partner Protocol Selector Field 06 Auto-Neg. Expansion Reserved Pardet Fault LP Next Pg Able Next Pg Able New Pg Rcv LP AutoN Cap.
16 Specified
Config. BP 4B5B BP SCR BP ALIGN BP_ADP OK Repeater TX FEF_EN RMII_E N Force 100LNK TST_SE LEDCO L_SEL RPDCTR -EN Reset St. Mch Pream. Supr. Sleep mode Remote LoopOut
17 Specified
10 HDX Reserve
d Reverse d Reverse d PHY ADDR [4:0] Auto-N. Monitor Bit [3:0] 10T Conf/Stat Rsvd LP Enable HBE Enable SQUE Enable JAB Enable 10T Serial Reserved Polarity Reverse PWDOR Reserved PD10DR V PD100l PDchip PDcrm PDaeq PDdrv PDecli PDeclo PD10 Specified config TSTSE1 TSTSE2 FORCE_ TXSD FORCE_ FEF Reserved MDIX_C NTL AutoNeg _dlpbk Mdix_fix Value Mdix_do wn MonSel1 MonSel0 Rmii_acc u PD_valu e MDINTR Int_sts Reserve d Reserve d Reverse d Fdx_msk Spd_msk Lnk_msk Int_msk Reserve d Reserve d Reverse d Fdx_chg Spd_chg Lnk_chg Reserve d Int_sts RCVER Receiver Error Counter
23 DIS_connec
t Reversed Disconnect_counter RSTLH Lh_led_ mode Lh_mdint r Lh_cabst s Lh_isolat e Lh_rmii Lh_seril1 Lh_repea ter Lh_testm ode Lh_op2 Lh_op1 Lh_op0 Lh_phya Lh_phya Lh_phya Lh_phya Lh_phya Key to Default In the register description that follows, the default column takes the form: <Reset Value>, <Access Type> / <Attribute(s)> Where： <Reset Value>: Bit set to logic one Bit set to logic zero X No default value (PIN#) Value latched in from pin # at reset <Access Type>: RO = Read only RW = Read/Write <Attribute (s)>: SC = Self clearing P = Value permanently set LL = Latching low LH = Latching high
Version: DM9161A-DS-P04 Jan.19, 2005
8.1 Basic Mode Control Register (BMCR) - 00
0.15 Reset 0, RW/SC Reset 1=Software reset 0=Normal operation This bit sets the status and controls the PHY registers to their default states. This bit, which is self-clearing, will keep returning a value of one until the reset process is completed 0.14 Loopback 0, RW Loopback Loop-back control register 1 = Loop-back enabled 0 = Normal operation When in 100Mbps operation mode, setting this bit may cause the descrambler to lose synchronization and produce a 720ms "dead time" before any valid data appears at the MII receive outputs 0.13 Speed selection 1, RW Speed Select 1 = 100Mbps 0 = 10Mbps Link speed may be selected either by this bit or by auto-negotiation. When auto-negotiation is enabled and bit 12 is set, this bit will return auto-negotiation selected medium type 0.12 Auto-negotiation enable 1, RW Auto-negotiation Enable 1 = Auto-negotiation is enabled, bit 8 and 13 will be in auto-negotiation status 0.11 Power down 0, RW Power Down While in the power-down state, the PHY should respond to management transactions. During the transition to power-down state and while in the power-down state, the PHY should not generate spurious signals on the MII 1=Power down 0=Normal operation 0.10 Isolate 0,RW Isolate 1 = Isolates the DM9161A from the MII with the exception of the serial management. (When this bit is asserted, the DM9161A does not respond to the TXD [0:3], TX_EN, and TX_ER inputs, and it shall present a high impedance on its TX_CLK, RX_CLK, RX_DV, RX_ER, RXD[0:3], COL and CRS outputs. When PHY is isolated from the MII it shall respond to the management transactions) 0 = Normal operation 0.9 Restart Auto-negotiation 0,RW/SC Restart Auto-negotiation 1 = Restart auto-negotiation. Re-initiates the auto-negotiation process. When auto-negotiation is disabled (bit 12 of this register cleared), this bit has no function and it should be cleared. This bit is self-clearing and it will keep returning to a value of 1 until auto-negotiation is initiated by the DM9161A. The operation of the auto-negotiation process will not be affected by the management entity that clears this bit 0 = Normal operation
25 Preliminary
Version: DM9161A-DS-P04 Jan.19,2005 0.8 Duplex mode 1,RW Duplex Mode 1 = Full duplex operation. Duplex selection is allowed when Auto-negotiation is disabled (bit 12 of this register is cleared). With auto-negotiation enabled, this bit reflects the duplex capability selected by auto-negotiation 0 = Normal operation 0.7 Collision test 0,RW Collision Test 1 = Collision test enabled. When set, this bit will cause the COL signal to be asserted in response to the assertion of TX_EN 0 = Normal operation 0.6-0.0 Reserved 0,RO Reserved Read as 0, ignore on write
8.2 Basic Mode Status Register (BMSR) - 01
1.15 100BASE-T4 0,RO/P 100BASE-T4 Capable 1 = DM9161A is able to perform in 100BASE-T4 mode 0 = DM9161A is not able to perform in 100BASE-T4 mode 1.14 100BASE-TX full-duplex 1,RO/P 100BASE-TX Full Duplex Capable 1 = DM9161A is able to perform 100BASE-TX in full duplex mode 0 = DM9161A is not able to perform 100BASE-TX in full duplex mode 1.13 100BASE-TX half-duplex 1,RO/P 100BASE-TX Half Duplex Capable 1 = DM9161A is able to perform 100BASE-TX in half duplex mode 0 = DM9161A is not able to perform 100BASE-TX in half duplex mode 1.12 10BASE-T full-duplex 1,RO/P 10BASE-T Full Duplex Capable 1 = DM9161A is able to perform 10BASE-T in full duplex mode 0 = DM9161A is not able to perform 10BASE-TX in full duplex mode 1.11 10BASE-T half-duplex 1,RO/P 10BASE-T Half Duplex Capable 1 = DM9161A is able to perform 10BASE-T in half duplex mode 0 = DM9161A is not able to perform 10BASE-T in half duplex mode 1.10-1.7 Reserved 0,RO Reserved Read as 0, ignore on write 1.6 MF preamble suppression 1,RO MII Frame Preamble Suppression 1 = PHY will accept management frames with preamble suppressed 0 = PHY will not accept management frames with preamble suppressed 1.5 Auto-negotiation Complete 0,RO Auto-negotiation Complete 1 = Auto-negotiation process completed 0 = Auto-negotiation process not completed 1.4 Remote fault 0, RO/LH Remote Fault 1 = Remote fault condition detected (cleared on read or by a chip reset). Fault criteria and detection method is DM9161A implementation specific. This bit will set after the RF bit in the ANLPAR (bit 13, register address 05) is set 0 = No remote fault condition detected 1.3 Auto-negotiation ability 1,RO/P Auto Configuration Ability 1 = DM9161A is able to perform auto-negotiation 0 = DM9161A is not able to perform auto-negotiation 1.2 Link status 0,RO/LL Link Status 1 = Valid link is established (for either 10Mbps or 100Mbps operation)
Version: DM9161A-DS-P04 Jan.19, 2005 0 = Link is not established The link status bit is implemented with a latching function, so that the occurrence of a link failure condition causes the link status bit to be cleared and remain cleared until it is read via the management interface 1.1 Jabber detect 0, RO/LH Jabber Detect 1 = Jabber condition detected 0 = No jabber This bit is implemented with a latching function. Jabber conditions will set this bit unless it is cleared by a read to this register through a management interface or a DM9161A reset. This bit works only in 10Mbps mode 1.0 Extended capability 1,RO/P Extended Capability 1 = Extended register capable 0 = Basic register capable only
8.3 PHY ID Identifier Register #1 (PHYID1) - 02
The PHY Identifier Registers #1 and #2 work together in a single identifier of the DM9161A. The Identifier consists of a concatenation of the Organizationally Unique Identifier (OUI), a vendor's model number, and a model revision number. DAVICOM Semiconductor's IEEE assigned OUI is 00606E. Bit Bit Name Default 2.15-2.0 OUI_MSB <0180h> OUI Most Significant Bits This register stores bit 3 to 18 of the OUI (00606E) to bit 15 to 0 of this register respectively. The most significant two bits of the OUI are ignored (the IEEE standard refers to these as bit 1 and 2)
8.4 PHY ID Identifier Register #2 (PHYID2) - 03
3.15-3.10 OUI_LSB <101110>, RO/P OUI Least Significant Bits Bit 19 to 24 of the OUI (00606E) are mapped to bit 15 to 10 of this register respectively 3.9-3.4 VNDR_MDL <001010>, RO/P Vendor Model Number Five bits of vendor model number mapped to bit 9 to 4 (most significant bit to bit 9) 3.3-3.0 MDL_REV <0000>, RO/P Model Revision Number Five bits of vendor model revision number mapped to bit 3 to 0 (most significant bit to bit 4)
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Version: DM9161A-DS-P04 Jan.19,2005
8.5 Auto-negotiation Advertisement Register (ANAR) - 04
This register contains the advertised abilities of this DM9161A device as they will be transmitted to its link partner during Auto-negotiation. Bit Bit Name Default 4.15 NP 0,RO/P Next page Indication 0 = No next page available 1 = Next page available The DM9161A has no next page, so this bit is permanently set to 0 4.14 ACK 0,RO Acknowledge 1 = Link partner ability data reception acknowledged 0 = Not acknowledged The DM9161A's auto-negotiation state machine will automatically control this bit in the outgoing FLP bursts and set it at the appropriate time during the auto-negotiation process. Software should not attempt to write to this bit. 4.13 RF 0, RW Remote Fault 1 = Local device senses a fault condition 0 = No fault detected 4.12-4.11 Reserved X, RW Reserved Write as 0, ignore on read 4.10 FCS 0, RW Flow Control Support 1 = Controller chip supports flow control ability 0 = Controller chip doesn’t support flow control ability 4.9 0, RO/P 100BASE-T4 Support 1 = 100BASE-T4 is supported by the local device 0 = 100BASE-T4 is not supported The DM9161A does not support 100BASE-T4 so this bit is permanently set to 0 4.8 TX_FDX 1, RW 100BASE-TX Full Duplex Support 1 = 100BASE-TX full duplex is supported by the local device 0 = 100BASE-TX full duplex is not supported 4.7 TX_HDX 1, RW 100BASE-TX Support 1 = 100BASE-TX half duplex is supported by the local device 0 = 100BASE-TX half duplex is not supported 4.6 10_FDX 1, RW 10BASE-T Full Duplex Support 1 = 10BASE-T full duplex is supported by the local device 0 = 10BASE-T full duplex is not supported 4.5 10_HDX 1, RW 10BASE-T Support 1 = 10BASE-T half duplex is supported by the local device 0 = 10BASE-T half duplex is not supported 4.4-4.0 Selector <00001>, RW Protocol Selection Bits These bits contain the binary encoded protocol selector supported by this node <00001> indicates that this device supports IEEE 802.3 CSMA/CD
Version: DM9161A-DS-P04 Jan.19, 2005
8.6 Auto-negotiation Link Partner Ability Register (ANLPAR) – 05
This register contains the advertised abilities of the link partner when received during Auto-negotiation. Bit Bit Name Default 5.15 NP 0, RO Next Page Indication 0 = Link partner, no next page available 1 = Link partner, next page available 5.14 ACK 0, RO Acknowledge 1 = Link partner ability data reception acknowledged 0 = Not acknowledged The DM9161A's auto-negotiation state machine will automatically control this bit from the incoming FLP bursts. Software should not attempt to write to this bit 5.13 RF 0, RO Remote Fault 1 = Remote fault indicated by link partner 0 = No remote fault indicated by link partner 5.12-5.11 Reserved 0, RO Reserved Read as 0, ignore on write 5.10 FCS 0, RO Flow Control Support 1 = Controller chip supports flow control ability by link partner 0 = Controller chip doesn’t support flow control ability by link partner 5.9 0, RO 100BASE-T4 Support 1 = 100BASE-T4 is supported by the link partner 0 = 100BASE-T4 is not supported by the link partner 5.8 TX_FDX 0, RO 100BASE-TX Full Duplex Support 1 = 100BASE-TX full duplex is supported by the link partner 0 = 100BASE-TX full duplex is not supported by the link partner 5.7 TX_HDX 0, RO 100BASE-TX Support 1 = 100BASE-TX half duplex is supported by the link partner 0 = 100BASE-TX half duplex is not supported by the link partner 5.6 10_FDX 0, RO 10BASE-T Full Duplex Support 1 = 10BASE-T full duplex is supported by the link partner 0 = 10BASE-T full duplex is not supported by the link partner 5.5 10_HDX 0, RO 10BASE-T Support 1 = 10BASE-T half duplex is supported by the link partner 0 = 10BASE-T half duplex is not supported by the link partner 5.4-5.0 Selector <00000>, RO Protocol Selection Bits Link partner’s binary encoded protocol selector
29 Preliminary
Version: DM9161A-DS-P04 Jan.19,2005
8.7 Auto-negotiation Expansion Register (ANER)- 06
6.15-6.5 Reserved 0, RO Reserved Read as 0, ignore on write 6.4 PDF 0, RO/LH Local Device Parallel Detection Fault PDF = 1: A fault detected via parallel detection function. PDF = 0: No fault detected via parallel detection function 6.3 LP_NP_ABLE 0, RO Link Partner Next Page Able LP_NP_ABLE = 1: Link partner, next page available LP_NP_ABLE = 0: Link partner, no next page 6.2 NP_ABLE 0,RO/P Local Device Next Page Able NP_ABLE = 1: DM9161A, next page available NP_ABLE = 0: DM9161A, no next page DM9161A does not support this function, so this bit is always 0 6.1 PAGE_RX 0, RO/LH New Page Received A new link code word page received. This bit will be automatically cleared when the register (register 6) is read by management 6.0 LP_AN_ABLE 0, RO Link Partner Auto-negotiation Able A “1” in this bit indicates that the link partner supports Auto-negotiation
8.8 DAVICOM Specified Configuration Register (DSCR) - 16
16.15 BP_4B5B 0,RW Bypass 4B5B Encoding and 5B4B Decoding 1 = 4B5B encoder and 5B4B decoder function bypassed 0 = Normal 4B5B and 5B4B operation 16.14 BP_SCR 0, RW Bypass Scrambler/Descrambler Function 1 = Scrambler and descrambler function bypassed 0 = Normal scrambler and descrambler operation 16.13 BP_ALIGN 0, RW Bypass Symbol Alignment Function 1 = Receive functions (descrambler, symbol alignment and symbol decoding functions) bypassed. Transmit functions (symbol encoder and scrambler) bypassed 0 = Normal operation 16.12 BP_ADPOK 1, RW BYPASS ADPOK Force signal detector (SD) active. This register is for debug only, not release to customer 1=Forced SD is OK, 0=Normal operation 16.11 REPEATER (Pin#38),RW Repeater/Node Mode The value of the Repeater/Node pin (38) is latched into this bit at power-up/reset 1 = Repeater mode 0 = Node mode 16.10 TX 1, RW 100BASE-TX Mode Control 1 = 100BASE-TX operation 16.9 Reserved 1, RO Reserved 16.8 RMII_Enable (Pin#36), RW Reduced MII Enable Select normal MII or reduced MII. The value of the RMII pin(36) is
Version: DM9161A-DS-P04 Jan.19, 2005 latched into this bit at power-up/reset 0 = Normal MII 1 = Enable Reduced MII 16.7 F_LINK_100 0, RW Force Good Link in 100Mbps 0 = Normal 100Mbps operation 1 = Force 100Mbps good link status This bit is useful for diagnostic purposes 16.6 SPLED_CTL 0, RW Speed LED Disable 0 = Normal SPEEDLED output to indicate speed status 1 = Disable SPEEDLED output and enable SD signal monitor (for internal debug). When this bit is set, it controls the SPEEDLED as 100BASE-X SD signal output .For debug only 16.5 COLLED_CTL 0, RW Collision LED Enable 0 = FDX/COLLED output is configured to indicate Full/half duplex status 1 = FDX/COLLED output is configured to indicate Full-duplex/Collision status 16.4 RPDCTR-EN 1, RW Reduced Power Down Control Enable This bit is used to enable automatic reduced power down 0 = Disable automatic reduced power down 1 = Enable automatic reduced power down 16.3 SMRST 0, RW Reset State Machine When writes 1 to this bit, all state machines of PHY will be reset. This bit is self-clear after reset is completed 16.2 MFPSC 1, RW MF Preamble Suppression Control MII frame preamble suppression control bit 1 = MF preamble suppression bit on 0 = MF preamble suppression bit off 16.1 SLEEP 0, RW Sleep Mode Writing a 1 to this bit will cause PHY entering the Sleep mode and power down all circuit except oscillator and clock generator circuit. When waking up from Sleep mode (write this bit to 0), the configuration will go back to the state before sleep; but the state machine will be reset 16.0 RLOUT 0, RW Remote Loopout Control When this bit is set to 1, the received data will loop out to the transmit channel. This is useful for bit error rate testing
31 Preliminary
Version: DM9161A-DS-P04 Jan.19,2005
8.9 DAVICOM Specified Configuration and Status Register (DSCSR) - 17
17.15 100FDX 1, RO 100M Full Duplex Operation Mode After auto-negotiation is completed, results will be written to this bit. If this bit is 1, it means the operation 1 mode is a 100M full duplex mode. The software can read bit [15:12] to see which mode is selected after auto-negotiation. This bit is invalid when it is not in the auto-negotiation mode 17.14 100HDX 1, RO 100M Half Duplex Operation Mode After auto-negotiation is completed, results will be written to this bit. If this bit is 1, it means the operation 1 mode is a 100M half duplex mode. The software can read bit [15:12] to see which mode is selected after auto-negotiation. This bit is invalid when it is not in the auto-negotiation mode 17.13 10FDX 1, RO 10M Full Duplex Operation Mode After auto-negotiation is completed, results will be written to this bit. If this bit is 1, it means the operation 1 mode is a 10M Full Duplex mode. The software can read bit [15:12] to see which mode is selected after auto-negotiation. This bit is invalid when it is not in the auto-negotiation mode 17.12 10HDX 1, RO 10M Half Duplex Operation Mode After auto-negotiation is completed, results will be written to this bit. If this bit is 1, it means the operation 1 mode is a 10M half duplex mode. The software can read bit [15:12] to see which mode is selected after auto-negotiation. This bit is invalid when it is not in the auto-negotiation mode 17.11-17. Reserved 0, RO Reserved Read as 0, ignore on write 17.8-17.4 PHYADR[4 :0] (PHYADR), RW PHY Address Bit 4:0 The first PHY address bit transmitted or received is the MSB of the address (bit 4). A station management entity connected to multiple PHY entities must know the appropriate address of each PHY 0, RO Auto-negotiation Monitor Bits These bits are for debug only. The auto-negotiation status will be written to these bits 0, RO Auto-negotiation Monitor Bits These bits are for debug only.The auto-negotiation status will be written to these bits. In IDLE state Ability match Acknowledge match Acknowledge match fail Consistency match Consistency match fail Parallel detects signal_link_ready Parallel detects signal_link_ready fail 8.10 10BASE-T Configuration/Status (10BTCSR) - 18
Version: DM9161A-DS-P04 Jan.19, 2005 Bit Bit Name Default 18.15 Reserved 0, RO Reserved Read as 0, ignore on write 18.14 LP_EN 1, RW Link Pulse Enable 1 = Transmission of link pulses enabled 0 = Link pulses disabled, good link condition forced This bit is valid only in 10Mbps operation 18.13 HBE 1,RW Heartbeat Enable 1 = Heartbeat function enabled 0 = Heartbeat function disabled When the DM9161A is configured for full duplex operation, this bit will be ignored (the collision/heartbeat function is invalid in full duplex mode) 18.12 SQUELCH 1, RW Squelch Enable 1 = Normal squelch 0 = Low squelch 18.11 JABEN 1, RW Jabber Enable Enables or disables the Jabber function when the DM9161A is in 10BASE-T full duplex or 10BASE-T transceiver loopback mode 1 = Jabber function enabled 0 = Jabber function disabled 18.10 10BT_SER (#PIN 34),RW 10BASE-T GPSI Mode ( Default value depend on #pin34 strap condition) 1 = 10BASE-T GPSI mode selected (#pin34 pull down) 0 = 10BASE-T MII mode selected (#pin34 pull up, default) GPSI mode is not supported for 100Mbps operation 18.9-18.1 Reserved 0, RO Reserved Read as 0, ignore on write 18.0 POLR 0, RO Polarity Reversed When this bit is set to 1, it indicates that the 10Mbps cable polarity is reversed. This bit is automatically set and cleared by 10BASE-T module
8.11 Power Down Control Register (PWDOR) - 19
19.15-19.9 Reserved 0, RO Reserved Read as 0, ignore on write 19.8 PD10DRV 0, RW Vendor powerdown control test 19.7 PD100DL 0, RW Vendor powerdown control test 19.6 PDchip 0, RW Vendor powerdown control test 19.5 PDcom 0, RW Vendor powerdown control test 19.4 PDaeq 0, RW Vendor powerdown control test 19.3 PDdrv 0, RW Vendor powerdown control test 19.2 PDedi 0, RW Vendor powerdown control test 19.1 PDedo 0, RW Vendor powerdown control test 19.0 PD10 0, RW Vendor powerdown control test * when selected , the powerdown value is control by Register 20.0 8.12 (Specified config) Register – 20 Bit Bit Name Default 20.15 TSTSE1 0,RW Vendor test select control 20.14 TSTSE2 0,RW Vendor test select control 20.13 FORCE_TXSD 0,RW Force Signal Detect
33 Preliminary
Version: DM9161A-DS-P04 Jan.19,2005 1: force SD signal OK in 100M 0: normal SD singal. 20.12 TSTSEL3 0,RW Vendor test select control 20.11-20. Reserved 0, RO Reserved Read as 0, ignore on write 20.7 MDIX_CNTL MDI/MDIX,RO The polarity of MDI/MDIX value 1: MDIX mode 0: MDI mode 20.6 AutoNeg_dpbk 0,RW Auto-negotiation loopback 1: test internal digital auto-negotiation loopback 0: normal. 20.5 Mdix_fix Value 0, RW MDIX_CNTL force value: When MDIX_DOWN = 1, MDIX_CNTL value depend on the register value. 20.4 Mdix_do wn 0,RW MDIX Down Manual force MDI/MDIX. 0: Enable auto MDI/MDIX 1: Disable auto MDI/MDIX, MDIX_CNTL value depend on 20.5 20.3 MonSel1 0,RW Vendor monitor select 20.2 MonSel0 0,RW Vendor monitor select 20.1 RMII_Ver 0,RW RMII version 0: support RMII 1.2 1: support RMII 1.0 20.0 PD_value 0,RW Powerdown control value Decision the value of each field Register 19. 1: powerdown 0: normal
8.13 DAVICOM Specified Interrupt Register – 21
21.15 INTR PEND 0, RO Interrupt Pending Indicates that the interrupt is pending and is cleared by the current read. This bit shows the same result as bit 0. (INTR Status) 21.14-21. Reserved 0, RO Reserved 21.11 FDX mask 1, RW Full-duplex Interrupt Mask When this bit is set, the Duplex status change will not generate the interrupt 21.10 SPD mask 1, RW Speed Interrupt Mask When this bit is set, the Speed status change will not generate the interrupt 21.12 LINK mask 1, RW Link Interrupt Mask When this bit is set, the link status change will not generate the interrupt 21.8 INTR mask 1, RW Master Interrupt Mask When this bit is set, no interrupts will be generated under any condition 21.7-21.5 Reserved 0, RO Reserved 21.4 FDX change 0,RO/LH Duplex Status Change Interrupt “1” indicates a change of duplex since last register read. A read of this register will clear this bit 21.3 SPD change 0, RO/LH Speed Status Change Interrupt
Version: DM9161A-DS-P04 Jan.19, 2005 “1” indicates a change of speed since last register read. A read of this register will clear this bit 21.2 LINK change 0, RO/LH Link Status Change Interrupt “1” indicates a change of link since last register read. A read of this register will clear this bit 21.1 Reserved 0, RO Reserved 21.0 INTR status 0, RO/LH Interrupt Status The status of MDINTR#. “1” indicates that the interrupt mask is off that one or more of the change bits are set. A read of this register will clear this bit
8.14 DAVICOM Specified Receive Error Counter Register (RECR) – 22
22.15-0 Rcv_ Err_ Cnt 0, RO Receive Error Counter Receive error counter that increments upon detection of RXER. Clean by read this register.
8.15 DAVICOM Specified Disconnect Counter Register (DISCR) – 23
23.15-23. Reserved 0, RO Reserved 23.7-23.0 Disconnect Counter 0, RO Disconnect Counter that increments upon detection of disconnection. Clean by read this register.
35 Preliminary
Version: DM9161A-DS-P04 Jan.19,2005
8.16 DAVICOM Hardware Reset Latch State Register (RLSR) – 24
LH_LEDMODE LEDMODE pin reset latch value LH_MDINTR MDINTR pin reset latch value LH_CSTS CABLESTS pin reset latch value LH_ISO TXCLK pin reset latch value LH_RMII COL pin reset latch value LH_TP10SER RXCLK pin reset latch value LH_REPTR RXER pin reset latch value LH_TSTMOD RXDV pin reset latch value LH_OP2 LED2 pin reset latch value LH_OP1 LED1 pin reset latch value LH_OP0 LED0 pin reset latch value LH_PH4 CRS pin reset latch value LH_PH3 RXD3 pin reset latch value LH_PH2 RXD2 pin reset latch value LH_PH1 RXD1 pin reset latch value LH_PH0 RXD0 pin reset latch value
Version: DM9161A-DS-P04 Jan.19, 2005 9. DC and AC Electrical Characteristics
9.1 Absolute Maximum Ratings ( 25°C )
Min. Max. Unit Conditions DVDD, Supply Voltage -0.3 3.6 V VIN DC Input Voltage (VIN) -0.5 5.5 V VOUT DC Output Voltage(VOUT) -0.3 3.6 V Tstg Storage Temperature Rang (Tstg) -65 +150 Tc Case Temperature LT Lead Temp. (TL, Soldering, 10 sec.) 235
9.2 Operating Conditions
Min. Max. Unit Conditions DVDD Supply Voltage 3.135 3.465 V TA Ambient Temperature Tc Case Temperature As TA = 70°C 100BASE-TX mA 3.3V 10BASE-T TX, normal activity traffic 50% utility. mA 3.3V 10BASE-T idle mA 3.3V Auto-negotiation mA 3.3V Power Reduced Mode (without cable ) mA 3.3V PD (Power Dissipation) Power Down Mode 3.8 mA 3.3V Comments Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated that in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
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Version: DM9161A-DS-P04 Jan.19,2005 9.3 DC Electrical Characteristics (DVDD = 3.3V) Symbol Parameter Min. Typ. Max. Unit Conditions TTL Inputs (TXD0~TXD3, TXCLK, MDC, MDIO, TXEN, TXER, RXEN, TESTMODE, RMII, PHYAD0~4, OPMODE0-2, RPTR, RESET# ) VIL Input Low Voltage 0.8 V VIH Input High Voltage 2.0 V IIL Input Low Leakage Current uA VIN = 0.4V IIH Input High Leakage Current uA VIN = 2.7V VOL Output Low Voltage 0.4 V IOL = 4mA VOH Output High Voltage 2.4 V IOH = -4mA Receiver VICM RX+/RX- Common mode Input Voltage 1.05 V 100 Ω Termination Across Transmitter VTD100 100TX+/- Differential Output Voltage 1.9 2.0 2.1 V Peak to Peak VTD10 10TX+/- Differential Output Voltage 4.4 5.6 V Peak to Peak ITD100 100TX+/- Differential Output Current │19│ │20│ │21│ mA ITD10 10TX+/- Differential Output Current │44│ │50│ │56│ mA
9.4 AC Electrical Characteristics & Timing Waveforms
9.4.1 TP Interface
Min. Typ. Max. Unit Conditions tTR/F 100TX+/- Differential Rise/Fall Time 3.0 5.0 ns tTM 100TX+/- Differential Rise/Fall Time Mismatch 0.5 ns tTDC 100TX+/- Differential Output Duty Cycle Distortion 0.5 ns tT/T 100TX+/- Differential Output Peak-to-Peak Jitter 1.4 ns XOST 100TX+/- Differential Voltage Overshoot
9.4.2 Oscillator/Crystal Timing
Min. Typ. Max. Unit Conditions OSC Frag 24.998 25.001 mhz 50ppm tCKC OSC Cycle Time 39.998 40.002 ns 50ppm tPWH OSC Pulse Width High ns tPWL OSC Pulse Width Low ns
Version: DM9161A-DS-P04 Jan.19, 2005
9.4.3 MDC/MDIO Timing
Min. Typ. Max. Unit Conditions MDC Cycle Time ns MDIO Setup Before MDC ns When OUTPUT By STA MDIO Hold After MDC ns When OUTPUT By STA MDC To MDIO Output Delay 300 ns When OUTPUT By DM9161A
9.4.4 MDIO Timing When OUTPUT by STA
(Min) 10ns (Min)
9.4.5 MDIO Timing When OUTPUT by DM9161A
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Version: DM9161A-DS-P04 Jan.19,2005 9.4.6 100BASE-TX Transmit Timing Parameters Symbol Parameter Min. Typ. Max. Unit Conditions tTXc TXCLK Cycle Time 39.998 40.002 ns 50ppm tTXh, tTXl TXCLK High/Low Time ns tTXs TXD [0:3], TXEN, TXER Setup To TXCLK High ns tTXh TXD [0:3], TXEN, TXER Hold From TXCLK High ns tTXOD TXCLK to Output Delay ns TXEN Sampled To CRS Asserted BT TXEN Sampled To CRS De-asserted BT tTXpd TXEN Sampled To TX+/- Out (Tx Latency) BT tTXr/f 100TX Driver Rise/Fall Time ns 90% To 10%, Into 100ohm Differential Note 1. Typical values are at 25℃and are for design aid only; not guaranteed and not subject to production testing. 9.4.7 100BASE-TX Transmit Timing Diagram TXCLK tTXh tTXS tTXpd tTXr/f TXD [0:3], TXEN, TXER CRS 100TX+/- tTXc tTXh tTXOD 9.4.8 100BASE-TX Receive Timing Parameters Symbol Parameter Min. Typ. Max. Unit Conditions tRXc RXCLK Cycle Time 39.998 40.002 50ppm TRXh, tRXl RXCLK High/Low Time tRXs RXD [0:3], RXDV, RXER Setup To RXCLK High ns tRXh RXD [0:3], RXDV, RXER Hold From RXCLK High ns tRXpd RX+/- In To RXD [0:3] Out (Rx Latency) BT CRS Asserted To RXD [0:3], RXDV, RXER BT CRS De-asserted To RXD [0:3], RXDV, RXER BT RX+/- In To CRS Asserted BT RX+/- Quiet To CRS De-asserted BT RX+/- In To COL De-Asserted BT 1. Typical values are at 25℃and are for design aid only; not guaranteed and not subject to production testing.
Version: DM9161A-DS-P04 Jan.19, 2005
9.4.9 MII 100BASE-TX Receive Timing Diagram
RXD [0:3], RXDV, RXER CRS RX+/- tRXS tRXh COL tRXc tRXh
9.4.10 MII 10BASE-T Nibble Transmit Timing Parameters
Min. Typ. Max. Unit Conditions tTXs TXD[0:3), TXEN, TXER Setup To TXCLK High ns tTXh TXD[0:3], TXEN, TXER Hold From TXCLK High ns TXEN Sampled To CRS Asserted BT TXEN Sampled To CRS De-asserted BT tTXpd TXEN Sampled To 10TXO Out (Tx Latency) BT
9.4.11 MII 10BASE-T Nibble Transmit Timing Diagram
TXD [0:3], TXEN, TXER CRS 10TX+/-
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Version: DM9161A-DS-P04 Jan.19,2005
9.4.12 MII 10BASE-T Receive Nibble Timing Parameters
Min. Typ. Max. Unit Conditions tRXs RXD [0:3], RXDV, RXER Setup To RXCLK High ns tRXh RXD [0:3], RXDV, RXER Hold From RXCLK High ns tRXpd RX+/- To RXD [0:3] Out (Rx Latency) BT CRS Asserted To RXD [0:3], RXDV, RXER,Asserted BT CRS De-asserted To RXD [0:3], RXDV, RXER,De-asserted BT RXI In To CRS Asserted BT RXI Quiet To CRS De-asserted BT
9.4.13 MII 10BASE-T Receive Nibble Timing Diagram
RXD [0:3], RXDV, RXER CRS RX+/- tRXS tRXh
9.4.14 Auto-negotiation and Fast Link Pulse Timing Parameters
Min. Typ. Max. Unit Conditions Clock/Data Pulse Width 100 ns Clock Pulse To Data Pulse Period 55.5 62.5 69.5 us DATA = 1 Clock Pulse To Clock Pulse Period 111 125 139 us FLP Burst Width ms FLP Burst To FLP Burst Period ms Clock/Data Pulses in a Burst pulse
9.4.15 Auto-negotiation and Fast Link Pulse Timing Diagram
Version: DM9161A-DS-P04 Jan.19, 2005 FAST LINK PULSES Clock Pulse Data Pulse Clock Pulse FLP Burst FLP Burst FLP Bursts
9.4.16 RMII Receive Timing Diagram
100 Mb/s Reception with no errors
9.4.17 RMII Transmit Timing Diagram
100 Mb/s Transmission
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9.4.18 RMII Timing Diagram
9.4.19 RMII Timing Parameter
Min. Typ. Max. Unit Conditions Fref REF_CLK Frequency 49.9985 50.0015 MHz 30ppm (1.5KHZ) Tref% REF_CLK Duty Cycle Tref REF_CLK Clock Cycle ns 30ppm Tsu TXD[1:0], TX_EN, RXD[1:0], CRS_DV, RX_ER Data Setup to REF_CLK rising edge ns Thold TXD[1:0], TX_EN, RXD[1:0], CRS_DV, RX_ER Data hold from REF_CLK rising edge ns TXD[1:0], TX_EN, RXD[1:0], CRS_DV, RX_ER REF_CLK Tsu Thold TREF
Version: DM9161A-DS-P04 Jan.19, 2005 10. Package Information LQFP 48L (F.P. 2mm) Outline Dimensions unit: inches/mm y Symbol Dimensions in inches Dimensions in mm Min. Nom. Max. Min. Nom. Max. A 0.063 1.60 0.002 0.006 0.05 0.15 0.053 0.055 0.057 1.35 1.40 1.45 b 0.007 0.009 0.011 0.17 0.22 0.27 0.007 0.008 0.009 0.17 0.20 0.23 C 0.004 0.008 0.09 0.20 0.004 0.006 0.09 0.16 D 0.354BSC 9.00BSC 0.276BSC 7.00BSC E 0.354BSC 9.00BSC 0.276BSC 7.00BSC e 0.020BSC 0.50BSC L 0.018 0.024 0.030 0.45 0.60 0.75 0.039REF 1.00REF y 0.003MAX 0.08MAX Notes: 1. To be determined at seating plane. 2. Dimensions D1 and E 1do not include mold protrusion. D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Dimensions b does not include dambar protrusion. Total in excess of the b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. 4. Exact shape of each corner is optional. 5. These dimensions apply to the flat section of the lead between 0.10mm and 0.25mm from the lead tip. 6. A1 is defined as the distance from the seating plane to the lowest point of the package body. 7. Controlling dimension: millimeter. 8. Reference documents: JEDEC MS-026, BBC. Θ 0-12° 0-12°
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Version: DM9161A-DS-P04 Jan.19,2005 11. Order Information Part Number Pin Count Package DM9161AE LQFP Disclaimer The information appearing in this publication is believed to be accurate. Integrated circuits sold by DAVICOM Semiconductor are covered by the warranty and patent indemnification, and the provisions stipulated in the terms of sale only. DAVICOM makes no warranty, express, statutory, implied or by description, regarding the information in this publication or regarding the freedom of the described chip(s) from patent infringement. FURTHER, DAVICOM MAKES NO WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. DAVICOM reserves the right to halt production or alter the specifications and prices at any time without notice. Accordingly, the reader is cautioned to verify that the data sheets and other information in this publication are current before placing orders. Products described herein are intended for use in normal commercial applications. Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical life support equipment, are specifically not recommended without additional processing by DAVICOM for such applications. Please note that application circuits illustrated in this document are for reference purposes only. DAVICOM‘s terms and conditions printed on the order acknowledgment govern all sales by DAVICOM. DAVICOM will not be bound by any terms inconsistent with these unless DAVICOM agrees otherwise in writing. Acceptance of the buyer’s orders shall be based on these terms. Company Overview DAVICOM Semiconductor, Inc. develops and manufactures integrated circuits for integration into data communication products. Our mission is to design and produce IC products that are the industry’s best value for Data, Audio, Video, and Internet/Intranet applications. To achieve this goal, we have built an organization that is able to develop chipsets in response to the evolving technology requirements of our customers while still delivering products that meet their cost requirements. Products We offer only products that satisfy high performance requirements and which are compatible with major hardware and software standards. Our currently available and soon to be released products are based on our proprietary designs and deliver high quality, high performance chipsets that comply with modem communication standards and Ethernet networking standards. Contact Windows For additional information about DAVICOM products, contact the sales department at: Headquarters Hsin-chu Office: No.6 Li-Hsin Rd. VI, Science-Based Industrial Park, Hsin-Chu, Taiwan, R.O.C. [Tel] +886-3-5798797 [Fax] +886-3-6669831 WARNING Conditions beyond those listed for the absolute maximum may destroy or damage the products. In addition, conditions for sustained periods at near the limits of the operating ranges will stress and may temporarily (and permanently) affect and damage structure, performance and/or function.