Interface

DIX4192

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DIX4192 Integrated Digital Audio Interface Receiver and Transmitter REVISED SEPTEMBER 2016

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Online Datasheet

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DIX4192 Integrated Digital Audio Interface Receiver and Transmitter datasheet (Rev. F)

Document overview

Manufacturer or author: Texas Instruments, Incorporated [SBFS031,F]
PDF pages: 70

Technical content

Sample & Buy T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. DIX4192 SBFS031F –FEBRUARY 2006–REVISED SEPTEMBER 2016 DIX4192IntegratedDigitalAudioInterfaceReceiverandTransmitter

1 Features

1• Digital Audio Interface Transmitter (DIT) – Supports Sampling Rates Up to 216 kHz – Includes Differential Line Driver and CMOS-Buffered Outputs

Digital Audio Interface Receiver (DIR) – PLL Lock Range Includes Sampling Rates from 20 kHz to 216 kHz – Four Differential-Input Line Receivers and an Input Multiplexer – Bypass Multiplexer Routes Line Receiver Outputs to Line Driver and Buffer Outputs – Automatic Detection of Non-PCM Audio Streams (DTS CD/LD and IEC 61937 formats) – Audio CD Q-Channel Sub-Code Decoding and Data Buffer – Low Jitter Recovered Clock Output
User-Selectable Serial Host Interface: SPI™ or I2C – Provides Access to On-Chip Registers and Data Buffers – Status Registers and Interrupt Generation for Flag and Error Conditions – Block-Sized Data Buffers for Both Channel Status and User Data
Two Audio Serial Ports (Ports A and B) – Synchronous Serial Interface to External Signal Processors, Data Converters, and Logic – Slave or Master Mode Operation With Sampling Rates Up to 216 kHz – Supports Left-Justified, Right-Justified, and Philips I2S™ Data Formats – Supports Audio Data Word Lengths Up to

24 Bits

Four General-Purpose Digital Outputs – Multifunction Programmable Through Control Registers
Extensive Power-Down Support – Functional Blocks May Be Disabled Individually When Not In Use
Operates From 1.8-V Core and 3.3-V I/O Power Supplies
Small TQFP-48 Package, Compatible With the SRC4382 and SRC4392

2 Applications

Digital Audio Recorders and Mixing Desks
Digital Audio Interfaces for Computers
Digital Audio Routers and Distribution Systems
Broadcast Studio Equipment
DVD and CD Recorders
Surround Sound Decoders and A/V Receivers
Car Audio Systems

3 Description

The DIX4192 device is a highly-integrated CMOS device designed for use in professional and broadcast digital audio systems. The DIX4192 combines a digital audio interface receiver (DIR) and transmitter (DIT), two audio serial ports, and flexible distribution logic for interconnection of the function block data and clocks. The DIR and DIT are compatible with the AES3, S/PDIF, IEC 60958, and EIAJ CP-1201 interface standards. The audio serial ports and DIT may be operated at sampling rates up to 216 kHz. The DIR lock range includes sampling rates from 20 kHz to 216 kHz. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) DIX4192 TQFP (48) 7.00 mm × 7.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. DIX4192 Typical Application

13.3 Receiving Notification of Documentation Updates 61

14 Mechanical, Packaging, and Orderable

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision E (April 2016) to Revision F Page Changes from Revision D (January 2016) to Revision E Page Changes from Revision C (June 2006) to Revision D Page

Added ESD Ratings table, Feature Description section, Device Functional Modes section, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation

5 Description (continued)

The DIX4192 device is configured using on-chip control registers and data buffers, which are accessed through either a 4-wire serial peripheral interface (SPI) port, or a 2-wire Philips I2C bus interface. Status registers provide access to a variety of flag and error bits, which are derived from the various function blocks. An open-drain interrupt output pin is provided, and is supported by flexible interrupt reporting and mask options through control register settings. A master reset input pin is provided for initialization by a host processor or supervisory functions. The DIX4192 device requires a 1.8-V core logic supply, in addition to a 3.3-V supply for powering portions of the DIR, DIT, and line driver and receiver functions. A separate logic I/O supply supports operation from 1.65 V to 3.6 V, providing compatibility with low voltage logic interfaces typically found on digital signal processors and programmable logic devices. The DIX4192 device is available in a lead-free, TQFP-48 package, and is pin- and register-compatible with the Texas Instruments SRC4382 and SRC4392 products.

6 Device Comparison Table

PART NUMBER 1.8 V IO MULTI-CH PCM ADC PCM PORTS S/PDIF PORTS DIX4192 Yes No No 2 4 differential Line IN and 1 differential Line Out PCM9211 No Yes Yes Up to 3 IN and up to 3 Out Up to 12 single-ended IN and up to 2 single-ended Out DIX9211 No Yes No Up to 3 IN and up to 3 Out Up to 12 single-ended IN and up to 2 single-ended Out

BCKBLRCKBSDINBSDOUTBBGNDDGND3VIO NC SDOUT ASDINALRCKABCKA RXCKI NC NC DGND1VDD18 CPMCS/A0 CCLK/SCL CDIN/A1 CDOUT/SDA INT RST 1 1 RX1+ RX1- RX2+ RX2- RX3+ RX3- RX4+ RX4- VCC AGND LOCK RXCKO 48 47 46 45 44 43 42 41 40 39 38 13 14 15 16 17 18 19 20 21 22 23 DIX4192 SBFS031F –FEBRUARY 2006–REVISED SEPTEMBER 2016 www.ti.com Product Folder Links: DIX4192 Submit Documentation Feedback Copyright © 2006–2016, Texas Instruments Incorporated (1) I = Input, O = Output, PWR = Power, GND = Ground

7 Pin Configuration and Functions

TYPE(1) DESCRIPTION NAME NO. AESOUT 34 O DIT buffered AES3-encoded data AGND 10 GND DIR comparator and PLL power-supply ground BCKA 37 I/O Audio serial Port A bit clock BCKB 48 I/O Audio serial Port B bit clock BGND 44 GND Substrate ground, connect to AGND (pin 10) BLS 35 I/O DIT block start clock CCLK or SCL 20 I Serial data clock for SPI mode or I2C mode CDIN or A1 21 I SPI port serial data input or programmable slave address for I2C mode CDOUT or SDA 22 I/O SPI port serial data output (tri-state output) or serial data I/O for I2C mode CPM 18 I Control port mode, 0 = SPI mode, 1 = I2C mode CS or A0 19 I Chip select (active low) for SPI mode or programmable slave address for I2C mode DGND1 16 GND Digital core ground DGND2 30 GND DIR line receiver bias and DIT line driver digital ground DGND3 43 GND Logic I/O ground GPO1 26 O General-purpose output 1 GPO2 27 O General-purpose output 2 GPO3 28 O General-purpose output 3 GPO4 29 O General-purpose output 4

www.ti.com SBFS031F –FEBRUARY 2006–REVISED SEPTEMBER 2016 Product Folder Links: DIX4192 Submit Documentation FeedbackCopyright © 2006–2016, Texas Instruments Incorporated Pin Functions (continued) PIN TYPE(1) DESCRIPTION NAME NO. INT 23 O Interrupt flag (open-drain, active low) LOCK 11 O DIR PLL lock flag (active low) LRCKA 38 I/O Audio serial Port A Left/Right clock LRCKB 47 I/O Audio serial Port B left/right clock MCLK 25 I Master clock NC 14, 15, 41 — No internal signal connection, internally bonded to ESD pad RST 24 I Reset (active low) RX1+ 1 I Line receiver 1, noninverting input RX1– 2 I Line receiver 1, inverting input RX2+ 3 I Line receiver 2, noninverting input RX2– 4 I Line receiver 2, inverting input RX3+ 5 I Line receiver 3, noninverting input RX3– 6 I Line receiver 3, inverting input RX4+ 7 I Line receiver 4, noninverting input RX4– 8 I Line receiver 4, inverting input RXCKI 13 I DIR reference clock RXCKO 12 O DIR recovered master clock (tri-state output) SDINA 39 I Audio serial Port A data input SDINB 46 I Audio serial Port B data input SDOUTA 40 O Audio serial Port A data output SDOUTB 45 O Audio serial Port B data output SYNC 36 O DIT internal sync clock TX+ 32 O DIT line driver noninverting output TX– 31 O DIT line driver inverting output VCC 9 PWR DIR comparator and PLL power supply, 3.3-V nominal VDD18 17 PWR Digital core supply, 1.8-V nominal VDD33 33 PWR DIR line receiver bias and DIT line driver supply, 3.3-V nominal VIO 42 PWR Logic I/O supply, 1.65 V to 3.6 V (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Procedures. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

8 Specifications

8.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT Power supply VDD18 –0.3 2 V VDD33 –0.3 4 V VIO –0.3 4 V VCC –0.3 4 V Digital input voltage: digital logic RXCKI, CPM, CS, CCLK, CDIN, CDOUT, INT, RST, MCLK, BLS, SYNC, BCKA, BCKB, LRCKA, LRCKB, SDINA, SDINB –0.3 (VIO + 0.3) V Line receiver input voltage (per pin) RX1+, RX1–, RX2+, RX2–, RX3+, RX3–, RX4+, RX4– (VDD33 + 0.3) VPP Input current (all pins except power and ground) ±10 mA Ambient operating temperature –40 85 °C Storage temperature, Tstg –65 150 °C

SBFS031F –FEBRUARY 2006–REVISED SEPTEMBER 2016 www.ti.com Product Folder Links: DIX4192 Submit Documentation Feedback Copyright © 2006–2016, Texas Instruments Incorporated (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

8.2 ESD Ratings

V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2500 V Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1500

8.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT Supply voltage VDD18 1.65 1.8 1.95 V VDD33 3 3.3 3.6 V VIO 1.65 3.3 3.6 V VCC 3 3.3 3.6 V (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

8.4 Thermal Information

THERMAL METRIC(1) DIX4192 UNITPFB (TQFP)

48 PINS

RθJA Junction-to-ambient thermal resistance 62.0 °C/W RθJC(top) Junction-to-case (top) thermal resistance 12.8 °C/W RθJB Junction-to-board thermal resistance 27.9 °C/W ψJT Junction-to-top characterization parameter 0.3 °C/W ψJB Junction-to-board characterization parameter 27.6 °C/W

8.5 Electrical Characteristics

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DIGITAL I/O CHARACTERISTICS (ALL I/O PINS EXCEPT LINE RECEIVERS AND LINE DRIVER) VIH High-level input voltage 0.7 × VIO VIO V VIL Low-level input voltage 0 0.3 × VIO V IIH High-level input current IO = –4 mA, MUTE, SDINA, and SDINB pins 0.5 25 μA IO = –4 mA, all other pins 0.5 10 IIL Low-level input current IO = 4 mA 0.5 10 μA VOH High-level output voltage 0.8 × VIO VIO V VOL Low-level output voltage 0 0.2 × VIO V CIN Input capacitance 3 pF LINE RECEIVER INPUTS (RX1+, RX1–, RX2+, RX2–, RX3+, RX3–, RX4+, RX4–) VTH Differential input sensitivity Voltage across a given differential input pair 150 200 mV VHY Input hysteresis 150 mV LINE DRIVER OUTPUTS (TX+, TX–) VTXO Differential output voltage RL = 110 Ω Across TX+ and TX– 5.4 VPP MASTER CLOCK INPUT fMCLK Master clock input (MCLK) frequency 1 27.7 MHz fMCLKD Master clock input (MCLK) duty cycle 45% 55% DIGITAL AUDIO INTERFACE RECEIVER (DIR) PLL lock range TA = 25°C 20 216 kHz fRXCKI Reference clock input (RXCKI) frequency 3.5 27.7 MHz fRXCKID Reference clock input (RXCKI) duty cycle 45% 55% fRXCKO Recovered clock output (RXCKO) frequency 3.5 27.7 MHz

www.ti.com SBFS031F –FEBRUARY 2006–REVISED SEPTEMBER 2016 Product Folder Links: DIX4192 Submit Documentation FeedbackCopyright © 2006–2016, Texas Instruments Incorporated Electrical Characteristics (continued) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT (1) The typical VIO supply current is measured using the DIX4192EVM evaluation module with loading from the DAIMB mother-board circuitry. VIO supply current is dependent upon the loading on the logic output pins. fRXCKOD Recovered clock output (RXCKO) duty cycle 45% 55% Recovered clock output (RXCKO) intrinsic jitter Measured cycle-to-cycle 250 ps RMS DIGITAL AUDIO INTERFACE TRANSMITTER (DIT) Intrinsic output jitter Measured cycle-to-cycle 200 ps RMS POWER SUPPLIES Supply current: initial startup All blocks powered down by default IDD18S VDD18 = 1.8 V 10 μA IDD33S VDD33 = 3.3 V 10 μA IIOS VIO = 3.3 V 300 μA ICCS VCC = 3.3 V 10 μA Supply current: quiescent All blocks powered up with no clocks applied IDD18Q VDD18 = 1.8 V 2.3 mA IDD33Q VDD33 = 3.3 V 0.6 mA IIOQ VIO = 3.3 V 0.3 mA ICCQ VCC = 3.3 V 6.3 mA Supply current: dynamic All blocks powered up, fS = 48 kHz IDD18D VDD18 = 1.8 V 5.1 mA IDD33D VDD33 = 3.3 V 14.1 mA IIOD(1) VIO = 3.3 V 46 mA ICCD VCC = 3.3 V 7.4 mA Supply current: high sampling rate All blocks powered up, fS = 192 kHz IDD18H VDD18 = 1.8 V 6.7 mA IDD33H VDD33 = 3.3 V 15 mA IIOH(1) VIO = 3.3 V 47 mA ICCH VCC = 3.3 V 7.5 mA Total power dissipation: initial startup All blocks powered down by default 1 mW Total power dissipation: quiescent All blocks powered up with no clocks applied 28 mW Total power dissipation: dynamic All blocks powered up, fS = 48 kHz 233 mW Total power dissipation: high sampling rate All blocks powered up, fS = 192 kHz 242 mW

8.6 Timing Requirements

AUDIO SERIAL PORTS (PORT A AND PORT B) fLRCK LRCK clock frequency 0 216 kHz tLRCKD LRCK clock duty cycle 50% fBCK BCK clock frequency 0 13.824 MHz tBCKH BCK high pulse width 10 ns tBCKL BCK low pulse width 10 ns tAIS Audio data Input (SDIN) set-up time 10 ns tAISH Audio data input (SDIN) hold time 10 ns tADD Audio data output (SDOUT) delay 10 ns HOST INTERFACE: SPI MODE fCCLK Serial clock (CCLK) frequency 0 40 MHz tCSCR CS falling to CCLK rising 8 ns tCFCS CCLK falling to CS rising 7 ns tCDS CDIN data set-up time 7 ns

SBFS031F –FEBRUARY 2006–REVISED SEPTEMBER 2016 www.ti.com Product Folder Links: DIX4192 Submit Documentation Feedback Copyright © 2006–2016, Texas Instruments Incorporated Timing Requirements (continued) MIN NOM MAX UNIT (1) All values referred to the VIH minimum and VIL maximum levels listed in the Digital I/O Characteristics section of this table. (2) A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIH minimum input level) to bridge the undefined region of the falling edge of SCL. (3) The maximum tHDDAT has only to be met if the device does not stretch the Low period (tLOW) of the SCL signal. (4) A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but the requirement that tSUDAT be 250 ns (minimum) must then be met. For the DIX4192, this condition is automatically the case, because the device does not stretch the Low period of the SCL signal. (5) CB is defined as the total capacitance of one bus line in picofarads (pF). If mixed with High-Speed mode devices, faster fall times are allowed. tCDH CDIN data hold time 6 ns tCFDO CCLK falling to CDOUT data valid 3 ns tCSZ CS rising to CDOUT high-impedance, 3 ns HOST INTERFACE: I2C STANDARD MODE(1) fSCL SCL clock frequency 0 100 kHz tHDSTA Hold time repeated START condition 4 μs tLOW Low period of SCL clock 4.7 μs tHIGH High period of SCL clock 4 μs tSUSTA Set-up time repeated START condition 4.7 μs tHDDAT Data hold time 0(2) 3.45(3) μs tSUDAT Data set-up time 250 ns tR Rise time for both SDA and SDL 1000 ns tF Fall time for both SDA and SDL 300 ns tSUSTO Set-up time for STOP condition 4 μs tBUF Bus free time between START and STOP 4.7 μs CB Capacitive load for each bus line 400 pF VNL Noise margin at low level (including hysteresis) 0.1 × VIO V VNH Noise margin at high level (including hysteresis) 0.2 × VIO V HOST INTERFACE: I2C FAST MODE(1) fSCL SCL clock frequency 0 400 kHz tHDSTA Hold time repeated START condition 0.6 μs tLOW Low period of SCL clock 1.3 μs tHIGH High period of SCL clock 0.6 μs tSUSTA Set-up time repeated START condition 0.6 μs tHDDAT Data hold time 0(2) 0.9(3) μs tSUDAT Data set-up time 100(4) ns tR Rise time for both SDA and SDL 20 + 0.2CB(5) 300 ns tF Fall time for both SDA and SDL 20 + 0.2CB(5) 300 ns tSUSTO Set-up time for STOP condition 0.6 μs tBUF Bus free time between START and STOP 1.3 μs tSP Spike pulse width suppressed by input filter 0 50 ns CB Capacitive load for each bus Line 400 pF VNL Noise margin at low level (including hysteresis) 0.1 × VIO V VNH Noise margin at high level (including hysteresis) 0.2 × VIO V

8.7 Typical Characteristics

Figure 4. DIR Jitter Attenuation Characteristics Figure 5. DIR Jitter Tolerance Plot

9 Detailed Description

9.1 Overview

The DIX4192 is an integrated digital audio interface receiver and transmitter (DIR and DIT). Two audio serial ports, Port A and Port B, support input and output interfacing to external data converters, signal processors, and logic devices. On-chip routing logic provides for flexible interconnection between the four functional blocks. The audio serial ports and DIT may be operated at sampling rates up to 216 kHz. The DIR is specified for a PLL lock range that includes sampling rates from 20 kHz to 216 kHz. All function blocks support audio data word lengths up to 24 bits. The DIX4192 requires an external host processor or logic for configuration control. The DIX4192 includes a user- selectable serial host interface, which operates as either a 4-wire serial peripheral interface (SPI) port or a 2-wire Philips I2C bus interface. The SPI port operates at bit rates up to 40 MHz. The I2C bus interface may be operated in standard or fast modes, supporting operation at 100 kbps and 400 kbps, respectively. The SPI and I2C interfaces provide access to internal control and status registers, as well as the buffers used for the DIR and DIT channel status and user data. The digital interface receiver (DIR) includes four differential input line receiver circuits, suitable for balanced or unbalanced cable interfaces. Interfacing to optical receiver modules and CMOS logic devices is also supported. The outputs of the line receivers are connected to a 1-of-4 data selector, referred to as the receiver input multiplexer, which is used to select one of the four line receiver outputs for processing by the DIR core. The outputs of the line receivers are also connected to a second data selector, the bypass multiplexer, which may be used to route input data streams to the DIT CMOS output buffer and differential line driver functions. This configuration provides a bypass signal path for AES3-encoded input data streams. The DIR core decodes the selected input stream data and separates the audio, channel status, user, validity, and parity data. Channel status and user data is stored in block-sized buffers, which may be accessed through the SPI or I2C serial host interface, or routed directly to the general-purpose output pins (GPO1 through GPO4). The validity and parity bits are processed to determine error status. The DIR core recovers a low jitter master clock, which may be used to generate word and bit clocks using on-chip or external logic circuitry. The digital interface transmitter (DIT) encodes digital audio input data into an AES3-formatted output data stream. Two DIT outputs are provided, including a differential line driver and a CMOS output buffer. Both the line driver and buffer include 1-of-2 input data selectors, which are used to choose either the output of the DIT AES3 encoder, or the output of the bypass multiplexer. The line driver output is suitable for balanced or unbalanced cable interfaces, while the CMOS output buffer supports interfacing to optical transmitter modules and external logic or line drivers. The DIT includes block-sized data buffers for both channel status and user data. These buffers are accessed through either the SPI or I2C host interface, or may be loaded directly from the DIR channel status and user data buffers. The DIX4192 includes four general-purpose digital outputs, or GPO pins. The GPO pins may be configured as simple logic outputs, which may be programmed to either a low or high state. Alternatively, the GPO pins may be connected to one of 13 internal logic nodes, allowing them to serve as functional, status, or interrupt outputs. The GPO pins provide added utility in applications where hardware access to selected internal logic signals may be necessary. Functional Block Diagram shows a simplified functional block diagram for the DIX4192. Additional details for each function block will be covered in respective sections of this data sheet.

DIR_OUTPORT_A_INPORT_B_IN Audio Serial Port□A Audio Serial Port□B Digital Interface Receiver□(DIR) Digital Interface Transmitter (DIT) TX+ TX/c45 SDINA SDOUTA LRCKA BC A K SDINB SDOUTB LRCKB BC B K CPM CS or A0 CCLK□or□SCL CDIN□or 1 A CDOUT or□SDA INT RST Host Interface (SPI□or I C) and Gene a r l- Purp s o e Outputs Master Cl ck o Distribution MC K L RXCKI From□RXCKO GP 1 O GP 2 O GP 3 O GP 4 O AESOUT RXCKO LOCK RX + 2 RX /c452 RX + 3 RX /c453 RX + 4 RX /c454 RX + 1 RX /c451 BLS SY C N Control□and□Status Registers DIR□C□and U Data□Buffers DIT□C□and U Data□Buffers DIX4192 Power VDD18 DGND1 VDD33 DGND2 VIO DGND3 VCC AG D N BG D NInternally□Tied to□Substrate PORT□APORT□BDIRDIT DIX4192 SBFS031F –FEBRUARY 2006–REVISED SEPTEMBER 2016 www.ti.com Product Folder Links: DIX4192 Submit Documentation Feedback Copyright © 2006–2016, Texas Instruments Incorporated

9.2 Functional Block Diagram

9.3 Feature Description

9.3.1 RESET Operation

The DIX4192 includes an asynchronous active low reset input, RST (pin 24), which may be used to initialize the internal logic at any time. The reset sequence forces all registers and buffers to their default settings. The reset low pulse width must be a minimum of 500 ns in length. The user must not attempt a write or read operation using either the SPI or I2C port for at least 500 μs after the rising edge of RST. See Figure 6 for the reset timing sequence of the DIX4192. In addition to reset input, the RESET bit in control register 0x01 may be used to force an internal reset, whereby all registers and buffers are forced to their default settings. Refer to Control Registers for details regarding the RESET bit function. Upon reset initialization, all functional blocks of the DIX4192 default to the power-down state, with the exception of the SPI or I2C host interface and the corresponding control registers. The user may then program the DIX4192 to the desired configuration, and release the desired function blocks from the power-down state using the corresponding bits in control register 0x01.

Figure 6. Reset Sequence Timing

9.3.2 Master and Reference Clocks

it may also be used as the master or reference clock source for the audio serial ports. source for the audio serial ports and the DIT, as well as external audio devices. (DIT) Operation for additional details. 24.576 MHz, may be used for this clock. designed or specified for low clock jitter.

9.3.3 Audio Serial Port Operation

to 24 bits. Philips I2S, Left-Justified, and Right-Justified serial data formats are supported. Refer to Figure 8. for parametric information and Figure 1 for a timing diagram related to audio serial port operation. descriptions of the control register bits. Figure 7. Audio Serial Port Block Diagram

Figure 8. Audio Data Formats

9.3.4 Overview of the AES3 Digital Audio Interface Protocol

sources listed in the Development Support section.

Preceding□state,□fr of□the□previous□frameom□the□□Parity□bit . preambles. Figure 10 shows the Biphase Mark and preamble encoding. capable of handling higher sampling rates, given that attention is paid to cable length and impedance matching. Dolby® AC-3, DTS, MPEG-1/2, and other data reduced audio formats. Figure 10. Biphase Mark Encoding

9.3.5 Digital Interface Transmitter (DIT) Operation

The DIT encodes a given two-channel or data-reduced audio input stream into an AES3-encoded output stream. In addition to the encoding function, the DIT includes differential line driver and CMOS-buffered output functions. functional block diagram for the DIT. control register 0x07 are used to select divide by 128, 256, 384, or 512 operation. delayed by one block in relation to the audio data.

through 31 of the AES3-encoded subframe are even parity. the outputs are disabled, they are forced to a low logic state. function is controlled using the TXMUTE bit in control register 0x08. Figure 11. Digital Interface Transmitter (DIT) Functional Block Diagram input or output. The input/output state of the BLS pin is programmed using the BLSM bit in control register 0x07. By default, the BLS pin is configured as an input. Control Registers and Channel Status and User Data Buffer Maps.

Figure 12. DIT Block Start Timing

9.3.6 Digital Interface Receiver (DIR) Operation

line receiver. External connections are discussed in Receiver Input Interfacing. Figure 13. Digital Interface Receiver (DIR) Functional Block Diagram

9.3.7 General-Purpose Digital Outputs

connected to one of 13 internal logic nodes, allowing the GPO pin to inherit the function of the selected signal. Table 1. General-Purpose Output Pin Configurations status and user data serial outputs.

9.3.8 Interrupt Output

pins from multiple DIX4192 devices to be connected in a wired OR configuration. Figure 18. Interrupt Output Pin Connections

9.4 Device Functional Modes

9.4.1 Host Interface Operation: Serial Peripheral Interface (SPI) Mode

data input for the port; the CDOUT output serves as the serial data output. products, including the DIT4096, DIT4192, the SRC418x series devices, and the SRC419x series devices. each data byte transferred, starting with the address specified by the command byte. diagram that highlight the key parameters for SPI operation. Figure 19. Serial Peripheral Interface (SPI) Protocol for the DIX4192

9.4.2 Host Interface Operation: PHILIPS I2C Mode

function as the hardware configurable portion of the 7-bit slave address. single operation, and is especially useful for block write and read operations. operations for one or more random register addresses, with or without auto-increment mode enabled. Figure 20. DIX4192 Slave Address and Register Address Byte Definitions

9.5 Register Maps

9.5.1 Register and Data Buffer Organization

the page selection corresponding to the Page Selection Register value. Table 2. Register Page Selection

00 Page 0, control and status registers

01 Page 1, DIR channel status and user data buffers

02 Page 2, DIT channel status and user data buffers

03 Page 3, reserved

Register Page 0 contains the control registers used to configure the various function blocks within the DIX4192. generating an interrupt signal when enabled. See Table 3 for the control and status register map. the DIR user data buffer map. Table 37 for the DIT channel status buffer map, and Table 38 for the DIT user data buffer map. useful in customer applications.

9.5.2 Control Registers

following pages provide detailed descriptions for each control and status register. Table 3. Control and Status Register Map (Register Page 0)

01 RESET 0 PDALL PDPA PDPB PDTX PDRX 0 Power-down and reset

07 TXCLK TXDIV1 TXDIV0 TXIS1 TXIS0 BLSM VALID BSSL Transmitter control

08 BYPMUX1 BYPMUX0 AESMUX LDMUX TXBTD AESOFF TXMUTE TXOFF Transmitter control

10 J1 J0 D13 D12 D11 D10 D9 D8 Receiver PLL configuration

11 D7 D6 D5 D4 D3 D2 D1 D0 Receiver PLL configuration

14 CSCRC PARITY VBIT BPERR QCHG UNLOCK QCRC RBTI Receiver status

16 MCSCRC MPARITY MVBIT MBPERR MQCHG MUNLOCK MQCRC MRBTI Receiver interrupt mask

18 QCHGM1 QCHGM0 UNLOCKM1 UNLOCKM0 QCRCM1 QCRCM0 RBTIM1 RBTIM0 Receiver interrupt mode

19 CSCRCM1 CSCRCM0 PARITYM1 PARITYM0 VBITM1 VBITM0 BPERRM1 BPERRM0 Receiver interrupt mode

20 Q8 Q9 Q10 Q11 Q12 Q13 Q14 Q15 Audio CD Q-channel sub-code

21 Q16 Q17 Q18 Q19 Q20 Q21 Q22 Q23 Audio CD Q-channel sub-code

22 Q24 Q25 Q26 Q27 Q28 Q29 Q30 Q31 Audio CD Q-channel sub-code

23 Q32 Q33 Q34 Q35 Q36 Q37 Q38 Q39 Audio CD Q-channel sub-code

24 Q40 Q41 Q42 Q43 Q44 Q45 Q46 Q47 Audio CD Q-channel sub-code

25 Q48 Q49 Q50 Q51 Q52 Q53 Q54 Q55 Audio CD Q-channel sub-code

26 Q56 Q57 Q58 Q59 Q60 Q61 Q62 Q63 Audio CD Q-channel sub-code

27 Q64 Q65 Q66 Q67 Q68 Q69 Q70 Q71 Audio CD Q-channel sub-code

28 Q72 Q73 Q74 Q75 Q76 Q77 Q78 Q79 Audio CD Q-channel sub-code

29 PC15 PC14 PC13 PC12 PC11 PC10 PC09 PC08 PC burst preamble, high byte

Figure 23. Register 01: Power-Down and Reset Table 4. Register 01: Power-Down and Reset Field Descriptions This bit is used to power-down the DIR and associated functions. All receiver outputs are forced low.

0 Enabled (default)

1 Disabled; the Receiver function block will operate normally based upon the applicable control register settings. This bit is used to power-down the DIT and associated functions. All transmitter outputs are forced low. 1 Disabled; the Transmitter function block will operate normally based upon the applicable control register settings. This bit is used to power-down the audio serial I/O Port B. All port outputs are forced low. 1 Disabled; Port B will operate normally based upon the applicable control register settings. This bit is used to power-down the audio serial I/O Port A. All port outputs are forced low. 1 Disabled; Port A will operate normally based upon the applicable control register settings. This bit is used to power-down all function blocks except the host interface port and the control and status registers. 1 Disabled; all function blocks will operate normally based upon the applicable control register settings. This bit is used to force a reset initialization sequence, and is equivalent to forcing an external reset through the RST input (pin 24).

0 Disabled (default)

1 Enabled; all control registers will be reset to the default state. Figure 24. Register 02: Global Interrupt Status (Read-Only) Table 5. Register 02: Global Interrupt Status (Read-Only) Field Descriptions registers 0x14 and 0x15 in order to determine which of the sources has generated an interrupt. register 0x0A in order to determine which of the sources has generated an interrupt.

Figure 25. Register 03: Port A Control Register 1

0 AMUTE AOUTS1 AOUTS0 AM/S AFMT2 AFMT1 AFMT0

Table 6. Register 03: Port A Control Register 1 Field Descriptions This bit is used to set the audio clock mode for Port A to either Slave or Master. 1 Master mode; the LRCK and BCK clocks are outputs, derived from the Port A master clock source. These bits are used to select the output data source for Port A. The data is output at SDOUTA (pin 40). This bit is used to mute the Port A audio data output. 1 Enabled; SDOUTA is forced low. Figure 26. Register 04: Port A Control Register 2 Table 7. Register 04: Port A Control Register 2 Field Descriptions These bits are used to set the master clock divider for generating the LRCKA clock for Port A when configured for Master mode operation. BCKA is always set to 64 times the LRCKA clock rate in Master mode. These bits are used to set the master clock source for Port A when configured for Master mode operation.

Table 7. Register 04: Port A Control Register 2 Field Descriptions (continued) Figure 27. Register 05: Port B Control Register 1

0 BMUTE BOUTS1 BOUTS0 BM/S BFMT2 BFMT1 BFMT0

Table 8. Register 05: Port B Control Register 1 Field Descriptions This bit is used to set the audio clock mode for Port B to either Slave or Master. 1 Master mode; the LRCK and BCK clocks are derived from the Port A master clock source. These bits are used to select the output data source for Port B. The data is output at SDOUTB (pin 45). This bit is used to mute the Port B audio data output. 1 Enabled; SDOUTB is forced low.

Figure 28. Register 06: Port B Control Register 2 Table 9. Register 06: Port B Control Register 2 Field Descriptions These bits are used to set the master clock divider for generating the LRCKB clock for Port B when configured for Master mode operation. BCKB is always set to 64 times the LRCKB clock rate in Master mode. These bits are used to set the master clock source for Port B when configured for Master mode operation. Figure 29. Register 07: Transmitter Control Register 1 Table 10. Register 07: Transmitter Control Register 1 Field Descriptions This bit is used to select the trigger source for the Transmitter TSLIP status and interrupt bit.

0 Data slip condition (default)

1 Block start condition

This bit is used to select the input and output mode for the DIT block start pin, BLS (pin 35).

0 Input (default)

1 Output

These bits are used to select the audio data source for the DIT function block.

Table 10. Register 07: Transmitter Control Register 1 Field Descriptions (continued) These bits are used to select the Transmitter master clock divider, which determines the output frame rate. 0 1 Divide the master clock by 256. 1 0 Divide the master clock by 384. 1 1 Divide the master clock by 512. This bit is used to select the master clock source for the Transmitter block.

0 MCLK input (default)

1 RXCKO; the recovered master clock from the DIR function block. Figure 30. Register 08: Transmitter Control Register 2 Table 11. Register 08: Transmitter Control Register 2 Field Descriptions This bit is used to enable or disable the TX+ (pin 32) and TX– (pin 31) line driver outputs. 1 Disabled; the line driver outputs are forced low. This bit is used to set the 24 bits of audio and auxiliary data to all zeros for both Channels 1 and 2. 1 Enabled; the audio data for both channels 1 and 2 are set to all zeros. This bit is used to enable or disable the AESOUT (pin 34) buffered AES3-encoded CMOS logic level output. 1 Disabled; the AESOUT pin is forced low. channel status (C) and user (U) data. data to be transmitted at the start of the next block. 1 Disabled; allows the user to update DIT C and U data buffers. Note: The TXCUS0 and TXCUS1 bits in control register 0x09 must be set to a non-zero value in order for DIT UA buffer updates to occur. This bit is used to select the input source for the DIT differential line driver outputs.

0 DIT AES3 encoder output (default)

1 Bypass multiplexer output

This bit is used to select the input source for the AESOUT CMOS logic level output.

Table 14. Register 0B: DIT Interrupt Mask Register Field Descriptions (continued) 1 TSLIP interrupt is enabled. Figure 34. Register 0C: DIT Interrupt Mode Register Table 15. Register 0C: DIT Interrupt Mode Register Field Descriptions These bits are used to select the active trigger state for the BTI interrupt. These bits are used to select the active trigger state for the TSLIP interrupt. Figure 35. Register 0D: Receiver Control Register 1 Table 16. Register 0D: Receiver Control Register 1 Field Descriptions These bits are used to select the output of the line receiver to be used as the input data source for the DIR core. This bit is used to select the reference clock source for PLL1 in the DIR core.

0 RXCKI (default)

1 MCLK

status (C) and user (U) data. 1 Disabled; the user may read C and U data from the DIR UA buffers.

Figure 36. Register 0E: Receiver Control Register 2 Table 17. Register 0E: Receiver Control Register 2 Field Descriptions 1 Enabled; the recovered master clock is available at RXCKO. 0 1 Divide the PLL2 clock output by 2. 1 0 Divide the PLL2 clock output by 4. 1 1 Divide the PLL2 clock output by 8. This bit is used to set the automatic mute function for the DIR block when a loss of lock is indicated by both the AES3 decoder and PLL2. 1 Enabled; audio data output from the DIR block is forced low for a loss of lock condition. This bit is used to set the mode of operation for PLL2 when a loss of lock condition occurs. 1 The PLL2 output clock free runs when a loss of lock condition occurs. Figure 37. Register 0F: Receiver PLL1 Configuration Register 1 Figure 38. Register 10: Receiver PLL1 Configuration Register 2

Figure 41. Register 13: Receiver Status Register 1 (Read-Only) Table 21. Register 13: Receiver Status Register 1 (Read-Only) Field Descriptions is determined and output from PLL2, as well as being loaded into the RXCKR0 and RXCKR1 status bits. RXCKOD0 and RXCKOD1 bits in control register 0x0E. 0 0 Clock rate not determined. Figure 42. Register 14: Receiver Status Register 2 (Read-Only) Note: Status bits must be unmasked in control register 0x16 in order for the status interrupts to be generated. Table 22. Register 14: Receiver Status Register 2 (Read-Only) Field Descriptions

0 No error

1 CRC error detected

1 Parity error detected

0 Valid audio data indicated

1 Non-valid data indicated

1 Biphase encoding error detected

0 No change in Q-channel sub-code data. registers 0x1F through 0x28. 0 No error; the DIR AES3 decoder and PLL2 are locked. 1 DIR lock error; the AES3 decoder and PLL2 are unlocked. 1 Q-channel sub-code data CRC error detected.

Table 22. Register 14: Receiver Status Register 2 (Read-Only) Field Descriptions (continued)

0 Buffer transfer incomplete, or no Buffer transfer interrupt indicated

1 Buffer transfer completed

Figure 43. Register 15: Receiver Status Register 3 (Read-Only) Note: Status bits must be unmasked in control register 0x17 in order for the status interrupts to be generated. Table 23. Register 15: Receiver Status Register 3 (Read-Only) Field Descriptions

1 DIR output data Slip or Repeat error detected

slave mode. Figure 44 shows the timing associated with the OSLIP interrupt. Port B are sourced by the DIR output, then the OSLIP status bit and interrupt applies to Port A only. Figure 44. DIR Output Slip and Repeat (OSLIP) Behavior

Figure 45. Register 16: Receiver Interrupt Mask Register 1 Table 24. Register 16: Receiver Interrupt Mask Register 1 Field Descriptions

0 Masked (default)

1 Enabled

Figure 46. Register 17: Receiver Interrupt Mask Register 2 Table 25. Register 17: Receiver Interrupt Mask Register 2 Field Descriptions

Figure 47. Register 18: Receiver Interrupt Mode Register 1 Table 26. Register 18: Receiver Interrupt Mode Register 1 Field Descriptions

9.5.2.1 Registers 1F through 28: Q-Channel Sub-Code Data Registers

data is decoded by the DIR block. Figure 54. Register 1F: Q-Channel Sub-Code Data Register 1 (Read-Only), Bits[7:0], Control and Address Figure 55. Register 20: Q-Channel Sub-Code Data Register 2 (Read-Only), Bits[15:8], Track Figure 56. Register 21: Q-Channel Sub-Code Data Register 3 (Read-Only), Bits[23:16], Index Figure 57. Register 22: Q-Channel Sub-Code Data Register 4 (Read-Only), Bits[31:24], Minutes Figure 58. Register 23: : Q-Channel Sub-Code Data Register 5 (Read-Only), Bits[39:32], Seconds Figure 59. Register 24: : Q-Channel Sub-Code Data Register 6 (Read-Only), Bits[47:40], Frame Figure 60. Register 25: Q-Channel Sub-Code Data Register 7 (Read-Only), Bits[55:48], Zero Figure 61. Register 26: Q-Channel Sub-Code Data Register 8 (Read-Only), Bits[63:56], AMIN Figure 62. Register 27: Q-Channel Sub-Code Data Register 9 (Read-Only), Bits[71:64], ASEC Figure 63. Register 28: Q-Channel Sub-Code Data Register 10 (Read-Only), Bits[79:72], AFRAME

9.5.2.2 Registers 29 through 2C: IEC61937 PC/PD Burst Preamble

Registers 0x29 through 0x2C contain the PC and PD preambles as decoded by the DIR block. Figure 64. Register 29: Burst Preamble PC High-Byte Status Register (Read-Only) Figure 65. Register 2A: Burst Preamble PC Low-Byte Status Register (Read-Only) Table 33. Register 2A: Burst Preamble PC Low-Byte Status Register (Read-Only) Field Descriptions

00 Null

01 Dolby AC-3

02 Reserved

03 Pause

04 MPEG-1 layer 1

05 MPEG-1 layer 2 or 3, or MPEG-2 without extension

06 MPEG-2 Data with extension

07 MPEG-2 AAC ADTS

08 MPEG-2 layer 1 low sample rate

09 MPEG-2 layer 2 or 3 low sample rate

Bits PC[6:5] are both set to 0. Bit PC[7] is an Error Flag, where: 0 = A valid burst-payload; 1 = Burst-payload may contain errors. Bits PC[12:8] are data-type dependent. Bits PC[15:13] indicate the stream number, which is set to 0. Figure 66. Register 2B: Burst Preamble PD High-Byte Status Register (Read-Only) Figure 67. Register 2C: Burst Preamble PD Low-Byte Status Register (Read-Only)

Figure 68. Register 7F: Page Selection Register Table 34. Register 7F: Page Selection Register Field Descriptions Page Selection Register is present on every register page at address 0x7F, allowing movement between pages as necessary.

9.5.3 Channel Status and User Data Buffer Maps

Table 35 through Table 38 show the buffer maps for the DIR and DIT channel status and user data buffers. Consumer. Bit 0 of Byte 0 defines the transmission mode, 0 for Consumer mode, and 1 for Professional mode. This is applicable for Table 35 and Table 36. encoded by the DIT. There is no requirement to program Byte 23 for either channel in Professional mode.

Table 35. DIR Channel Status Data Buffer Map (Register Page 1)

Table 36. DIR User Data Buffer Map (Register Page 1)

Table 37. DIT Channel Status Data Buffer Map (Register Page 2)

Table 38. DIT User Data Buffer Map (Register Page 2)

www.ti.com SBFS031F –FEBRUARY 2006–REVISED SEPTEMBER 2016 Product Folder Links: DIX4192 Submit Documentation FeedbackCopyright © 2006–2016, Texas Instruments Incorporated NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

10.1 Application Information

Typical application diagrams and power-supply connections are presented in this section to aid the customer in hardware designs employing the DIX4192 device. Figure 69 shows typical application connections for the DIX4192 using an SPI host interface. The SPI host will typically be a microcontroller, digital signal processor, or programmable logic device. In addition to providing the SPI bus master, the host may be used to process interrupt and flag outputs from the DIX4192. The audio serial ports are connected to external digital audio devices, which may include data converters, digital signal processors, digital audio interface receivers or transmitters, or other logic devices. The DIR inputs and DIT outputs are connected to line, optical, or logic interfaces (see Receiver Input Interfacing and Transmitter Output Interfacing). Master and DIR reference clock sources are also shown. Figure 70 shows typical application connections for the DIX4192 using an I2C bus interface. The I2C bus master will typically be a microcontroller, digital signal processor, or programmable logic device. In addition to providing the I2C bus master, the host may be used to process interrupt and flag outputs from the DIX4192. Pullup resistors are connected from SCL (pin 20) and SDA (pin 22) to the VIO supply rail. These resistors are required for the open drain outputs of the I2C interface. All other connections to the DIX4192 are the same as the SPI host case discussed previously. Figure 71 shows the recommended power-supply connections and bypassing for the DIX4192. In this case, it is assumed that the VIO, VDD33, and VCC supplies are powered from the same 3.3-V power source. The VDD18 core supply is powered from a separate supply, or derived from the 3.3-V supply using a linear voltage regulator, as shown with the optional regulator circuitry of Figure 71. The 0.1-μF bypass capacitors are surface-mount X7R ceramic, and must be located as close to the device as possible. These capacitors must be connected directly between the supply and corresponding ground pins of the DIX4192. The ground pin is then connected directly to the ground plane of the printed circuit board (PCB). The larger value capacitors, shown connected in parallel to the 0.1-μF capacitors, are recommended. At a minimum, there must at least be footprints on the PCB for installation of these larger capacitors, so that experiments can be run with and without the capacitors installed, in order to determine the effect on the measured performance of the DIX4192. The larger value capacitors can be surface-mount X7R multilayer ceramic or tantalum chip. The substrate ground, BGND (pin 44), must be connected by a PCB trace to AGND (pin 10). The AGND pin is then connected directly to the ground plane. This connection helps to reduce noise in the DIR section of the device, aiding the overall jitter and noise tolerance for the receiver. A series resistor is shown between the 3.3-V supply and VCC (pin 9) connection. This resistor combines with the bypass capacitors to create a simple RC filter to remove higher frequency components from the VCC supply. The series resistor must be a metal film type for best filtering characteristics. As a substitute for the resistor, a ferrite bead can be used, although it may have to be physically large in order to contribute to the filtering.

10 F/c109

R□may□be set□from□2 t ced□b fe te□b/c87 y□a rri eo 10 or□repla/c87, ad.

0.1 F/c109

Figure 71. Recommended Power-Supply Connections

10.1.1 Digital Audio Transformer Vendors

Scientific Conversion: http://scientificonversion.com
Schott Corporation: http://schottcorp.com
Pulse Engineering: http://pulseeng.com

10.1.2 Receiver Input Interfacing

line interfaces, in addition to optical receiver and external logic interfacing, are discussed. For professional digital audio interfaces, 110-Ω balanced line interfaces are either required or preferred. Transformer coupling is commonly employed to provide isolation and to improve common-mode noise rejection. transformer is specified for a 1:1 turn ratio, and must exhibit low inter-winding capacitance for best performance. ceramic chip type with an X7R or C0G dielectric.

(1)□T oshiba□TORX141□or□equivalent. (1)□Insert□a□0.1 F□cap common-mode□DC/c109 acitor□when□blocking components.

75 Unbalan/c87 ced

110 B/c87 alanced

Figure 72. Transformer-Coupled Balanced Input Interface shows the transformer-free interface, which is commonly used for S/PDIF consumer connections. Figure 73. Unbalanced Line Input Interfaces from either a single 3.3-V or 5-V supply and have a TTL–, CMOS-, or low-voltage CMOS-compatible logic output. buffer includes a 5-V tolerant digital input, and provides the logic level translation required for the interface. Figure 74. Interfacing to a 3.3-V Optical Receiver Module

(1)□T oshiba□TORX173,□TORX176,□TORX179,□or□equivalent. Figure 75. Interfacing to a 5-V Optical Receiver Module translators available from Texas Instruments. Figure 76. CMOS and TTL Input Logic Interface

10.1.3 Transmitter Output Interfacing

For professional digital audio interfaces, 110-Ω balanced line interfaces are either required or preferred.

The□TX+□output□impedance□is□negligible. Figure 77. Transformer-Coupled Balanced Output Interface for S/PDIF consumer connections. Figure 78. Unbalanced Line Output Interfaces input configuration. Figure 79 shows the recommended optical transmitter interface circuits.

10.2 Typical Application

Figure 82. DIX4192 Typical Application

10.2.1 Design Requirements

For this design example, use the parameters listed in Table 39. Table 39. Design Parameters

10.2.2 Detailed Design Procedure

10.2.2.1 Differential Line Inputs and Output

either of the serial ports or the DIR itself. User data and channel status data can be updated in registers.

10.2.2.2 Serial Ports

PCM5242 DAC on the other serial port.

10.2.3 Application Curves

Figure 83. DIR Jitter Attenuation Characteristics Figure 84. DIR Jitter Tolerance Plot

11 Power Supply Recommendations

capacitors for the power supplies must be placed close to the device terminals.

12 Layout

12.1 Layout Guidelines

Decoupling capacitors must be placed as close to power pins as possible (VCC, VDD33, VDD18, VIO).
Further guidelines can be found in Layout Example.

12.2 Layout Example

Figure 85. DIX4192 Board Layout

13 Device and Documentation Support

13.1 Device Support

13.1.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

13.1.2 Development Support

For developmental support, see the following:

AES web site: http://www.aes.org
IEC web site: http://www.iec.ch
ANSI web site: http://www.ansi.org
Japanese Electronics and Information Technologies Industries Association (JEITA) website: http://www.jeita.or.jp/english
Philips we site: http://www.philips.com
Scientificonversion web site: http://www.scientificonversion.com
Schott Magnetics web site: http://www.schottcorp.com/
Pulse Electronics web site: http://www.pulseelectronics.com/

13.2 Documentation Support

13.2.1 Related Documentation

For related documentation, see the following:

DIT4096 96-kHz Digital Audio Transmitter, SBOS225
DIT4192 192-kHz Digital Audio Transmitter, SBOS229
SRC4184 4-Channel, Asynchronous Sample Rate Converter, SBFS026
SRC419 x 192-kHz Stereo Asynchronous Sample-Rate Converters, SBFS022
SN74LVC1G125 Single Bus Buffer Gate With 3-State Output, SCES223
SN74AVC1T45 Single-Bit Dual-Supply Bus Transceiver With Configurable Voltage Translation and 3-State Outputs, SCES530
SN75ALS191 Dual Differential Line Driver, SLLS032

13.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

13.4 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.

13.5 Trademarks

E2E is a trademark of Texas Instruments.

13.5 Trademarks (continued)

Dolby is a registered trademark of Dolby Laboratories, Inc. SPI is a trademark of Motorola. I2S is a trademark of NXP Semiconductors. All other trademarks are the property of their respective owners.

13.6 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

13.7 Glossary

SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.

14 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

www.ti.com 10-Nov-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) DIX4192IPFB Active Production TQFP (PFB) | 48 250 | JEDEC TRAY (5+1) Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 DIX4192I DIX4192IPFB.A Active Production TQFP (PFB) | 48 250 | JEDEC TRAY (5+1) Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 DIX4192I DIX4192IPFBR Active Production TQFP (PFB) | 48 1000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 DIX4192I DIX4192IPFBR.A Active Production TQFP (PFB) | 48 1000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 DIX4192I DIX4192IPFBRG4 Active Production TQFP (PFB) | 48 1000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 DIX4192I (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

www.ti.com 10-Nov-2025 OTHER QUALIFIED VERSIONS OF DIX4192 :

Automotive : DIX4192-Q1 NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 3-Aug-2026 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 3-Aug-2026 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DIX4192IPFBR TQFP PFB 48 1000 350.0 350.0 43.0 Pack Materials-Page 2

www.ti.com PACKAGE OUTLINE C 48X 0.27 0.1744X 0.5 PIN 1 ID (0.13) TYP

0.05 MIN0 -7

4X 5.5 9.2

8.8 TYP

0.75 0.45 B7.2 6.8 NOTE 3 A 7.2 6.8 NOTE 3 0.25 GAGE PLANE

1.2 MAX

(1) PLASTIC QUAD FLATPACK TQFP - 1.2 mm max heightPFB0048A PLASTIC QUAD FLATPACK 4215157/A 03/2024 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Reference JEDEC registration MS-026. 13 24 3748

0.08 C A B

0.08 A 16 DETAIL A TYPICAL SCALE 1.900

www.ti.com EXAMPLE BOARD LAYOUT

0.05 MAX

0.05 MIN

(8.5) (8.5) 44X (0.5) 48X (1.35) 48X (0.25) (R0.05) TYP TQFP - 1.2 mm max heightPFB0048A PLASTIC QUAD FLATPACK 4215157/A 03/2024 NOTES: (continued) 4. Publication IPC-7351 may have alternate designs. 5. Solder mask tolerances between and around signal pads can vary based on board fabrication site. LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SYMM SYMM 48 37 13 24 SEE DETAILS METAL SOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS EXPOSED METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL

www.ti.com EXAMPLE STENCIL DESIGN 44X (0.5) 48X (1.35) 48X (0.25) (R0.05) TYP (8.5) (8.5) TQFP - 1.2 mm max heightPFB0048A PLASTIC QUAD FLATPACK 4215157/A 03/2024 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 7. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE SCALE:8X SYMM SYMM 48 37 13 24

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Texas Instruments DIX4192 overview.

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Summary

DIX4192 Integrated Digital Audio Interface Receiver and Transmitter REVISED SEPTEMBER 2016

Description

DIX4192 Integrated Digital Audio Interface Receiver and Transmitter REVISED SEPTEMBER 2016

Source title DIX4192 Datasheet(PDF) - Texas Instruments

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