DIR9001

96-kHz, 24-Bit Digital Audio Interface Receiver datasheet (Rev. A)

Document overview

• Manufacturer or author: Texas Instruments, Incorporated [SLES198,A]
• PDF pages: 38

Technical content

Audio□Data Formatter ERROR Detector Function Control Audio□Data MUTE Control Channel Status and User□Data Output Product Folder Sample & Buy T echnical Documents Tools & Software Support & Community DIR9001 SLES198A –DECEMBER 2006–REVISED MAY 2015 DIR900196-kHz,24-BitDigitalAudioInterfaceReceiver

1 Features 3 Description

The DIR9001 is a digital audio interface receiver that 1• One-Chip Digital Audio Interface Receiver (DIR) can receive a 28-kHz to 108-kHz sampling-Including Low-Jitter Clock-Recovery System frequency, 24-bit-data-word, biphase-encoded signal.• Compliant With Digital Audio Interface Standards: The DIR9001 complies with IEC60958-3, JEITA CPR- IEC60958 (former IEC958), JEITA CPR-1205 1205 (Revised version of EIAJ CP-1201), AES3, (former EIAJ CP-1201, CP-340), AES3, EBU EBUtech3250, and it can be used in various tech3250 applications that require a digital audio interface.

• Clock Recovery and Data Decode From Biphase The DIR9001 supports many output system clock and Input Signal, Generally Called S/PDIF, EIAJ CP- output data formats and can be used flexibly in many 1201, IEC60958, AES/EBU application systems. As the all functions which the DIR9001 provides can be controlled directly through• Biphase Input Signal Sampling Frequency (fS) control pins, it can be used easily in an applicationRange: 28 kHz to 108 kHz system that does not have a microcontroller. Also, as• Low-Jitter Recovered System Clock: 50 ps dedicated pins are provided for the channel-status bit
• Jitter Tolerance Compliant With IEC60958-3 and user-data bit, processing of their information can be easily accomplished by connecting with a• Selectable Recovered System Clock: 128 fS, microcontroller, DSP, or others.256 fS, 384 fS, 512 fS
• Serial Audio Data Output Formats: 24-Bit I2S; The DIR9001 does not require an external clock source or resonator for decode operation if theMSB-First, 24-Bit Left-Justified; MSB-First 16-, 24- internal actual-sampling-frequency calculator is notBit Right-Justified used. Therefore, it is possible to reduce the cost of a• User Data, Channel-Status Data Outputs system.Synchronized With Decoded Serial Audio Data The operating temperature range of the DIR9001 is• No External Clock Required for Decode specified as –40°C to 85°C, which makes it suitable• Includes Actual Sampling Frequency Calculator for automotive applications.(Needs External 24.576-MHz Clock)
• Function Control: Parallel (Hardware) Device Information PART NUMBER PACKAGE BODY SIZE (NOM)• Functions Similar and Pin Assignments Equivalent to Those of DIR1703 DIR9001 TSSOP (28) 4.40 mm × 9.70 mm
• Single Power Supply: 3.3 V (2.7 V to 3.6 V) (1) For all available packages, see the orderable addendum at the end of the data sheet.• Wide Operating Temperature Range: –40°C to 85°C
• 5 V-Tolerant Digital Inputs Block Diagram• Package: 28-pin TSSOP, Pin Pitch: 0,65 mm

2 Applications

• AV/DVD Receiver, AV Amplifier
• Car or Mobile Audio System
• Digital Television
• Musical Instruments
• Recording Systems
• High-End Audio/Sound Card for PC
• Replacement of DIR1703
• Other Applications Requiring S/PDIF Receiver An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

SLES198A –DECEMBER 2006–REVISED MAY 2015 www.ti.com Table of Contents

4 Revision History

Changes from Original (Dec 2006) to Revision A Page

• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device

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5 Device Comparison Table

5.1 Differences From DIR1703

The DIR9001 has many improved functions compared to the DIR1703. The DIR9001 functions are similar to those of the DIR1703. The DIR9001 pin assignment is equivalent to that of the DIR1703. The DIR9001 biphase input signal decoding function is almost equivalent to that of the DIR1703. The differences between the DIR9001 and DIR1703 are shown in Table 1. Table 1. Main Differences Between DIR1703 and DIR9001 The differences between the DIR1703 and DIR9001 I/O pins are shown in Table 2. Table 2. The Differences Between DIR1703 and DIR9001 in All I/O Pin

1 ADFLG AUDIO Pin name only Channel-status data information of non-audio sample word, active-low

2 BRATE0 FSOUT0 Pin name only Actual-sampling-frequency calculated result output 0

3 BRATE1 FSOUT1 Pin name only Actual-sampling-frequency calculated result output 1

4 SCKO SCKO Same function System clock output

6 DGND DGND Same function Digital ground

7 XTO XTO Same function Oscillation amplifier output

8 XTI XTI Same function Oscillation amplifier input, or external XTI source clock input

9 CKTRNS CLKST CLKST is active-high Clock change/transition signal output

10 LRCKO LRCKO Same function Audio data latch enable output

11 BCKO BCKO Same function Audio data bit clock output

12 DOUT DOUT Same function 16 bit–24 bit decoded serial digital audio data output

13 SCF0 PSCK0 Pin name only SCKO output frequency selection 0

14 SCF1 PSCK1 Pin name only SCKO output frequency selection 1

15 CSBIT COUT Pin name only Channel-status data serial output synchronized with LRCKO

1 AUDIO

Table 2. The Differences Between DIR1703 and DIR9001 in All I/O Pin (continued)

16 URBIT UOUT Pin name only User data serial output synchronized with LRCKO

17 EMFLG EMPH Pin name only Channel-status data Information of pre-emphasis (50 μs/15 μs)

18 BFRAME BFRAME Same function Indication of top block of biphase input signal

19 BRSEL RSV Reserved Reserved, must be connected to DGND

20 DIN RXIN Pin name only Biphase digital data input

21 RST RST Same function Reset control input, active-low

22 FILT FILT Same function External filter connection terminal. Recommended filter must be connected.

23 AGND AGND Same function Analog ground

25 FMT0 FMT0 Same function Decoded serial digital audio data output format selection 0

26 FMT1 FMT1 Same function Decoded serial digital audio data output format selection 1

27 UNLOCK ERROR Pin name only Indication of internal PLL or data parity error

28 CKSEL CKSEL Same function Selection of system clock source, Low: PLL (VCO) clock, High: XTI clock

6 Pin Configuration and Functions

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www.ti.com SLES198A –DECEMBER 2006–REVISED MAY 2015 Pin Functions PIN PULLI/O REMARKS DESCRIPTIONUP/DOWNNAME NO. AGND 23 – Analog ground AUDIO 1 OUT CMOS Channel-status data information of non-audio sample word, active-low BCKO 11 OUT CMOS Audio data bit clock output BFRAME 18 OUT CMOS Indication of top block of biphase input signal CKSEL 28 IN Pulldown 5-V tolerant TTL Selection of system clock source, Low: PLL (VCO) clock, High: XTI clock(1) CLKST 9 OUT CMOS Clock change/transition signal output COUT 15 OUT CMOS Channel-status data serial output synchronized with LRCKO DGND 6 – Digital ground DOUT 12 OUT CMOS 16-bit/24-bit decoded serial digital audio data output EMPH 17 OUT CMOS Channel-status data information of pre-emphasis (50 μs/15 μs) ERROR 27 OUT CMOS Indication of internal PLL or data parity error FILT 22 – External filter connection terminal; must connect recommended filter. FMT0 25 IN Pulldown 5-V tolerant TTL Decoded serial digital audio data output format selection 0 (1) FMT1 26 IN Pulldown 5-V tolerant TTL Decoded serial digital audio data output format selection 1 (1) FSOUT0 2 OUT CMOS Actual sampling frequency calculated result output 0 FSOUT1 3 OUT CMOS Actual sampling frequency calculated result output 1 LRCKO 10 OUT CMOS Audio data latch enable output PSCK0 13 IN Pulldown 5-V tolerant TTL PLL source SCKO output frequency selection 0(1) PSCK1 14 IN Pulldown 5-V tolerant TTL PLL source SCKO output frequency selection 1(1) RST 21 IN Pullup 5-V tolerant TTL Reset control input, active-low (2) RSV 19 IN Pulldown Reserved, must be connected to DGND(1) RXIN 20 IN 5-V tolerant TTL Biphase digital data input(3) SCKO 4 OUT CMOS System clock output UOUT 16 OUT CMOS User data serial output synchronized with LRCKO VCC 24 – Analog power supply, 3.3-V VDD 5 – Digital power supply, 3.3-V CMOSXTI 8 IN Oscillation amplifier input, or external XTI source clock inputSchmitt-trigger XTO 7 OUT CMOS Oscillation amplifier output (1) TTL Schmitt-trigger input with internal pulldown (51 kΩ typical), 5-V tolerant (2) TTL Schmitt-trigger input with internal pullup (51 kΩ typical), 5-V tolerant (3) TTL Schmitt-trigger input, 5-V tolerant. Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: DIR9001

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7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT VCC Supply voltage –0.3 4 V VDD VCC to VDD Supply voltage differences –0.1 0.1 V AGND to Ground voltage differences –0.1 0.1 VDGND Digital input –0.3 6.5Digital input Vvoltage Digital output –0.3 (VDD + 0.3) < 4 XTI, XTO –0.3 (VCC + 0.3) < 4Analog input Vvoltage FILT –0.3 (VCC + 0.3) < 4 Input current (any pins except supplies) –10 10 mA Ambient temperature under bias –40 125 °C Junction temperature 150 °C Lead temperature (soldering) 260 °C Package temperature (reflow, peak) 260 °C Tstg Storage temperature –55 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±500 V(ESD) Electrostatic discharge VCharged-device model (CDM), per JEDEC specification JESD22- ±250C101(2) (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VCC Analog supply voltage 2.7 3.3 3.6 VDC VDD Digital supply voltage 2.7 3.3 3.6 VDC XTI is connected to clock source 24.576 MHz Digital input clock frequency XTI is connected to DGND Not required MHz Digital output load capacitance, except SCKO 20 pF Digital output load capacitance (SCKO) 10 pF TA Operating free-air temperature –40 85 °C

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7.4 Thermal Information

THERMAL METRIC(1) TSSOP (PW) UNIT

28 PINS

RθJA Junction-to-ambient thermal resistance 81.9 °C/W RθJC(top) Junction-to-case (top) thermal resistance 22.5 °C/W RθJB Junction-to-board thermal resistance 40 °C/W ψJT Junction-to-top characterization parameter 0.7 °C/W ψJB Junction-to-board characterization parameter 39.4 °C/W (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics

All specifications at TA = 25°C, VDD = VCC = 3.3 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DIGITAL INPUT/OUTPUT CHARACTERISTICS VIH 0.7 VDD VDD Input logic level(1) VDC VIL 0.3 VDD VIH 2 5.5 Input logic level(2) VDC VIL 0.8 VOH IO = 4 mA 0.85 VDD Output logic level(3) VDC VOL IO = –4 mA 0.15 VDD IIH VIN = VDD 65 100 Input leakage current(4) μA IIL VIN = 0 V –10 10 IIH VIN = VDD –10 10 Input leakage current(5) μA IIL VIN = 0 V –100 –65 IIH VIN = VDD –10 10 Input leakage current(6) μA IIL VIN = 0 V –10 10 BIPHASE SIGNAL INPUT AND PLL Jitter tolerance — (IEC60958-3) IEC60958-3 (2003-01) Compliant RECOVERED CLOCK AND DATA Serial audio data width 16 24 Bit fS = 48 kHz, SCKO = 256 fS, measuredSCKO jitter 50 100 ps rmsperiodic XTI SOURCE CLOCK Frequency accuracy XTI is connected to clock source –100 100 ppm POWER SUPPLY AND SUPPLY CURRENT VCC 2.7 3.3 3.6 Operation voltage range VDC VDD 2.7 3.3 3.6 fS = 96 kHz, PLL locked, XTI connected 6 8.3 mA to DGND ICC Supply current(7) fS = 96 kHz, PLL locked, XTI connected 6 8.3 mA to 24.576-MHz resonator RXIN = H or L, XTI = L, RST = L 130 μA (1) CMOS compatible input: XTI (not 5-V tolerant) (2) 5-V tolerant TTL inputs: RXIN, FMT0, FMT1, PSCK0, PSCK1, CKSEL, RST, RSV (3) CMOS outputs: XTO, SCKO, BCKO, LRCKO, DOUT, UOUT, COUT, BFRAME, ERROR, CLKST, AUDIO, EMPH, FSOUT0, FSOUT1 (4) Internal pulldowns: FMT0, FMT1, PSCK0, PSCK1, CKSEL, RSV (5) Internal pullup: RST (6) No internal pullup and pulldown: RXIN, XTI (7) No load connected to SCKO, BCKO, LRCKO, DOUT, COUT, VOUT, BFRAME, FSOUT0, FSOUT1, CLKST, ERROR, EMPH, AUDIO Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: DIR9001

SLES198A –DECEMBER 2006–REVISED MAY 2015 www.ti.com Electrical Characteristics (continued) All specifications at TA = 25°C, VDD = VCC = 3.3 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fS = 96 kHz, PLL locked, XTI connected 6 8.3 mA to DGND IDD Supply current(7) fS = 96 kHz, PLL locked, XTI connected 9 12.4 mA to 24.576-MHz resonator RXIN = H or L, XTI = L, RST = L 72 μA fS = 96 kHz, PLL locked, XTI connected 40 55 mW to DGND PD Power dissipation (7) fS = 96 kHz, PLL locked, XTI connected 50 68 mW to 24.576-MHz resonator RXIN = H or L, XTI = L, RST = L 0.67 mW TEMPERATURE RANGE TA Operation temperature range –40 85 °C θJA Thermal resistance 28-pin T-SSOP 105 °C/W

7.6 Timing Requirements

All specifications at TA = 25°C, VDD = VCC = 3.3 V (unless otherwise noted) MIN NOM MAX UNIT BIPHASE SIGNAL INPUT AND PLL Input sampling frequency range 28 108 kHz XTI SOURCE CLOCK XTI is connected to clock source 24.576 XTI source clock frequency MHz XTI is connected to DGND Not required XTI input-clock duty cycle XTI is connected to clock source 45% 55% CLKST tCLKST CLKST pulse duration, high 4 20 μs LATENCY tLATE LRCKO/DOUT latency See Figure 14 3/fS s DATA OUTPUT(1) tSCY System clock pulse cycle time 18 ns Delay time of SCK rising edge to BCK risingtSCBC 4 8 15 nsedge tCKLR Delay time of BCKO falling edge to LRCKO valid –5 0.5 0.5 ns See Figure 16tBCY BCKO pulse cycle time 1/64fS s tBCH BCKO pulse duration, HIGH 60 ns tBCL BCKO pulse duration, LOW 60 ns tBCDO Delay time of BCKO falling edge to DOUT valid –5 1 5 ns tr Rising time of all signals 10 ns tf Falling time of all signals 10 ns (1) Load capacitance of the LRCKO, BCKO, and DOUT pins is 20 pF. DOUT, LRCKO, and BCKO are synchronized with SCKO.

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7.7 Switching Characteristics

All specifications at TA = 25°C, VDD = VCC = 3.3 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT BIPHASE SIGNAL INPUT AND PLL From biphase signal detection toPLL lock-up time 100 mserror-out release (ERROR = L) RECOVERED CLOCK AND DATA 128 fS 3.584 13.824 256 fS 7.168 27.648 SCKO frequency MHz 384 fS 10.752 41.472 512 fS 14.336 55.296 BCKO frequency 64 fS 1.792 6.912 MHz LRCKO frequency fS 28 108 kHz SCKO duty cycle 45% 55% Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Links: DIR9001

25 C° –25 C°

7.8 Typical Characteristics

Figure 1. Supply Current vs Locked Sampling Frequency Figure 2. Supply Current vs Locked Sampling Frequency Figure 3. Scko Jitter vs Locked Sampling Frequency

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Audio□Data Formatter ERROR Detector Function Control Audio□Data MUTE Control Channel Status and User□Data Output DIR9001 www.ti.com SLES198A –DECEMBER 2006–REVISED MAY 2015

8 Detailed Description

8.1 Overview

The DIR9001 is a digital audio interface receiver that can receive a 28-kHz to 108-kHz sampling frequency, 24- bit-data-word, biphase-encoded signal and output a serial audio signal. The DIR9001 complies with the jitter specification IEC60958-3, JEITA CPR1205 (Revised version of EIAJ CP-1201), AES3, EBUtech3250, and it can be used in various applications that require a digital audio interface. The DIR9001 supports MSB-first PCM data output in 24-bit I2S, 24-bit left justified, 24-bit right justified, or 16-bit right justified form. Sampling rates of 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, and 96 kHz are supported on the serial audio data output when in PLL mode. All functions which the DIR9001 provides can be controlled directly through control pins. This means that they can be pulled high or low for full operation of the DIR9001 without a microcontroller. A microcontroller can also be used to drive the function pins to provide an adaptable system. Also, as dedicated pins are provided for the channel-status bit and user-data bit, processing of their information can be easily accomplished by connecting with a microcontroller, DSP, and so on. The DIR9001 can derive a system clock by recovering the source’s clock from the biphase input signal. Therefore, the DIR9001 does not require an external clock source or resonator for decode operation if the internal actual-sampling-frequency calculator is not used which in turn can reduce the system cost. The serial audio data output can also be driven by an external source such as a crystal or ceramic resonator. The operating temperature range of the DIR9001 is specified as –40°C to 85°C, which makes it suitable for automotive applications.

8.2 Functional Block Diagram

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8.3 Feature Description

8.3.1 Acceptable Biphase Input Signal and Biphase Input Pin (RXIN)

The DIR9001 can decode the biphase signal format which is specified in one of the following standards. Generally, these following standards may be called Sony/Philips digital interface format (S/PDIF) or AES/EBU.

• IEC60958 (revised edition of former IEC958)
• JEITA CPR-1205 (revised edition of former EIAJ CP-1201, CP-340)
• AES3
• EBU tech3250 The sampling frequency range and data word length which DIR9001 can decode is as follows:
• Sampling frequency range is 28 kHz to 108 kHz.
• Maximum audio sample word length is 24-bit. Note of others about the biphase input signal.
• The capture ratio of the built-in PLL complies with level III of sampling frequency accuracy (±12.5%), which is specified in IEC60958-3.
• The jitter tolerance of the DIR9001 complies with IEC60958-3.
• The PLL may also lock in outside of the specified sampling-frequency range, but extended range is not assured. Notice about the signal level and transmission line of the biphase input signal.
• The signal level and the transmission line (optical, differential, single-ended) are different in each standard.
• The biphase input signal is connected to the RXIN pin of the DIR9001.
• The RXIN pin has a 5-V tolerant TTL-level input.
• An optical receiver module (optical to electric converter) such as TOSLINK, which is generally used in consumer applications, is connected directly to the RXIN pin without added external components.
• The output waveform of the optical receiver module varies depending on the characteristics of each product type, so a dumping resistor or buffer amplifier might be required between the optical receiver module output and the DIR9001 input. Careful handling is required if the optical receiver module and the DIR9001 are separated by a long distance.
• The DIR9001 needs an external amplifier if it is connected to a coaxial transmission line.
• The DIR9001 needs an external differential to single-ended converter, attenuator, etc., for general consumer applications if non-optical transmission line is used.

8.3.2 System Reset

The DIR9001 reset function is controlled by and external reset pin, RST. DIR9001 requires reset operation with a 100-ns period after the supply voltage rises above 2.7 V. Figure 4. Required System Reset Timing

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The state of each output pins during reset is shown in Table 3. Table 3. Output-Pin States During Reset Period

8.3.3 Clock Description

8.3.3.1 System Clock Source

DIR9001 has the following two clock sources for the system clock.

• PLL source (128 fS, 256 fS, 384 fS, 512 fS are available, recovered by built-in PLL)
• XTI source (One 24.576-MHz resonator or external clock source is required.) Two clock sources are used for the following purpose.
• PLL source: Recovered system clock from the biphase input signal
• XTI source: Clock source for peripheral devices (for example, A/D converter, microcontroller, etc.) Measurement reference clock for the internal actual-sampling-frequency calculator Description of PLL clock source
• The PLL clock source is the output clock of built-in PLL (including VCO).
• The PLL clock source frequency is selectable from 128 fS, 256 fS, 384 fS, 512 fS by PSCK[1:0].
• When the PLL is in the locked condition, the PLL clock source is the clock recovered from the biphase input signal.
• When PLL is in the unlocked condition, the PLL clock source is the built-in free-running clock of the VCO.
• The frequency of the PLL clock source in the unlocked condition is not constant. (The VCO free-running frequency is dependent on supply voltage, temperature, and variations in the die’s wafer.) Description of XTI clock source
• The XTI clock source is not used to recover the clock and decode data from the biphase input signal.
• Therefore, if the DIR9001 is used only for recovering the clock and decoding data from the biphase input signal, an XTI clock source is not required. In this case, the XTI pin must be connected to the DGND pin. (The DIR9001 does not have a selection pin for using an XTI clock source or not using one.) The selection method of clock source
• The output clock is selected from two clock sources by the level of the CKSEL pin.
• The selection of the system clock source depends only on the input level of CKSEL pin.
• CKSEL = L setting is required for recovering the clock and decoding data from biphase input.
• CKSEL = H setting is required for XTI clock source output.
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• This method enables selection of the clock source automatically, using the DIR9001 ERROR status. The PLL source clock is output when ERROR = L; the XTI source is output when ERROR = H.
• To enable automatic clock source selection, the CKSEL pin must be connected to the ERROR pin.
• If XTI clock source is needed during the ERROR period, this method is recommended.
• Because the clock source during ERROR status is XTI, if an XTI clock source is not provided to the XTI pin, then SCKO, BCKO, and LRCKO are not output during the ERROR period. The relationship between the clock/data source and the combination of CKSEL pin and PLL status inputs is shown in Table 12. The clock tree system is shown in Figure 5.

Figure 5. Clock Tree Diagram

8.3.4 PLL Clock Source (Built-In PLL and VCO) Description

The DIR9001 has on-chip PLL (including VCO) for recovering the clock from the biphase input signal. The clock that is output from the built-in VCO is defined as the PLL clock source. In the locked state, the built-in PLL generates a system clock that synchronizes with the biphase input signal. The system clock frequency of the PLL is selected by PSCK[1:0]. independent of the setting of PSCK[1:0].

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Table 4. SCKO, BCKO, and LRCKO Frequencies Set by PSCK[1:0] In PLL mode (CKSEL = L), output clocks (SCKO, BCKO, LRCKO) are generated from the PLL source clock. biphase input signal are shown in Table 5. Table 5. Output Clock Frequency in PLL Locked State (CKSEL = L)

8.3.5 Required PLL Loop Filter Description

The DIR9001 incorporates a PLL for generating a clock synchronized with the biphase input signal. The built-in PLL requires an external loop filter, which is specified as follows. Operation and performance is assured for recommended filter components R1, C1, and C2.

• The resistor and capacitors which comprise the filter should be located and routed as close as possible to the DIR9001.
• A carbon film resistor or metal film resistor, with tolerance less than 5%, is recommended.
• Film capacitors, with tolerance is less than 5%, is recommended.
• If ceramic capacitors are used for C1 and C2, parts with a low voltage coefficient and low temperature coefficient, such as CH or C0G, are recommended.
• The external loop filter must be placed on FILT pins.
• The GND node of the external loop filter must be directly connected with the AGND pin of the DIR9001; it must be not combined with other signals. The configuration of external loop filter and the connection with the DIR9001 is shown in Figure 6.

Figure 6. Loop Filter Connection

The recommended values of loop filter components is shown in Table 6. Table 6. Recommended Value of Loop Filter Components

8.3.6 XTI Clock Source and Oscillation Amplifier Description

the XTI source. A 24.576-MHz fundamental resonator or external 24.576-MHz clock is used as the XTI source.

• The measurement reference clock of actual-sampling-frequency calculator
• The clock source for the XTI source mode (CKSEL = H setting) (That is, the DIR9001 does not require an XTI source if it is only decoding the biphase input signal.) The XTI clock source is supplied in one of the following two ways; the details are described in Figure 7.
• Setting up an oscillation circuit by connecting a resonator with the built-in amplifier
• Applying a clock from an external oscillator circuit or oscillator module To set up an oscillation circuit by connecting a resonator with the built-in amplifier:
• Connect a 24.576-MHz resonator between the XTI pin and XTO pin.
• The resonator should be a fundamental-mode type.
• A crystal resonator or ceramic resonator can be used.
• The load capacitor CL1, CL2, and the current-limiting resistor Rd depend on the characteristics of the resonator.
• No external feedback resistor between the XTI pin and XTO pin is required, as an appropriate resistor is incorporated in the device.
• No load other than the resonator is allowed on the XTO pin. To connect an external oscillator circuit or oscillator module:
• Provide a 24.576-MHz clock on the XTI pin
• Note that the XTI pin is not 5-V tolerant; it is simple CMOS input.
• The XTO pin must be open.

Figure 7. XTI and XTO Connection Diagram

• The built-in oscillation amplifier is always working.
• If the XTI source clock is not used, then the XTI pin must be connected to DGND.
• For reducing power dissipation, it is recommended to not use the XTI source clock. In XTI mode (CKSEL = H), output clocks (SCKO, BCKO, LRCKO) are generated from XTI source clock. The relation between output clock frequency (SCKO, BCKO, LRCKO) and the XSCK pin setting in XTI source mode is shown in Table 7.

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Table 7. SCKO, BCKO, LRCKO Output Frequency at XTI Mode

8.3.7 Channel-Status Data and User Data Serial Outputs

Each output data has its own dedicated output pin. Channel-status data (C, hereinafter) is output through COUT pin. User data (U, hereinafter) is output through UOUT pin. The C and U outputs are synchronized with LRCKO recovered from the biphase input signal. The polarity of LRCKO recovered from the biphase input signal depends on FMT[1:0] setting. For detecting the top of the block of channel-status data or user data, the BFRAME pin is provided. output pulse on the BFRAME pin is used as the top-of-block signal. The relationship among LRCKO, BFRAME, DOUT, COUT, and UOUT is shown in Figure 8. When in the XTI mode and the PLL-locked state, COUT and UOUT output L. NOTE: The numbers 0 through 191 of DOUT, COUT, and UOUT indicate frame numbers of the biphase input. Figure 8. LRCKO, DOUT, BFRAME, COUT, UOUT Output Timing

8.3.8 Channel-Status Data Information Output Terminal

channel-status data on the COUT pin, which is synchronized with biphase input signal, can be used.

These outputs are synchronized with the top of block. The information that can be output through the dedicated pins is shown as follows.

8.3.8.1 AUDIO Pin

This is the output pin for the audio sample word information of the channel-status data bit 1. Table 8. Audio Sample Word Information L Audio sample word represents linear PCM samples. H Audio sample word is used for other purposes.

8.3.8.2 EMPH Pin

This is the output pin for the emphasis information of the channel-status data bit 3. Table 9. Pre-Emphasis Information NOTE: The numbers 0 through 191 of DOUT indicate frame numbers of the biphase input. Figure 9. AUDIO and EMPH Output Timing

8.3.9 Errors And Error Processing

8.3.9.1 Error Output Description

• PLL responds with unlock for data in which the rule of biphase encoding is lost (biphase error and frame- length error).
• PLL responds with unlock for data in which the preamble B, M, W can not be detected. Error processing function and error output pins
• The DIR9001 has a data error detect function and an error output pin, ERROR.
• The ERROR pin is defined as the logical OR of data error and parity error detection.
• The ERROR rising edge is synchronized with CLKST.
• The ERROR falling edge is synchronized with LRCK. The relationship between data error and detected parity error is shown in Figure 10.

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Figure 10. ERROR Output The state of the ERROR pin and the details of error are shown in Table 10. Table 10. State of ERROR Output Pin

8.3.9.2 Parity Error Processing

• For PCM data, interpolation processing by previous data is performed.
• For non-PCM data, interpolation is not performed and data is directly output with no processing. (Non-PCM data is data with channel-status data bit 1 = 1.) The processing for parity error occurrence is shown in Figure 11.

Figure 11. Processing for Parity Error Occurrence

8.3.9.3 Other Error

frequency causes the PLL to lose lock.

8.3.10 Calculation of Actual Sampling Frequency

as a measurement reference clock to calculate the actual sampling frequency. If the XTI pin is connected to DGND, calculation of the actual sampling frequency is not performed. If there is an error in the XTI clock frequency, the calculation result and range are shifted correspondingly. channel-status data (bit 24–bit 27). The sampling frequency information of the channel-status data (bit 24–bit 27) is not output through these pins. The calculation result is decoded into 2-bit data, which is output on the FSOUT[1:0] pins. output to indicate an abnormality. When the XTI source clock is not supplied before power on, FSOUT [1:0] always outputs LL. When the XTI source clock is stopped, the fS calculator holds the last value of the fS calculator result. If XTI source clock is supplied, the fS calculator resumes operation. The calculated value is held until reset. The relationship between the FSOUT[1:0] outputs and the range of sampling frequencies is shown in Table 11. Table 11. Calculated Sampling Frequency Output

8.4 Device Functional Modes

8.4.1 Operation Mode and Clock Transition Signal Out

8.4.1.1 Operation Mode

The DIR9001 has the following three operation modes. These modes are selected by the connection of the CKSEL pin.

• PLL MODE: For demodulating a biphase input signal; always outputs PLL source clock
• XTI MODE: For clock generator; always outputs XTI source clock
• AUTO MODE: Automatic clock source selection; output source depends on ERROR pin. Notes about operation mode selection:
• Normally, the PLL mode: CKSEL = L is selected to decode a biphase input signal.
• The XTI mode is a mode that supplies the XTI source clock to peripheral devices (A/D converters, etc); therefore, recovered clock and decoded data is not output.
• When the XTI source is not used, an XTI source is not required. In this case, clocks are not output in the XTI mode.
• At the time of XTI mode selection, biphase decode function continues to operate. Therefore, the biphase input status (ERROR) and the result of the sampling frequency calculator (a required XTI source for operation), are always monitored. That is, the following output pins: ERROR, BFRAME, FSOUT[1:0], CLKST, AUDIO and EMPH are always enabled.

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The details of these three modes are given in Table 12. Table 12. Operation Mode and Clock Source temperature, and process variations. Figure 12. Clock Source, Source Selector and Data Path

8.4.1.2 Clock Transition Signal Out

The DIR9001 provides an output pulse that is synchronized with the PLL’s LOCK/UNLOCK status change. only on the status change of the PLL. This clock change/transition signal is output through CLKST. appropriate functions in an application. A clock source selection caused by the CLKSEL pin does not affect the output of CLKST.

Note: means clock source change. CLKST does change due to PLL status change even if CKSEL = H in the XTI source mode. not output. That is, the priority of reset is higher than CLKST. BCKO, LRCKO), and data (DOUT) is shown in Figure 13. Figure 13. Lock-In and Unlock Process

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8.5 Programming

8.5.1 Data Description

8.5.1.1 Decoded Serial Audio Data Output and Interface Format

The DIR9001 supports following 4-data formats for the decoded data.

• 16-bit, MSB-first, right-justified
• 24-bit, MSB-first, right-justified
• 24-bit, MSB-first, left-justified
• 24-bit, MSB-first, I2S Decoded data is MSB first and 2s-complement in all formats. The decoded data is provided through the DOUT pin. The format of the decoded data is selected by the FMT[1:0] pins. The data formats for each FMT[1:0] pin setting are shown in Table 13.

Table 13. Serial Audio Data Output Format Set by FMT[1:0] Figure 14. Latency Time Between Biphase Input and LRCKO/DOUT The relationships among BCKO, LRCKO, and DOUT for each format are shown in Figure 15.

Figure 15. Decoded Serial Audio Data Output Formats

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Figure 16. Decoded Audio Data Output Timing

SLES198A –DECEMBER 2006–REVISED MAY 2015 www.ti.com

9 Application and Information

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

9.1 Application Information

The DIR9001 is an audio receiver capable of accepting S/PDIF, EIAJ CP-1201, IEC60958, and AES/EBU up to a 108-kHz sampling rate. When receiving a biphase differential signal, a clock can be recovered to be used as a master clock or use an external crystal. 16-bit and 24-bit PCM serial audio data can be output in master mode. All settings are controlled in hardware by setting pins high or low, this can be done with pull up/down resistors or with GPIO from a microcontroller. User and channel data from the S/PDIF or AES/EBU standard is processed and output at the UOUT and COUT pins. BFRAME is a synching signal meant to indicate the start of a frame of information. A 3.3-V analog and 3.3-V digital supply are required, this could come from the same 3.3-V supply or separate supplies.

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Product Folder Links: DIR9001

9.2 Typical Application

Figure 17 illustrates typical circuit connection. R2: Current-limiting resistor; generally, a 100 Ω–500 Ω resistor is used, but it depends on the crystal resonator. C1: Loop filter capacitor, 0.068 μF. C2: Loop filter capacitor, 0.0047 μF. C5, C8: 10-μF electrolytic capacitor typical, depending on power-supply quality and PCB layout. C6, C7: 0.1-μF ceramic capacitor typical, depending on power-supply quality and PCB layout. X1: Crystal resonator, use a 24.576-MHz fundamental resonator when XTI clock source is needed. Figure 17. Typical Circuit Connection Diagram

9.2.1 Design Requirements

• Control: Hardware
• Audio Input: Biphase differential signal
• Audio Output: PCM serial audio data
• Master Clock: 24.576-MHz crystal Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback 27 Product Folder Links: DIR9001

9.2.2 Detailed Design Procedure

• Hardware control with GPIO of microcontroller
• Select crystal capacitors by reading the crystal data sheet
• Select if system will be run off the recovered clock or the external crystal by setting CKSEL high for the external crystal and low for the recovered clock
• Decide sampling rate and audio related settings
• Configure microcontroller to receive PCM data along with User and Channel data from S/PDIF or AES/EBU data stream

9.2.3 Application Curve

Figure 18. SCKO Jitter vs Locked Sampling Frequency

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10 Power Supply Recommendations

The DIR9001 requires that 3.3 V be supplied to the digital VDD pin and analog VCC pin. For better separation of analog and digital components two supplies can be used but is not required. Decoupling capacitors for the power supplies should be placed close to the device terminals. For both VDD and VCC, a 10-µF and 0.1-µF capacitor should be used.

11 Layout

11.1 Layout Guidelines

• Use a ground plane with multiple vias for each terminal to create a low-impedance connection to GND for minimum ground noise.
• A single common GND plane between AGND and DGND is recommended to avoid a potential voltage difference between them. To avoid signal interference between digital and analog signals, take care to separate analog and digital signals and return paths.
• Use supply decoupling capacitors as shown in Figure 17 and described in Power Supply Recommendations.
• Series resistors can be used on MCLK, LRCK, and BCK to reduce or eliminate reflections and noise. These are to be tuned as each PCB is different but the resistors are usually below 50 Ohms. Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback 29 Product Folder Links: DIR9001

11.2 Layout Example

Figure 19. Layout Example

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12 Device and Document Support

12.1 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.

12.2 Trademarks

SpAct, E2E are trademarks of Texas Instruments. All other trademarks are the property of their respective owners.

12.3 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

12.4 Glossary

SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback 31 Product Folder Links: DIR9001

www.ti.com 10-Nov-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) DIR9001PW Active Production TSSOP (PW) | 28 50 | TUBE Yes NIPDAU Level-1-260C-UNLIM -40 to 85 DIR9001 DIR9001PW.B Active Production TSSOP (PW) | 28 50 | TUBE Yes NIPDAU Level-1-260C-UNLIM -40 to 85 DIR9001 DIR9001PWG4 Active Production TSSOP (PW) | 28 50 | TUBE Yes NIPDAU Level-1-260C-UNLIM -40 to 85 DIR9001 DIR9001PWG4.B Active Production TSSOP (PW) | 28 50 | TUBE Yes NIPDAU Level-1-260C-UNLIM -40 to 85 DIR9001 DIR9001PWR Active Production TSSOP (PW) | 28 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 DIR9001 DIR9001PWR.B Active Production TSSOP (PW) | 28 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 DIR9001 (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

www.ti.com 10-Nov-2025 OTHER QUALIFIED VERSIONS OF DIR9001 :

• Automotive : DIR9001-Q1 NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 10-Aug-2026 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 10-Aug-2026 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DIR9001PWR TSSOP PW 28 2000 350.0 350.0 43.0 Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 10-Aug-2026 TUBE L - Tube length T - Tube height W - Tube width B - Alignment groove width *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) DIR9001PW PW TSSOP 28 50 530 10.2 3600 3.5 DIR9001PW.B PW TSSOP 28 50 530 10.2 3600 3.5 DIR9001PWG4 PW TSSOP 28 50 530 10.2 3600 3.5 DIR9001PWG4.B PW TSSOP 28 50 530 10.2 3600 3.5 Pack Materials-Page 3

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