DG401 RENESAS
Document overview
- Manufacturer or author: Provided By www.digicamel.com(free datasheet download site)
- PDF pages: 12
Technical content
Features
- Fast Switching Action
- Low Charge Injection
- DG401 Dual SPST; Same Pinout as HI-5041
- DG403 Dual SPDT; DG190, IH5043, IH5151, HI-5051
- TTL, CMOS Compatible
- Single or Split Supply Operation
- Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
- Audio Switching
- Battery Operated Systems
- Data Acquisition
- Hi-Rel Systems
- Sample and Hold Circuits
- Communication Systems
- Automatic Test Equipment D NC NC NC NC NC D NC GND V L IN IN1 D NC NC GND VL IN2 IN1
Ordering Information
NUMBER* PART MARKING TEMP . RANGE (°C) PACKAGE PKG. DWG. # DG401DY* DG401DY -40 to +85 16 Ld SOIC M16.15 DG401DYZ* (Note) DG401DYZ -40 to +85 16 Ld SOIC (Pb-free) M16.15 DG401DVZ* (Note) DG401 DVZ -40 to +85 16 Ld TSSOP (Pb-free) M16.173 DG403DY* DG403DY -40 to +85 16 Ld SOIC M16.15 DG403DYZ* (Note) DG403DYZ -40 to +85 16 Ld SOIC (Pb-free) M16.15 DG403DVZ* (Note) DG403 DVZ -40 to +85 16 Ld TSSOP (Pb-free) M16.173 *Add “-T” suffix for tape and reel. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
DG401, DG403 FN3284 Rev 11.00 Page 2 of 12 Nov 20, 2006 Schematic Diagram TRUTH TABLE LOGIC DG401 DG403 SWITCH SWITCH 1, 2 SWITCH 3, 4 0O F F O F F O N 1O N O N O F F NOTE: Logic “0” 0.8V. Logic “1” 2.4V. Functional Diagrams DG401 DG403 SWITCHES SHOWN FOR LOGIC “1” INPUT 1S1 IN1 IN2 VL V+ GND V- 12 11 13 14 IN1 IN2 VL V+ GND V- 12 11 13 14 VL VIN GND DRAIN SOURCE
DG401, DG403 FN3284 Rev 11.00 Page 3 of 12 Nov 20, 2006 Absolute Maximum Ratings Thermal Information Whichever Occurs First Peak Current, S or D (Pulsed 1ms, 10% Duty Cycle, Max). . 100mA Operating Conditions Thermal Resistance (Typical, Note 2) JA (°C/W) (SOIC and TSSOP- Lead Tips Only) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. Signals on SX, DX, or INX exceeding V+ or V- will be clamped by internal diodes. Limit forward diode current to maximum current ratings. 2. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. Electrical Specifications Test Conditions: V+ = +15V, V- = -15V, VIN = 2.4V, 0.8V (Note 3), VL = 5V, Unless Otherwise Specified PARAMETER TEST CONDITIONS TEMP (°C) (NOTE 4) MIN (NOTE 5) TYP (NOTE 4) MAX UNITS DYNAMIC CHARACTERISTICS Turn-ON Time, tON RL = 300, CL = 35pF +25 - 100 150 ns Turn-OFF Time, tOFF +25 - 60 100 ns Break-Before-Make Time Delay (DG403), tD RL = 300, CL = 35pF +25 5 12 - ns Charge Injection, Q (Figure 3) C L = 10nF, VG = 0V, RG = 0 +25 - 60 - pC OFF Isolation (Figure 4) R L = 100, CL = 5pF, f = 1MHz +25 - 72 - dB Crosstalk (Channel-to-Channel) (Figure 6) +25 - -90 - dB Source OFF Capacitance, CS(OFF) f = 1MHz, VS = VD = 0V (Figure 7) +25 - 12 - pF Drain OFF Capacitance, CD(OFF) +25 - 12 - pF Channel ON Capacitance, CD(ON) + CS(ON) +25 - 39 - pF DIGITAL INPUT CHARACTERISTICS Input Current with V IN Low, IIL VIN Under Test = 0.8V, All Others = 2.4V Full -1 0.005 1 A Input Current with VIN High, IIH VIN Under Test = 2.4V, All Others = 0.8V Full -1 0.005 1 A ANALOG SWITCH CHARACTERISTICS Analog Signal Range, V ANALOG Full -15 - 15 V Drain-Source ON Resistance, rDS(ON) V+ = 13.5V, V- = -13.5V, IS = 10mA, V D = 10V +25 - 20 45 Full - - 55 rDS(ON) Matching Between Channels, rDS(ON) V+ = 16.5V, V- = -16.5V, IS = -10mA, VD = 5, 0, -5V +25 - 3 3 Full - - 5 Source OFF Leakage Current, IS(OFF) V+ = 16.5V, V- = -16.5 VD = 15.5V, VS = 15.5V Full -5 - 5 nA Drain OFF Leakage Current, ID(OFF) +25 -0.5 -0.01 0.5 nA Full -5 - 5 nA Channel ON Leakage Current, ID(ON) +I S(ON) V = 16.5V, VD = VS = 15.5V +25 -1 -0.04 1 nA Full -10 - 10 nA
FIGURE 28. SWITCHING TIME vs POSITIVE SUPPLY VOLTAGE (NOTE 8)
- Refer to Figure 1 for test conditions.
DG401, DG403 FN3284 Rev 11.00 Page 11 of 12 Nov 20, 2006 Thin Shrink Small Outline Plastic Packages (TSSOP) NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-153-AB, Issue E. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E1” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimen- sions are not necessarily exact. (Angles in degrees) INDEX AREA D N 123 -B- 0.10(0.004) C AM BS e -A- b M -C- A SEATING PLANE 0.10(0.004) c E 0.25(0.010) BM M L 0.25 0.010 GAUGE PLANE 0.05(0.002) M16.173
16 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE
A - 0.043 - 1.10 - A1 0.002 0.006 0.05 0.15 - A2 0.033 0.037 0.85 0.95 - b 0.0075 0.012 0.19 0.30 9 c 0.0035 0.008 0.09 0.20 - D 0.193 0.201 4.90 5.10 3 E1 0.169 0.177 4.30 4.50 4 e 0.026 BSC 0.65 BSC - E 0.246 0.256 6.25 6.50 - L 0.020 0.028 0.50 0.70 6 N1 6 1 6 7 0° 8° 0° 8° - Rev. 1 2/02
FN3284 Rev 11.00 Page 12 of 12 Nov 20, 2006 DG401, DG403 Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com For additional products, see www.intersil.com/en/products.html © Copyright Intersil Americas LLC 1999-2006. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. Small Outline Plastic Packages (SOIC) NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. INDEX AREA E D N 123 -B- 0.25(0.010) C AM BS e -A- L B M -C- A SEATING PLANE 0.10(0.004) h x 45° C H 0.25(0.010) BM M M16.15 (JEDEC MS-012-AC ISSUE C)
16 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
A 0.0532 0.0688 1.35 1.75 - A1 0.0040 0.0098 0.10 0.25 - B 0.013 0.020 0.33 0.51 9 C 0.0075 0.0098 0.19 0.25 - D 0.3859 0.3937 9.80 10.00 3 E 0.1497 0.1574 3.80 4.00 4 e 0.050 BSC 1.27 BSC - H 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 L 0.016 0.050 0.40 1.27 6 N1 6 1 6 7 0° 8° 0° 8° - Rev. 1 6/05