RAA236100 RENESAS
Document overview
- Manufacturer or author: Provided By www.digicamel.com(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 37
Technical content
Datasheet sections
- 1.1 Block Diagram
- 2.1 Pin Assignments
- 2.2 Pin Descriptions
- 3.1 Absolute Maximum Ratings
- 3.2 Recommended Operation Conditions
- 3.3 Thermal Specifications
- 3.4 Electrical Specifications
- 5.1 Output Voltage and VSEL for RAA236100 (I 2C Variant)
- 5.2 Output Voltage and Input Current Li mit for RAA236105 (Current Limit variant)
- 5.3 Power-On Sequencing
- 5.3.1 RAA236100
- 5.3.2 RAA236105
- 5.4 VIN Ramp Rate
- 5.5 Input Current Limit (ICL)
- 5.6 Dynamic Voltage Scaling (DVS)
- 5.7 Soft Discharge
- 5.8 Device Protection
- 5.8.1 Undervoltage Lockout (UVLO)
- 5.8.2 Overcurrent and Undervoltage Protection
- 5.8.3 Thermal Shutdown
- 5.9 Output Discharge and Pre-Bias Startup
- 5.10 Audible Noise Prevention
- 5.11 Buck-Boost Conversion Topology
- 5.11.1 Pulse Width Modulation (PWM) Operation
- 5.11.2 Pulse Frequency Modulation (PFM) Operation
- 5.11.3 Operation With V IN Close to VOUT
- 5.11.4 Forced Operating Modes
- 5.11.5 Adaption Scheme for Zero Crossing Detector
- 6.1 I 2C General Operation
- 6.1.1 Data Validity
- 6.1.2 START and STOP Condition
- 6.1.3 Byte Format
- 6.1.4 Acknowledge (ACK)
- 6.1.5 Not Acknowledge (NACK)
- 6.1.6 Device Address and R/W Bit
- 6.2 RAA236100 Communication Protocol
- 6.2.1 Device Addresses Byte
- 6.2.2 Register Size
- 6.2.3 I 2C Write Operation
Features
▪ Single output buck-boost converter ▪ 130nA input quiescent current ▪ 96% peak efficiency (VIN = 3.6V; VOUT = 3.3V) ▪ Output current: up to 400mA (VIN > 2.5V, VOUT =3 . 3 V ) ▪ Input voltage range: 1.8V to 5.5V, supports single-cell Li-ion, 2x or 3×1.5V AA/AAA batteries ▪ Output voltage range: 1.8V to 5.0V ▪ Output voltage control using a pin reader (RAA236105) ▪ Selectable input current limit ▪ DVS with settable slew rate control ▪ Selectable forced bypass power saving mode ▪ PWM/PFM and buck/boost with seamless transition ▪ Ultrasonic mode for audible noise suppression ▪ I2C control and voltage adjustability (RAA236100 only)
- Standard, Fast, and High-Speed mode ▪ 10-Ld DFN package ▪ Pb-free (RoHS compliant)
Applications
▪ Smart watches/wristbands, wireless earphones ▪ Internet of Things (IoT) devices ▪ Water, gas, and oil meters ▪ Energy harvesting Versions ▪ I2C interface (RAA236100) ▪ Pin reader output voltage with input current limit (RAA236105) RAA236100, RAA236105 Ultra-low IQ Buck-Boost Regulators with Bypass
R16DS0419EU0103 Rev.1.03 Page 4 Jan 24, 2025 RAA236100, RAA236105 Datasheet
1.1 Block Diagram
Figure 3. Block Diagram
2.1 Pin Assignments
2.2 Pin Descriptions
Figure 4. 10 Ld DFN (RAA236100) - Top View Figure 5. 10 Ld DFN (RAA236105) - Top View Table 1. RAA236100 Pin Descriptions 1 EN Input Active high, device enable input. Do not leave floating. 3 BYPASS Input Active high, buck-boost forced bypass control input. Do not leave floating. 4 SDA Input/Output I2C bi-directional serial data connection (high impedance input / open drain output). Pull down to GND if not being used. Do not leave floating. used. Do not leave floating. 6 VOUT Output Buck-boost converter output voltage pin. 7 LX2 Power Switch node for boost, output side terminal of the inductor. 8 GND Ground Main controller ground pin. 9 LX1 Power Switch node for the buck, input side terminal of the inductor. 10 VIN Input Input voltage supply pin.
Table 2. RAA236105 Pin Descriptions 1 EN Input Active high, device enable input. Do not leave floating. 2 RSVD - Reserved. Do not leave floating. Pull down to GND. 3 BYPASS Input Active high, buck-boost forced bypass control input. Do not leave floating. 4 ILIM Input Pin reader input to set the input current limit. Do not leave floating. 5 VSET Input Pin reader input to set the output voltage target. Do not leave floating. 6 VOUT Output Buck-boost converter output voltage pin. 7 LX2 Power Switch node for boost, output side terminal of the inductor. 8 GND Ground Main controller ground pin. 9 LX1 Power Switch node for the buck, input side terminal of the inductor. 10 VIN Input Input voltage supply pin.
R16DS0419EU0103 Rev.1.03 Page 8 Jan 24, 2025 RAA236100, RAA236105 Datasheet 3. Specifications
3.1 Absolute Maximum Ratings
Caution: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions can adversely impact product reliability and result in failures not covered by warranty.
3.2 Recommended Operation Conditions
3.3 Thermal Specifications
Parameter[1] 1. Voltage (to GND unless otherwise stated) Minimum Maximum Unit VIN, VOUT -0.3 6.0 V LX1, LX2 -0.3 6.0 V LX1, LX2 (less than 10ns) -2 8 V All other pins -0.3 6.0 V Maximum Junction Temperature (T J)- + 1 2 5 ° C Maximum Storage Temperature Range (TS)- 6 5 + 1 5 0 ° C Human Body Model (Tested per JS-001-2023) - ±2k V Charged Device Model (Tested per JS-002-2022) - ±1k V Latch-Up (Tested per JESD78E; Class 2, Level A) - 100 mA Parameter [1] 1. Voltages referred to GND unless otherwise stated. Minimum Maximum Unit Ambient Temperature Range (TA)- 4 0 + 8 5 ° C Supply Voltage (VIN) Range 1.8 5.5 V Load Current (IOUT) Range (DC) 0 400 mA Effective Output Capacitance (COUT)6 - µ F Effective Input Capacitance (CIN)5 - µ F Parameter Package Symbol Conditions Typical Value Unit Thermal Resistance 10 Ld DFN Package θJA[1] 1. θJA is measured in free air with the component mounted on a high-effective thermal conductivity test board with direct attach features. See TB379. Junction to ambient 75 °C/W θJC[2] 2. For θJC, the case temperature location is the center of the exposed metal pad on the package underside. See TB379. Junction to case 29 °C/W
R16DS0419EU0103 Rev.1.03 Page 9 Jan 24, 2025 RAA236100, RAA236105 Datasheet
3.4 Electrical Specifications
VIN = VEN =4 . 0 V , VOUT= 3.3V, I2C pull-up voltage = VIN, L1 = 1µH, C1 = 10µF, effective C2 = 6µF, TA = +25°C, unless specified otherwise Boldface limits apply across the recommended operating temperature range (-40°C to +85°C) and input voltage range (1.8V to 5.5V), unless specified otherwise. Parameter Symbol Test Conditions [1] Min[2] Typ Max [2] Unit Power Supply Input Voltage Range V IN - 1.8 - 5.5 V VIN Undervoltage Lockout Threshold and Hysteresis VUVLO_R VIN rising 1.62 - 1.78 V HYSTUVLO - 3 54 68 0 m V VIN Quiescent Current I Q No switching; VIN =4 . 0 V , VOUT = 3.5V overdriven -1 3 0 750 nA VOUT Quiescent Current IQ_VOUT VIN = 4.0V, VOUT =3 . 5 V - 1 0 0 1 4 0 n A VIN Supply Current Shutdown ISD EN = LOW - 22 110 nA VIN Supply Current, Standby (RAA236100) ISTBY EN = HIGH, shutdown using I2C register - 45 150 nA VIN Supply Current, Forced Bypass Mode IFBYP Forced Bypass Mode using I2C register or VBYPASS =H I G H -1 0 5- n A Output Voltage Regulation Output Voltage Range V OUT VIN = 1.8V to 5.5V, IOUT =1 m A 1.8 3.3 5.0 V Output Voltage Accuracy VOUT_ACC VIN = 4.0V, VOUT =3 . 3 V IOUT = 1mA, PFM -3.0 - +3.0 % VIN = 4.0V, VOUT =3 . 3 V IOUT = 100µA, PWM -3.0 - +3.0 % Output Voltage Resolution VOUT_STEP I2C enabled - 50 - mV Output Voltage Resolution Pin Reader VOUT_STEP_PR I2C disabled; Pin Reader enabled (RAA236105) -1 0 0- m V Output Voltage Ripple V OUT_RIP VIN = 3.6V, VOUT =3 . 3 V , IOUT = 1mA, PFM mode -8 0- m V P-P VIN = 3.6V, VOUT =3 . 3 V , IOUT = 1mA, PWM mode -1 5- m V P-P Load Regulation V OUT_LOAD_REG VIN =3 . 6 V , VOUT =3 . 3 V , ILOAD 0mA vs. 400mA -± 1- % Line Regulation V OUT_LINE_REG VOUT =3 . 3 V , ILOAD =1 2 0 m A , VIN 1.8V vs. 5.5V -± 0 . 5- % Soft-Start and Soft Discharge Time to read OTP (RAA236100) tOTP_I2C Time from when VIN > VUVLO_R and EN signal asserts to when output voltage ramp starts. V IN ramp rate faster than 3V/ms -4 0 0- µ s
R16DS0419EU0103 Rev.1.03 Page 10 Jan 24, 2025 RAA236100, RAA236105 Datasheet Time to read OTP (RAA236105) tOTP_PR Time from when VIN > VUVLO_R and EN signal asserts to when output voltage ramp starts. VIN ramp rate faster than 3V/ms -4 0 0- µ s V OUT Ramp Rate for Soft-Start DVSRATE Default at POR - 3.125 - mV/µs Programmable using I2C after POR (only RAA36100) 6.25 1.5625 0.78125 -m V / µ s VOUT Soft Discharge Resistance (RAA236100) r DISCHG EN < ENIL or shutdown using I2C register -1 2 5- Ω Inrush current amplitude IRUSH IOUT = 1mA, output cap C2 as specified. Does not include current into input cap C1 -0 . 5- A P-Channel MOSFET ON-Resistance (Buck) rDS(ON)_A VIN = 3.6V, VOUT = 3.6V -9 0- m Ω N-Channel MOSFET ON-Resistance (Buck) rDS(ON)_B -9 0- m Ω P-Channel MOSFET ON-Resistance (Boost) rDS(ON)_D -9 0- m Ω N-Channel MOSFET ON-Resistance (Boost) rDS(ON)_C -9 0- m Ω P-Channel MOSFET ON-Resistance (Bypass) r DS(ON)_E -1 . 3- Ω Inductor Peak Current Limit Peak Current Limit I LIM 2.5V < VIN ≤ 5.5V - 2 - A 1.8V ≤ VIN ≤ 2.5V - 1.8×(V IN/2) - A Output Current Maximum Load Current [3] IOUT_MAX VIN and VOUT ≥ 2.5V (Buck Mode) 400 - - mA Maximum Current Derating at Minimum V IN[3] IOUT_MAX_DERATING VIN = 1.8V, VOUT = 5.0V 86.4 - - mA VIN = VEN =4 . 0 V , VOUT= 3.3V, I2C pull-up voltage = VIN, L1 = 1µH, C1 = 10µF, effective C2 = 6µF, TA = +25°C, unless specified otherwise Boldface limits apply across the recommended operating temperature range (-40°C to +85°C) and input voltage range (1.8V to 5.5V), unless specified otherwise. (Cont.) Parameter Symbol Test Conditions [1] Min[2] Typ Max [2] Unit
R16DS0419EU0103 Rev.1.03 Page 11 Jan 24, 2025 RAA236100, RAA236105 Datasheet Input Current Limit Function (RAA236100 and RAA236105) Average Current Limit on the input ICL VIN = 4.0V, VOUT under ridden, ICL setting=1mA -1- m A VIN = 4.0V, VOUT under ridden, ICL setting=2mA -2- m A VIN = 4.0V, VOUT under ridden, ICL setting=5mA -5- m A VIN = 4.0V, VOUT under ridden, ICL setting=10mA -1 0- m A VIN = 4.0V, VOUT under ridden, ICL setting=20mA -2 0- m A VIN = 4.0V, VOUT under ridden, ICL setting=50mA -5 0- m A Efficiency Efficiency η VIN = 3.6V, VOUT = 5.0V, IOUT = 50mA -9 4- VIN = 3.6V, VOUT = 3.3V, IOUT = 50mA -9 6- VIN = 3.6V, VOUT = 1.8V, IOUT = 50mA -9 1- VIN = 3.6V, VOUT = 5.0V, IOUT = 10µA -9 2- VIN = 3.6V, VOUT = 3.3V, IOUT = 10µA -9 2- VIN = 3.6V, VOUT = 1.8V, IOUT = 10µA -8 6- Switching Frequency Regulator switching frequency fSW_PWM VIN = 3.6V, VOUT = 1.8V, IOUT = 1mA, Forced PWM -2 . 0- M H z fSW_US VIN = 3.6V, VOUT = 1.8V, IOUT = 0mA, Ultrasonic Mode (RAA236100) -4 2- k H z Fault Management Hiccup Time t HICCUP Fault occurrence time from shutdown to restart -1 0 0- m s Thermal Shutdown Temperature TSD Temperature Rising - 140 - °C Thermal Shutdown Hysteresis TSD_HYST Temperature Falling - 20 - °C VIN = VEN =4 . 0 V , VOUT= 3.3V, I2C pull-up voltage = VIN, L1 = 1µH, C1 = 10µF, effective C2 = 6µF, TA = +25°C, unless specified otherwise Boldface limits apply across the recommended operating temperature range (-40°C to +85°C) and input voltage range (1.8V to 5.5V), unless specified otherwise. (Cont.) Parameter Symbol Test Conditions [1] Min[2] Typ Max [2] Unit
Figure 26. Output Short-Circuit Behavior; Hiccup Mode Figure 27. Output Short-Circuit Behavior;
between PFM and PWM modes are seamless as well.
5.1 Output Voltage and VSEL for RAA236100 (I 2C Variant)
LSB of bckBst_0 and bckBst_1 registers are for the output voltage setting. using the bckBst slew rate bits of the STARTUP DISCHARGE register.
5.2 Output Voltage and Input Curren t Limit for RAA236105 (Current Limit
the complete set of decoded combinations. Table 3. Pin Reader Resistor (REXT) Decoding for Current Limit
5.3 Power-On Sequencing
5.3.1 RAA236100
undervoltage lockout threshold. First, the IC is initialized, and its One-Time Programmable (OTP) memory is read. and the output voltage rises at the default ramp rate until it reaches the target output voltage. The I2C interface (RAA236100) is active within 120µs of EN going high and remains active as long as VIN>UVLO. Table 4. Pin Reader Resistor (REXT) Decoding for Output Voltage Table 3. Pin Reader Resistor (REXT) Decoding for Current Limit (Cont.)
at which VOUT comes up. VOUT ramp rate is about 3.12V/ms. A typical power-on sequence is seen in Figure 28. EN pin can be tied to the PVIN. See Electrical Specifications for pin capability. not reset the register values.
5.3.2 RAA236105
EN pin can be tied to the PVIN. See Electrical Specifications for pin capability. device is disabled by driving EN LOW, the output discharges naturally based on the load current.
5.4 VIN Ramp Rate
when VIN = 3.6V, if ramp time > 500µs, the start-up time is increased by 12ms. Figure 28. RAA236100 Power-On Sequence Figure 29. VIN Ramp Rate
R16DS0419EU0103 Rev.1.03 Page 20 Jan 24, 2025 RAA236100, RAA236105 Datasheet
5.5 Input Current Limit (ICL)
The RAA236100 features a programmable average input current limit ranging from 1mA to 50mA, which can be set by Reg0x00 [2:0]. The ICL should not be changed on the fly. To enable or select the current limit levels, the output first needs to be disabled by resetting the Regulator EN bit (Reg0x00 [4] = 0’b) before making the change in ICL setting. When the ICL setting is done, the output can be enabled (Reg0x00[4] = 1’b). The input current limit function cannot include the current that goes into the input capacitors. This function is not available in forced PWM mode. Input current control works in PFM only. It regulates the time between PFM pulses. When ICL is enabled, the modulator tri-states switch D (Figure 31) in the buck tri-state, resulting in lower efficiency. On the RAA236105, the current limit is set by an external resistor on the ILIM pin.
5.6 Dynamic Voltage Scaling (DVS)
The RAA236100 also features pin-controlled Dynamic Voltage Scaling (DVS) with programmable slew rate options. There are two banks of registers to store two different target voltages: Reg0x06 and Reg0x07. The VSEL pin determines the selected output bank. Do not leave the VSEL pin floating. If VSEL is LOW, the value of Reg0x07 decides the VOUT target. However, if VSEL is HIGH, VOUT is determined by the value of Reg0x06.To help slew down to the lower voltage target quickly, there is an option for the converter to enter forced PWM mode when slewing down (Reg0x0C [3]). This option is not available on the RAA236105.
5.7 Soft Discharge
An internal discharge resistor between VOUT and PGND can be activated to discharge the output capacitor slowly. This internal discharge resistor has a typical resistance of 130Ω. The soft discharge function is accessed using I2C while keeping the EN pin high. Using the STARTUP/DISCHARGE register, set the Discharge_enable bit to 1 and disable the IC by setting the Regulator_enable bit to 0. In case of a WOC or OTP fault, this setting overrides the response to a fault in the Reg0x08 [3:0] setting. All devices, excluding the RAA236100, are discharged naturally based on the load current.
5.8 Device Protection
The RAA236100 features extensive protection mechanisms to handle failure conditions and protect the IC and application from damage automatically, including cycle-by-cycle monitoring of inductor current, VOUT under regulation level, and die temperature. Monitoring VOUT and inductor current begins after the soft-start is complete and ends when the regulator is disabled. Fault conditions are monitored and reported by the FAULT REPORT register. Latched faults are actioned as defined by the FAULT CONFIG MASTER register. Clear the latched faults by writing 0 to the registers, setting EN low, or VIN<UVLO. The Fault Report is not available in pin reader options (RAA236105).
5.8.1 Undervoltage Lockout (UVLO)
When VIN falls below the UVLO_falling level, the RAA236100 is disabled. Configure the output to be actively discharged using the internal discharge resistor (soft-discharge) or discharge naturally based on the load current. All devices, excluding the RAA236100, are discharged naturally based on the load current. VIN must go below 1.1V for more than 5µs to soft-reset (POR).
5.8.2 Overcurrent and U ndervoltage Protection
the FAULT REPORT register. The RAA236100 provides overcurrent protection by monitoring the inductor current. down for 100ms and then tries to restart. The WOC feature is disabled during the soft start. mode, the IC shuts down for 100ms and then tries to restart.
5.8.3 Thermal Shutdown
register value or the external resistors.
5.9 Output Discharge and Pre-Bias Startup
to ground) and does not allow negative current flow into ground or VIN.
5.10 Audible No ise Prevention
the audible frequency range under light or no-load conditions. (Reg0x0C Bit[3] = 1’b) to prevent excessive negative current flowing into ground or VIN. This feature is not available in the pin reader option (RAA236105). Figure 30. Overcurrent Protection
5.11 Buck-Boost Conversion Topology
Figure 31 shows a simplified diagram of the internal switches and an external inductor.
5.11.1 Pulse Width Modulation (PWM) Operation
another dead-time interval. After this, Switch A is turned ON again, and the entire sequence repeats. dead-time interval. After this, Switch C is turned ON again, and the entire sequence repeats. PFM/PWM mode), or Forced PWM mode is enabled by setting the FMODE bits in the CONFIG register to 0x01.
5.11.2 Pulse Frequency Modulation (PFM) Operation
During PFM operation in Buck mode, Switch D is kept permanently closed, and Switch C is permanently open. switching cycle repeats after that. Figure 31. Buck-Boost Topology
R16DS0419EU0103 Rev.1.03 Page 23 Jan 24, 2025 RAA236100, RAA236105 Datasheet A is turned ON. Then, just like the Boost PWM operation, Switch C is turned ON, followed by a dead time, and then Switch D is turned ON. The inductor current ramps up and down, respectively, and the energy contained in this current pulse charges up V OUT. After this, unlike the PWM operation, both switches remain OFF, and even Switch A is turned OFF, until VOUT discharges down to the lower threshold of the hysteretic controller. The switching cycle repeats after that. In most operating conditions, multiple switching pulses are needed to charge up the output capacitor. These pulses continue until VOUT has achieved the VOUT target. Switching then stops and remains stopped until VOUT decays to the lower threshold. In low Iq mode, the lower threshold is 60mV below the VOUT target. As load increases, the frequency of PFM pulses increases as VOUT gets discharged faster and needs to be recharged more often. This continues until the PFM pulses start bunching together, and the part then makes a seamless transition to sustained PWM operation. The converter operates in PFM mode under only one condition: load is light enough in the Normal Mode (Auto PFM/PWM mode).
5.11.3 Operation With V IN Close to VOUT
When the output voltage is close to the input voltage, the RAA23610x rapidly and smoothly switches between Boost, Buck-Boost, and Buck modes to maintain the regulated output voltage. This behavior provides excellent efficiency and low output voltage ripple. When VIN = VOUT, there are two possible cycles that regulate. One is the non-switching one, and the other is buck-boost cycles. The part can stay in one or another or can flip between the two. Under high VIN and high VOUT conditions (VIN = VOUT ˃ 4V), there are more disturbances to the inductor current - small changes in the timing of the LX switching converter have a bigger effect on the inductor current. The part has more difficulty finding this non-switching state. When it does find it, it stays there.
5.11.4 Forced Operating Modes
Forced operating modes include Forced PWM mode and Forced Bypass mode. Forced operating modes are selected using the FMODE bits in the CONFIG register. The power-up default mode is Normal operation with automatic mode transitions to optimize efficiency. Forced PWM mode can be selected to minimize the switching frequency variation and to obtain a tight VOUT accuracy, although this comes at the expense of increased input current. Forced PWM mode is available only in the RAA236100. Forced Bypass mode can be selected to minimize power losses when output voltage regulation is not required. When the device enters Bypass mode, Switches A, D, and E are turned ON, providing a direct path from the input to output through the inductor. In Bypass mode, all other blocks, except POR and I2C, are turned off to minimize quiescent current consumption. For the DFN package, the Forced Bypass mode can also be selected by asserting the BYPASS pin.
5.11.5 Adaption Scheme fo r Zero Crossing Detector
The converter employs an adaptive scheme to dynamically adapt the crossing point of the inductor current. The scheme adjusts the offset of the zero cross comparator every 16 switching cycles and corrects variation on V IN, VOUT, temperature, process, and mismatch to try and give a crossing point, which is as close as possible to 0A, optimizing the efficiency and avoiding reverse currents. 6. Serial Interface The RAA236100 includes a standard I2C serial interface. The two-wire interface links one or more Masters and uniquely addressable Slave devices. The Master generates clock signals and is responsible for initiating data transfers. The serial clock is on the SCL line, and the serial data (bidirectional) is on the SDA line. The RAA236100 supports clock rates up to 3.4MHz (High-Speed Mode) and is backward compatible with standard 100kHz (Standard mode) and 400kHz (Fast mode) clock rates.
R16DS0419EU0103 Rev.1.03 Page 24 Jan 24, 2025 RAA236100, RAA236105 Datasheet The SDA and SCL lines must be HIGH when the bus is free (not in use). An external pull-up resistor (typically 1kΩ to 4.7kΩ depending on pull-up voltage and bus capacitance) or current source is required for SDA and SCL.
6.1 I 2C General Operation
6.1.1 Data Validity
The data on the SDA line must be stable (clearly defined as HIGH or LOW) during the HIGH period of the clock signal. The state of the SDA line can only change when the SCL line is low (except to create a START or STOP condition). The voltage levels used to indicate a logical 0 (LOW) and logical 1 (HIGH) are determined by the VIL and VIH thresholds, respectively; see Electrical Specifications.
6.1.2 START and STOP Condition
All I2C communication begins with a START condition - indicating the beginning of a transaction, and ends with a STOP condition, signaling the end of the transaction. A START condition is signified by a HIGH to LOW transition on the serial data line (SDA) while the serial clock line (SCL) is HIGH. A STOP condition is signified by a LOW to HIGH transition on the SDA line while SCL is HIGH. See timing specifications in Electrical Specifications. The Master always initiates START and STOP conditions. After a START condition, the bus is considered busy. After a STOP condition, the bus is considered free. The RAA236100 also supports repeated STARTs, where the bus remains busy for continued transaction(s).
6.1.3 Byte Format
Every byte on SDA must be eight bits in length. After every byte of data sent by the transmitter, there must be an acknowledge bit (from the receiver) to signify that the previous eight bits were transferred successfully. Data is always transferred on SDA with the most significant bit (MSB) first. If the data is larger than eight bits, then it can be separated into multiple 8-bit bytes.
6.1.4 Acknowledge (ACK)
Each 8-bit data transfer is followed by an Acknowledge (ACK) bit from the receiver. The acknowledge bit signifies that the previous eight bits of data were transferred successfully (master-slave or slave-master). When the Master sends data to the Slave (such as during a WRITE transaction), after the 8th bit of a data byte is transmitted, the Master tri-states the SDA line during the 9th clock. The Slave device acknowledges that it received all eight bits by pulling down the SDA line, generating an ACK bit. When the Master receives data from the Slave (such as during a data READ transaction), after the 8th bit is transmitted, the Slave tri-states the SDA line during the 9th clock. The Master acknowledges that it received all eight bits by pulling down the SDA line, generating an ACK bit.
6.1.5 Not Acknowledge (NACK)
A Not Acknowledge (NACK) is generated when the receiver does not pull down the SDA line during the acknowledge clock (for example, the SDA line remains HIGH during the 9th clock). This indicates to the Master that it can generate a STOP condition to end the transaction and free the bus. A NACK can be generated for various reasons, for example: ▪ After an I 2C device address is transmitted, there is NO receiver on the bus with that address to respond. ▪ The receiver is busy performing an internal operation (such as reset or recall) and cannot respond. ▪ The Master (acting as a receiver) needs to indicate the end of a transfer with the Slave (acting as a transmitter).
6.1.6 Device Address and R/W Bit
the I2C bus) the Master wishes to communicate with. operation - the Master receives data from the RAA236100 (transmitter).
6.2 RAA236100 Communication Protocol
6.2.1 Device Addresses Byte
a direction bit, which can be 0 for WRITE or 1 for READ. This is not part of the unique 7-bit I2C device address.
6.2.2 Register Size
received. If a partial data byte is received, that transaction is ignored.
6.2.3 I 2C Write Operation
middle of a data byte, the write is not performed. The basic write transaction structure is shown below. Figure 32. 1-Byte Write to Register M Figure 33. Sequential Data Write Starting at Register M
6.2.4 I 2C Read Operation
subsequent data bytes are sent from sequentially incremental register locations. so subsequent data bytes are sent out from sequentially incremental register locations.
6.2.5 I 2C Timing
Figure 34. 1-Byte Read to Register M Figure 35. Sequential Data Read Starting at Register M Figure 36. I2C Timing Table 5. I2C Timing Characteristics
6.3 Unimplemented Registers
ignored/disregarded and return a fixed value of (0×00) to read commands.
- External Component Selection
are fully integrated, and no additional external MOSFETs or diodes are needed.
- Measured from the falling edge of SCL, applies to data in transmission and acknowledge
- V DD = external pull-up voltage
Table 5. I2C Timing Characteristics (Cont.)
7.1 Inductor Selection
operating conditions. They also should have low DCR and core loss to help achieve high efficiency.
7.2 Output Capacitor Selection
output capacitor are equal to its ESR multiplied by the worst-case inductor ripple current. rating, applied temperature, and DC bias must be considered to ensure enough capacitance is used in the design. X7R and X5R type capacitors are recommended.
7.3 Input Capacitor Selection
Ceramic input capacitors source the AC component of the input current flowing into the high-side MOSFETs. IN and the battery/power supply to dampen ringing and overshoot at startup. Table 6. Recommended Output Inductors Table 7. Recommended Output Capacitors Table 8. Recommended Input Capacitors
Any register addresses (pointers) not indicated in the following section are reserved and should not be used. tiating a new startup sequence. Table 8. Recommended Input Capacitors (Cont.)
R16DS0419EU0103 Rev.1.03 Page 30 Jan 24, 2025 RAA236100, RAA236105 Datasheet 0x01 Register Name - CONFIG Type - (RW) 0x4D / 77 [7:6] SDAslewRate This setting adjust SDA falling time depend- ing on which I2C mode we are in (Standard, Fast, Fast plus, High Speed etcetera) 00 = slowest 01 = slow 10 = fast 11 = fastest <01> [5:4] FMODE bckBst buck-boost operating modes 00 = normal operation, automatic PFM/PWM transitions and ultra sonic disabled 01 = normal operation, automatic PFM/PWM transitions and ultra sonic enabled 10 = forced PWM mode 11 = forced bypass, disable switching <00> [3] set VDD I2C to VIN 0 = external VDD_I2C is a fixed 1.8 or 3.3V rail 1 = external VDD_I2C pulled up to VIN <1> [2] FLL EN bckBst Enable Frequency control loop (FLL) on buck-boost. When the FLL is enabled the frequency is locked at a 2MHz in PWM and Ton+Toff=1/2MHz in PFM mode 0 = FLL disabled 1 = FLL enabled <1> [1] not used <0> [0] EN INT bckBst Enables integrator in buck-boost error amplifier 0 = Type I error amplifier for best tran- sient response with voltage position- ing 1 = Type II error amplifier for best DC accuracy <1> 0x02 Register Name - ID Type - (Read-Only) 0x30 / 48 [7:5] Family ID This is an identifier to distinguish between Renesas stand alone regulators and PMIC 001 = 2nd gen stand alone converter <001> [4:3] Chip Rev This setting indicates th e silicon revision 00 = first revision 01 = second revision 10 = third revision 11 = final revision <10> [2:0] Chip ID This setting refer to different regulators type; i.e. buck-boost, buck or boost convert- ers 000 = buck boost with Vin_min=1.8V <000> 0x03 Reserved for Renesas Internal Use 0x04 Reserved for Renesas Internal Use 0x05 Reserved for Renesas Internal Use
R16DS0419EU0103 Rev.1.03 Page 31 Jan 24, 2025 RAA236100, RAA236105 Datasheet 0x06 Register Name - bckBst 1 Type - (RW) 0x1E / 30 [7] not used <0> [6:0] bckBst setting 1 VOUT_targ et when VSEL pin is "HIGH" VOUT_target = 1.8V + N x 50mV where N is bckBst_setting_1 code in deci- mal Output voltage examples: 0x00 = 1.8 ---- 0x10 = 2.6V ---- 0x1E = 3.3V ---- 0x40 = 5.0V 0x41 = 5.0V 0x42 = 5.0V ---- 0x7F = 5.0V <0011110> 0x07 Register Name - bckBst 0 Type - (RW) 0x1E / 30 [7] not used <0> [6:0] bckBst setting 0 VOUT_targ et when VSEL pin is "LOW" VOUT_target = 1.8V + N x 50mV where N is bckBst_setting_0 code in deci- mal Output voltage examples: 0x00 = 1.8 ---- 0x10 = 2.6V ---- 0x1E = 3.3V ---- 0x40 = 5.0V 0x41 = 5.0V 0x42 = 5.0V ---- 0x7F = 5.0V <0011110>
R16DS0419EU0103 Rev.1.03 Page 32 Jan 24, 2025 RAA236100, RAA236105 Datasheet 0x08 Register Name - FAULT CONFIG MASTER Type - (RW) 0x1D / 29 [7] Master Fault 0->1 transition if any of the latched faults (register 0x09<6:4>) transition from 0->1 0 = no fault 1 = fault <0> [6:5] not used <00> [4] EnUvProt If the under voltage protection is enabled the threshold is fixed at Vout_uv=1.65V. The action of the fault is defined by the content of bits <3:2>: 00 = No Action 01 = Hard shutdown. Requires restart over I2C or EN pin 10 = Hiccup mode (100ms wait) with dis- charge allowed 11 = Hiccup mode (100ms wait) with dis- charge inhibited 0 = Under Voltage disabled 1 = Under Voltage enabled <1> [3:2] bckBst WOC action bckBst Way Over Current handling mode: No action: the regulator will keep switching using a cycle by cycle current limit Hard shutdown: the regulator will stop switching - it requires a restart using either Software_reset bit, EN pin "HIGH" -> "LOW" - > "HIGH" transition or VIN power cycle Hiccup mode: the regulator will stop switch- ing for 100msec - the regulator will go through a startup sequence again after this time The option to discharge or not discharge is overridden by Discharge_bckBst_enable bit- field 00 = No Action 01 = Hard shutdown 10 = Hiccup mode (100ms wait) with discharge resistor enabled 11 = Hiccup mode (100ms wait) with discharge resistor disabled <11> [1:0] Over temperature action Over temperature handling mode Hard shutdown: the regulator will stop switching - it requires a restart using either Software_reset bit, EN pin "HIGH" -> "LOW" - > "HIGH" transition or VIN power cycle The option to discharge or not discharge is overridden by Discharge_bckBst_enable bit- field 00 = Shut down+ start when cooled (discharge resistor enabled) 01 = Shut down+ start when cooled (discharge resistor disabled) 1X = Hard shutdown <01>
R16DS0419EU0103 Rev.1.03 Page 33 Jan 24, 2025 RAA236100, RAA236105 Datasheet 0x09 Register Name - FAULT REPORT Type - (RW) 0x00 / 0 [7] not used <0> [6] bckBst WOC latch Latched if way over current protection is hit Cleared by writing low. Will set again if fault still present/reoccurs 0 = no fault 1 = latched fault <0> [5] Over temperature latch Latched if way over temperature protection is hit Cleared by writing low. Will set again if fault still present/reoccurs 0 = no fault 1 = latched fault <0> [4] UVLO latch This bit shows the status of the Vin UVLO comparator. If high Latch high on falling edge of the compara- tor output (vddOk from "HIGH" to "LOW"). The comparator output is ignored for at least 10us after EN goes high. Cleared by writing low. Will set again if fault still present/reoccurs 0 = no fault (VIN>UVLO) 1 = latched fault (VIN≤UVLO) <0> [3] bckBst BOOSTING This bit is only active during switching oper- ation and indicates that Vout is 0.4V above Vin and the regulator will only issue boost cycle, without any buck cycle. The bit is not latched 0 = VOUT≤VIN+0.4 1 = VOUT>VIN+0.4 <0> [2] eprom reading fault This bit is set if the eprom reading at startup has failed. A new attempt can be made by executing a Software_reset or VIN power cycle 0 = no fault 1 = latched fault <0> [1] bckBst WOC live This bit will in dicate the 'live' status of the Way Over Current comparator. It is not latched as bit<6> and clears itself if fault condition is removed 0 = no fault 1 = live fault <0> [0] Over temperature liveThis bit will indicate the 'live' status of the over temperature comparator. It is not latched as bit<5> and clears itself if fault condition is removed 0 = no fault 1 = live fault <0> 0x0A Reserved for Renesas Internal Use 0x0B Reserved for Renesas Internal Use
R16DS0419EU0103 Rev.1.03 Page 34 Jan 24, 2025 RAA236100, RAA236105 Datasheet 0x0C Register Name - STARTUP DISCHARGE Type - (RW) 0xA0 / 160 [7:6] bckBst slew rate buck-boost so ft start and slew rate between levels 00 = 0.78125mV/us 01 = 1.5625mV/us 10 = 3.125mV/us 11 = 6.25mV/us <10> [5:4] bckBst fast DVS <10> [3] bckBst slew mode This bit, if set, allows a faster ramp down rate if no load is applied. Once Vout reaches the new target the forced in PWM condition will be removed 0 = device stays in normal mode when VOUT is changed downwards 1 = device goes to forced PWM mode during VOUT change downwards <0> [2] bckBst entry byp mode This bit will force PWM when entrying bypass until the Vout voltage is close to Vin. Once Vout~Vin the bypass switch will be turned on and the forced PWM mode condi- tion is removed. By setting this bit high the entry in forced bypass mode will be indipendent from the external load. If bit[3] above is set then this bit here is not relevant. 0 = device stays in normal mode when entering bypass and VOUT is going downwards 1 = device goes to forced PWM mode when entering bypass and VOUT is going downwards <0> [1] not used <0> [0] Discharge bckBst enable Discharge resistor is disabled indipendently from this setting when VIN goes below the internal POR level. In case of a WOC or OTP fault This setting overrides reg0x08<3:0> setting 0 = Discharge resistor disabled 1 = Discharge resistor enabled <0>
R16DS0419EU0103 Rev.1.03 Page 35 Jan 24, 2025 RAA236100, RAA236105 Datasheet 9. Package Outline Drawings For the most recent package outline drawing, see L10.2.5x2.5. L10.2.5x2.5 10 Lead 2.5x2.5 Dual Flat No-Lead Plastic Package Rev 0, 11/20
R16DS0419EU0103 Rev.1.03 Page 36 Jan 24, 2025 RAA236100, RAA236105 Datasheet 10. Ordering Information 11. Revision History Part Number[1] 1. For Moisture Sensitivit y Level (MSL), see the RAA236100, RAA236105 product pages. For more information about MSL, see TB363. Part Marking Default VOUT (V) Package Description[2] (RoHS Compliant) 2. For the Pb-Free Reflow Profile, see TB493. Pkg. Dwg. # Carrier Type[3] 3. See TB347 for details about reel specifications. Temp. Range RAA2361002GNP#HC5[4] 4. These Pb-free plastic packaged products em ploy special Pb-free material sets; molding compounds/die attach materials and NiPdAu-Ag plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J-STD-020. 610 3.3; I 2C programmable 10 Ld DFN 0.5mm pitch L10.2.5x2.5 Reel, 6k -40 to +85°C RAA2361052GNP#HC5[4] 105 1.8 to 4.8 in100mV steps and 5.0V; pin reader 10 Ld DFN 0.5mm pitch L10.2.5x2.5 Reel, 6k -40 to +85°C RTKA236100DE0010BU Evaluation B oard for RAA2361002GNP#HC5 RTKA236105DE0010BU Evaluation B oard for RAA2361052GNP#HC5 Revision Date Description 1.03 Jan 24, 2025 Updated the Forced Bypass mode current consumption on page 1. 1.02 Nov 11, 2024 Updated input quiescent current values on page 1 to match spec values. Corrected mislabeled pin 2 on RAA236105 diagram.
1.01 Jun 25, 2024
Updated Electrical Specifications: - VIN Quiescent Current, Typical, from 100 to 130nA. - Output Voltage Accuracy, from IOUT = 1mA to IOUT = 100µA. - Removed SCL/SDA Input High and Low Voltage High Speed Mode (RAA236100)
1.00 Mar 27, 2024 Initial release
TOYOSU FORESIA, 3-2-24 Toyosu, Koto-ku, Tokyo 135-0061, Japan www.renesas.com Contact Information For further information on a product, technology, the most up-to-date version of a document, or your nearest sales office, please visit www.renesas.com /contact-us/ . Trademarks Renesas and the Renesas logo are trademarks of Renesas Electronics Corporation. All trademarks and registered trademarks are the property of their respective owners. IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD-PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for developers who are designing with Renesas products. You are solely responsible for (1) selecting the appropriate products for your application, (2) designing, validating, and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. Renesas grants you permission to use these resources only to develop an application that uses Renesas products. Other reproduction or use of these resources is strictly prohibited. No license is granted to any other Renesas intellectual property or to any third-party intellectual property. Renesas disclaims responsibility for, and you will fully indemnify Renesas and its representatives against, any claims, damages, costs, losses, or liabilities arising from your use of these resources. Renesas' products are provided only subject to Renesas' Terms and Conditions of Sale or other applicable terms agreed to in writing. No use of any Renesas resources expands or otherwise alters any applicable warranties or warranty disclaimers for these products. (Disclaimer Rev.1.01) © 2025 Renesas Electronics Corporation. All rights reserved.