TPS563201 TI
Document overview
- Manufacturer or author: Provided By www.digicamel.com(free datasheet download site)
- PDF pages: 27
Technical content
Output Current (A) Efficiency 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% D023 VOUT = 1.05 V VOUT = 1.5 V VOUT = 1.8 V VOUT = 3.3 V VOUT = 5 V TPS563201 VIN SW GND1 3 4 VOUT VOUT EN VINC OUT C IN VBST EN VFB Product Folder Sample & Buy T echnical Documents Tools & Software Support & Community TPS563201,TPS563208 SLVSD90 –DECEMBER 2015 TPS56320x4.5-Vto17-VInput,3-ASynchronousStep-DownVoltageRegulatorinSOT-23
1 Features 3 Description
The TPS563201 and TPS563208 are simple, easy-to- 1• TPS563201 and TPS563208 3-A Converter use, 3 A synchronous step-down converters in SOT-Integrated 95-mΩ and 57-mΩ FETs 23 package.• D-CAP2™ Mode Control with fast transient The devices are optimized to operate with minimumresponse external component counts and also optimized to• Input Voltage Range: 4.5 V to 17 V achieve low standby current.
- Output Voltage Range: 0.76 V to 7 V These switch mode power supply (SMPS) devices• Pulse-skip mode (TPS563201) or Continuous employ D-CAP2 mode control providing a fastCurrent Mode (TPS563208) transient response and supporting both low-
- 580-kHz Switching Frequency equivalent series resistance (ESR) output capacitors such as specialty polymer and ultra-low ESR ceramic• Low Shutdown Current Less than 10 µA capacitors with no external compensation• 2% Feedback Voltage Accuracy (25 ºC) components.
- Startup from Pre-Biased Output Voltage TPS563201 operates in pulse skip mode, which• Cycle-by-Cycle Overcurrent Limit maintains high efficiency during light load operation.
- Hiccup-mode Overcurrent Protection The TPS563201 and TPS563208 are available in a 6- pin 1.6-mm × 2.9-mm SOT (DDC) package, and• Non-Latch UVP and TSD Protections specified from a –40°C to 125°C junction• Fixed Soft Start: 1.0 ms temperature.
2 Applications Device Information(1)
- Digital TV Power Supply PART NUMBER PACKAGE BODY SIZE (NOM)
- High Definition Blu-ray™ Disc Players TPS563201 DDC (6) 1.60 mm × 2.90 mmTPS563208• Networking Home Terminal (1) For all available packages, see the orderable addendum at• Digital Set Top Box (STB) the end of the data sheet.
- Surveillance Simplified Schematic TPS563201 Efficiency An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS563201,TPS563208 SLVSD90 –DECEMBER 2015 www.ti.com Table of Contents
4 Revision History
December 2015 * Initial release.
2 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated
Product Folder Links: TPS563201 TPS563208
TPS563201,TPS563208 www.ti.com SLVSD90 –DECEMBER 2015
5 Pin Configuration and Functions
NAME NO. Ground pin Source terminal of low-side power NFET as well as the ground terminal forGND 1 — controller circuit. Connect sensitive VFB to this GND at a single point. SW 2 O Switch node connection between high-side NFET and low-side NFET. VIN 3 I Input voltage supply pin. The drain terminal of high-side power NFET. VFB 4 I Converter feedback input. Connect to output voltage with feedback resistor divider. EN 5 I Enable input control. Active high and must be pulled up to enable the device. Supply input for the high-side NFET gate drive circuit. Connect 0.1 µF capacitor betweenVBST 6 O VBST and SW pins.
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT VIN, EN –0.3 19 V VBST –0.3 25 V VBST (10 ns transient) –0.3 27 V Input voltage VBST (vs SW) –0.3 6.5 V VFB –0.3 6.5 V SW –2 19 V SW (10 ns transient) –3.5 21 V Operating junction temperature, TJ –40 150 °C Storage temperature, Tstg –55 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±3000 V(ESD) Electrostatic discharge VCharged-device model (CDM), per JEDEC specification JESD22- ±1500C101(2) (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: TPS563201 TPS563208
TPS563201,TPS563208 SLVSD90 –DECEMBER 2015 www.ti.com
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VIN Supply input voltage range 4.5 17 V VBST –0.1 23 VBST (10 ns transient) –0.1 26 VBST (vs SW) –0.1 6.0 VI Input voltage range EN –0.1 17 V VFB –0.1 5.5 SW –1.8 17 SW (10 ns transient) –3.5 20 TJ Operating junction temperature –40 125 °C
6.4 Thermal Information
THERMAL METRIC(1) DDC (SOT) UNIT
6 PINS
RθJA Junction-to-ambient thermal resistance 92.6 °C/W RθJC(top) Junction-to-case (top) thermal resistance 48.5 °C/W RθJB Junction-to-board thermal resistance 15.5 °C/W ψJT Junction-to-top characterization parameter 2.5 °C/W ψJB Junction-to-board characterization parameter 15.5 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.
4 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated
Product Folder Links: TPS563201 TPS563208
TPS563201,TPS563208 www.ti.com SLVSD90 –DECEMBER 2015
6.5 Electrical Characteristics
TJ = –40°C to 125°C, VIN = 12 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY CURRENT TPS563201 380 520Operating – non-switchingIVIN VIN current, EN = 5 V, VFB = 0.8 V µAsupply current TPS563208 590 750 IVINSDN Shutdown supply current VIN current, EN = 0 V 1 10 µA LOGIC THRESHOLD VENH EN high-level input voltage EN 1.6 V VENL EN low-level input voltage EN 0.8 V REN EN pin resistance to GND VEN = 12 V 225 400 900 kΩ VFB VOLTAGE AND DISCHARGE RESISTANCE VFB threshold voltage VO = 1.05 V, IO = 10 mA, Eco-mode™ operation 774 mV VFBTH VFB threshold voltage VO = 1.05 V, continuous mode operation 749 768 787 mV IVFB VFB input current VFB = 0.8 V 0 ±0.1 µA MOSFET RDS(on)h High-side switch resistance TA = 25°C, VBST – SW = 5.5 V 95 mΩ RDS(on)l Low-side switch resistance TA = 25°C 57 mΩ CURRENT LIMIT THERMAL SHUTDOWN Shutdown temperature 172Thermal shutdownTSDN °Cthreshold(1) Hysteresis 37 ON-TIME TIMER CONTROL tOFF(MIN) Minimum off time VFB = 0.5 V 220 310 ns SOFT START Tss Soft-start time Internal soft-start time 1.0 ms FREQUENCY Fsw Switching frequency VIN = 12 V, VO = 1.05 V, FCCM mode 580 kHz OUTPUT UNDERVOLTAGE AND OVERVOLTAGE PROTECTION VUVP Output UVP threshold Hiccup detect (H > L) 65% THICCUP_WAIT Hiccup on time 1.8 ms THICCUP_RE Hiccup time before restart 15 ms UVLO Wake up VIN voltage 4.0 4.3 UVLO UVLO threshold Shutdown VIN voltage 3.3 3.6 V Hysteresis VIN voltage 0.4 (1) Not production tested. Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: TPS563201 TPS563208
6.6 Typical Characteristics
Figure 1. TPS563201 Supply Current vs Junction Figure 2. VFB Voltage vs Junction Temperature Figure 3. EN Pin UVLO Low Voltage vs Junction Figure 4. EN Pin UVLO High Voltage vs Junction Figure 5. High-Side Rds-On vs Junction Temperature Figure 6. Low-Side Rds-On vs Junction Temperature
6 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated
8 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated
3 VIN
6 VBST
1 GND
TPS563201,TPS563208 www.ti.com SLVSD90 –DECEMBER 2015
7 Detailed Description
7.1 Overview
The TPS563201 and TPS563208 are 3-A synchronous step-down converters. The proprietary D-CAP2 mode control supports low ESR output capacitors such as specialty polymer capacitors and multi-layer ceramic capacitors without complex external compensation circuits. The fast transient response of D-CAP2 mode control can reduce the output capacitance required to meet a specific level of performance.
7.2 Functional Block Diagram
7.3 Feature Description
7.3.1 Adaptive On-Time Control and PWM Operation
The main control loop of the TPS563201 and TPS563208 is adaptive on-time pulse width modulation (PWM) controller that supports a proprietary D-CAP2 mode control. The D-CAP2 mode control combines adaptive on- time control with an internal compensation circuit for pseudo-fixed frequency and low external component count configuration with both low-ESR and ceramic output capacitors. It is stable even with virtually no ripple at the output. At the beginning of each cycle, the high-side MOSFET is turned on. This MOSFET is turned off after internal one shot timer expires. This one shot duration is set proportional to the converter input voltage, VIN, and inversely proportional to the output voltage, VO, to maintain a pseudo-fixed frequency over the input voltage range, hence it is called adaptive on-time control. The one-shot timer is reset and the high-side MOSFET is turned on again when the feedback voltage falls below the reference voltage. An internal ramp is added to reference voltage to simulate output ripple, eliminating the need for ESR induced output ripple from D-CAP2 mode control. Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Links: TPS563201 TPS563208
OUT(LL) SW IN (V V ) V1I 2 L f V u u u u TPS563201,TPS563208 SLVSD90 –DECEMBER 2015 www.ti.com Feature Description (continued)
7.3.2 Pulse Skip Control (TPS563201)
The TPS563201 is designed with advanced Eco-mode to maintain high light load efficiency. As the output current decreases from heavy load condition, the inductor current is also reduced and eventually comes to point that its rippled valley touches zero level, which is the boundary between continuous conduction and discontinuous conduction modes. The rectifying MOSFET is turned off when the zero inductor current is detected. As the load current further decreases the converter runs into discontinuous conduction mode. The on-time is kept almost the same as it was in the continuous conduction mode so that it takes longer time to discharge the output capacitor with smaller load current to the level of the reference voltage. This makes the switching frequency lower, proportional to the load current, and keeps the light load efficiency high. The transition point to the light load operation IOUT(LL) current can be calculated in Equation 1. (1)
7.3.3 Soft Start and Pre-Biased Soft Start
The TPS563201 and TPS563208 have an internal 1-ms soft-start. When the EN pin becomes high, the internal soft-start function begins ramping up the reference voltage to the PWM comparator. If the output capacitor is pre-biased at startup, the devices initiate switching and start ramping up only after the internal reference voltage becomes greater than the feedback voltage VFB. This scheme ensures that the converters ramp up smoothly into regulation point.
7.3.4 Current Protection
The output over-current limit (OCL) is implemented using a cycle-by-cycle valley detect control circuit. The switch current is monitored during the OFF state by measuring the low-side FET drain to source voltage. This voltage is proportional to the switch current. To improve accuracy, the voltage sensing is temperature compensated. During the on time of the high-side FET switch, the switch current increases at a linear rate determined by Vin, Vout, the on-time and the output inductor value. During the on time of the low-side FET switch, this current decreases linearly. The average value of the switch current is the load current Iout. If the monitored current is above the OCL level, the converter maintains low-side FET on and delays the creation of a new set pulse, even the voltage feedback loop requires one, until the current level becomes OCL level or lower. In subsequent switching cycles, the on-time is set to a fixed value and the current is monitored in the same manner. There are some important considerations for this type of over-current protection. The load current is higher than the over-current threshold by one half of the peak-to-peak inductor ripple current. Also, when the current is being limited, the output voltage tends to fall as the demanded load current may be higher than the current available from the converter. This may cause the output voltage to fall. When the VFB voltage falls below the UVP threshold voltage, the UVP comparator detects it. And then, the device will shut down after the UVP delay time (typically 24 µs) and re-start after the hiccup time (typically 15 ms). When the over current condition is removed, the output voltage returns to the regulated value.
7.3.5 Undervoltage Lockout (UVLO) Protection
UVLO protection monitors the internal regulator voltage. When the voltage is lower than UVLO threshold voltage, the device is shut off. This protection is non-latching.
7.3.6 Thermal Shutdown
The device monitors the temperature of itself. If the temperature exceeds the threshold value (typically 172°C), the device is shut off. This is a non-latch protection.
10 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated
Product Folder Links: TPS563201 TPS563208
TPS563201,TPS563208 www.ti.com SLVSD90 –DECEMBER 2015
7.4 Device Functional Modes
7.4.1 Normal Operation
When the input voltage is above the UVLO threshold and the EN voltage is above the enable threshold, the TPS563201 and TPS563208 can operate in their normal switching modes. Normal continuous conduction mode (CCM) occurs when the minimum switch current is above 0 A. In CCM, the TPS563201 and TPS563208 operate at a quasi-fixed frequency of 580 kHz.
7.4.2 Eco-mode Operation
When the TPS563201 and TPS563208 are in the normal CCM operating mode and the switch current falls to 0 A, the TPS563201 and TPS563208 begin operating in pulse skipping Eco-mode. Each switching cycle is followed by a period of energy saving sleep time. The sleep time ends when the VFB voltage falls below the Eco- mode threshold voltage. As the output current decreases, the perceived time between switching pulses increases.
7.4.3 Standby Operation
When the TPS563201 and TPS563208 are operating in either normal CCM or Eco-mode, they may be placed in standby by asserting the EN pin low. Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Links: TPS563201 TPS563208
8 Application and Implementation
validate and test their design implementation to confirm system functionality.
8.1 Application Information
8.2 Typical Application
available as the evaluation module (EVM). The sections provide the design procedure. Figure 19 shows the TPS563201 and TPS563208 4.5-V to 17-V input, 1.05-V output converter schematics. Figure 19. TPS563201 and TPS563208 1.05-V/3-A Reference Design
12 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated
2 L C
8.2.1 Design Requirements
Table 1 shows the design parameters for this application. Table 1. Design Parameters
8.2.2 Detailed Design Procedure
8.2.2.1 Output Voltage Resistors Selection
tolerance or better divider resistors. Start by using Equation 2 to calculate VOUT. susceptible to noise and voltage errors from the VFB input current will be more noticeable.
8.2.2.2 Output Filter Selection
adequate phase margin for a stable circuit. To meet this requirement use the values recommended in Table 2. Table 2. Recommended Component Values
12 V L f
current and the RMS or heating current rating must be greater than the calculated RMS current. inductor used is a WE 74431122 with a peak current rating of 13 A and an RMS current rating of 9 A. µF. Use Equation 7 to determine the required RMS current rating for the output capacitor. For this design two TDK C3216X5R0J226M 22-µF output capacitors are used. The typical ESR is 2 mΩ each. The calculated RMS current is 0.286 A and each output capacitor is rated for 4 A.
8.2.2.3 Input Capacitor Selection
capacitor voltage rating needs to be greater than the maximum input voltage.
8.2.2.4 Bootstrap Capacitor Selection
recommends to use a ceramic capacitor.
8.2.3 Application Curves
Figure 20. TPS563201 and TPS563208 Load Regulation, Figure 21. TPS563201 and TPS563208 Load Regulation,
14 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated
Figure 28. TPS563208 Output Voltage Ripple, IOUT = 0 A Figure 29. TPS563201 Transient Response, 0.1 to 1.5 A Figure 32. TPS563201 Start Up Relative to VI Figure 33. TPS563201 Start-Up Relative to EN
16 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated
Figure 34. TPS563201 Shutdown Relative to VI Figure 35. TPS563201 Shutdown Relative to EN
9 Power Supply Recommendations
TPS563201 and TPS563208 are designed to operate from input supply voltage in the range of 4.5 V to 17 V.
10 Layout
10.1 Layout Guidelines
- VIN and GND traces should be as wide as possible to reduce trace impedance. The wide areas are also of
advantage from the view point of heat dissipation.
- The input capacitor and output capacitor should be placed as close to the device as possible to minimize
- Provide sufficient vias for the input capacitor and output capacitor.
- Keep the SW trace as physically short and wide as practical to minimize radiated emissions.
- Do not allow switching current to flow under the device.
- A separate VOUT path should be connected to the upper feedback resistor.
- Make a Kelvin connection to the GND pin for the feedback path.
- Voltage feedback loop should be placed away from the high-voltage switching trace, and preferably has
- The trace of the VFB node should be as small as possible to avoid noise coupling.
- The GND trace between the output capacitor and the GND pin should be as wide as possible to minimize its
10.2 Layout Example
Figure 36. TPS563201 and TPS563208 Layout
18 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated
11 Device and Documentation Support
11.1 Related Links
resources, tools and software, and quick access to sample or buy. Table 3. Related Links
11.2 Community Resources
solve problems with fellow engineers. contact information for technical support.
11.3 Trademarks
D-CAP2, Eco-mode, E2E are trademarks of Texas Instruments. WEBENCH is a registered trademark of Texas Instruments. Blu-ray is a trademark of Blu-ray Disc Association. All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
www.ti.com 10-Dec-2020 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples TPS563201DDCR ACTIVE SOT-23-THIN DDC 6 3000 RoHS & Green Call TI | SN Level-1-260C-UNLIM -40 to 125 3201 TPS563201DDCT ACTIVE SOT-23-THIN DDC 6 250 RoHS & Green Call TI | SN Level-1-260C-UNLIM -40 to 125 3201 TPS563208DDCR ACTIVE SOT-23-THIN DDC 6 3000 RoHS & Green Call TI | SN Level-1-260C-UNLIM -40 to 125 3208 TPS563208DDCT ACTIVE SOT-23-THIN DDC 6 250 RoHS & Green Call TI | SN Level-1-260C-UNLIM -40 to 125 3208 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
www.ti.com 10-Dec-2020 Addendum-Page 2 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
PACKAGE MATERIALS INFORMATION www.ti.com 28-Apr-2023 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant TPS563201DDCR SOT-23- THIN TPS563201DDCT SOT-23- THIN TPS563208DDCR SOT-23- THIN TPS563208DDCT SOT-23- THIN Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION www.ti.com 28-Apr-2023 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS563201DDCR SOT-23-THIN DDC 6 3000 210.0 185.0 35.0 TPS563201DDCT SOT-23-THIN DDC 6 250 210.0 185.0 35.0 TPS563208DDCR SOT-23-THIN DDC 6 3000 210.0 185.0 35.0 TPS563208DDCT SOT-23-THIN DDC 6 250 210.0 185.0 35.0 Pack Materials-Page 2
www.ti.com PACKAGE OUTLINE C 0.20
0.12 TYP
0.25 3.05 2.55 4X 0.95 1.1 0.7 0.1
0.0 TYP
6X 0.5 0.3 0.6
0.3 TYP
1.9 0 -8 TYP A 3.05 2.75 B1.75 1.45 SOT-23 - 1.1 max heightDDC0006A SMALL OUTLINE TRANSISTOR 4214841/C 04/2022 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Reference JEDEC MO-193. 3 4
0.2 C A B
0.1 C SCALE 4.000
www.ti.com EXAMPLE BOARD LAYOUT
0.07 MAX
0.07 MIN
6X (1.1) 6X (0.6) (2.7) 4X (0.95) (R0.05) TYP 4214841/C 04/2022 SOT-23 - 1.1 max heightDDC0006A SMALL OUTLINE TRANSISTOR NOTES: (continued) 4. Publication IPC-7351 may have alternate designs. 5. Solder mask tolerances between and around signal pads can vary based on board fabrication site. SYMM LAND PATTERN EXAMPLE EXPLOSED METAL SHOWN SCALE:15X SYMM 3 4 SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL METALSOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDERMASK DETAILS EXPOSED METAL
www.ti.com EXAMPLE STENCIL DESIGN (2.7) 4X(0.95) 6X (1.1) 6X (0.6) (R0.05) TYP SOT-23 - 1.1 max heightDDC0006A SMALL OUTLINE TRANSISTOR 4214841/C 04/2022 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 7. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 THICK STENCIL SCALE:15X SYMM SYMM 3 4
IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2023, Texas Instruments Incorporated