DAC37J82

DAC3xJ82 Dual-Channel, 16-Bit, 1.6/2.5 GSPS, Digital-to-Analog Converters with 12.5 Gbps JESD204B Interface datasheet (Rev. B)

Document overview

• Manufacturer or author: Texas Instruments, Incorporated [SLASE16,B]
• PDF pages: 119

Technical content

(48-bit NCO) 8 lanes @ 12.5 Gbps RF JESD204B Interface Product Folder Sample & Buy T echnical Documents Tools & Software Support & Community DAC37J82, DAC38J82 SLASE16B – JANUARY 2014– REVISED MAY 2014 DAC3xJ82Dual-Channel,16-Bit,1.6/2.5GSPS,Digital-to-AnalogConverters with12.5GbpsJESD204BInterface

1 Features 3 Description

The pin-compatible DAC37J82/DAC38J82 family is a 1• Resolution: 16-Bit very low power, 16-bit, dual-channel, 1.6/2.5 GSPS• Maximum Sample Rate: digital to analog converter (DAC) with JESD204B – DAC37J82: 1.6 GSPS interface. The maximum input data rate is 1.23 GSPS.– DAC38J82: 2.5 GSPS

• Maximum Input Data Rate: 1.23GSPS Digital data is input to the device through 1, 2, 4 or 8 configurable serial JESD204B lanes running up to• JESD204B Interface 12.5 Gbps with on-chip termination and– 8 JESD204B Serial Input Lanes programmable equalization. The interface allows – 12.5 Gbps Maximum Bit Rate per Lane JESD204B Subclass 1 SYSREF based deterministic latency and full synchronization of multiple devices.– Subclass 1 Multi-DAC synchronization
• On-Chip Very Low Jitter PLL The device includes features that simplify the design of complex transmit architectures. Fully bypassable• Selectable 1x -16x Interpolation 2x to 16x digital interpolation filters with over 90 dB of• Independent Complex Mixers with 48-bit NCO/ or stop-band attenuation simplify the data interface and±n×Fs/8 reconstruction filters. An on-chip 48-bit Numerically
• Wideband Digital Quadrature Modulator Controlled Oscillator (NCO) and independent Correction complex mixers allow flexible and accurate carrier placement.• Sinx/x Correction Filters A high-performance low jitter PLL simplifies clocking• Fractional Sample Group Delay Correction of the device without significant impact on the• Flexible Routing to Four Analog Outputs via dynamic range. The digital Quadrature ModulatorOutput Multiplexer Correction (QMC) and Group Delay Correction (QDC)• 3/4-Wire Serial Control Bus (SPI) enable complete IQ compensation for gain, offset,
• Integrated Temperature Sensor phase, and group delay between channels in direct up-conversion applications. A programmable Power• JTAG Boundary Scan Amplifier (PA) protection mechanism is available to• Pin-compatible with Quad-channel provide PA protection in cases when the abnormalDAC37J84/DAC38J84 power behavior of the input data is detected.
• Power Dissipation: 1.1W at 2.5GSPS DAC37J82/DAC38J82 family provides four analog• Package: 10x10mm, 144-Ball Flip-Chip BGA outputs, and the data from the internal two digital paths can be routed to any two out of these four DAC 2 Applications outputs via the output multiplexer.
• Cellular Base Stations Device Information(1)
• Diversity Transmit PART NUMBER PACKAGE BODY SIZE (NOM)
• Wideband Communications DAC37J82 FCBGA (144) 10.00 mm x 10.00 mm
• Direct Digital Synthesis (DDS) Instruments DAC38J82 FCBGA (144) 10.00 mm x 10.00 mm
• Millimeter/Microwave Backhaul (1) For all available packages, see the orderable addendum at
• Automated Test Equipment the end of the datasheet.
• Cable Infrastructure
• Radar An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

DAC37J82, DAC38J82 SLASE16B – JANUARY 2014– REVISED MAY 2014 www.ti.com Table of Contents

4 Revision History

Changes from Revision A (January 2014) to Revision B Page Changes from Original (January 2014) to Revision A Page

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GND IOUT AP IOUT AN IOUTBN IOUTBP GND GND IOUTCP IOUTCN IOUTDN IOUTDP GND GND GND GND GND GND GND GND GND GND GND GND DACCLKP VDDAPLL18 EXTIO RBIAS SDIO SDO DACCLKN LPF A TEST SCLK SDENB GND GND GND GND GND GND GND RESETB ALARM SLEEP SYSREFP SYNCBP GND GND GND GND SYNC_N_CD NC SYSREFN SYNCBN GND GND GND GND SYNC_N_AB NC GND GND IFORCE GND GND GND GND TXENABLE TDI TDO GND GND VSENSE VDDDIG09 TCLK TMS GND RX7P GND GND AMUX1 AMUX0 TRSTB TESTMODE GND RX3P RX7N GND GND GND GND GND GND GND GND RX3N RX6N RX6P RX5P RX5N RX4N RX4P RX0P RX0N RX1N RX1P RX2P RX2N 1 1 1 1 A B C D E F G H J K L M GND VDDAPLL18 VDDS18 VDDS18 VDDCLK09VDDCLK09 VDDDIG09 VDDT09 VDDT09 VDDR18 VDDR18 VDDDIG09 VDDDIG09 VDDDIG09 VDDDIG09 VDDDIG09 VDDDIG09 VDDDIG09 VDDDIG09 VDDIO18 VDDIO18 VDDAREF18VDDADAC33VDDADAC33VDDADAC33VDDADAC33VDDAREF18 VDDDAC09 VDDDAC09 VDDDAC09 VDDDAC09 VDDDAC09 VDDDAC09 VQPS18 VQPS18 VDDDIG09 DAC37J82, DAC38J82 www.ti.com SLASE16B – JANUARY 2014– REVISED MAY 2014 Device Comparison Table DEVICE MAXIMUM SAMPLE RATE PACKAGE DRAWING/TYPE(1) TA DAC37J82IAAV 1.6 GSPS AAV/144-ball flip chip BGA –40°C to 85°C DAC38J82IAAV 2.5 GSPS AAV/144-ball flip chip BGA –40°C to 85°C (1) MSL Peak Temperature: Level-3-260C-168 HR

5 Pin Configuration and Functions

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DAC37J82, DAC38J82 SLASE16B – JANUARY 2014– REVISED MAY 2014 www.ti.com Pin Functions PIN I/O DESCRIPTION NAME NUMBER CMOS output for ALARM condition. The ALARM output functionality is defined through the ALARM L8 O config7 register. Default polarity is active high, but can be changed to active high via config0 alarm_out_pol control bit. If not used it can be left open. AMUX0 H3 I/O Analog test pin for SerDes, Lane 0 to Lane 3. It can be left open if not used. AMUX1 E3 I/O Analog test pin for SerDes, Lane 4 to Lane 7. It can be left open if not used. ATEST K9 I/O Analog test pin for DAC, references and PLL. It can be left open if not used. Positive LVPECL clock input for DAC core with Vcm = 0.5V. It can be PLL reference clock or DACCLKP A10 I external DAC sampling rate clock. If not used, DACCLK is self-biased with 100mV differential at Vcm = 0.5V. DACCLKN A9 I Complementary LVPECL clock input for DAC core. (see the DACCLKP description) Used as external reference input when internal reference is disabled through config27 extref_ena = ‘1’. Used as internal reference output when config27 extref_ena = ‘0’(default).EXTIO F10 I/O Requires a 0.1 μF decoupling capacitor to analog GND when used as reference output. It can be left open if not used. A12, F12, G12, M12, A11, B11, C11, D11, E11, F11, G11, H11, J11, K11, L11, M11, C8, D8, E8, F8, G8, H8, J8,GND I These pins are ground for all supplies.E7, F7, G7, H7, E6, F6, G6, H6, A5, B5, E5, F5, G5, H5, A4, B4, M4, B3, C3, L3, B2, C2, D2, E2, H2, J2, K2, L2 IFORCE C5 I/O Analog test pin for on chip parametric. It can be left open if not used. IOUTAP B12 O A-Channel DAC current output. Must tied to GND if not used. IOUTAN C12 O A-Channel DAC complementary current output. Must tied to GND if not used. IOUTBP E12 O B-Channel DAC current output. Must tied to GND if not used. IOUTBN D12 O B-Channel DAC complementary current output. Must tied to GND if not used. IOUTCP H12 O C-Channel DAC current output. Must tied to GND if not used. IOUTCN J12 O C-Channel DAC complementary current output. Must tied to GND if not used. IOUTDP L12 O D-Channel DAC current output. Must tied to GND if not used. IOUTDN K12 O D-Channel DAC complementary current output. Must tied to GND if not used. LPF C9 I/O External PLL loop filter connection. It can be left open if not used. Full-scale output current bias. Change the full-scale output current through coarse_dac(3:0).RBIAS G10 O Expected to be 1.92kΩ to GND. Active low input for chip RESET, which resets all the programming registers to their defaultRESETB K8 I state. Internal pull-up. It can be left open if not used. CML SerDes interface lane 0 input, positive, expected to be AC coupled. It can be left open ifRX0P G1 I not used. CML SerDes interface lane 0 input, negative, expected to be AC coupled. It can be left open ifRX0N H1 I not used. CML SerDes interface lane 1 input, positive, expected to be AC coupled. It can be left open ifRX1P K1 I not used. CML SerDes interface lane 1 input, negative, expected to be AC coupled. It can be left open ifRX1N J1 I not used. CML SerDes interface lane 2 input, positive, expected to be AC coupled. It can be left open ifRX2P L1 I not used. CML SerDes interface lane 2 input, negative, expected to be AC coupled. It can be left open ifRX2N M1 I not used. CML SerDes interface lane 3 input, positive, expected to be AC coupled. It can be left open ifRX3P M3 I not used.

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DAC37J82, DAC38J82 www.ti.com SLASE16B – JANUARY 2014– REVISED MAY 2014 Pin Functions (continued) PIN I/O DESCRIPTION NAME NUMBER CML SerDes interface lane 3 input, negative, expected to be AC coupled. It can be left open ifRX3N M2 I not used. CML SerDes interface lane 4 input, positive, expected to be AC coupled. It can be left open ifRX4P F1 I not used. CML SerDes interface lane 4 input, negative, expected to be AC coupled. It can be left open ifRX4N E1 I not used. CML SerDes interface lane 5 input, positive, expected to be AC coupled. It can be left open ifRX5P C1 I not used. CML SerDes interface lane 5 input, negative, expected to be AC coupled. It can be left open ifRX5N D1 I not used. CML SerDes interface lane 6 input, positive, expected to be AC coupled. It can be left open ifRX6P B1 I not used. CML SerDes interface lane 6 input, negative, expected to be AC coupled. It can be left open ifRX6N A1 I not used. CML SerDes interface lane 7 input, positive, expected to be AC coupled. It can be left open ifRX7P A3 I not used. CML SerDes interface lane 7 input, negative, expected to be AC coupled. It can be left open ifRX7N A2 I not used. LVPECL SYSREF positive input with Vcm = 0.5V. This positive/negative pair is captured with the rising edge of DACCLKP/N. It is used for JESD204B Subclass 1 deterministic latency andSYSREFP A7 I multiple DAC synchronization, which can be periodic or pulsed. If not used, it is self-biased with 100mV differential at Vcm = 0.5V. SYSREFN A6 I LVPECL SYSREF negative input with Vcm = 0.5V. (See the SYSREFP description) SCLK L9 I Serial interface clock. Internal pull-down. It can be left open if not used. Active low serial data enable, always an input to the DAC37J82/DAC38J82. Internal pull-up. ItSDENB M9 I can be left open if not used. Serial interface data. Bi-directional in 3-pin mode (default) and 4-pin mode. Internal pull-down.SDIO L10 I/O It can be left open if not used. Uni-directional serial interface data in 4-pin mode. The SDO pin is tri-stated in 3-pin interfaceSDO M10 O mode (default). It can be left open if not used. Active high asynchronous hardware power-down input. Internal pull-down. It can be left open ifSLEEP M8 I not used. SYNCBP B7 O Synchronization request to transmitter, LVDS positive output. It can be left open if not used. SYNCBN B6 O Synchronization request to transmitter, LVDS negative output. It can be left open if not used. Synchronization request to transmitter, CMOS output. Defaults to link 0, but can beSYNC_N_AB L6 O programmable for any link. It can be left open if not used. Synchronization request to transmitter, CMOS output. Defaults to link 1, but can beSYNC_N_CD L7 O programmable for any link. It can be left open if not used. TCLK K4 I JTAG test clock. It can be left open if not used. TDI L5 I JTAG test data in. It can be left open if not used. TDO M5 O JTAG test data out. It can be left open if not used. TMS L4 I JTAG test mode select. It can be left open if not used. JTAG test reset. Must be tied to GND to hold the JTAG state machine status reset if the JTAGTRSTB J3 I port is not used. To enable analog output data transmission, set sif_txenable in register config3 to “1”or pull CMOS TXENABLE pin to high. Transmit enable active high input. Internal pull-down. ToTXENABLE K5 I disable analog output, set sif_txenable to “0”and pull CMOS TXENABLE pin to low. The DAC output is forced to midscale. It can be left open if not used. TESTMODE K3 O This pin is used for factory testing. Internal pull-down. It can be left open if not used. D10, E10, H10,VDDADAC33 I Analog supply voltage. (3.3V)J10, VDDAPLL18 B10, B9 I PLL analog supply voltage. (1.8V) VDDAREF18 C10, K10 I Analog reference supply voltage (1.8V) Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: DAC37J82 DAC38J82

DAC37J82, DAC38J82 SLASE16B – JANUARY 2014– REVISED MAY 2014 www.ti.com Pin Functions (continued) PIN I/O DESCRIPTION NAME NUMBER Internal clock buffer supply voltage (0.9V). It is recommended to isolate this supply fromVDDCLK09 A8, B8 I VDDDIG09. D9, E9, F9, G9,VDDDAC09 I DAC core supply voltage. (0.9V). It is recommended to isolate this supply from VDDDIG09.H9, J9 J7, J6, D5, J5, Digital supply voltage. (0.9V). It is recommended to isolate this supply from VDDCLK09 andVDDDIG09 D4, E4, F4, G4, I VDDDAC09.H4, J4, D3 VDDIO18 K7, K6 I Supply voltage for all digital I/O and CMOS I/O. (1.8V) VDDR18 F2, G2 I Supply voltage for SerDes (1.8V) VDDS18 C7, C6 I Supply voltage for LVDS SYNCBP/N (1.8V) VDDT09 F3, G3 I Supply voltage for SerDes termination (0.9V) Fuse supply voltage. This supply pin is also used for factory fuse programming. Connect toVQPS18 D7, D6 I 1.8V. VSENSE C4 I/O Analog test pin for on chip parametric. It can be left open if not used.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT VDDDAC09, VDDDIG09 –0.3 1.3 V VDDCLK09 –0.3 1.3 V VDDT09 –0.3 1.3 VSupply voltage(2) VDDR18, VDDIO18, VDDS18, VQPS18 –0.3 2.45 V VDDAPLL18, VDDAREF18 –0.3 2.45 V VDDADAC33 –0.3 4.0 V RX[7..0]P/N –0.5 V VDDT09 + 0.5 V V SDENB, SCLK, SDIO, SDO, TXENA, ALARM, RESETB, SLEEP, TMS, –0.5 V VDDIO18 + 0.5 V VTCLK, TDI, TDO, TRSTB, TESTMODE, SYNC_N_AB, SYNC_N_CD DACCLKP/N, SYSREFP/N –0.5 V VDDAPLL18 + 0.5 V V SYNCBP/N –0.5 V VDDS18 + 0.5 V V Pin voltage(2) LPF –0.5 V VDDAPLL18 + 0.5 V V IOUTAP/N, IOUTBP/N, IOUTCP/N, IOUTDP/N –0.5 V 1.0 V V RBIAS, EXTIO, ATEST –0.5 V VDDAREF18 + 0.5 V V IFORCE, VSENSE –0.5 V VDDDIG09 + 0.5 V V AMUX1, AMUX0 –0.5 V VDDT09 + 0.5 V V Peak input current (any input) 20 mA Peak total input current (all inputs) –30 mA Absolute maximum junction temperature TJ 150 °C Operating free-air temperature range, TA: DAC37J82/DAC38J82 –40 85 °C (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of these or any other conditions beyond those indicated under “recommended operating conditions”is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) Measured with respect to GND.

6.2 Handling Ratings

Tstg Storage temperature range –65 150 °C

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6.3 Recommended Operating Conditions

Recommended operating junction temperature(1) 105 °C TJ Maximum rated operating junction temperature 125 °C TA Recommended free-air temperature -40 25 85 °C (1) Prolonged use at this junction temperature may increase the device failure-in-time (FIT) rate.

6.4 Thermal Information

THERMAL CONDUCTIVITY(1) UNIT AAV (144 PINS) RθJA Theta junction-to-ambient (still air) 31.4 RθJB Theta junction-to-board 12.6 RθJC Theta junction-to-case, top 1.8 °C/W ψJT Psi junction-to-top of package 0.2 ψJB Psi junction-to-bottom of package 12 (1) Air flow or heat sinking reduces θJA and may be required for sustained operation at 85° and maximum operating conditions.

6.5 DC Electrical Characteristics

Typical values at TA = 25°C, full temperature range is TMIN = -40°C to TMAX = 85°C, nominal supplies, unless otherwise noted. DAC37J82 DAC38J82 PARAMETER TEST CONDITIONS UNIT MIN TYP MAX MIN TYP MAX Resolution 16 16 Bits DC ACCURACY DNL Differential nonlinearity ±4 ±4 LSB1 LSB = IOUTFS/216 INL Integral nonlinearity ±6 ±6 LSB ANALOG OUTPUT Coarse gain linearity ±0.04 ±0.04 LSB Offset error Mid code offset ±0.001 ±0.001 %FSR With external reference ±2 ±2 Gain error %FSR With internal reference ±2 ±2 Gain mismatch With internal reference ±2 ±2 %FSR Full scale output current 20 30 20 30 mA Output compliance range –0.5 0.6 –0.5 0.6 V Output resistance 300 300 kΩ Output capacitance 5 5 pF REFERENCE OUTPUT VREF Reference output voltage 0.9 0.9 V Reference output current(1) 100 100 nA REFERENCE INPUT VEXTIO Input voltage range External reference mode 0.1 0.9 1 0.1 0.9 1 V Input resistance 1 1 MΩ Input capacitance 50 50 pF TEMPERATURE COEFFICIENTS Offset drift ±1 ±1 Ppm/°C With external reference ±15 ±15 Gain drift ppm/°C With internal reference ±30 ±30 Reference voltage drift ±8 ±8 ppm/°C (1) Use an external buffer amplifier with high impedance input to drive any external load. Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: DAC37J82 DAC38J82

DAC37J82, DAC38J82 SLASE16B – JANUARY 2014– REVISED MAY 2014 www.ti.com Typical values at TA = 25°C, full temperature range is TMIN = -40°C to TMAX = 85°C, nominal supplies, unless otherwise noted. DAC37J82 DAC38J82 PARAMETER TEST CONDITIONS UNIT MIN TYP MAX MIN TYP MAX POWER SUPPLY PSRR Power Supply Rejection Ratio DC tested ±0.2 ±0.2 %FSR/V POWER CONSUMPTION I(VDDADAC33) Analog supply current - 64 80MODE 1:(DAC38J82) I(VDDDIG09) Digital supply current - 628 800fDAC=2.46GSPS, 2x interpolation,I(VDDDAC09) DAC supply current - 13 25 NCO on, QMC on, inverse I(VDDCLK09) Clock supply current - 86 120 mAsinc on, GDC off, PAP off, PLL on,I(VDDT09) SerDes core supply current - 168 250 LMF=421, I(VDDR18) SerDes analog supply current - 18 35SerDes rate = 12.3GSPS, 20mA FS output,I(VDD18) Other 1.8V supply current - 53 80 IF=150MHz.P Power dissipation - 1144 1290(2) mW I(VDDADAC33) Analog supply current 64 64 MODE 2: (DAC37J82)I(VDDDIG09) Digital supply current 418 418 fDAC=1.6GSPS, 2xI(VDDDAC09) DAC supply current 10 10interpolation, I(VDDCLK09) Clock supply current 57 57 mANCO on, QMC on, invsinc on, GDC off, PAP off, PLL on,I(VDDT09) SerDes core supply current 139 139 LMF=421, I(VDDR18) SerDes analog supply current 12 12SerDes rate = 8GSPS, I(VDD18) Other 1.8V supply current 50 5020mA FS output, IF=150MHz. P Power dissipation 884 884 mW I(VDDADAC33) Analog supply current 64 64 MODE 3:I(VDDDIG09) Digital supply current 363 363 fDAC=1.47456GSPS, 2xI(VDDDAC09) DAC supply current 10 10interpolation, I(VDDCLK09) Clock supply current 50 50 mANCO on, QMC off, invsinc off, GDC off,I(VDDT09) SerDes core supply current 135 135 PAP off, PLL off, LMF=421, I(VDDR18) SerDes analog supply current 12 12SerDes rate = 7.3728GSPS, I(VDD18) Other 1.8V supply current 30 3020mA FS output, IF=150MHz. P Power dissipation 789 789 mW I(VDDADAC33) Analog supply current 64 64 MODE 4:I(VDDDIG09) Digital supply current 312 312 fDAC=1.47456GSPS, 4xI(VDDDAC09) DAC supply current 10 10interpolation, I(VDDCLK09) Clock supply current 50 50 mANCO on, QMC off, invsinc off, GDC off, PAP off, PLL off,I(VDDT09) SerDes core supply current 76 76 LMF=222,I(VDDR18) SerDes analog supply current 12 12SerDes rate = 7.3728GSPS, I(VDD18) Other 1.8V supply current 30 3020mA FS output, IF=150MHz. P Power dissipation 690 690 mW (2) The MAX power limit is set separately which is NOT equal to the power consumption when all of the power supplies are at the MAX current.

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DAC37J82, DAC38J82 www.ti.com SLASE16B – JANUARY 2014– REVISED MAY 2014 Typical values at TA = 25°C, full temperature range is TMIN = -40°C to TMAX = 85°C, nominal supplies, unless otherwise noted. DAC37J82 DAC38J82 PARAMETER TEST CONDITIONS UNIT MIN TYP MAX MIN TYP MAX I(VDDADAC33) Analog supply current 13 13 I(VDDDIG09) Digital supply current 263 263MODE 5: I(VDDDAC09) DAC supply current 8 8fDAC=1.47456GSPS, x4, NCO off, QMC off, invsinc off,I(VDDCLK09) Clock supply current 50 50 mA GDC off, PAP off, I(VDDT09) SerDes core supply current 76 76PLL off, LMF=222, SerDes rate = 7.3728GSPS,I(VDDR18) SerDes analog supply current 12 12 DAC output in sleep mode.I(VDD18) Other 1.8V supply current 26 26 P Power dissipation 469 469 mW I(VDDADAC33) Analog supply current 64 64 MODE 6:I(VDDDIG09) Digital supply current 257 257 fDAC=1000MSPS, 2xI(VDDDAC09) DAC supply current 8 8interpolation, I(VDDCLK09) Clock supply current 36 36 mANCO off, QMC off, invsinc off, GDC off, PAP off, PLL on,I(VDDT09) SerDes core supply current 85 85 LMF=222, SerDes rate =I(VDDR18) SerDes analog supply current 15 1510GSPS, I(VDD18) Other 1.8V supply current 50 5020mA FS output, IF=150MHz. P Power dissipation 676 676 mW I(VDDADAC33) Analog supply current 64 64 MODE 7:I(VDDDIG09) Digital supply current 256 256 fDAC=1000MSPS, 2xI(VDDDAC09) DAC supply current 8 8interpolation, I(VDDCLK09) Clock supply current 35 35 mANCO off, QMC off invsinc off, GDC off,I(VDDT09) SerDes core supply current 85 85 PAP off, PLL off, LMF=222,I(VDDR18) SerDes analog supply current 15 15SerDes rate = 10GSPS, I(VDD18) Other 1.8V supply current 29 2920mA FS output, IF=150MHz. P Power dissipation 636 636 mW I(VDDADAC33) Analog supply current 64 64 MODE 8:I(VDDDIG09) Digital supply current 195 195 fDAC=625MSPS, 2xI(VDDDAC09) DAC supply current 4 4interpolation, I(VDDCLK09) Clock supply current 22 22 mANCO off, QMC off, invsinc off, GDC off,I(VDDT09) SerDes core supply current 119 119 PAP off, PLL off, LMF=421,I(VDDR18) SerDes analog supply current 11 11SerDes rate = 3.125GSPS, I(VDD18) Other 1.8V supply current 25 2520mA FS output, IF=20MHz. P Power dissipation 582 582 mW I(VDDADAC33) Analog supply current 64 64 MODE 9:I(VDDDIG09) Digital supply current 311 311 fDAC=1.23GSPS, noI(VDDDAC09) DAC supply current 10 10interpolation, I(VDDCLK09) Clock supply current 42 42 mANCO off, QMC off, invsinc off, GDC off,I(VDDT09) SerDes core supply current 165 165 PAP off, PLL off, LMF=421, I(VDDR18) SerDes analog supply current 18 18SerDes rate = 12.3GSPS, I(VDD18) Other 1.8V supply current 29 2920mA FS output, IF=150MHz; P Power dissipation 771 771 mW I(VDDADAC33) Analog supply current 5 5 I(VDDDIG09) Digital supply current 76 76 I(VDDDAC09) DAC supply current 1 1MODE 10: I(VDDCLK09) Clock supply current 1 1 mAPower down mode, no clock, DAC in sleep mode,I(VDDT09) SerDes core supply current 9 9 SerDes in sleep modeI(VDDR18) SerDes analog supply current 0 0 I(VDD18) Other 1.8V supply current 10 10 P Power dissipation 112 112 mW Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Links: DAC37J82 DAC38J82

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6.6 Digital Electrical Characteristics

Typical values at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, nominal supplies, unless otherwise noted. DAC37J82 DAC38J82 PARAMETER TEST CONDITIONS UNIT MIN TYP MAX MIN TYP MAX CML SERDES INPUTS: RX[7:0]P/N VDIFF Receiver input amplitude 50 1200 50 1200 mV Input common mode 600 600(TERM=111) Input common mode 700 700(TERM=001) VCOM mV Input common mode 0 0(TERM=100) Input common mode 250 250(TERM=101) Internal differentialZDIFF 85 100 115 85 100 115 Ωtermination fDATA Serdes bit rate 0.78125 12.5 0.78125 12.5 Gbps LVPECL INPUTS: SYSREFP/N VCOM Input common mode voltage 0.5 0.5 V Differential input peak-to-VIDPP 400 800 400 800 mVpeak voltage ZT Internal termination 100 100 Ω CL Input capacitance 2 2 pF LVPECL INPUTS: DACCLKP/N VCOM Input common mode voltage 0.5 0.5 V Differential input peak-to-VIDPP 400 800 400 800 mVpeak voltage ZT Internal termination 100 100 Ω CL Input capacitance 2 2 pF Duty cycle 40% 60% 40% 60% DACCLKP/N InputfDACCLK 1.6 2.5 GHzFrequency LVDS OUTPUTS: SYNCBP/N Output common modeVCOM 1.2 1.2 Vvoltage ZT Internal termination 100 100 Ω Differential output voltageVOD 0.5 0.5 Vswing CMOS INTERFACE: SDENB, SCLK, SDIO, SDO, TXENA, ALARM, RESETB, SLEEP, TMS, TCLK, TDI, TDO, TRSTB, TESTMODE, SYNC_N_AB, SYNC_N_CD 0.7 x 0.7 x VIH High-level input voltage VDDIO1 VDDIO1 V 8 8 0.3 x 0.3 x VIL Low-level input voltage VDDI VDDIO V O18 18 IIH High-level input current -40 40 -40 40 µA IIL Low-level input current -40 40 -40 40 µA CI CMOS Input capacitance 2 2 pF VDDIO1 VDDIO1Iload =–100 μA 8 – 0.2 8 – 0.2 VOH ALARM, SDO, SDIO, TDO V0.8 x 0.8 x Iload = –2 mA VDDIO1 VDDIO1 8 8 Iload = 100 μA 0.2 0.2 VOL ALARM, SDO, SDIO, TDO V Iload = 2 mA 0.5 0.5

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DAC37J82, DAC38J82 www.ti.com SLASE16B – JANUARY 2014– REVISED MAY 2014 Digital Electrical Characteristics (continued) Typical values at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, nominal supplies, unless otherwise noted. DAC37J82 DAC38J82 PARAMETER TEST CONDITIONS UNIT MIN TYP MAX MIN TYP MAX PHASE LOCKED LOOP pll_vcosel = '1', pll_vco = '010001'(17), pll_vcoitune = '10', VCO Frequency = Assured Assured 3932.16MHz pll_vcosel = '1', pll_vco = '011111'(31), pll_vcoitune = '10', VCO Frequency = Assured Assured 4120MHz pll_vcosel = '1', pll_vco = '110010'(50), pll_vcoitune = '10', VCO Frequency = Assured Assured 4423.68MHz pll_vcosel = '0', pll_vco = '001101'(13), PLL/VCO operating frequency pll_vcoitune = '11', VCO Frequency = Assured Assured 4608MHz pll_vcosel = '0', pll_vco = '011010'(26), pll_vcoitune = '11', VCO Frequency = Assured Assured 4800MHz pll_vcosel = '0', pll_vco = '100001'(33), pll_vcoitune = '11', VCO Frequency = Assured Assured 4915.2MHz pll_vcosel = '0', pll_vco = '100110'(38), pll_vcoitune = '11', VCO Frequency = Assured Assured 5000MHz

6.7 AC Electrical Characteristics

Typical values at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, nominal supplies, unless otherwise noted. DAC37J82 DAC38J82 PARAMETER TEST CONDITIONS / COMMENTS UNIT MIN TYP MAX MIN TYP MAX ANALOG OUTPUT (1) 4x or higher interpolation 1600 2500 fDAC Maximum DAC rate 2x interpolation 1600 2460 MSPS 1x interpolation 1230 1230 No interpolation, FIFO off, Mixer off, QMC off, Inverse 11 11sinc off 2x Interpolation 83 83 4x Interpolation 211 211 8x Interpolation 483 483 16x Interpolation 1051 1051 NCO 48 48Digital latency DAC clock QMC 32 32 cycles(F=2, 2x interpolation) Inverse Sinc 36 36 PA Protection (pap_dlylen_sel = "0") 68 68 Dithering 0 0 Complex Summation 0 0 Coarse Fractional Delay 51 51 Fine Fractional Delay 52 52 (1) Measured single ended into 50 Ω load. Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Links: DAC37J82 DAC38J82

DAC37J82, DAC38J82 SLASE16B – JANUARY 2014– REVISED MAY 2014 www.ti.com Typical values at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, nominal supplies, unless otherwise noted. DAC37J82 DAC38J82 PARAMETER TEST CONDITIONS / COMMENTS UNIT MIN TYP MAX MIN TYP MAX AC PERFORMANCE (2) fDAC = 2.5 GSPS, fOUT = 20 MHz, 0 dBFS - 79 fDAC = 2.5 GSPS, fOUT = 70 MHz, 0dBFS - 78 fDAC = 2.5 GSPS, fOUT = 150 MHz, 0 dBFS - 72 fDAC = 2.5 GSPS, fOUT = 230 MHz, 0dBFS - 67 fDAC = 2.5 GSPS, fOUT = 20 MHz, -12 dBFS - 79 fDAC = 2.5 GSPS, fOUT = 70 MHz, –12dBFS - 75 fDAC = 2.5 GSPS, fOUT = 150 MHz, -12 dBFS - 70 fDAC = 2.5 GSPS, fOUT = 230 MHz, –12dBFS - 65Spurious free dynamicSFDR dBc(0 to fDAC/2) fDAC = 1.6 GSPS, fOUT = 20 MHz, 0 dBFS 81 81 fDAC = 1.6 GSPS, fOUT = 70 MHz, 0 dBFS 77 77 fDAC = 1.6 GSPS, fOUT = 150 MHz, 0 dBFS 72 72 fDAC = 1.6 GSPS, fOUT = 230 MHz, 0 dBFS 68 68 fDAC = 1.6 GSPS, fOUT = 20 MHz, -12 dBFS 76 76 fDAC = 1.6 GSPS, fOUT = 70 MHz, –12 dBFS 72 72 fDAC = 1.6 GSPS, fOUT = 150 MHz, -12 dBFS 67 67 fDAC = 1.6 GSPS, fOUT = 230 MHz, –12 dBFS 64 64 fDAC = 2.5 GSPS, fOUT = 70 ± 0.5 MHz - 83 fDAC = 2.5 GSPS, fOUT = 150 ± 0.5 MHz - 75 fDAC = 2.5 GSPS, fOUT = 230 ± 0.5 MHz - 70 fDAC = 2.0 GSPS, fOUT = 70 ± 0.5 MHz - 86Third-order two-tone IMD3 intermodulation distortion fDAC = 2.0 GSPS, fOUT = 150 ± 0.5 MHz - 78 dBc Each tone at –6dBFS fDAC = 2.0 GSPS, fOUT = 230 ± 0.5 MHz - 73 fDAC = 1.6 GSPS, fOUT = 70 ± 0.5 MHz 83 83 fDAC = 1.6 GSPS, fOUT = 150 ± 0.5 MHz 73 73 fDAC = 1.6 GSPS, fOUT = 230 ± 0.5 MHz 66 66 fDAC = 2.5 GSPS, fOUT = 70 MHz - -161 fDAC = 2.5 GSPS, fOUT = 150 MHz - –159 fDAC = 2.5 GSPS, fOUT = 230 MHz - -157 fDAC = 2.0 GSPS, fOUT = 70 MHz - -161 Noise spectral density(2) NSD fDAC = 2.0 GSPS, fOUT = 150 MHz - -160 dBFS/HzTone at –6dBFS fDAC = 2.0 GSPS, fOUT = 230 MHz - -158 fDAC = 1.6 GSPS, fOUT = 70 MHz -161 -161 fDAC = 1.6 GSPS, fOUT = 150 MHz -159 -159 fDAC = 1.6 GSPS, fOUT = 230 MHz -157 -157 fDAC = 2.4576 GSPS, fOUT = 70 MHz - 82 fDAC = 2.4576 GSPS, fOUT = 150 MHz - 80 fDAC = 2.4576 GSPS, fOUT = 230 MHz - 78 fDAC = 1.96608 GSPS, fOUT = 70 MHz - 82 Adjacent channel leakageACLR(3) fDAC = 1.96608 GSPS, fOUT = 150 MHz - 80 dBcratio, single carrier fDAC = 1.96608 GSPS, fOUT = 230 MHz - 77 fDAC = 1.47456 GSPS, fOUT = 70 MHz 82 82 fDAC = 1.47456 GSPS, fOUT = 150 MHz 80 80 fDAC = 1.47456 GSPS, fOUT = 230 MHz 76 76 fDAC = 2.5 GSPS, fOUT = 20 MHz - 93 Channel isolation dBc fDAC = 1.6 GSPS, fOUT = 20 MHz 93 93 (2) 2:1 transformer output termination, 50 Ω doubly terminated load. (3) Single carrier, W-CDMA with 3.84 MHz BW, 5-MHz spacing, centered at IF. TESTMODEL 1, 10 ms

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Product Folder Links: DAC37J82 DAC38J82

DAC37J82, DAC38J82 www.ti.com SLASE16B – JANUARY 2014– REVISED MAY 2014

6.8 Timing Requirements

Typical values at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, nominal supplies, unless otherwise noted. DAC37J82 DAC38J82 PARAMETER TEST CONDITIONS UNIT MIN TYP MAX MIN TYP MAX DIGITAL INPUT TIMING SPECIFICATIONS TIMING SYSREF INPUT: DACCLKP/N RISING EDGE LATCHING Setup time, SYSREFP/N ts(SYSREF) valid to rising edge of 50 50 ps DACCLKP/N Hold time, SYSREF/N valid th(SYSREF) after rising edge of 50 50 ps DACCLKP/N TIMING SERIAL PORT Setup time, SDENB to risingts(SDENB) 20 20 nsedge of SCLK Setup time, SDIO valid tots(SDIO) 10 10 nsrising edge of SCLK Hold time, SDIO valid toth(SDIO) 5 5 nsrising edge of SCLK Register config7 read 1 1 µs(temperature sensor read)t(SCLK) Period of SCLK All other registers 100 100 ns Data output delay after fallingtd(Data) 10 10 nsedge of SCLK Minimum RESETBtRESET 25 25 nspulsewidth ANALOG OUTPUT (1) ts(DAC) Output settling time to 0.1% Transition: Code 0x0000 to 0xFFFF 10 10 ns IOUT current settling to 1% of IOUTFS fromDAC wake-up time 90 90deep sleepPower- µsup Time IOUT current settling to less than 1% ofDAC sleep time 90 90IOUTFS in deep sleep (1) Measured single ended into 50 Ω load.

6.9 Switching Characteristics

Typical values at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, nominal supplies, unless otherwise noted. DAC37J82 DAC38J82 PARAMETER TEST CONDITIONS UNIT MIN TYP MAX MIN TYP MAX ANALOG OUTPUT (1) Output propagation delay DAC outputs are updated on the falling tpd edge of DAC clock. Does not include 2 2 ns Digital Latency (see below). Output rise time 10% totr(IOUT) 50 50 ps90% Output fall time 90% totf(IOUT) 50 50 ps10% (1) Measured single ended into 50 Ω load. Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback 13 Product Folder Links: DAC37J82 DAC38J82

6.10 Typical Characteristics

input, 20mA full scale output current with 2:1 transformer, LMF = 421 and PLL is disabled. Figure 1. Integral Nonlinearity Figure 2. Differential Nonlinearity Figure 3. SFDR vs Output Frequency Over Input Scale Figure 4. Second Harmonic Distortion vs Output Frequency Figure 5. Third Harmonic Distortion vs Output Frequency Figure 6. SFDR vs Output Frequency Over Interpolation

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input, 20mA full scale output current with 2:1 transformer, LMF = 421 and PLL is disabled. Figure 13. IMD3 vs Output Frequency Over Input Scale Figure 14. IMD3 vs Output Frequency Over Interpolation Figure 15. IMD3 vs Output Frequency Over fDAC Figure 16. IMD3 vs Output Frequency Over Output Current Figure 17. IMD3 vs Output Frequency Over Clocking Figure 18. Two-tone Spectral Plot

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input, 20mA full scale output current with 2:1 transformer, LMF = 421 and PLL is disabled. Figure 25. NSD vs Output Frequency Over Clocking Options Figure 26. ACLR (Adjacent Channel) vs Output Frequency Figure 27. ACLR (Alternate Channel) vs Output Frequency Figure 28. ACLR (Adjacent Channel) vs Output Frequency Figure 29. ACLR (Alternate Channel) vs Output Frequency Figure 30. Channel Isolation

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input, 20mA full scale output current with 2:1 transformer, LMF = 421 and PLL is disabled. Figure 37. 1.8V Supply Current Excluding VDDR18 vs fDAC Figure 38. VDDDIG09 Current vs fDAC Over Digital Figure 39. VDDDIG09 Current vs fDAC Over Interpolation Figure 40. Power Consumption vs fDAC Over Interpolation Figure 41. VDDDIG09 Current vs fDAC Over Interpolation Figure 42. Power Consumption vs fDAC Over Interpolation

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217.250000000 MHz

168.250000000 MHz

88.250000000 MHz

137.250000000 MHz

82.750000000 MHz

input, 20mA full scale output current with 2:1 transformer, LMF = 421 and PLL is disabled. Figure 49. 10MHz Single Carrier LTE Test Mode 3.1 Figure 50. 10MHz Single Carrier LTE Test Mode 3.1 Figure 51. 10MHz Single Carrier LTE Test Mode 3.1 Figure 52. 20MHz Single Carrier LTE Test Mode 3.1 Figure 53. 20MHz Single Carrier LTE Test Mode 3.1 Figure 54. 20MHz Single Carrier LTE Test Mode 3.1

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(FMIX or CMIX) AB-QMC Gain and Phase 16-b DACA 16-b DACB Control Interface Temp Sensor Clock Distribution EXTIO RBIAS IOUTAP IOUTAN IOUTBP IOUTBN DACCLKP DACCLKN D7P D7N D0P D0N SYSREFP SYSREFN QMC A-offset QMC B-offset SDO SDIO SDENB SCLK TXENABLE RESETB VDDCLK09 VDDDIG09 VQPS18 VDDADAC33 GND LVPECL LVPECL JESD204B Interface xN xN x sin(x) x sin(x) IOUTCP IOUTCN IOUTDP IOUTDN DAC Gain 16-b DACC 16-b DACD Low Jitter PLL FIR4 AB 48-bit NCO cos sin ALARM SLEEP SYNCBP SYNCBN TESTMODE PLLLPF VDDAPLL18 VDDIO 1.2 V Reference Serial Lanes Fractional Delay Fractional Delay Input Mux Output Mux VDDADAC09 VDDS18 VDDT09 VDDR18 JTAG TCLK TDI TDO TMS TRSTB ATEST AMUX0/1 IFORCE VSENSE TESTMODE VDDAREF18 PA Protect Dither CMIX (± n*Fs/8) DAC37J82, DAC38J82 www.ti.com SLASE16B – JANUARY 2014– REVISED MAY 2014

7 Detailed Description

7.1 Overview

The pin-compatible DAC37J82/DAC38J82 family is a very low power, 16-bit, 1.6/2.5 GSPS digital to analog converter (DAC) with JESD204B interface up to 12.5 Gbps. The maximum input data rate is 1.23 GSPS. The DAC37J82/DAC38J82 family is also pin-compatible with the 16-bit, dual-channel, 1.6/2.5GSPS DAC37J82/DAC38J82. Digital data is input to the device through 1, 2, 4 or 8 configurable serial JESD204B lanes running up to 12.5 Gbps with on-chip termination and programmable equalization. The interface allows JESD204B Subclass 1 SYSREF based deterministic latency and full synchronization of multiple devices. The device includes features that simplify the design of complex transmit architectures. Fully bypassable 2x to 16x digital interpolation filters with over 90 dB of stop-band attenuation simplify the data interface and reconstruction filters. An on-chip 48-bit Numerically Controlled Oscillator (NCO) and independent complex mixers allow flexible and accurate carrier placement. A high-performance low jitter PLL simplifies clocking of the device without significant impact on the dynamic range. The digital Quadrature Modulator Correction (QMC) and Group Delay Correction (GDC) enable complete wideband IQ compensation for gain, offset, phase, and group delay between channels in direct up-conversion applications. A programmable Power Amplifier (PA) protection mechanism is available to provide PA protection in cases when the abnormal power behavior of the input data is detected. DAC37J82/DAC38J82 family provides four analog outputs, and the data from the internal two digital paths can be routed to any two out of these four DAC outputs via the output multiplexer.

7.2 Functional Block Diagram

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7.3 Feature Description

7.3.1 Serdes Input

Figure 55. Serial Lane Input Termination (TERM), as described in Table 1. Table 1. Receiver Termination Selection

000 Reserved

mode, which is set to optimize the input sensitivity of the receiver. 100 Common point set to GND. This configuration is for applications that require a 0V common mode. 101 Common point set to 0.25V. This configuration is for applications that require a low common mode.

110 Reserved

transmit link parter to 0 and 0.6V. Note: this mode is not compatible with JESD204B. Data input is sampled by the differential sensing amplifier using clocks derived from the clock recovery algorithm. The polarity of RXP and RXN can be inverted by setting the INVPAIR [7:0] bit of the corresponding lane to “1”. (LOOPBACK) bit must be set to “00”.

7.3.2 Serdes Rate

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Table 2. Lane Rate Selection 00 Full rate. Four data samples taken per SerDes PLL output clock cycle. 01 Half rate. Two data samples taken per SerDes PLL output clock cycle.. 10 Quarter rate. One data samples taken per SerDes PLL output clock cycle. 11 Eighth rate. One data samples taken every two SerDes PLL output clock cycles.

7.3.3 Serdes PLL

reference frequency of the SerDes PLL can be in the range of 100-800MHz nominal, and 300-800MHz optimal. Figure 56. Reference Clock of SerDes PLL frequency, the reference frequency can be obtained by dividing this by the multiply factor specified via MPY. should not be employed without prior consultation with TI. Table 3. Relationship Between Lane Rate and SerDes PLL Output Frequency

Table 3. Relationship Between Lane Rate and SerDes PLL Output Table 4. SerDes PLL Modes Selection highest reference frequency achievable is always preferable. [9] (VRANGE) bit. If the PLL output frequency is below 2.17GHz, VRANGE should be set high. frequency as shown in Table 5. Table 5. SerDes PLL Loop Bandwidth Selection

00 Medium loop bandwidth 13 14 16

01 Ultra high loop bandwidth 7 8 8

10 Low loop bandwidth 21 23 30

11 High loop bandwidth 10 11 14

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7.3.4 Serdes Equalizer

Figure 57. Equalizer Frequency Response 6x106 divided by the CDR activity level. For CDR (rw_cfgrx0[18:16]) = 110, this is 1.5x106UI. Table 6. Receiver Equalization Configuration No equalization. The equalizer provides a flat response at the maximum gain. This setting may be appropriate0 if jitter at the receiver occurs predominantly as a result of crosstalk rather than frequency dependent loss. positions in the received data. This setting should be used for most applications. Precursor equalization analysis. The data patterns and transition positions in the received data are analyzed10 to determine whether the transmit link partner is applying more or less precursor equalization than necessary.

0 Default

[2] Boost. Equalizer gain boosted by 6dB, with a 20% reduction in bandwidth, and an increase of 5mW power1 consumption. May improve performance over long links.

Table 7. Receiver Equalizer Hold 0 Equalizer adaption enabled. The equalizer adaption and analysis algorithm is enabled. This should be the default state. Table 8. Receiver Equalizer Gain Boost

1. Enable the equalizer by setting EQHLD low and EQ to 001. Allow sufficient time for the equalizer to adapt;
2. Set EQHLD to 1 to lock the equalizer and reset the adaption algorithm. This also causes both EQOVER and
3. Wait at least 48UI, and proportionately longer if the CDR activity is less than 100%, to ensure the 1 on
4. Set EQ to 010 or 011, and EQHLD to 0. The equalization characteristics of the received signal are analysed
5. Wait at least 150×103UI to allow time for the analysis to occur, proportionately longer if the CDR activity is
6. Examine EQOVER and EQUNDER for results of analysis.
7. Repeat items 3–7 if required;
8. Set EQ to 001, and EQHLD to 0 to exit analysis mode and return to normal adaptive equalization.

case, there is a chance the equalizer could be reset by a transitory input state (i.e., if EQ is momentarily 000). EQHLD can be set to 0 at the same time as EQ is changed. adaptive equalizer can provide.

7.3.5 JESD204B Descrambler

test, see jesd_testbus_sel for the specific configuration needed.

7.3.6 JESD204B Frame Assembly

• L is the number of lanes per link
• M is the number of converters per device
• F is the number of octets per frame clock period

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• S is the number of samples per frame
• HD is the High-Density bit which controls whether a sample may be divided over more lanes. Table 9 list the available JESD204B formats for the DAC37J82/DAC38J82. Table 10 and Table 11 list the speed limits of DAC38J82/DAC37J82. The ranges are limited by the Serdes PLL VCO frequency range, the Serdes PLL reference clock range, the maximum Serdes line rate, and the maximum DAC sample frequency.

Table 9. JESD204B Frame Assembly Byte Representation

Table 10. DAC38J82 Speed Limits

16 N/A N/A N/A N/A N/A N/A N/A

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Table 11. DAC37J82 Speed Limits

7.3.7 Serial Peripheral Interface (SPI)

detailed description of each bit. The data transfer cycle consists of two bytes. Table 12. Instruction Byte of the Serial Interface [A6 : A0] Identifies the address of the register to be accessed during the read or write operation. Figure 58. Serial Interface Write Timing Diagram of SDENB when they will 3-state.

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Figure 59. Serial Interface Read Timing Diagram

• NORMAL: The NORMAL register type allows data to be written and read from. All 16-bits of the data are registered at the same time. There is no synchronizing with an internal clock thus all register writes are asynchronous with respect to internal clocks. There are three subtypes of NORMAL: – AUTOSYNC: A NORMAL register that causes a sync to be generated after the write is finished. These are used when it is desirable to synchronize the block after writing the register or in the case of a single field that spans across multiple registers. For instance, the NCO requires three 16-bit register writes to set the frequency. Upon writing the last of these registers an autosync is generated to deliver the entire field to the NCO block at once, rather than in pieces after each invidiual register write. For a field that spans multiple registers, all non-AUTOSYNC registers for the field must be written first before the actual AUTOSYNC register. – No RESET Value: These are NORMAL registers, but the reset value cannot be guaranteed. This could be because the register has some read_only bits or some internal logic partially controls the bit values.
• READ_ONLY: Registers that can be read from but not written to.
• WRITE_TO_CLEAR: These registers are just like NORMAL registers with one exception. They can be written and read, however, when the internal logic asynchronously sets a bit high in one of these registers, that bit stays high until it is written to ‘0’. This way interrupts will be captured and stay constant until cleared by the user. In the DAC37J82/DAC38J82, register config100-108 are WRTE_TO_CLEAR registers.

7.3.8 Multi-Device Synchronization

latency using SYSREF (JESD204B Subclass 1). the SYSREF input can be enabled and disabled via the SPI interface.

7.3.9 Input Multiplexer

to be routed to any signal cannel A-B. See pathx_in_sel for details on how to configure the cross-bar switches.

7.3.10 FIR Filters

limited to 1230MSPS. See more details in Table 10 and . with less than 0.03 dB error. the user is then able to optimize the back-off of the signal based on its frequency. SNR due to decrease in signal amplitude. Figure 60. Magnitude Spectrum for FIR0 Figure 61. Magnitude Spectrum for FIR1

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Figure 68. Magnitude Spectrum for Inverse Sinc Filter

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Table 13. FIR Filter Coefficients

59 Taps 23 Taps 11 Taps 11 Taps 9 Taps

(1) Center taps are highlighted in BOLD.

7.3.11 Full Complex Mixer

the complex mixing. The NCO block diagram is shown in Figure 69.

48 Accumulator48

16 Look Up

Figure 69. NCO Block Diagram modulator with a real output simply by only using the IOUT branch and ignoring the QOUT branch. Figure 70. Complex Mixer Block Diagram sine and cosine arguments are equal to 2π × fNCOt + δ (2N-1) x π/4 (N = 1, 2, ...).

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7.3.12 Coarse Mixer

mixers will result in lower power consumption. Table 14. Coarse Mixer Combinations

0000 Disabled Disabled Disabled Disabled No mixing

0001 Disabled Disabled Disabled Enabled –Fs/4

0010 Disabled Disabled Enabled Disabled Fs/2

0100 Disabled Enabled Disabled Disabled +Fs/4

1000 Enabled Disabled Disabled Disabled +Fs/8

1010 Enabled Disabled Enabled Disabled –3Fs/8

1100 Enabled Enabled Disabled Disabled +3Fs/8

1110 Enabled Enabled Enabled Disabled –Fs/8

7.3.13 Dithering

mixer. This feature is enabled by set dither_ena to “1” and can be useful in reducing the high order harmonics.

7.3.14 Complex Summation

B with Channel D, and the resulted complex summation are divided by 2 and sent via channel A and channel B. This feature is enabled by set output_sum to “1”and can be useful for multi-band application.

7.3.15 Quadrature Modulation Correction (QMC)

7.3.15.1 Gain and Phase Correction

contains 3 programmable parameters.

gain block that allows control with > 20 bits resolution, which can be used to improve the sideband suppression). dBc for a frequency independent IQ imbalance. LO feed-through can be minimized by adjusting the DAC offset feature described below. Figure 71. QMC Block Diagram

7.3.15.2 Offset Correction

to 4095. The LSB resolution of the offset allows LO suppression to better than 90 dBFS.

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Figure 72. Digital Offset Block Diagram

7.3.16 Group Delay Correction Block

A complex transmitter system typically is consisted of a DAC, reconstruction filter network, and I/Q modulator. or the original input to the block. The large fractional delay sub-block can also be completely bypassed if desired. A&B have the same integer delay, and channel C&D have the same integer delay.

Figure 73. Diagram of Group Delay Correction

7.3.16.1 Fine Fractional Delay FIR Filter

coefficients are fixed, which puts limits on the range of values each coefficient can acquire. Table 15. Small Fractional Delay FIR Coefficient Range

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Table 15. Small Fractional Delay FIR Coefficient Table 16. Example Coefficient Sets for the Small Fractional Delay

Table 16. Example Coefficient Sets for the Small Fractional Delay (continued)

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7.3.16.2 Coarse Fractional Delay FIR Filter

resultant fractional delay is provided in Table 17. Table 17. Available Coefficient Sets for Large Fractional Delay FIR

7.3.17 Output Multiplexer

pathx_out_sel for details on how to configure the cross-bar switches.

7.3.18 Power Measurement And Power Amplifier Protection

generate a single tone signal, which causes abnormally high average power and could be dangerous to the PA. derives from a delay-line, there is deterministic latency of at least N cycles from the block input to block output. The PA protection is enabled by setting the pap_ena bit to “1”.

Figure 74. Diagram of Power Measurement and PA Protection Mechanism

7.3.19 Serdes Test Modes

The DAC37J82/DAC38J82 supports a number of basic pattern generation and verification of SerDes via SIF. selection is via the TESTPATT fields of rw_cfgrx0[14:12], as shown in Table 18. Table 18. SerDes Test Pattern Selection 001 Alternating 0/1 Pattern. An alternating 0/1 pattern with a period of 2UI. 010 Generate or Verify 27-1 PRBS. Uses a 7-bit LFSR with feedback polynomial x7 + x6 + 1. 011 Generate or Verify 223 -1 PRBS. Uses an ITU O.150 conformant 23-bit LFSR with feedback polynomial x23 + x18 + 1. 100 Generate or Verify 231-1 PRBS. Uses an ITU O.150 conformant 31-bit LFSR with feedback polynomial x31 + x28 + 1. setting dtest[3:0] to “0011”.

• Accumulation of pattern verification errors;
• The ability to map out the width and height of the receive eye, known as Eye Scan;
• Real-time monitoring of internal voltages and currents; The SerDes blocks support the following IEEE1500 instructions:

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Table 19. IEEE1500 Instruction for SerDes Receivers ws_cfg 0x35 Configuration. Write protection options for other instructions. ws_core 0x30 Core. Fields also accessible via dedicated core-side ports. ws_tuning 0x31 Tuning. Fields for fine tuning macro performance. ws_unshadowed 0x34 Unshadowed. Fields for silicon characterization. ws_char 0x33 Char. Fields used for eye scan. written to SerDes Block R0 Data Registers should be prefixed with an extra 0. Table 20. ws_cfg Chain CORE_WE Core chain write enable. CORE_WE Core chain write enable. TUNING_WE Tuning chain write enable. CHAR_WE Char chain write enable. CORE_WE Core chain write enable. TUNING_WE Tuning chain write enable. Table 21. ws_core Chain

Table 21. ws_core Chain (continued) SLEEPRX Receiver sleep mode. ALIGN[1:0] Symbol alignment. LOS[2:0] Loss of signal enable. CDR[2:0] Clock/data recovery. BSINRXP Boundary scan initialization. BSINRXN Boundary scan initialization. testpatt[2:0] Testpattern selection. TESTFAIL Test failure (real time). LOSDTCT Loss of signal detected (real time). OCIP Offset compensation in progress. EQOVER Received signal over equalized. EQUNDER Received signal under equalized. LOSDTCT Loss of signal detected (sticky). BSINITCLK Boundary scan initialization clock. ENBSTX Enable Tx boundary scan. ENBSRX Enable Rx boundary scan. ENBSPT Rx pulse boundary scan. CFG OVR Configuration over-ride.

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Table 22. ws_tuning Chain PATTERRTHR[2:0] Resync error threshold. ENCOR Enable clear-on-read for error counter. EQZERO[4:0] EQZ OVRi Equalizer zero. EQZ OVR Equalizer zero over-ride. EQLEVEL[15:0] EQ OVRi Equalizer gain observe or set. EQBOOST[1:0] Equalizer gain boost. RXASEL[2:0] Selects amux output. ASEL[3:0] Selects amux output. USR PATT[19:0] User-defined test pattern. Table 23. ws_char Chain TESTFAIL Test failure (sticky). ESWORD[7:0] Eye scan word masking. ESPO[6:0] Eye scan phase offset. ES BIT SELECT[4:0] Eye scan compare bit select. ESVO[5:0] Eye scan voltage offset. ESVO OVR Eye scan voltage offset override. ESLEN[1:0] Eye scan run length.

7.3.20 Error Counter

section), though can be used independently of this..

7.3.21 Eye Scan

performed externally, typically in software.

• Enable dedicated eye scan input samplers, and generate an error when the value sampled differs from the normal data sample;
• Apply a voltage offset to the dedicated eye scan input samplers, to effectively reduce their sensitivity;
• Apply a phase offset to adjust the point in the eye that the dedicated eye scan data samples are taken;
• Reset the error counter to remove any false errors accumulated as a result of the voltage or phase offset adjustments;
• Run in this state for a period of time, periodically checking to see if any errors have occurred;
• Change voltage and/or phase offset, and repeat. Alternatively, the algorithm can be configured to optimize the voltage offset at a specified phase offset, over a specified time interval. Eye scan can be used in both synchronous and asynchronous systems, while receiving normal data traffic. The IEEE1500 Char fields used to directly control eye scan and symbol response extraction are ES, ESWORD, ES BIT SELECT, ESLEN, ESPO, ESVO, ESVO OVR, ESRUN and ESDONE, see Table 23. Eye scan errors are accumulated in ECOUNT. The required eyescan mode is selected via the ES field, as shown in Table 24. When enabled, only data from the bit position within the 20-bit word specified via ES BIT SELECT is analyzed. In other words, only eye scan errors associated with data output at this bit position will accumulate in ECOUNT. The maximum legal ES BIT SELECT is 10011.

Table 24. Eye Scan Mode Selection 0000 Disabled. Eye scan is disabled. 0x01 Compare. Counts mismatches between the normal sample and the eye scan sample if ES[2] = 0, and matches otherwise. 0x10 Compare zeros. As ES = 0x01, but only analyses zeros, and ignores ones. 0100 Count ones. Increments ECOUNT when the eye scan sample is a 1. is not necessary to set it back to 0). When analysis completes, ESDONE will be set to 1.

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Table 25. Eye Scan Run Length voltage offset to be read back via ESVO. Table 26. Eye Scan Voltage Offset as shown in Table 27. In normal use, the range should be limited to ±0.5UI (+15 to –16 phase steps). Table 27. Eye Scan Phase Offset

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7.3.22 JESD204B Pattern Test

The DAC37J82/DAC38J82 supports the following test patterns for JESD204B:

• Link layer test pattern – Verify repeating /D.21.5/ high frequency pattern for random jitter (RJ) – Verify repeating /K.28.5/ mixed frequency pattern for deterministic jitter (DJ) – Verify repeating initial lane alignment (ILA) sequence – RPAT, JSPAT or JTSPAT pattern can be verified using errors counter of 8b/10b errors produced over an amount of time to get an estimate of BER.
• Transport layer test pattern: implements a short transport layer pattern check based on F = 1,2,4 or 8. The short test pattern has a duration of one frame period and is repeated continuously for the duration of the test. Refer to JESD204B standard section 5.1.6 for more details. – F = 1 : Looks for a constant 0xF1. – F = 2 : Each frame should consist of 0xF1, 0xE2 – F = 4 : Looks for a constant 0xF1, 0xE2, 0xD3, 0xC4 – F = 8 : Each frame should consist of 0xF1, 0xE2, 0xD3, 0xC4, 0xB5, 0xA6, 0x97, 0x81 Users can select to output the internal data (ex, the 8b/10 decoder output, comma alignment output, lane alignment output, frame alignment output, descrambler output, etc ) of a JESD link for test purpose. See jesd_testbus_sel for configuration details.

7.3.23 Temperature Sensor

The DAC37J82/DAC38J82 incorporates a temperature sensor block which monitors the temperature by measuring the voltage across 2 transistors. The voltage is converted to an 8-bit digital word using a successive- approximation (SAR) analog to digital conversion process. The result is scaled, limited and formatted as a twos complement value representing the temperature in degrees Celsius. The sampling is controlled by the serial interface signals SDENB and SCLK. If the temperature sensor is enabled (tsense_sleep = “0” in register config26) a conversion takes place each time the serial port is written or read. The data is only read and sent out by the digital block when the temperature sensor is read in memin_tempdata in config7. The conversion uses the first eight clocks of the serial clock as the capture and conversion clock, the data is valid on the falling eighth SCLK. The data is then clocked out of the chip on the rising edge of the ninth SCLK. No other clocks to the chip are necessary for the temperature sensor operation. As a result the temperature sensor is enabled even when the device is in sleep mode. In order for the process described above to operate properly, the serial port read from config6 must be done with an SCLK period of at least 1 μs. If this is not satisfied the temperature sensor accuracy is greatly reduced.

7.3.24 Alarm Monitoring

The DAC37J82/DAC38J82 includes a flexible set of alarm monitoring that can be used to alert of a possible malfunction scenario. All the alarm events can be accessed either through the SIP registers and/or through the ALARM pin. Once an alarm is set, the corresponding alarm bit in register configtbd must be reset through the serial interface to allow further testing. The set of alarms includes the following conditions:

• JESD alarms – multiframe alignment_error. Occurs when multiframe alignment fails. – frame alignment error. Occurs when multiframe alignment fails. – link configuration error. Occurs when there is wrong link configuration. – elastic buffer overflow. Occurs when bad RBD value is used. – elastic buffer match error. Occurs when the first non-/K/ doesn’t match the programmed data. – code synchronization error. – 8b/10b not-in-table decode error. – 8b/10 disparity error. – alarm_from_shorttest. Occurs when fails the short pattern test.
• SerDes alarms – memin_rw_losdct. Occurs when there are loss of signal detect from SerDes lanes.

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Product Folder Links: DAC37J82 DAC38J82

– FIFO write error. Occurs if write request and FIFO is full. – FIFO write full: Occurs if FIFO is full. – FIFO read error. Occurs if read request and FIFO is empty. – FIFO read empty: Occurs if FIFO is empty. – alarm_rw0_pll. Occurs if the PLL in the SerDes block R0 goes out of clock. – alarm_rw1_pll. Occurs if the PLL in the SerDes block R0 goes out of clock.

• SYSREF alarm – alarm_sysref_err. Occurs when the SYSREF is received at an unexpected time. If too many of these occur it will cause the JESD to go into synchronization mode again.
• DAC PLL alarm – alarm_from_pll. Occurs when the DAC PLL is out of lock.
• PAP alarms – alarm_pap. Occurs when the average power is above the threshold. While any alarm_pap is asserted the attenuation for the appropriate data path is applied.

7.3.25 LVPECL Inputs

Figure 75 shows an equivalent circuit for the DAC input clock (DACCLKP/N) and the SYSREF (SYSREFP/N). Figure 75. DACCLKP/N and SYSREFP/N Equivalent Input Circuit

7.3.26 CMOS Digital Inputs

thresholds. The pull-up and pull-down circuitry is approximately equivalent to 100kΩ. Figure 76. CMOS Digital Equivalent Input

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7.3.27 Reference Operation

The DAC37J82/DAC38J82 uses a bandgap reference and control amplifier for biasing the full-scale output current. The full-scale output current is set by applying an external resistor RBIAS to pin BIASJ. The bias current IBIAS through resistor RBIAS is defined by the on-chip bandgap reference voltage and control amplifier. The default full-scale output current equals 64 times this bias current and can thus be expressed as: IOUTFS = 16 x IBIAS = 64 x VEXTIO / RBIAS The DAC37J82/DAC38J82 has a 4-bit coarse gain control coarse_dac(3:0) in the configtbd register. Using gain control, the IOUTFS can be expressed as: IOUTFS = (coarse_dac + 1) /16 x IBIAS x 64 = (coarse_dac + 1) /16 x VEXTIO / RBIAS x 64 where VEXTIO is the voltage at pin EXTIO. The bandgap reference voltage delivers an accurate voltage of 0.9V. This reference is active when extref_ena = ‘0’ in configtbd. An external decoupling capacitor CEXT of 0.1 µF should be connected externally to pin EXTIO for compensation. The bandgap reference can additionally be used for external reference operation. In that case, an external buffer with high impedance input should be applied in order to limit the bandgap load current to a maximum of 100 nA. The internal reference can be disabled and overridden by an external reference by setting the extref_ena control bit. Capacitor CEXT may hence be omitted. Pin EXTIO thus serves as either input or output node. The full-scale output current can be adjusted from 30 mA down to 10 mA by varying resistor RBIAS or changing the externally applied reference voltage.

7.3.28 Analog Outputs

The CMOS DACs consist of a segmented array of PMOS current sources, capable of sourcing a full-scale output current up to 30 mA. Differential current switches direct the current to either one of the complimentary output nodes IOUTP or IOUTN. Complimentary output currents enable differential operation, thus canceling out common mode noise sources (digital feed-through, on-chip and PCB noise), dc offsets, even order distortion components, and increasing signal output power by a factor of four. The full-scale output current is set using external resistor RBIAS in combination with an on-chip bandgap voltage reference source (+0.9 V) and control amplifier. Current IBIAS through resistor RBIAS is mirrored internally to provide a maximum full-scale output current equal to 16 times IBIAS. The relation between IOUTP and IOUTN can be expressed as: IOUTFS = IOUTP + IOUTN We will denote current flowing into a node as –current and current flowing out of a node as +current. Since the output stage is a current source the current flows from the IOUTP and IOUTN pins. The output current flow in each pin driving a resistive load can be expressed as: IOUTP = IOUTFS x CODE / 65536 IOUTN = IOUTFS x (65535 – CODE) / 65536 where CODE is the decimal representation of the DAC data input word. For the case where IOUTP and IOUTN drive resistor loads RL directly, this translates into single ended voltages at IOUTP and IOUTN: VOUTP = IOUT1 x RL VOUTN = IOUT2 x RL Assuming that the data is full scale (65535 in offset binary notation) and the RL is 25 Ω, the differential voltage between pins IOUTP and IOUTN can be expressed as: VOUTP = 20mA x 25 Ω = 0.5 V VOUTN = 0mA x 25 Ω = 0 V VDIFF = VOUTP – VOUTN = 0.5V Note that care should be taken not to exceed the compliance voltages at node IOUTP and IOUTN, which would lead to increased signal distortion.

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7.3.29 DAC Transfer Function

transformer results in an output between –0.5 V and +0.5 V. Figure 77. Driving a Doubly Terminated 50 Ω Cable Using a 1:1 Impedance Ratio Transformer Figure 78. Driving a Doubly Terminated 50 Ω Cable Using a 4:1 Impedance Ratio Transformer

7.4 Device Functional Modes

7.4.1 Clocking Modes

requirements. In this case the DACCLK pins are used as the reference frequency input to the PLL.

7.4.1.1 PLL Bypass Mode

extremely demanding applications.

1. pll_ena bit in register config49 to “0”to bypass the PLL circuitry.
2. pll_sleep bit in register config26 to “1”to put the PLL and VCO into sleep mode.

7.4.1.2 PLL Mode

256, and VCO prescaler divider from 2 to 18. Figure 79. PLL Block Diagram

1. pll_ena bit in register config49 to “1”to route to the PLL and clock path.
2. pll_sleep bit in register config26 to “0”to enable the PLL and VCO.

hot temp environment. In case of cold temp environment, shift by -1 on the variable pll_vco is recommended. where pll_vcosel = "0" and pll_vcoitune = "11". where pll_vcosel = "1" and pll_vcoitune = "10".

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Figure 80. Typical PLL VCO Center Frequency vs Coarse Tuning Bits recommended for better phase noise performance. Table 28. VCO Operation

The M divider is used to determine the phase-frequency-detector (PFD) and charge-pump (CP) frequency. Table 29. PFD and CP Operation The N divider in the loop allows the PFD to operate at a lower frequency than the reference clock. with P-ratio and M-ratio set as 2 and 4, the DACCLK frequency would be 2.5GHz and PFD frequency 625MHz. This needs 600µA charge pump current to stabilize the loop and gives the optimized phase noise performance.

7.4.2 PRBS Test Mode

1. config74, set bits 4:0 to 0x1E to disable JESD clock.
2. config61, set bits 14:12 to 0x2 to enable the 7-bit PRBS test pattern; or set bits 14:12 to 0x3 to enable the

23-bit PRBS test pattern; or set bits 14:12 to 0x4 to enable the 31-bit PRBS test pattern.

1. config27, set bits 11:8 to 0x3 to output PRBS testfail on ALARM pin.
2. config27, set bits 14:12 to the lane to be tested (0 through 7).
3. config62, make sure bits 12:11 are set to 0x0 to disable character alignment.

toggling if marginal). If the test is passing, the ALARM will be low.

7.5 Register Map

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Table 30. Register Map

Table 30. Register Map (continued)

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7.5.1 Register Descriptions

Table 31. Register Name: config0 – Address: 0x00, Default: 0x0218 the AB data path when asserted. coming out of the JESD block.

Table 32. Register Name: config1 – Address: 0x01, Default: 0x0003 through the matched delay line. through the matched delay line.

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Table 33. Register Name: config2 – Address: 0x02, Default: 0x2002 a lower priority than the dieid_ena bit. the fs/2, fs/4, -fs/4 and fs/8 modes. data is arriving at the input. Otherwise offset binary is presumed. Table 34. Register Name: config3 – Address: 0x03, Default: 0xF380

Table 35. Register Name: config4 – Address: 0x04, Default: 0x00FF Table 36. Register Name: config5 – Address: 0x05, Default: 0xFFFF

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Table 37. Register Name: config6 – Address: 0x06, Default: 0xFFFF Table 38. Register Name: config7 – Address: 0x07, Default: 0x0000 RESET these bits the SIF interface must be extremely slow, 1MHz range. released and measured in terms of JESD clock. Table 39. Register Name: config8 – Address: 0x08, Default: 0x0000 Table 40. Register Name: config9 – Address: 0x09, Default: 0x0000 Table 41. Register Name: config10 – Address: 0x0A, Default: 0x0000

Table 42. Register Name: config11 – Address: 0x0B, Default: 0x0000 Table 43. Register Name: config12 – Address: 0xC, Default: 0x0400 Table 44. Register Name: config13 – Address: 0xD, Default: 0x0400 Table 45. Register Name: config14 – Address: 0x0E, Default: 0x0400

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Table 46. Register Name: config15 – Address: 0x0F, Default: 0x0400 Table 47. Register Name: config16 – Address: 0x10, Default: 0x0000 Table 48. Register Name: config17 – Address: 0x11, Default: 0x0000 Table 49. Register Name: config18 – Address: 0x12, Default: 0x0000 Table 50. Register Name: config19 – Address: 0x13, Default: 0x0000 Table 51. Register Name: config20 – Address: 0x14, Default: 0x0000

Table 52. Register Name: config21 – Address: 0x15, Default: 0x0000 Table 53. Register Name: config22 – Address: 0x16, Default: 0x0000 Table 54. Register Name: config23 – Address: 0x17, Default: 0x0000 Table 55. Register Name: config24 – Address: 0x18, Default: 0x0000 Table 56. Register Name: config25 – Address: 0x19, Default: 0x0000 Table 57. Register Name: config26 – Address: 0x1A, Default: 0x0020 also affects the SYSREF receiver as well.

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Table 58. Register Name: config27 – Address: 0x1B, Default: 0x0000

Table 58. Register Name: config27 – Address: 0x1B, Default: 0x0000 (continued) Table 59. Register Name: config28 – Address: 0x1C, Default: 0x0000 Table 60. Register Name: config29 – Address: 0x1D, Default: 0x0000

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Table 61. Register Name: config30 – Address: 0x1E, Default: 0x1111 place allows the selected sync to pass to the block. place allows the selected sync to pass to the block. allows the selected sync to pass to the block. allows the selected sync to pass to the block. Table 62. Register Name: config31 – Address: 0x1F, Default: 0x1111 the selected sync to pass to the block. the selected sync to pass to the block. allows the selected sync to pass to the block.

Table 63. Register Name: config32 – Address: 0x20, Default: 0x0000 Table 64. Register Name: config33 – Address: 0x21, Default: 0x0000

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Table 65. Register Name: config34 – Address: 0x22, Default: 0x1B1B

Table 66. Register Name: config35 – Address: 0x23, Default: 0xFFFF bits do not override the SIF bits, just the SLEEP signal from the pin. Table 67. Register Name: config36 – Address: 0x24, Default: 0x0000 100 = Skip one SYSREF pulse then use all pulses. Table 68. Register Name: config37 – Address: 0x25, Default: 0x8000

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Table 69. Register Name: config38 – Address: 0x26, Default: 0x0000 Table 70. Register Name: config39 – Address: 0x27, Default: 0x0000 Table 71. Register Name: config40 – Address: 0x28, Default: 0x0000 Table 72. Register Name: config41 – Address: 0x29, Default: 0x0000 Table 73. Register Name: config42 – Address: 0x2A, Default: 0x0000 Table 74. Register Name: config43 – Address: 0x2B, Default: 0x0000 Table 75. Register Name: config44 – Address: 0x2C, Default: 0x0000

Table 76. Register Name: config45 – Address: 0x2D, Default: 0x0000 Table 77. Register Name: config46 – Address: 0x2E, Default: 0xFFFF measurement is greater than this activate the PA protection logic. Table 78. Register Name: config47 – Address: 0x2F, Default: 0x0004 Table 79. Register Name: config48 – Address: 0x30, Default: 0x0000

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Table 80. Register Name: config49 – Address: 0x31, Default: 0x0000 and will indicate an unlocked state more often. Table 81. Register Name: config50 – Address: 0x32, Default: 0x0000 Table 82. Register Name: config51 – Address: 0x33, Default: 0x0100 00000 will hold the LPF pin at 0V.

Table 83. Register Name: config52 – Address: 0x34, Default: 0x0000 effuse_sel multiplexer. ATEST must be set to 111001 to enable this output. Table 84. Register Name: config53 – Address: 0x35, Default: 0x0000 Table 85. Register Name: config54 – Address: 0x36, Default: 0x0000 Table 86. Register Name: config55 – Address: 0x37, Default: 0x0000 Table 87. Register Name: config56 – Address: 0x38, Default: 0x0000 Table 88. Register Name: config57 – Address: 0x39, Default: 0x0000 Table 89. Register Name: config58 – Address: 0x3A, Default: 0x0000

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Table 90. Register Name: config59 – Address: 0x3B, Default: 0x0000 the SerDes PLL reference divider input clock. refclk_div divider amount is serdes_refclk_div plus one. Table 91. Register Name: config60 – Address: 0x3C, Default: 0x0000 Bit15 – ENDIVCLK, enables output of a divide-by-5 of PLL clock. Bit12:11 – LB, specify loop bandwidth settings. Bit10 – SLEEPPLL, puts the PLL into sleep state when high. Bit9 – VRANGE, select between high and low VCO. Bit8:1 – MPY, select PLL multiply factor between 4 and 25. Table 92. Register Name: config61 – Address: 0x3D, Default: 0x0000 2 PRBS patterns, a user defined pattern or a clock test pattern. Bit7 – ENOC, enable samplers offset compensation. Bit6 – EQHLD, hold the equalizer in its current status. Bit2:0 – CDR, configure the clock/data recovery algorithm.

Table 93. Register Name: config62 – Address: 0x3E, Default: 0x0000 Bit15:1 – LOS, enable loss of signal detection. Bit10:8 – TERM, select input termination options for serial lanes. Note: AC coupling is recommended for JESD204B compliance. Bit6:5 – RATE, operating rate, select full, half, quarter or eighth rate operation. Bit4:2 – BUSWIDTH, select the parallel interface width (16 bit or 20bit). Note: 16bit is not compatible with JESD204B. Table 94. Register Name: config63 – Address: 0x3F, Default: 0x0000 Table 95. Register Name: config64 – Address: 0x40, Default: 0x0000 Table 96. Register Name: config65 – Address: 0x41, Default: 0x0000 Table 97. Register Name: config66 – Address: 0x42, Default: 0x0000

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Table 98. Register Name: config67 – Address: 0x43, Default: 0x0000 Table 99. Register Name: config68 – Address: 0x44, Default: 0x0000 Table 100. Register Name: config69 – Address: 0x45, Default: 0x0000 Table 101. Register Name: config70 – Address: 0x46, Default: 0x0120 Table 102. Register Name: config71 – Address: 0x47, Default: 0x3450 Table 103. Register Name: config72 – Address: 0x48, Default: 0x31C3

Table 104. Register Name: config73 – Address: 0x49, Default: 0x0000 Table 105. Register Name: config74 – Address: 0x4A, Default: 0x001E sequences comes out the lane alarms bit0. 1= fail and 0 = pass. paths, reducing the power of the DIG block. JESD description of the correct startup sequence. Table 106. Register Name: config75 – Address: 0x4B, Default: 0x0000 supports 1,2,4 or 8 octets per frame so the only valid values are 0,1,3, and 7.

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Table 107. Register Name: config76 – Address: 0x4C, Default: 0x0000 Table 108. Register Name: config77 – Address: 0x4D, Default: 0x0300 Table 109. Register Name: config78 – Address: 0x4E, Default: 0x0F0F Table 110. Register Name: config79 – Address: 0x4F, Default: 0x1CC1 user can program it to any character. programmed to ‘0’then the first non-K will start the buffering. RX won’t flag errors in the configuration portion of the ILA.

Table 111. Register Name: config80 – Address: 0x50, Default: 0x0000 except for lane configuration checking. except for lane configuration checking. except for lane configuration checking. except for lane configuration checking. except for lane configuration checking. Table 112. Register Name: config81 – Address: 0x51, Default: 0x00FF except for lane configuration checking. Table 113. Register Name: config82 – Address: 0x52, Default: 0x00FF except for lane configuration checking.

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Table 114. Register Name: config83 – Address: 0x53, Default: 0x0000 for lane configuration checking. for lane configuration checking. for lane configuration checking. for lane configuration checking. for lane configuration checking. Table 115. Register Name: config84 – Address: 0x54, Default: 0x00FF except for lane configuration checking. Table 116. Register Name: config85 – Address: 0x55, Default: 0x00FF except for lane configuration checking.

Table 117. Register Name: config86 – Address: 0x56, Default: 0x0000 for lane configuration checking. for lane configuration checking. for lane configuration checking. for lane configuration checking. for lane configuration checking. Table 118. Register Name: config87 – Address: 0x57, Default: 0x00FF except for lane configuration checking. Table 119. Register Name: config88 – Address: 0x58, Default: 0x00FF except for lane configuration checking.

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Table 120. Register Name: config89 – Address: 0x59, Default: 0x0000 for lane configuration checking. for lane configuration checking. for lane configuration checking. for lane configuration checking. for lane configuration checking. Table 121. Register Name: config90 – Address: 0x5A, Default: 0x00FF except for lane configuration checking. Table 122. Register Name: config91 – Address: 0x5B, Default: 0x00FF except for lane configuration checking.

Table 123. Register Name: config92 – Address: 0x5C, Default: 0x1111 100 = Skip one SYSREF pulse then use all pulses. 110 = Skip two SYSREF pulses then use all pulses. 100 = Skip one SYSREF pulse then use all pulses. 110 = Skip two SYSREF pulses then use all pulses. 100 = Skip one SYSREF pulse then use all pulses. 110 = Skip two SYSREF pulses then use all pulses. 100 = Skip one SYSREF pulse then use all pulses. 110 = Skip two SYSREF pulses then use all pulses. Table 124. Register Name: config93 – Address: 0x5D, Default: 0x0000 Table 125. Register Name: config94 – Address: 0x5E, Default: 0x0000 the checksum comparison against ILA values. the checksum comparison against ILA values.

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Table 126. Register Name: config95 – Address: 0x5F, Default: 0x0123

Table 127. Register Name: config96 – Address: 0x60, Default: 0x4567

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Table 128. Register Name: config97 – Address: 0x61, Default: 0x000F Table 129. Register Name: config98 – Address: 0x62, Default: 0x0000 Table 130. Register Name: config99 – Address: 0x63, Default: 0x0000

config100 – config107 become the DIEID(127:0). Normal function (config47(14)=’0’) is shown below. Table 131. Register Name: config100 – Address: 0x64, Default: 0x0000 “match_ctrl”and “match_data”programmed values. Table 132. Register Name: config101 – Address: 0x65, Default: 0x0000 “match_ctrl”and “match_data”programmed values.

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Table 133. Register Name: config102 – Address: 0x66, Default: 0x0000 “match_ctrl”and “match_data”programmed values. Table 134. Register Name: config103 – Address: 0x67, Default: 0x0000 “match_ctrl”and “match_data”programmed values.

Table 135. Register Name: config104 – Address: 0x68, Default: 0x0000 “match_ctrl”and “match_data”programmed values. Table 136. Register Name: config105 – Address: 0x69, Default: 0x0000 “match_ctrl”and “match_data”programmed values.

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Table 137. Register Name: config106 – Address: 0x6A, Default: 0x0000 “match_ctrl”and “match_data”programmed values. Table 138. Register Name: config107 – Address: 0x6B, Default: 0x0000 “match_ctrl”and “match_data”programmed values.

Table 139. Register Name: config108 – Address: 0x6C, Default: 0x0000 bit after start to monitor accurately. bit after start to monitor accurately. Table 140. Register Name: config109 – Address: 0x6D, Default: 0x00xx Table 141. Register Name: config110 – Address: 0x6E, Default: 0x0000

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Table 142. Register Name: config111 – Address: 0x6F, Default: 0x0000 Table 143. Register Name: config112 – Address: 0x70, Default: 0x0000 Table 144. Register Name: config113 – Address: 0x71, Default: 0x0000 Table 145. Register Name: config114 – Address: 0x72, Default: 0x0000 Table 146. Register Name: config115 – Address: 0x73, Default: 0x0000 Table 147. Register Name: config116 – Address: 0x74, Default: 0x0000 Table 148. Register Name: config117 – Address: 0x75, Default: 0x0000

Table 149. Register Name: config118 – Address: 0x76, Default: 0x0000 Table 150. Register Name: config119 – Address: 0x77, Default: 0x0000 Table 151. Register Name: config120 – Address: 0x78, Default: 0x0000 Table 152. Register Name: config121 – Address: 0x79, Default: 0x0000 Table 153. Register Name: config122 – Address: 0x7A, Default: 0x0000 Table 154. Register Name: config123 – Address: 0x7B, Default: 0x0000 Table 155. Register Name: config124 – Address: 0x7C, Default: 0x0000

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Table 156. Register Name: config125 – Address: 0x7D, Default: 0x0000 Table 157. Register Name: config126 – Address: 0x7E, Default: 0x0000 Table 158. Register Name: config127 – Address: 0x7F, Default: 0x0009 change through a hardwire connection outside the DIG block. accessible outside the DIG block for changing.

8 Applications and Implementation

8.1 Application Information

advanced technologies, such as LTE-Advanced and carrier aggregation on multiple antennas.

8.2 Typical Applications

8.2.1 Low-IF Wideband LTE Transmitter

Gbps and the minimum number of serdes lanes is desired. Figure 81. Low-IF Wideband LTE Transmitter Diagram

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DAC37J82, DAC38J82 www.ti.com SLASE16B – JANUARY 2014– REVISED MAY 2014 Typical Applications (continued)

8.2.1.1 Design Requirements

For this design example, use the parameters listed in the table below as the input parameters. DESIGN PARAMETER EXAMPLE VALUE Signal Bandwidth (BWsignal) 80 MHz Total DAC Output Bandwidth (BWtotal) 240 MHz DAC PLL On DAC PLL Reference Frequency 307.2 MHz Maximum FPGA Serdes Data Rate 12.5 Gbps

8.2.1.2 Detailed Design Procedure

8.2.1.2.1 Data Input Rate

Nyquist theory says that the data rate must be at least two times the highest signal frequency. The data will be sent to the DAC as complex baseband data. For 240 MHz of signal bandwidth only 120 MHz of input bandwidth is needed, setting the minimum data input rate as 240 MSPS. Further, the process of interpolation requires low pass filters that limit the useable input bandwidth to about 40 percent of Fdata. Therefore, the minimum data input rate is 300 MSPS. The standard telecom data rate of 307.2 MSPS is chosen.

8.2.1.2.2 Intermediate Frequency

The intermediate frequency is chosen to keep low order harmonics out of band while staying low enough to not degrade the ACPR performance. The band of interest is 240 MHz wide, while the signal bandwidth is 80 MHz wide. The lowest frequency that the second harmonic of the signal will fall at is given on the left side of the inequality shown below based on the chosen IF center frequency. The highest frequency in the band of interest (Total DAC Output Bandwidth) is the right side of the inequality. Solving the inequality for IF and choosing a center frequency higher than that will keep the second harmonic out of the bandwidth of interest. (IF - BWsignal / 2) * 2 ≥ IF + BWtotal/2 (3) The lowest IF that satisfies the inequality is shown below. IF ≥ BWsignal + BWtotal / 2 (4) So for a signal bandwidth of 80 MHz and a total bandwidth of 240 MHz, the lowest IF that satisfies the inequality is 200 MHz. Choose 220 MHz to move HD2 slightly away from the band. The full complex mixer can be enabled with the NCO frequency chosen as 220 MHz to realize this IF frequency.

8.2.1.2.3 Interpolation

It is desired to use the highest DAC output rate as possible to move the DAC images further from the signal of interest to ease the analog filter requirements. The DAC output rate must be greater than two times the highest output frequency, in this case 2 * (220 MHz + BWtotal/2) = 680 MHz. The table below shows the possible DAC output rates based on the data input rate and available interpolation settings. The DAC image frequency is also listed. Based on the result, 8x interpolation will push the image frequency 1777.6 MHz away from the band of interest, so the DAC output rate is chosen as 2457.6 MSPS. Although not shown the high output rate also pushes higher order harmonics out of the band of interest that would have aliased back in at 1228.8 MSPS. LOWEST IMAGE DISTANCE FROM BAND OFINTERPOLATION DAC OUTPUT RATE POSSIBLE? FREQUENCY INTEREST 1 307.2 MSPS No N/A N/A 2 614.4 MSPS No N/A N/A 4 1228.8 MSPS Yes 888.8 MHz 548.8 MHz 8 2457.6 MSPS Yes 2117.6 MHz 1777.6 MHz 16 4915.2 MSPS No N/A N/A Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback 103 Product Folder Links: DAC37J82 DAC38J82

3 D B

8.2.1.2.4 DAC PLL Setup

frequency of 2457.6 MHz, so the Prescalar is set to 2 and the H-band VCO is selected.

8.2.1.2.5 Serdes Lanes

DAC requires a serialized data rate of 6144 Mbps, as given by the equation below. mode (LMF) for the DAC as 124 mode.

8.2.1.3 Application Performance Plots

Figure 83. Four Carrier 20MHz LTE Signal ACPRFigure 82. Four Carrier 20MHz LTE Signal Spectrum

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8.2.2 Zero-IF Wideband Transmitter

minimum number of serdes lanes is desired. Figure 84. Zero-IF Wideband Transmitter Diagram

8.2.2.1 Design Requirements

For this design example, use the parameters listed in the table below as the input parameters.

8.2.2.2 Detailed Design Procedure

8.2.2.2.1 Data Input Rate

8.2.2.2.2 Interpolation

DAC37J82, DAC38J82 SLASE16B – JANUARY 2014– REVISED MAY 2014 www.ti.com LOWEST IMAGE DISTANCE FROM BAND OFINTERPOLATION DAC OUTPUT RATE POSSIBLE? FREQUENCY INTEREST 1 1.2 GSPS Yes 720 MHz 240 MHz 2 2.4 GSPS Yes 1920 MHz 1440 MHz 4 4.8 GSPS No N/A N/A 8 9.6 GSPS No N/A N/A 16 19.2 GSPS No N/A N/A

8.2.2.2.3 Serdes Lanes

It is desired to use the minimum number of serdes lanes while staying under the maximum serdes line rate possible with the chosen FPGA. In the design requirements, the FPGA maximum serdes data rate was given as 12.5 Gbps. For the chosen input data rate of 1.2 GSPS and with 8b/10b encoding on the serdes lanes, each DAC requires a serialized data rate of 24 Gbps, as given by the equation below. Serialized Data Rate = Fdata * 16 * (10 / 8) (6) The total serialized data rate with a quad DAC is 24 Gbps * 2 = 48 Gbps. This total serialized data rate is split among the total number of lanes. The table below shows the line rate versus the total number of lanes. Four lanes must be chosen to support this data rate. This sets the JESD204B mode (LMF) for the DAC as 421 mode. NUMBER OF LANES LINE RATE POSSIBLE? 1 48 Gbps No 2 24 Gbps No 4 12 Gbps Yes 8 6 Gbps Yes

8.2.2.2.4 LO Feedthrough and Sideband Correction

Although the I/Q modulation process will inherently reduce the level of the RF sideband signal, a zero-IF system will likely need additional sideband suppression to maximize performance. Further, any mixing process will result in some feedthrough of the LO source. The DAC37J82 and DAC38J82 contain digital features to cancel both the LO feedthrough and sideband signal. The LO feedthrough is corrected by adding a DC offset to the DAC outputs until the LO feedthrough is suppressed. The sideband suppression can be improved by correcting gain, phase, and group delay differences between the I and Q analog outputs. The phase and gain adjustments are made using the QMC block of the DAC while the group delay adjustments are done using the small fractional delay filter. First the phase should be adjusted to suppress the sideband signal at low DAC output frequencies due to phase error. Then the gain can be adjusted to further improve the suppression. Finally, the small fractional filter can be used to improve the sideband suppression across the rest of the signal bandwidth.

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8.2.2.3 Application Performance Plots

Figure 86. 192MHz Wideband 256QAM Signal ACPR Figure 85. 192MHz Wideband 256QAM Signal Spectrum

8.3 Initialization Set Up

The following start up sequence is recommended to power up the DAC38J82/DAC37J82 family.

1. Supply all 0.9-V supplies (VDDDIG09, VDDT09, VDDDAC09, VDDCLK09), all 1.8-V supplies (VDDR18,
2. RESET the JTAG port by either toggling TRSTB low if using the JTAG port or holding TRSTB low if not using
3. Start the DACCLK generation.
4. Toggle RESETB low to reset the SIF registers.
5. Program the DAC PLL settings (config26, config49, config50, config51). If the PLL is not used, set pll_sleep

and pll_reset to “1”and pll_ena to “0”.

1. Program the SERDES settings (config61, config62) including the serdes_clk_sel and serdes_refclk_div.
2. Program the SERDES lane settings (config63, config71, config73, config74, config96).
3. Program clkjesd_div, cdrvser_sysref_mode, and interp.
4. Program the JESD settings (config3, config74-77, config79, config80-85, config92, config97).
5. Program the DIG block settings (NCO, PA protection, QMC, fractional delay, etc.) and set the preferred

SYNC modes for the digital blocks (config30-32).

1. Verify the SERDES PLL lock status by checking the SERDES PLL alarms: alarm_rw0_pll (alarm for lanes 0

through 3) and alarm_rw1_pll (alarm for lanes 4 through 7).

1. Set init_state to “0000”and jesd_reset_n to “1”to start the JESD204B link initialization.
2. Start the SYSREF generation.
3. Enable transmission of data by asserting the TXENABLE pin or setting sif_txenable to “1”.
4. Clear the alarms, then wait approximately 1-2µs and check values.
5. Verify that DAC output is the desired output.

DAC37J82, DAC38J82 SLASE16B – JANUARY 2014– REVISED MAY 2014 www.ti.com

9 Power Supply Recommendations

The DAC37J82 and DAC38J82 use three different power supply voltages. Some of the DAC power supplies are noise sensitive. The table below is a summary of the various power supply of the DAC. Care should be taken to keep clean power supplies routing away from noisy digital supplies. It is recommended to use at least two power layers. Avoid placing digital supplies and clean supplies on adjacent board layers and use a ground layer between noisy and clean supplies if possible. All supplies pins should be decoupled as close to the pins as possible using small value capacitors, with larger bulk capacitors placed further away. POWER SUPPLY VOLTAGE NOISE SENSITIVE? RECOMMENDATION Provide clean voltage, avoidVDDADAC33 3.3 V Yes spurious noise Provide clean voltage, avoidVDDAPLL18 1.8 V Yes spurious noise Provide clean voltage, avoidVDDAREF18 1.8 V Yes spurious noise Provide clean voltage, avoidVDDCLK09 0.9 V Yes spurious noise Provide clean voltage, avoidVDDDAC09 0.9 V Yes spurious noise Digital supply, keep separated VDDDIG09 0.9 V No from noise sensitive 0.9 V supplies. VDDIO18 1.8 V No No concern VDDR18 1.8 V Yes Provide clean voltage VDDS18 1.8 V No No concern VDDT09 0.9 V Yes Provide clean voltage VQPS18 1.8 V No No concern

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DAC37J82, DAC38J82 www.ti.com SLASE16B – JANUARY 2014– REVISED MAY 2014

10 Layout

10.1 Layout Guidelines

• DAC output termination resistors should be placed as close to the output pins as possible to provide a DC path to ground and set the source impedance.
• For PLL mode, if the external loop filter is not used then leave the pin floating without any board routing. Signals coupling to this node may cause clock mixing spurs in the DAC output.
• Route the high speed serdes lanes as impedance-controlled, tightly-coupled, differential traces.
• Maintain a solid ground plane under the serdes lanes without any ground plane splits.
• AC couple the serdes lines between the logic device and the DAC using 0201 size capacitors that maintain low impedance at the serialized data rate.
• Simulation of the serdes channel is recommended to verify JESD204B standard compliance to ensure compatibility between devices.
• Keep the SYSREF routing away from the DACCLK routing to reduce coupling. Using a pulsed SYSREF or disabling a continuous SYSREF is recommended during normal operation to avoid spurs in the output spectrum.
• Keep routing for RBIAS short, for instance a resistor can be placed on the bottom of the board directly connecting the RBIAS ball to a GND ball.
• Decoupling capacitors should be placed as close to the supply pins as possible, for instance a capacitor can be placed on the bottom of the board directly connecting the supply ball to a GND ball.
• Noisy power supplies should be routed away from clean supplies. Use two power plane layers, preferably with a GND layer in between. Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback 109 Product Folder Links: DAC37J82 DAC38J82

10.2 Layout Examples

Figure 87. DAC37J82/DAC38J82 Layout for Power Supplies

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Figure 88. DAC37J82/DAC38J82 Layout for Signals

11 Device and Documentation Support

11.1 Related Links

resources, tools and software, and quick access to sample or buy. Table 159. Related Links

11.2 Trademarks

All trademarks are the property of their respective owners.

11.3 Electrostatic Discharge Caution

during storage or handling to prevent electrostatic damage to the MOS gates.

11.4 Glossary

This glossary lists and explains terms, acronyms, and definitions.

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12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical packaging and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback 113 Product Folder Links: DAC37J82 DAC38J82

www.ti.com 10-Nov-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) DAC37J82IAAV Active Production FCCSP (AAV) | 144 168 | JEDEC TRAY (5+1) Yes SNAGCU Level-3-260C-168 HR -40 to 85 DAC37J82I DAC37J82IAAV.B Active Production FCCSP (AAV) | 144 168 | JEDEC TRAY (5+1) Yes SNAGCU Level-3-260C-168 HR -40 to 85 DAC37J82I DAC37J82IAAVR Active Production FCCSP (AAV) | 144 1000 | LARGE T&R Yes SNAGCU Level-3-260C-168 HR -40 to 85 DAC37J82I DAC37J82IAAVR.B Active Production FCCSP (AAV) | 144 1000 | LARGE T&R Yes SNAGCU Level-3-260C-168 HR -40 to 85 DAC37J82I DAC38J82IAAV Active Production FCCSP (AAV) | 144 168 | JEDEC TRAY (5+1) Yes SNAGCU Level-3-260C-168 HR -40 to 85 DAC38J82I DAC38J82IAAV.B Active Production FCCSP (AAV) | 144 168 | JEDEC TRAY (5+1) Yes SNAGCU Level-3-260C-168 HR -40 to 85 DAC38J82I DAC38J82IAAVR Active Production FCCSP (AAV) | 144 1000 | LARGE T&R Yes SNAGCU Level-3-260C-168 HR -40 to 85 DAC38J82I DAC38J82IAAVR.B Active Production FCCSP (AAV) | 144 1000 | LARGE T&R Yes SNAGCU Level-3-260C-168 HR -40 to 85 DAC38J82I (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Addendum-Page 1

www.ti.com 10-Nov-2025 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

www.ti.com PACKAGE OUTLINE C 1.91 1.70 0.405

0.325 TYP

8.8 TYP

8.8 TYP

0.8 TYP

144X 0.51 0.41 (0.67) A 10.15 9.85 B 10.15 9.85 (0.6) TYP ( 8) (0.5) (0.6) TYP FCBGA - 1.91 mm max heightAAV0144A BALL GRID ARRAY 4219578/D 03/2023 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Dimension is measured at the maximum solder ball diameter, parallel to primary datum C. 4. Primary datum C and seating plane are defined by the spherical crowns of the solder balls. 5. The lids are electrically floating (e.g. not tied to GND). BALL A1 CORNER SEATING PLANE BALL TYP 0.1 C NOTE 4 M L K J H G F E D C B A 1 2 3

0.15 C A B

0.08 C SYMM SYMM NOTE 3 5 6 7 8 9 10 11 12 SCALE 1.400

www.ti.com EXAMPLE BOARD LAYOUT 144X ( 0.4) (0.8) TYP (0.8) TYP ( 0.4) METAL

0.05 MAX

( 0.4) SOLDER MASK OPENING

0.05 MIN

FCBGA - 1.91 mm max heightAAV0144A BALL GRID ARRAY 4219578/D 03/2023 NOTES: (continued) 6. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. For more information, see Texas Instruments literature number SPRU811 (www.ti.com/lit/spru811). SYMM SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X B C D E F G H J K L M 2 3 4 5 6 7 8 9 10 11 12 NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DETAILS NOT TO SCALE EXPOSED METAL SOLDER MASK DEFINED EXPOSED METAL

www.ti.com EXAMPLE STENCIL DESIGN (0.8) TYP FCBGA - 1.91 mm max heightAAV0144A BALL GRID ARRAY 4219578/D 03/2023 NOTES: (continued) 7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. SOLDER PASTE EXAMPLE BASED ON 0.15 mm THICK STENCIL SCALE:8X SYMM SYMM B C D E F G H J K L M 2 3 4 5 6 7 8 9 10 11 12

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