DAC3174

Texas Instruments

Dual 14-bit 500 MSPS Digital to Analog Converter

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DAC3174 Dual, 14-Bit, 500-MSPS, Digital-to-Analog Converter datasheet (Rev. B)

Document overview

Manufacturer or author: Texas Instruments, Incorporated [SLAS837,B]
PDF pages: 55

Technical content

Copyright © 2017, Texas Instruments Incorporated 800-MHz Local Oscillator RF OUT Real Mixer Band-Pass Filter RF OUT Real Mixer Band-Pass Filter 800-MHz Local Oscillator Product Folder Order Now T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. DAC3174 SLAS837B –APRIL 2013–REVISED JANUARY 2017 DAC3174Dual,14-Bit,500-MSPS,Digital-to-AnalogConverter

1 Features

1• Dual-Channel

14-Bit Resolution
Maximum Sample Rate: 500 MSPS
Pin Compatible With Dual-Channel DAC3154, DAC3164, and Single-Channel DAC3151, DAC3161, and DAC3171
Input Interface: – 14 LVDS Inputs – Single, 14-Bit Interface or Dual, 7-Bit Interface – Single or Dual DDR Data Clock – Internal FIFO
Chip-to-Chip Synchronization
Power Dissipation: 460 mW
Spectral Performance at 20 MHz IF: – SNR: 76 dBFS – SFDR: 78 dBc
Current-Sourcing DACs
Compliance Range: –0.5 V to +1 V
Package: 64-Pin VQFN (9 mm × 9 mm)

2 Applications

Multi-Carrier, Multi-Mode Cellular Infrastructure Base Stations
Radar
Signal Intelligence
Software-Defined Radios
Test and Measurement Instrumentation

3 Description

The DAC3174 is a dual-channel, 14-bit, 500-MSPS, digital-to-analog converter (DAC). The DAC3174 uses a 14-bit, low-voltage differential signaling (LVDS) digital bus, with one or two independent dual- data rate (DDR) data clocks for flexibility in providing data from different sources in each channel. An input first-in first out block (FIFO) allows independent data and sample clocks. FIFO input and output pointers can be synchronized across multiple devices for precise signal synchronization. The DAC outputs are current sourcing and terminate to GND with a compliance range of –0.5 V to +1 V. The DAC3174 is pin compatible with the dual- channel, 500-MSPS, 12-bit DAC3164 and 10-bit DAC3154, and the single-channel, 500-MSPS, 14-bit DAC3171, 12-bit DAC3161, and 10-bit DAC3151. The device is available in a 64-pin VQFN PowerPAD™ package. and is specified over the full industrial temperature range of –40°C to +85°C. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) DAC3174 VQFN (64) 9.00 mm × 9.00 mm (1) For all available packages, see the package option addendum at the end of the data sheet. Typical Application

11.2 Receiving Notification of Documentation Updates 46

12 Mechanical, Packaging, and Orderable

4 Revision History

Changes from Revision A (May 2013) to Revision B Page

Added Device Information, ESD Ratings, Recommended Operating Conditions, and Timing Requirements tables, and Detailed Description, Application and Implementation, Power Supply Recommendations, Layout, Device and
Added typical application diagram to front page and moved existing block diagrams to Functional Block Diagrams Changes from Original (April 2013) to Revision A Page

64 VDDA1817DATA9P

63 NC18DATA9N

62 NC19DATA8P

61 IOUTAP20DATA8N

60 IOUTAN21DIGVDD18

59 VDDA3322DATA7P

58 EXTIO23DATA7N

57 BIASJ24DATACLKP

56 VDDA3325DATACLKN

55 VDDA3326DATA6P

54 IOUTBN27DATA6N

53 IOUTBP28DIGVDD18

52 NC29DATA5P

51 NC30DATA5N

50 VDDA1831DATA4P

49 SLEEP32DATA4N

5 Pin Configuration and Functions

Pin Functions: Single-Bus Mode PIN I/O DESCRIPTION NAME NO. CONTROL AND SERIAL ALARM 47 O CMOS output for ALARM condition. RESETB 41 I Serial interface reset input, active low. Initialized internal registers during high-to-low transition. Asynchronous. Internal pullup. A reset event after every power cycle may be required to reinitialize all SPI registers to default values. SCLK 43 I Serial interface clock. Internal pulldown. SDENB 42 I Serial data enable. Internal pullup. SDIO 44 I/O Bidirectional serial data in 3-pin mode (default). In 4-pin interface mode (sif4_ena [config0, bit 9]), the SDIO pin in an input only. Internal pulldown.

SLAS837B –APRIL 2013–REVISED JANUARY 2017 www.ti.com Product Folder Links: DAC3174 Submit Documentation Feedback Copyright © 2013–2017, Texas Instruments Incorporated Pin Functions: Single-Bus Mode (continued) PIN I/O DESCRIPTION NAME NO. SDO 46 O Unidirectional serial interface data in 4-pin mode (sif4_ena [config0, bit 9]). The SDO pin is made high impedance in 3-pin interface mode (default). Internal pulldown. SLEEP 49 I Puts device in sleep, active high. Internal pulldown. TXENABLE 48 I Transmit enable, active high input. TXENABLE must be high for the data to the DAC to be enabled. When TXENABLE is low, the digital logic section is forced to all 0, and any input data are ignored. Internal pulldown. DATA INTERFACE ALIGNN 5 I LVPECL FIFO output synchronization. This positive or negative pair is captured with the rising edge of DACCLKx. This pin is used to reset the clock dividers and for multiple DAC synchronization. If unused, this pin can be left unconnected.ALIGNP 4 I DATA[13:0]N 10, 12, 14, 16, 18, 20, 23, 27, 30, 32, 34, 36, 38, 40 I LVDS input data bits for both channels. Each positive and negative LVDS pair has an internal 100-Ω termination resistor. Data format relative to DATACLKx clock is dual data rate (DDR) with two data transfers per DATACLKx clock cycles. The data format is interleaved with channel A (rising edge) and channel B (falling edge). In the default mode (reverse bus not enabled): DATA13x is most significant data bit (MSB) DATA0x is least significant data bit (LSB) DATA[13:0]P 9, 11, 13, 15, 17, 19, 22, 26, 29, 31, 33, 35, 37, 39 I DATACLKN 25 I DDR differential input data clock. Edge to center nominal timing. Ch A rising edge, Ch B falling edge in multiplexed output mode.DATACLKP 24 I SYNCN 7 I This pin resets the FIFO or is used as a syncing source. These two functions are captured with the rising edge of DATACLKx. The signal captured by the falling edge of DATACLKx.SYNCP 6 I OUTPUT AND CLOCK DACCLKN 2 I LVPECL clock input for DAC core with a self-bias of approximately CLKVDD18 / 2. DACCLKP 1 I IOUTAN 60 O A-Channel DAC current output. An offset binary data pattern of 0x0000 at the DAC input results in a full-scale current source, and the most positive voltage on the IOUTAP pin. Similarly, a 0xFFFF data input results in a 0-mA current source, and the least positive voltage on the IOUTAP pin. The IOUTAN pin is the complement of IOUTAP. IOUTAP 61 O IOUTBN 54 O B-Channel DAC current output. An offset binary data pattern of 0x0000 at the DAC input results in a full-scale current source, and the most positive voltage on the IOUTBP pin. Similarly, a 0xFFFF data input results in a 0-mA current source, and the least positive voltage on the IOUTBP pin. The IOUTBN pin is the complement of IOUTBP. IOUTBP 53 O REFERENCE BIASJ 57 O Full-scale output current bias. For 20-mA full-scale output current, connect a 960-Ω resistor to GND. EXTIO 58 I/O Used as external reference input when internal reference is disabled. Requires a 0.1-µF decoupling capacitor to GND when used as reference output. POWER SUPPLY CLKVDD18 3 I 1.8-V clock supply. DIGVDD18 21, 28 I 1.8-V digital supply. Also supplies LVDS receivers. IOVDD 45 I Supply voltage for CMOS I/Os. 1.8 V to 3.3 V. VDDA18 50, 64 I Analog 1.8-V supply. VDDA33 55, 56, 59 I Analog 3.3-V supply. VFUSE 8 I Digital supply voltage (1.8 V). This supply pin is also used for factory fuse programming. Connect to DVDD pins for normal operation. NC 51, 52, 62, 63 — Not used. These pins can be left open or tied to ground in actual application use. GND PAD — — This thermal pad is the electrical ground connection for the device (backside).

64 VDDA1817DA2P

63 NC18DA2N

62 NC19DA1P

61 IOUTAP20DA1N

59 VDDA3322DA0P

6DA_CLKP 43 SCLK

58 EXTIO23DA0N

7DA_CLKN 42 SDENB

57 BIASJ24DB_CLKP

56 VDDA3325DB_CLKN

55 VDDA3326DB6P

54 IOUTBN27DB6N

52 NC29DB5P

51 NC30DB5N

50 VDDA1831DB4P

49 SLEEP32DB4N

www.ti.com SLAS837B –APRIL 2013–REVISED JANUARY 2017 Product Folder Links: DAC3174 Submit Documentation FeedbackCopyright © 2013–2017, Texas Instruments Incorporated 64-Pin VQFN Top View Pin Functions: Dual-Bus Mode PIN I/O DESCRIPTION NAME NO. CONTROL AND SERIAL ALARM 47 O CMOS output for alarm condition. RESETB 41 I Serial interface reset input, active low. Initializes internal registers during high to low transition. Asynchronous. Internal pullup. A reset event after every power cycle may be required to reinitialize all SPI registers to default values. SCLK 43 I Serial interface clock. Internal pulldown. SDENB 42 I Serial data enable. Internal pullup. SDIO 44 I/O Bidirectional serial data in 3-pin mode (default). In 4-pin interface mode (sif4_ena [config0, bit 9]), the SDIO pin in an input only. Internal pulldown.

SLAS837B –APRIL 2013–REVISED JANUARY 2017 www.ti.com Product Folder Links: DAC3174 Submit Documentation Feedback Copyright © 2013–2017, Texas Instruments Incorporated Pin Functions: Dual-Bus Mode (continued) PIN I/O DESCRIPTION NAME NO. SDO 46 O Unidirectional serial interface data in 4-pin mode (sif4_ena [config0, bit 9]). The SDO pin is made high impedance in 3-pin interface mode (default). Internal pulldown. SLEEP 49 I Puts device in sleep, active high. Internal pulldown. TXENABLE 48 I Transmit enable, active high input. TXENABLE must be high for the data to the DAC to be enabled. When TXENABLE is low, the digital logic section is forced to all 0, and any input data are ignored. Internal pulldown. DATA INTERFACE 16, 18 I LVDS positive input data bits for channel A. Each positive or negative LVDS pair has an internal 100-Ω termination resistor. Data format relative to DA_CLKx clock is dual data rate (DDR) with two data transfers per DA_CLKx clock cycle. The data format is 7 MSBs (rising edge) and 7 LSBs (falling edge). In the default mode (reverse bus not enabled): DA6x is most significant data bit (MSB) DA0x is least significant data bit (LSB) 15, 17, 19 I DB[6:0]N 27, 30, 32, 34, 36, 38, I LVDS positive input data bits for channel B. Each positive or negative LVDS pair has an internal 100-Ω termination resistor. Data format relative to DB_CLKx clock is dual data rate (DDR) with two data transfers per DB_CLKx clock cycle. The data format is 7 MSBs (rising edge) and 7 LSBs (falling edge). In the default mode (reverse bus not enabled): DB6x is most significant data bit (MSB) DB0x is least significant data bit (LSB) DB[6:0]P 26, 29, 31, 33, 35, 37, I DA_CLKN 7 I DDR differential input data clock for channel A. Edge to center nominal timing. DA_CLKP 6 I DB_CLKN 25 I DDR differential input data clock for channel B. Edge to center nominal timing. DB_CLKP 24 I OUTPUT AND CLOCK DACCLKN 2 I LVPECL clock negative input for DAC core with a self-bias of approximately CLKVDD18 / 2. DACCLKP 1 I LVPECL clock positive input for DAC core with a self-bias of approximately CLKVDD18 / 2. IOUTAN 60 O A-Channel DAC current output. An offset binary data pattern of 0x0000 at the DAC input results in a full-scale current source, and the most positive voltage on the IOUTAP pin. Similarly, a 0xFFFF data input results in a 0-mA current source, and the least positive voltage on the IOUTAP pin. The IOUTAN pin is the complement of IOUTAP. IOUTAP 61 O IOUTBN 54 O B-Channel DAC current output. An offset binary data pattern of 0x0000 at the DAC input results in a full-scale current source, and the most positive voltage on the IOUTBP pin. Similarly, a 0xFFFF data input results in a 0-mA current source, and the least positive voltage on the IOUTBP pin. The IOUTBN pin is the complement of IOUTBP. IOUTBP 53 O REFERENCE BIASJ 57 O Full-scale output current bias. For 20-mA full-scale output current, connect a 960-Ω resistor to GND. EXTIO 58 I/O Used as external reference input when internal reference is disabled. Requires a 0.1-µF decoupling capacitor to GND when used as reference output. POWER SUPPLY CLKVDD18 3 I 1.8-V clock supply. DIGVDD18 21, 28 I 1.8-V digital supply. Also supplies LVDS receivers. IOVDD 45 I Supply voltage for CMOS I/Os. 1.8 V to 3.3 V. VDDA18 50, 64 I Analog 1.8-V supply. VDDA33 55, 56, 59 I Analog 3.3-V supply. VFUSE 8 I Digital supply voltage (1.8 V). This supply pin is also used for factory fuse programming. Connect to DVDD pins for normal operation. NC 4, 5, 51, 52, 62, 63 — Not used. In actual application, pins 51, 52, 62, and 63 can be left open or tied to ground. TI recommends tying pins 4 and 5 to DIGVDD18 and ground, respectively. GND PAD — — This thermal pad is the electrical ground connection for the device (backside).

www.ti.com SLAS837B –APRIL 2013–REVISED JANUARY 2017 Product Folder Links: DAC3174 Submit Documentation FeedbackCopyright © 2013–2017, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT Supply voltage VDDA33 to GND –0.5 4 V VDDA18 to GND –0.5 2.3 CLKVDD18 to GND –0.5 2.3 IOVDD to GND –0.5 4 DIGVDD18 to GND –0.5 2.3 Terminal voltage CLKVDD18 to DIGVDD18 –0.5 0.5 V VDDA18 to DIGVDD18 –0.5 0.5 DA[6:0]P, DA[6:0]N, DB[6:0]P, DB[6:0]N, D[13:0]P, D[13:0]N, DATACLKP, DATACLKN, DA_CLKP, DA_CLKPN, DB_CLKP, DB_CLKN, SYNCP, SYNCN to GND –0.5 DIGVDD18 + 0.5 DACCLKP, DACCLKN, ALIGNP, ALIGNN –0.5 CLKVDD18 + 0.5 TXENABLE, ALARM, SDO, SDIO, SCLK, SDENB, RESETB to GND –0.5 IOVDD + 0.5 IOUTAP, IOUTAN, IOUTBP, IOUTBN to GND –0.7 1.4 EXTIO, BIASJ to GND –0.5 VDDA33 + 0.5 Temperature Operating ambient free-air, TA –40 85 °CMaximum junction, TJ 125 Storage, Tstg –65 150 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.2 ESD Ratings

V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500 (1) Sets CMOS IO voltage levels; nominal 1.8 V, 2.5 V, or 3.3 V. (2) Prolonged use at this junction temperature may increase the device failure-in-time (FIT) rate.

6.3 Recommended Operating Conditions

CLKVDD18 Clock buffer supply 1.71 1.8 1.89 V DIGVDD18 Digital supply 1.71 1.8 1.89 V VDDA18 1.8-V analog supply 1.71 1.8 1.89 V VFUSE Fuse bank supply 1.71 1.8 1.89 V IOVDD IO supply(1) 1.71 3.45 V VDDA33 3.3-V analog supply 3.15 3.3 3.45 V TA Operating ambient free-air temperature –40 25 85 °C TJ Operating junction temperature(2) 105 °C

SLAS837B –APRIL 2013–REVISED JANUARY 2017 www.ti.com Product Folder Links: DAC3174 Submit Documentation Feedback Copyright © 2013–2017, Texas Instruments Incorporated (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.4 Thermal Information

THERMAL METRIC(1) DAC3174 UNITRGC (VQFN)

64 PINS

RθJA Junction-to-ambient thermal resistance 23 °C/W RθJC(top) Junction-to-case (top) thermal resistance 7.6 °C/W RθJB Junction-to-board thermal resistance 2.8 °C/W ψJT Junction-to-top characterization parameter 0.1 °C/W ψJB Junction-to-board characterization parameter 2.8 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 0.2 °C/W

6.5 Electrical Characteristics: DC Specifications

Typical values at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, DAC sample rate = 500 MSPS, 50% clock duty cycle, VDDA33 = IOVDD = 3.3 V, VDDA18 = CLKVDD18 = DIGVDD18 = 1.8 V, and IOUTFS = 20 mA (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Resolution 14 Bits DC ACCURACY DNL Differential nonlinearity 1 LSB = IOUTFS / 214 ±1 LSB INL Integral nonlinearity 1 LSB = IOUTFS / 214 ±2 LSB ANALOG OUTPUTS Coarse gain linearity ±0.4 LSB Offset error Midcode offset 0.01 %FSR Gain error With external reference ±2 %FSR With internal reference ±2 Gain mismatch With internal reference –2 2 %FSR Minimum full-scale output current Nominal full-scale current, IOUTFS = 16 × IBAIS current 2 mA Maximum full-scale output current Nominal full-scale current, IOUTFS = 16 × IBAIS current 20 mA Output compliance IOUTFS = 20 mA –0.5 1 V Output resistance 300 kΩ Output capacitance 5 pF REFERENCE OUTPUT VREF Reference output voltage 1.14 1.2 1.26 V Reference output current 100 nA REFERENCE INPUT VEXTIO input voltage External reference mode 0.1 1.2 1.25 V Input resistance 1 MΩ Small-signal bandwidth 500 kHz Input capacitance 100 pF TEMPERATURE COEFFICIENTS Offset drift ±1 ppm of FSR/°C Gain drift With external reference ±15 With internal reference ±30 Reference voltage drift ±8 ppm /°C

www.ti.com SLAS837B –APRIL 2013–REVISED JANUARY 2017 Product Folder Links: DAC3174 Submit Documentation FeedbackCopyright © 2013–2017, Texas Instruments Incorporated Electrical Characteristics: DC Specifications (continued) Typical values at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, DAC sample rate = 500 MSPS, 50% clock duty cycle, VDDA33 = IOVDD = 3.3 V, VDDA18 = CLKVDD18 = DIGVDD18 = 1.8 V, and IOUTFS = 20 mA (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER CONSUMPTION IVDDA33 3.3-V analog supply current MODE 1, fDAC = 491.52 MSPS, QMC on, IF = 20 MHz 52 59 mA MODE 2, fDAC = 320 MSPS, QMC on, IF = 20 MHz 51 MODE 3, sleep mode, fDAC = 491.52 MSPS, DAC in sleep mode 2.6 MODE 4, power-down mode, no clock, DAC in sleep mode 1.6 4 ICLKVDD18 1.8-V clock and analog supply current (CLKVDD18 and VDDA18) MODE 1, fDAC = 491.52 MSPS, QMC on, IF = 20 MHz 49 57 mA MODE 2, fDAC = 320 MSPS, QMC on, IF = 20 MHz 38 MODE 3, sleep mode, fDAC = 491.52 MSPS, DAC in sleep mode 43 MODE 4, power-down mode, no clock, DAC in sleep mode 1.8 4 IDIGVDD18 1.8-V digital supply current (DIGVDD18 and VFUSE) MODE 1, fDAC = 491.52 MSPS, QMC on, IF = 20 MHz 115 130 mA MODE 2, fDAC = 320 MSPS, QMC on, IF = 20 MHz 87 MODE 3, sleep mode, fDAC = 491.52 MSPS, DAC in sleep mode 110 MODE 4, power-down mode, no clock, DAC in sleep mode 0.7 3 IIOVDD 1.8-V IO supply current MODE 1, fDAC = 491.52 MSPS, QMC on, IF = 20 MHz 0.002 0.015 mA MODE 2, fDAC = 320 MSPS, QMC on, IF = 20 MHz 0.002 MODE 3, sleep mode, fDAC = 491.52 MSPS, DAC in sleep mode 0.003 MODE 4, power-down mode, no clock, DAC in sleep mode 0.003 0.015 Pdis Total power dissipation MODE 1, fDAC = 491.52 MSPS, QMC on, IF = 20 MHz 464 530 mW MODE 2, fDAC = 320 MSPS, QMC on, IF = 20 MHz 396 MODE 3, sleep mode, fDAC = 491.52 MSPS, DAC in sleep mode 284 MODE 4, power-down mode, no clock, DAC in sleep mode 10 26 PSRR Power-supply rejection ratio DC tested –0.4 0.4 %FSR/V

6.6 Electrical Characteristics: AC Specifications

26 DACCLK

SFDR Spurious free dynamic fDAC = 500 MSPS, fout = 10.1 MHz 82 dBcfDAC = 500 MSPS, fout = 20.1 MHz 78 fDAC = 500 MSPS, fout = 70.1 MHz 74 IMD3 Intermodulation distortion fDAC = 500 MSPS, fout = 10.1 ±0.5 MHz 84 dBc fDAC = 500 MSPS, fout = 20.1 ±0.5 MHz 84 fDAC = 500 MSPS, fout = 70.1 ±0.5 MHz 75 fDAC = 500 MSPS, fout = 150.1 ±0.5 MHz 63 NSD Noise spectral density fDAC = 500 MSPS, fout = 10.1 MHz 160 dBc/HzfDAC = 500 MSPS, fout = 20.1 MHz 157 fDAC = 500 MSPS, fout = 70.1 MHz 155 ACLR Adjacent channel leakage ratio fDAC = 491.52 MSPS, fout = 30.72 MHz, WCDMA TM1 78 dBc f AC = 491.52 MSPS, fout = 153.6 MHz, WCDMA TM1 74

6.7 Electrical Characteristics: Digital Specifications

Typical values at T A = 25°C, full temperature range is T MIN = –40°C to T MAX = 85°C, DAC sample rate = 500 MSPS, 50% clock duty cycle, VDDA33 = IOVDD = 3.3 V, VDDA18 = CLKVDD18 = DIGVDD18 = 1.8 V, and IOUT FS = 20 mA (unless otherwise noted). PARAMETERS TEST CONDITIONS MIN TYP MAX UNIT CMOS DIGITAL INPUTS (RESETB, SDENB, SCLK, SDIO, TXENABLE) VIH High-level input voltage IOVDD = 3.3 V, 2.5 V, or 1.8 V IOVDD × 0.6 V VIL Low-level input voltage IOVDD = 3.3 V, 2.5 V, or 1.8 V 0.25 × IOVDD V IIH High-level input current IOVDD = 3.3 V, 2.5 V, or 1.8 V –40 40 µA IIL Low-level input current IOVDD = 3.3 V, 2.5 V, or 1.8 V –40 40 µA DIGITAL OUTPUTS – CMOS INTERFACE (SDOUT, SDIO) VOH High-level output voltage IOVDD = 3.3 V, 2.5 V, or 1.8 V 0.85 × IOVDD V VOL Low-level output voltage 0.125 × IOVDD V LVPECL INPUTS – (DACCLKx, ALIGNx) VCM LVPECL input common-mode voltage 0.5 V VIDIFF Differential input peak-to-peak voltage 0.4 1 V

6.8 Timing Requirements

Typical values at T A = 25°C, full temperature range is T MIN = –40°C to T MAX = 85°C, DAC sample rate = 500 MSPS, 50% clock duty cycle, VDDA33 = IOVDD = 3.3 V, VDDA18 = CLKVDD18 = DIGVDD18 = 1.8 V, and IOUT FS = 20 mA (unless otherwise noted). MIN TYP MAX UNIT SERIAL PORT TIMING ts(SENDB) Setup time, SDENB to rising edge of SCLK 20 ns ts(SDIO) Setup time, SDIO to rising edge of SCLK 10 ns th(SDIO) Hold time, SDIO from rising edge of SCLK 5 ns t(SCLK) Period of SCLK 100 ns t(SCLKH) High time of SCLK 40 ns t(SCLKL) Low time of SCLK 40 ns td(DATA) Data output delay after falling edge of SCLK 10 ns TRESET Minimum RESTB pulse duration 25 ns LVDS INPUT TIMING ts(DATA) Setup time D[x..0] valid to DATACLK rising or falling edge for single bus single clock mode ; DA/DB[x… 0] valid to DB_CLK rising or falling edge for dual bus single clock mode; DA[x..0] valid to DA_CLK rising or falling edge, and DB[x… 0] valid for DB_CLK rising or falling edge for dual bus dual clock mode config3 Setting ps datadly clkdly 0 0 –20 0 1 –120 0 2 –220 0 3 –310 0 4 –390 0 5 –480 0 6 –560 0 7 –630 1 0 70 2 0 150 3 0 230 4 0 330 5 0 430 6 0 530 7 0 620

edge for dual bus dual clock mode. Figure 1. Input Data Timing for Single-Bus, Single-Clock Mode

6.9 Typical Characteristics

scale output current (unless otherwise noted). Figure 5. Integral Nonlinearity Figure 6. Differential Nonlinearity Figure 7. SFDR vs Output Frequency Over Input Scale Figure 8. Second-Order Harmonic Distortion Figure 9. Third-Order Harmonic Distortion Figure 10. SFDR vs Output Frequency Over fDAC

1 R M

3 D B

scale output current (unless otherwise noted). Figure 23. ACPR – LTE 10-MHz FDD E-TM 1.1 Figure 24. ACPR – LTE 20-MHz FDD E-TM 1.1

7 Detailed Description

7.1 Overview

FIFO input and output pointers can be synchronized across multiple devices for precise signal synchronization.

7.2 Functional Block Diagrams

Figure 25. 14-Bit Interface Mode

Figure 26. 7-Bit Interface Mode

7.3 Feature Description

7.3.1 Alarm Monitoring

The DAC3174 includes flexible alarm monitoring that can be used to alert a possible malfunction scenario. All alarm events can be accessed either through the SIP registers and through the ALARM pin. After an alarm is set, the corresponding alarm bit in register config5 must be reset through the serial interface in order to allow further testing. The set of alarms includes the following conditions:

Zero check alarm – Alarm_from_zerochk: Occurs when the FIFO write pointer has an all zeros pattern. Because the write pointer is a shift register, all zeros cause the input point to be stuck until the next sync event. When this happens, a sync to the FIFO block is required.
FIFO alarms – alarm_from_fifo: Occurs when there is a collision in the FIFO pointers or a collision event is close. – alarm_fifo_2away: Pointers are within two addresses of each other. – alarm_fifo_1away: Pointers are within one address of each other. – alarm_fifo_collision: Pointers are equal to each other.
Clock alarms – clock_gone: Occurs when either the DACCLK or DATACLOCK have been stopped. – alarm_dacclk_gone: Occurs when the DACCLK has been stopped. – alarm_dataclk_gone: Occurs when the DATACLK has been stopped.
Pattern checker alarm – alarm_from_iotest: Occurs when the input data pattern does not match the pattern key. To prevent unexpected DAC outputs from propagating into the transmit channel chain, the DAC3174 includes a feature that disables the outputs when a catastrophic alarm occurs. The catastrophic alarms include FIFO pointer collision, the loss DACCLK, or the loss of DATACLK. When any of these alarms occur, the internal TXenable signal is driven low and causes a zeroing of the data going to the DAC in < 10 T, where T = DACCLK period. One caveat is that if both clocks stop, the circuit cannot determine clock loss, so no alarms are generated; therefore, no zeroing of output data occurs.

7.4 Device Functional Modes

7.4.1 Data Input Formats

Table 1 through Table 4 list the single and dual bus clock modes of the DAC3174. Table 1. Single Bus Single Clock Mode Table 2. Single Channel SDR Mode

Table 3. Dual Bus Single Clock Mode Table 4. Dual Bus Dual Clock Mode using the 7-bit interface, each of the 7 bits are reversed.

7.4.2 Synchronization Modes

There are three modes of syncing included in the DAC3174:

NORMAL Dual Sync— The SYNCx pin is used to align the input side of the FIFO (write pointers) with the A(0) sample. The ALIGNx pin is used to reset the output side of the FIFO (read pointers) to the offset value. Multiple chip alignment can be accomplished with this kind of syncing.
SYNC_ONLY— In this mode, only the SYNCx pin is used to sync both the read and write pointers of the FIFO. There is an asynchronous handoff between the DATACLK and DACCLK when using this mode; therefore, it is impossible to accurately align multiple chips closer than 2T or 3T, where T = DACCLK period.
SIF_SYNC— When neither SYNCx nor ALIGNx are used, a programmable synchronizing pulse is used to synchronize the design. However, the same issues for SYNC_ONLY mode apply. There is an asynchronous handoff between the serial clock domain and the two sides of the FIFO. Because of the asynchronous nature of SIF_SYNC method, it is impossible to align the sync with any sample at the input. SIF_SYNC mode is the only synchronization mode supported in dual-bus mode. NOTE When ALIGNP and ALIGNN are not used, TI recommends clearing alignrx_ena (config 1, bit 4), tying ALIGNP to DIGVDD18, and tying ALIGNN to ground. When SYNCP and SYNCN are not used, TI recommends clearing syncrx_ena (config 0, bit 3). Then, the unused SYNCP and SYNCN pins can be left open or tied to ground.

7.5 Programming

7.5.1 Initialization

Set TXENABLE low to prevent spurious output while initializing the device.
Supply all 1.8-V voltages (VDDA18, DIGVDD18, CLKVDD18, and VFUSE) and all 3.3-V voltages (VDDA33,
Provide all LVPECL inputs: DACCLKP, DACCLKN, and the optional ALIGNP and ALIGNN. These inputs can

also be provided after the SIF register programming.

Toggle the RESETB pin active low for a minimum pulse duration of 25 ns.
Program the SIF registers.
Make sure the FIFO pointers are properly initialized using one of the following methods:

7.5.2 Serial Interface Description

detailed description of each bit. The data transfer cycle consists of two bytes. Table 5. Instruction Byte of the Serial Interface operation from the DAC3174, and a low indicates a write operation to the DAC3174. [A6:A0] Identifies the address of the register to be accessed during the read or write operation.

7.6 Register Maps

Table 6 lists the register maps for the DAC3174. In the SIF interface, there are three types of registers: 1. NORMAL – The NORMAL register type allows data to be written and read from. All 16-bits of the data are registered at the same time. There is no synchronizing with an internal clock thus all register writes are asynchronous with respect to internal clocks. There are three subtypes of NORMAL: – AUTOSYNC: A NORMAL register that causes a sync to be generated after the write is finished. These are most commonly used in things like offsets and phaseadd, where there is a word or block setup that extends across multiple registers, and all of the registers required to be programmed before any take effect on the circuit. For example, the phaseadd is two registers long. There is no benefit to have the first write 16 of the 32 bits cause a change in the frequency, so the design allows all the registers to be written. When the last register write for this block is finished, an autosync is generated for the mixer to read all the new SIF values. This occurs on a mixer clock cycle so that no metastability errors occur. – No RESET Value: These are NORMAL registers, but for one reason or another, the reset value can not be ensured. The reason may be because the register has some read-only bits, or some internal logic partially controls the bit values. An example is the SIF_CONFIG6 register. The bits come from the temperature sensor and the fuses. Depending on which fuses are blown and what the die temperature is, the reset value is different. – FUSE controlled: While not a type of register, fuses can affect what is read as the default value. The default values shown in this data sheet are for when no fuses are blown. 2. READ_ONLY – Registers that are internal wires ANDed with the address bus, and then connected to the SIF output data bus. 3. WRITE_TO_CLEAR: – These registers are just like NORMAL registers with one exception: these registers can be written and read. However, when the internal logic asynchronously sets a bit high in one of these registers, that bit stays high until written to 0. In this way, interrupts are captured and stay constant until cleared by the user.

Table 6. Register Map

Figure 29. config0 Register Table 7. config0 Register Field Descriptions all 14-bits are reversed as one word. bit has a lower priority than the dieid_ena bit. bus mode, and SIF_SYNC mode in single bus mode).

Figure 30. config1 Register Table 8. config1 Register Field Descriptions with the rising edge of SYNC. 14 bsideclk_ena When asserted the input clock for the B side datapath is enabled. sync pulse is generated. 1 → 0 has no effect.

Figure 33. config4 Register Table 11. config4 Register Field Descriptions and [6:0] match up with bits from port B.

Figure 34. config5 Register Table 12. config5 Register necessary to restart the FIFO write pointer. necessary to restart the FIFO write pointer. 1xx: FIFO pointer collision. to 0 for CDRV_SER outputs to resume normal operation. pattern in the iotest_pattern registers. pattern in the iotest_pattern registers.

Figure 35. config6 Register Table 13. config6 Register Field Descriptions 0x06 15:8 tempdata This the output from the chip temperature sensor. available functionality in the chip.

8 Application and Implementation

validate and test their design implementation to confirm system functionality.

8.1 Application Information

cable head-end equipment, and so on.

8.2 Typical Application

modulated communication signal. Figure 56. Real IF Transmitter

8.2.1 Design Requirements

out the undesired signal image and the local oscillator.

8.2.2 Detailed Design Procedure

Figure 57. Signal Spectrum in a Real IF Transmitter MHz is a good, balanced choice in this example, and makes the design of the band-pass filter reasonably easy. telecommunications sample rate), so that the sample data rate into the DAC3174 is also 500 MSPS.

8.2.3 Application Curve

intermediate frequency of 100 MHz. Figure 58. Single-Carrier, WCDMA Signal ACPR at 100 MHz

9 Power Supply Recommendations

pins as possible using small value capacitors, with larger bulk capacitors placed further away. Table 34. DAC Power Supplies

10 Layout

10.1 Layout Guidelines

DAC output termination resistors must be placed as close to the output pins as possible to provide a dc path to ground and set the source impedance.
Route the LVDS data signals as impedance-controlled, tightly-coupled, matched-length differential traces.
Maintain a solid ground plane under the LVDS signals without any ground plane splits.
Place a thermal ground pad under the device with an adequate number of vias to the ground planes of the board.

10.2 Layout Example

Figure 59. DAC3174 Layout Example

11 Device and Documentation Support

11.1 Device Support

11.1.1 Device Nomenclature

Adjacent Carrier Leakage Ratio (ACLR): Defined as the ratio in decibels relative to the carrier (dBc) between the measured power within a channel and that of its adjacent channel. Analog and Digital Power Supply Rejection Ratio (APSSR, DPSSR): Defined as the percentage error in the ratio of the delta IOUT and delta supply voltage normalized with respect to the ideal IOUT current. Differential Nonlinearity (DNL): Defined as the variation in analog output associated with an ideal 1 LSB change in the digital input code. Gain Drift: Defined as the maximum change in gain, in terms of ppm of full-scale range (FSR) per °C, from the value at ambient (25°C) to values over the full operating temperature range. Gain Error: Defined as the percentage error (in FSR%) for the ratio between the measured full-scale output current and the ideal full-scale output current. Integral Nonlinearity (INL): Defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero scale to full scale. Intermodulation Distortion (IMD3): The two-tone IMD3 is defined as the ratio (in dBc) of the 3rd-order intermodulation distortion product to either fundamental output tone. Offset Drift: Defined as the maximum change in DC offset, in terms of ppm of full-scale range (FSR) per °C, from the value at ambient (25°C) to values over the full operating temperature range. Offset Error: Defined as the percentage error (in FSR%) for the ratio between the measured mid-scale output current and the ideal mid-scale output current. Output Compliance Range: Defined as the minimum and maximum allowable voltage at the output of the current-output DAC. Exceeding this limit may result reduced reliability of the device or adversely affecting distortion performance. Reference Voltage Drift: Defined as the maximum change of the reference voltage in ppm per degree Celsius from value at ambient (25°C) to values over the full operating temperature range. Spurious Free Dynamic Range (SFDR): Defined as the difference (in dBc) between the peak amplitude of the output signal and the peak spurious signal. Signal to Noise Ratio (SNR): Defined as the ratio of the RMS value of the fundamental output signal to the RMS sum of all other spectral components below the Nyquist frequency, including noise, but excluding the first six harmonics and dc.

11.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

11.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.

11.4 Trademarks

PowerPAD, E2E are trademarks of Texas Instruments. All other trademarks are the property of their respective owners.

11.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

11.6 Glossary

SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

www.ti.com 10-Nov-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) DAC3174IRGCR Active Production VQFN (RGC) | 64 2000 | LARGE T&R Yes NIPDAU Level-3-260C-168 HR -40 to 85 DAC3174I DAC3174IRGCR.A Active Production VQFN (RGC) | 64 2000 | LARGE T&R Yes NIPDAU Level-3-260C-168 HR -40 to 85 DAC3174I DAC3174IRGCT Active Production VQFN (RGC) | 64 250 | SMALL T&R Yes NIPDAU Level-3-260C-168 HR -40 to 85 DAC3174I DAC3174IRGCT.A Active Production VQFN (RGC) | 64 250 | SMALL T&R Yes NIPDAU Level-3-260C-168 HR -40 to 85 DAC3174I (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 9-Aug-2017 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DAC3174IRGCR VQFN RGC 64 2000 336.6 336.6 28.6 DAC3174IRGCT VQFN RGC 64 250 367.0 367.0 38.0 PACKAGE MATERIALS INFORMATION www.ti.com 9-Aug-2017 Pack Materials-Page 2

www.ti.com GENERIC PACKAGE VIEW Images above are just a representation of the package family, actual package may vary. Refer to the product data sheet for package details. VQFN - 1 mm max heightRGC 64 PLASTIC QUAD FLATPACK - NO LEAD9 x 9, 0.5 mm pitch 4224597/A

www.ti.com PACKAGE OUTLINE C 9.15 8.85 9.15 8.85 1.0 0.8 0.05 0.00 2X 7.5 60X 0.5 2X 7.5 64X 0.5 0.3 64X 0.30 0.18 7.4 0.1 (0.2) TYP VQFN - 1 mm max heightRGC0064H PLASTIC QUAD FLATPACK - NO LEAD 4219011/A 05/2018 0.08 C

0.1 C A B

0.05 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. PIN 1 INDEX AREA SEATING PLANE PIN 1 ID SYMMEXPOSED THERMAL PAD SYMM 17 32 4964 SCALE 1.500 AB

www.ti.com EXAMPLE BOARD LAYOUT 60X (0.5) (R0.05) TYP

0.07 MAX

0.07 MIN

(1.16) TYP (3.45) TYP (1.16) TYP (3.45) TYP 64X (0.6) 64X (0.24) (8.8) (8.8) ( 7.4) ( 0.2) TYP VIA VQFN - 1 mm max heightRGC0064H PLASTIC QUAD FLATPACK - NO LEAD 4219011/A 05/2018 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. SYMM SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SEE SOLDER MASK DETAIL 17 32 4964 METAL EDGE SOLDER MASK OPENING EXPOSED METAL METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METAL NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED SOLDER MASK DETAILS

www.ti.com EXAMPLE STENCIL DESIGN 64X (0.6) 64X (0.24) 60X (0.5) (8.8) (8.8) 36X ( 0.96) (R0.05) TYP (0.58) (1.16) TYP (0.58) (1.16) TYP VQFN - 1 mm max heightRGC0064H PLASTIC QUAD FLATPACK - NO LEAD 4219011/A 05/2018 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SOLDER PASTE EXAMPLE BASED ON 0.125 MM THICK STENCIL SCALE: 10X EXPOSED PAD 65 61% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SYMM SYMM 17 32 4964

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Selected Specification

Texas Instruments DAC3174 overview.

Summary

Dual 14-bit 500 MSPS Digital to Analog Converter

Description

Dual 14-bit 500 MSPS Digital to Analog Converter

Source title DAC3174 Datasheet(PDF) - Texas Instruments

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