Summary
72-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT
Description
72-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT
Source title
CY7C25702KV18-400BZC Datasheet(PDF) - Cypress Semiconductor