Summary
36-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT
Description
36-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT
Source title
CY7C2268KV18-550BZC Datasheet(PDF) - Cypress Semiconductor