Summary
18-Mbit DDR II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency) with ODT
Description
18-Mbit DDR II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency) with ODT
Source title
CY7C21701KV18-400BZXC Datasheet(PDF) - Cypress Semiconductor