Summary
36-Mbit QDR??II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency)
Description
36-Mbit QDR??II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency)
Source title
CY7C1263V18-300BZI Datasheet(PDF) - Cypress Semiconductor