Summary
36-Mbit QDR짰 II+ SRAM Four-Word Burst Architecture (2.0 Cycle Read Latency)
Description
36-Mbit QDR짰 II+ SRAM Four-Word Burst Architecture (2.0 Cycle Read Latency)
Source title
CY7C1241KV18_12 Datasheet(PDF) - Cypress Semiconductor