Summary
36-Mbit QDR짰 II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency)
Description
36-Mbit QDR짰 II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency)
Source title
CY7C12411KV18 Datasheet(PDF) - Cypress Semiconductor