CSD95480RWJ Synchronous Buck NexFET Smart Power Stage datasheet
Document overview
- Manufacturer or author: Texas Instruments, Incorporated [SLPS670,*]
- PDF pages: 14
Technical content
BOOT BOOT_R VOS VSW TAO REFINIOUTPGNDLSET PVDD VDD EN/FCCM PWM VIN CSD95480RWJ BOOT BOOT_R VOS VSW TAO REFINIOUTPGNDLSET PVDD VDD EN/FCCM PWM VIN CSD95492QVM BOOT BOOT_R VOS VSW TAO REFINIOUTPGNDLSET PVDD VDD EN/FCCM PWM VIN TPS53679AVSP AVSN ADDR PWM1 ASKIP# ACSP1 TSEN APWM6 ACSP6 VREF BVSN BVSP BPWM1 BSKIP# BCSP1 V3P3 VIN_CSNIN CSPIN BEN_VCCIO SCLK SDIO SALERT# PIN_ALT# VR_HOT# SMB_CLK SMB_ALERT# SMB_DIO AVR_RDY BVR_RDY AVR_EN VR_FAULT# RESET# AGND VCCIO P12V P12V P12V P12V 3.3V VREF LOAD LOAD P5V P5V P5V Copyright © 2016, Texas Instruments Incorporated Output Current (A) Efficiency (%) Power Loss (W) 0 10 20 30 40 50 60 70 30 0 40 2.5 50 5 60 7.5 70 10 80 12.5 90 15 100 17.5 D000 VDD = 5 V VIN = 12 V VOUT = 1.8 V LOUT = 150 nH fSW = 600 kHz TA = 25qC Product Folder Order Now T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. CSD95480RWJ SLPS670 –JUNE 2017 CSD95480RWJSynchronousBuckNexFET™ SmartPowerStage
1 Features
1• 70-A Continuous Operating Current Capability
- Over 95% System Efficiency at 30 A
- High-Frequency Operation (up to 1.25 MHz)
- Diode Emulation Function
- Temperature Compensated Bi-Directional Current Sense
- Analog Temperature Output
- Fault Monitoring
- 3.3-V and 5-V PWM Signal Compatible
- Tri-State PWM Input
- Integrated Bootstrap Switch
- Optimized Dead Time for Shoot-Through Protection
- High-Density QFN 5-mm × 6-mm Footprint
- Ultra-Low-Inductance Package
- System Optimized PCB Footprint
- Thermally Enhanced Topside Cooling
- RoHS Compliant – Lead-Free Terminal Plating
- Halogen Free Application Diagram
2 Applications
- Multiphase Synchronous Buck Converters – High-Frequency Applications – High-Current, Low-Duty Cycle Applications
- POL DC-DC Converters
- Memory and Graphic Cards
- Desktop and Server VR12.x / VR13.x V-Core Synchronous Buck Converters
3 Description
The CSD95480RWJ NexFET™ power stage is a highly optimized design for use in a high-power, high- density synchronous buck converter. This product integrates the driver IC and power MOSFETs to complete the power stage switching function. This combination produces high-current, high-efficiency, and high-speed switching capability in a small 5-mm × 6-mm outline package. It also integrates the accurate current sensing and temperature sensing functionality to simplify system design and improve accuracy. In addition, the PCB footprint has been optimized to help reduce design time and simplify the completion of the overall system design. Device Information(1) DEVICE MEDIA QTY PACKAGE SHIP CSD95480RWJ 13-Inch Reel 2500 QFN 5.00-mm × 6.00-mm Package Tape and ReelCSD95480RWJT 7-Inch Reel 250 (1) For all available packages, see the orderable addendum at the end of the data sheet. Typical Power Stage Efficiency and Power Loss
SLPS670 –JUNE 2017 www.ti.com Product Folder Links: CSD95480RWJ Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Table of Contents
9 Mechanical, Packaging, and Orderable
4 Revision History
June 2017 * Initial release.
10 11 12 13 14 15 16 17 18 19 30313233343536373839 VOS AGND VDD PVDD PGND NC PGND PGND PGND PGND PGND PGND PGND PGND SW SW SW SW SW SW SW SW SW SW VIN BOOT PWM EN/FCCM TAO/FLT IOUT REFIN NC BOOTR LSET VIN VIN VIN VIN VIN
40 VIN
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5 Pin Configuration and Functions
DESCRIPTION
VOS 1 Output voltage sensing pin for the internal current sensing circuitry. AGND 2 This pin is internally connected to PGND. VDD 3 Supply voltage for internal circuitry. This pin should be bypassed directly to pin 2. PVDD 4 Supply voltage for gate drivers. This pin should be bypassed to PGND. PGND 5 Power ground. NC 6 Not connected. This pin needs to be left floating in application. PGND 7-9 Power ground. VSW 10-19 Phase node connecting the HS MOSFET source and LS MOSFET drain – pin connection to the output inductor. PGND 20-24 Power ground. VIN 25-30 Input voltage pin. Connect input capacitors close to this pin. NC 31 Not connected. This pin needs to be left floating in application. BOOTR 32 Return path for HS gate driver. It is connected to VSW internally. BOOT 33 Bootstrap capacitor connection. Connect a minimum 0.1-µF, 16-V, X5R ceramic capacitor from BOOT to BOOTR pins. The bootstrap capacitor provides the charge to turn on the control FET. The bootstrap diode is integrated. PWM 34 Tri-state input from external controller. Logic low sets control FET gate low and sync FET gate high. Logic high sets control FET gate high and sync FET gate low. Both MOSFET gates are set low if PWM stays in Hi-Z for greater than the tri-state shutdown holdoff time (T3HT). EN/FCCM 35 This dual function pin either enables the diode emulation function or can be used as a simple enable for the device. When this pin is driven into the tri-state window and held there for more than the tri-state holdoff time, diode emulation mode is enabled for sync FET. When the pin is high, device operates in forced continuous conduction mode. When the pin is low, both FETs are held off. An internal resistor pulls this pin low if left floating. TAO/FLT 36 Temperature amplifier output. Reports a voltage proportional to the IC temperature. An ORing diode is integrated in the IC. When used in multiphase application, a single wire can be used to connect the TAO pins of all the ICs. Only the highest temperature will be reported. TAO will be pulled up to 3.3 V if thermal shutdown LSOC or HSS detection circuit is tripped. LSET 37 A resistor from this pin to PGND pin sets the inductor value for the internal current sensing circuitry. IOUT 38 Output of current sensing amplifier. V(IOUT) – V(REFIN) is proportional to the phase current. REFIN 39 External reference voltage input for current sensing amplifier. PGND 40 Power ground. NC 41 Not connected. This pin needs to be left floating in application.
SLPS670 –JUNE 2017 www.ti.com Product Folder Links: CSD95480RWJ Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) Should not exceed 7 V.
6 Specifications
6.1 Absolute Maximum Ratings
TA = 25°C (unless otherwise stated)(1) MIN MAX UNIT VIN to PGND –0.3 20 V VIN to VSW –0.3 20 V VIN to VSW (10 ns) 23 V VSW to PGND –0.3 20 V VSW to PGND (10 ns) –7 23 V VDD to PGND –0.3 7 V PVDD to PGND –0.3 7 V EN/FCCM, TAO/FLT, LSET to PGND –0.3 VDD + 0.3 V IOUT, VOS, PWM to PGND –0.3 7 V REFIN –0.3 3.6 V BOOT to BOOTR(2) –0.3 VDD + 0.3 V BOOT to PGND –0.3 30 V TJ Operating junction temperature –55 150 °C Tstg Storage temperature –55 150 °C
6.2 ESD Ratings
V(ESD) Electrostatic discharge Human-body model (HBM) ±2000 V Charged-device model (CDM) ±500 (1) Operating at high VIN can create excessive AC voltage overshoots on the switch node (VSW) during MOSFET switching transients. For reliable operation, the switch node (VSW) to ground voltage must remain at or below the Absolute Maximum Ratings. (2) Measurement made with six 10-µF (TDK C3216X7R1C106KT or equivalent) ceramic capacitors across VIN to PGND pins. (3) System conditions as defined in Note 2. Peak output current is applied for tp = 50 µs.
6.3 Recommended Operating Conditions
TA = 25°C (unless otherwise stated) MIN MAX UNIT VDD Driver supply voltage 4.5 5.5 V PVDD Gate drive voltage 4.5 5.5 V VIN Input supply voltage(1) 4.5 16 V VOUT Output voltage 5.5 V PWM to PGND VDD + 0.3 V IOUT Continuous output current VIN = 12 V, VDD = 5 V, PVDD = 5 V, VOUT = 1.2 V, ƒSW = 500 kHz(2) 70 A IOUT-PK Peak output current(3) 90 A ƒSW Switching frequency CBST = 0.1 µF (min), VOUT = 2.5 V (max) 1250 kHz On-time duty cycle ƒSW = 1 MHz 85% Minimum PWM on-time 20 ns Operating junction temperature –40 125 °C
www.ti.com SLPS670 –JUNE 2017 Product Folder Links: CSD95480RWJ Submit Documentation FeedbackCopyright © 2017, Texas Instruments Incorporated thick FR4 board based on hottest board temperature within 1 mm of the package.
6.4 Thermal Information
TA = 25°C (unless otherwise stated) THERMAL METRIC MIN TYP MAX UNIT θJC Thermal resistance, junction-to-case (top of package) 7.4 °C/W θJB Thermal resistance, junction-to-board(1) 2.2 °C/W ΨJT Junction-to-top characterization parameter 0.9 °C/W
7 Application Schematic
Figure 1. Application Schematic
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8 Device and Documentation Support
8.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.
8.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.
8.3 Trademarks
NexFET, E2E are trademarks of Texas Instruments. All other trademarks are the property of their respective owners.
8.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
8.5 Glossary
SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.
C
1.05 MAX
13X 0.3 0.2 0.05 0.00 16X 0.3 0.2 10X 0.3 0.2 16X 0.45 0.35 2.25 0.1 .000 PKG 0.3 0.1 0.4 0.1 0.8 0.1 0.1 0.1 2.2 0.1 2.6 0.1
0.13 TYP
14X 0.45 1.75 0.1 .000 PKG 0.9 0.1 0.4 0.1 TYP 2.225 0.1 9X 0.45 10X 0.45 2.275 2.175 2.05 1.95 2.025 1.3 0.1 2.05 R0.05 TYP A 6.1 5.9 B 5.1 4.9 (0.203) TYP 4221590/C 01/2017 PIN 1 INDEX AREA 0.08 SEATING PLANE 9 20 10 19 X0.3) (45 PIN 1 ID
0.1 C A B
0.05 0.08 0.08 0.08 0.08 CSD95480RWJ SLPS670 –JUNE 2017 www.ti.com Product Folder Links: CSD95480RWJ Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated
9 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
9.1 Mechanical Drawing
- All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pads must be soldered to the printed circuit board for optimal thermal and mechanical performance.
.0000 .000 PKG 0 ( ) 2.4 ( ) 2 ( )1.75 ( )1.55 3X ( )0.875 ( ) 0.2 ( ) 0.4 3X ( )1.15 ( ) TYP2.22 ( ) TYP2.7 2X ( )2.11 ( ) 2.9 ( )2.25 ( )2.05 ( )1.275 ( ) 0.5 ( ) 0.3 ( ) 0.3 5X ( )1.15 5X ( ) 2 ( ) 2.6 ( ) TYP3.2 ( )0.025 ( ) 2.2 ( ) 0.8 ( ) 0.4 ( ) 0.1 ( ) 0.3 ( )2.25 16X (0.6) 16X (0.25) 14X (0.45) 3X ( ) 2 3X ( ) 1 2X ( ) 1 2X ( ) 2 ( )1.75 ( ) 1.3 ( ) TYP2.7 19X (0.45) ( )1.05 ( )2.025 ( )2.05 ( )2.175 ( ) TYP2.75 20X (0.25) ( ) TYP 2.225 ( ) TYP 2.225 (R0.05) TYP ( ) 0.9 (0.05) MIN TYP ( 0.2) VIA TYP LAND PATTERN EXAMPLE PKG METAL UNDER SOLDER MASK TYP SOLDER MASK OPENING, TYP 10 19 30 39 CSD95480RWJ www.ti.com SLPS670 –JUNE 2017 Product Folder Links: CSD95480RWJ Submit Documentation FeedbackCopyright © 2017, Texas Instruments Incorporated
9.2 Recommended PCB Land Pattern
- All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This package is designed to be soldered to thermal pads on the board. For more information, see QFN/SON PCB Attachment (SLUA271).
.000 PKG .000 PKG 0 29X (0.6) 29X (0.25) 24X (0.45) ( ) TYP2.4 ( ) 2 2X ( )1.665 2X ( )0.975 2X ( )0.775 2X ( )0.085 2X ( )0.42 2X ( )1.05 2X ( )1.25 2X ( ) 1.9 ( ) TYP2.4 4X ( )2.245 4X ( )1.375 4X ( )1.175 4X ( )0.305 3X ( )0.13 3X ( )1.05 3X ( )1.25 4X ( )2.17 ( ) 2.6 ( ) TYP3.2 ( ) TYP2.75 ( )0.375 ( )0.25 ( )0.025 ( ) 0.1 ( ) 0.4 ( )0.84 ( )1.05 2X ( ) 1.9 2X ( ) 1.1 2X ( ) 0.9 2X ( ) 0.1 2X ( ) 0.1 2X ( ) 0.9 ( ) 1.1 ( ) 1.9 10X (0.25) 9X (0.45) ( )2.025 (R0.05) TYP ( )1.75 ( ) 1.3 SOLDER PAST EXAMPLE BASED ON 0.125 mm THICK STENCIL PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE EXPOSED METAL METAL UNDER SOLDER MASK TYP SOLDER MASK OPENING TYP EXPOSED METAL EXPOSED METAL 1 30 39 CSD95480RWJ SLPS670 –JUNE 2017 www.ti.com Product Folder Links: CSD95480RWJ Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated
9.3 Recommended Stencil Opening
- All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations.
www.ti.com 6-Feb-2026 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) CSD95480RWJ NRND Production VQFN-CLIP (RWJ) | 41 2500 | LARGE T&R ROHS Exempt NIPDAU | SN Level-2-260C-1 YEAR -55 to 150 95480RWJ CSD95480RWJT NRND Production VQFN-CLIP (RWJ) | 41 250 | SMALL T&R ROHS Exempt NIPDAU | SN Level-2-260C-1 YEAR -55 to 150 95480RWJ (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1
PACKAGE MATERIALS INFORMATION www.ti.com 28-Mar-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant CSD95480RWJ VQFN- CLIP CSD95480RWJT VQFN- CLIP Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION www.ti.com 28-Mar-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CSD95480RWJ VQFN-CLIP RWJ 41 2500 346.0 346.0 33.0 CSD95480RWJT VQFN-CLIP RWJ 41 250 210.0 185.0 35.0 Pack Materials-Page 2
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