CS51313

CS51313 CHERRY

Document overview

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Technical content

Features

Regulator Controller for CPU V CORE I Dual N-Channel MOSFET Synchronous Buck Design I V2TM Control Topology I 200ns Transient Loop Response I 5-bit DAC with 1.2% Tolerance I Hiccup Mode Overcurrent Protection I 40ns Gate Rise and Fall Times (3.3nF load) I 65ns Adaptive FET Non-overlap Time I Adaptive Voltage Positioning I Power-Good Output Monitors Regulator Output I VCC Monitor Provides Under Voltage Lockout I OVP Output Monitors Regulator Output I Enable Through use of the COMP pin I +1.23V Reference Voltage Available Externally Package Options CS51313 Synchronous CPU Buck Controller Capable of Implementing Multiple Linear Regulators CS51313

Description

The CS51313 is a synchronous dual NFET Buck Regulator Controller. It is designed to power the core logic of the latest high performance CPUs. It uses the V 2TM control method to achieve the fastest possible transient response and best overall regulation. It incorporates many additional features required to ensure the proper operation and protec- tion of the CPU and Power system. The CS51313 provides the industry’s most highly integrated solution, minimizing external component count, total solution size, and cost. The CS51313 is specifically designed to power Intel’s Pentium ® II processor and includes the following features: 5-bit DAC with 1.2% tolerance, Power-Good output, overcurrent hiccup mode protec- tion, over voltage protection, V CC moni- tor, Soft Start, adaptive voltage position- ing and adaptive FET non-overlap time. A precision reference trimmed to 1% is also externally available for use by other regulators. The CS51313 will operate over an 8.4V to 14V range and is avail- able in 16 lead narrow body surface mount package. Application Diagram VOUT VID0 VID1 VID2 VID3 VREF VID4 VFB COMP COFF VCC PWRGD OVP GATE(L) GATE(H) Gnd

16 Lead SO Narrow

Pentium is a registered trademark of Intel Corporation. A Company ® V2 is a trademark of Switch Power, Inc. Rev. 3/11/99 Cherry Semiconductor Corporation

2000 South County Trail, East Greenwich, RI 02818

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PACKAGE PIN # PIN SYMBOL FUNCTION Absolute Maximum Ratings Pin Symbol Pin Name VMAX VMIN ISOURCE ISINK VREF Bandgap Reference Voltage 6V -0.3V 1mA 1mA VCC IC Power Input 16V -0.3V N/A 1.5A Peak 200mA DC COMP Compensation Pin 6V -0.3V 1mA 5mA V FB, VOUT, VID0-4 Voltage Feedback Input, Output 6V -0.3V 1mA 1mA Voltage Sense Pin, Voltage ID DAC Inputs C OFF Off-Time Pin 6V -0.3V 1mA 50mA GATE(H), GATE(L) High-Side, Low Side FET Drivers 16V -0.3V 1.5APeak 1.5A Peak 200mA DC 200mA DC PWRGD Power-Good Output 6V -0.3V 1mA 30mA OVP Overvoltage Protection 15V -0.3V 30mA 1mA Gnd Ground 0V 0V 1.5A Peak N/A 200mA DC CS51313 1,2,3,4,6 V IDO – VID4 Voltage ID DAC inputs. These pins are internally pulled up to 5.65V if left open. V ID4 selects the DAC range. When VID4 is high (logic one), the Error Amp reference range is 2.125V to 3.525V with 100mV increments. When V ID4 is low (logic zero), the Error amp reference voltage is 1.325V to 2.075V with 50mV increments. CC Input power supply pin for the internal circuitry. Decouple with filter capacitor to Gnd.

10 GATE(H) High side switch FET driver pin

11 Gnd Ground pin. 12 GATE(L) Low side synchronous FET driver pin. 14 PWRGD Power-Good Output. Open collector output drives low when V FB is out of regulation. 16 COMP Error amp output. PWM comparator inverting input. A capacitor to Gnd provides error amp compensation. 15 C OFF Off-Time Capacitor Pin. A capacitor from this pin to Gnd sets the off time for the regulator 8V OUT Current limit comparator inverting input. 7V FB Error amp inverting input, PWM comparator non-inverting input, current limit comparator non-inverting input, PWRGD and OVP comparator input. REF Bandgap Reference Voltage. It can be used to generate other regulated output voltages. 13 OVP Overvoltage protection pin. Goes high when overvoltage condition is detected on VFB. Lead Temperature Soldering

Electrical Characteristics: 0˚C < TA < 70˚C; 0˚C < TJ < 125˚C; 9V < VCC < 14V; 2.0V DAC Code (VID4 = VID3 =VID2 = VID1 = 0, VID0 = 1), CGATE(H) = CGATE(L) = 3.3nF, COFF = 390pF; Unless otherwise stated. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT CS51313 I Voltage Identification DAC Measure VFB = VCOMP, VCC = 12V (Note 2) 75°C ≤ TJ ≤ 125°C 25°C ≤ TJ ≤ 75°C VID4 VID3 VID2 VID1 VID0 MIN TYP MAX ± TOL MIN TYP MAX ± TOL UNIT I Error Amplifier COMP Source Current V COMP = 1.2V to 3.6V; VFB = 1.9 V 15 30 60 µA COMP Sink Current V COMP = 1.2V; VFB = 2.1V 30 60 120 µA Open Loop Gain C COMP = 0.1µF 80 dB Unity Gain Bandwidth C COMP = 0.1µF 50 kHz PSRR @ 1kHz C COMP = 0.1µF 70 dB Transconductance 3.2 mmho Output Impedance 0.5 M Ω

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT CS51313 Electrical Characteristics: 0˚C < TA < 70˚C; 0˚C < TJ < 125˚C; 9V < VCC < 14V; 2.0V DAC Code (VID4 = VID3 =VID2 = VID1 = 0, VID0 = 1), CGATE(H) = CGATE(L) = 3.3nF, COFF = 390pF; Unless otherwise stated. Line Regulation 9V ≤ VCC ≤ 14V 0.01 %/V Input Threshold V ID4, VID3, VID2, VID1, VID0 1.00 1.25 2.40 V Input Pull-up Resistance V ID4, VID3, VID2, VID1, VID0 25 50 100 k Ω Pull-up Voltage 5.48 5.65 5.82 V I Bandgap Reference Voltage VREF IVREF = 10µA sourcing,VCC = 12V 1.211 1.230 1.248 V I GATE(H) and GATE(L) High Voltage at 100mA Measure V CC –GATE(L)/(H) 1.2 2.1 V Low Voltage at 100mA Measure GATE(L)/H 1.0 1.5 V Rise Time 1.6V < GATE(H)/(L) < (V CC – 2.5V) 40 80 ns Fall Time (V CC – 2.5V) > GATE(L)/(H) > 1.6V 40 80 ns GATE(H) to GATE(L) Delay GATE(H)<2V, GATE(L)>2V 30 65 110 ns VCC = 12V GATE(L) to GATE(H) Delay GATE(L)<2V, GATE(H)>2V 30 65 110 ns VCC = 12V GATE pull-down Resistance to Gnd (Note 3) 20 50 115 k Ω I Overcurrent Protection OVC Comparator Offset Voltage 0V ≤ VOUT ≤ 3.5V 77 86 101 mV Discharge Threshold Voltage 0.2 0.25 0.3 V OVC Latch Discharge Current V COMP = 1V 100 800 2500 µA I PWM Comparator PWM Comparator Offset Voltage 0V ≤ VFB ≤ 3.5V 0.99 1.10 1.23 V Transient Response V FB = 0 to 3.5V 200 300 ns I COFF Off-Time 1.0 1.6 2.3 µs Charge Current V COFF = 1.5V 550 µA Discharge Current V COFF = 1.5V 25 mA I Power-Good Output PWRGD Sink Current V FB = 1.7V, VPWRGD = 1V 0.5 4 15 mA PWRGD Upper Threshold % of nominal DAC code 5 8.5 12 % PWRGD Lower Threshold % of nominal DAC code -12 -8.5 -5 % PWRGD Output Low Voltage V FB = 1.7V, IPWRGD = 500uA 0.2 0.3 V I Overvoltage Protection (OVP) Output OVP Source Current OVP = 1V 1 10 25 mA OVP Threshold % of nominal DAC code 5 8.5 12 % OVP Pull-up Voltage I OVP = 1mA, VCC - VOVP 1.1 1.5 V

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT I General Electrical Specifications VCC Monitor Start Threshold 7.9 8.4 8.9 V VCC Monitor Stop Threshold 7.6 8.1 8.6 V Hysteresis Start - Stop 0.15 0.30 0.60 V VCC Supply Current No Load on GATE(H), GATE(L) 12 20 mA CS51313 Note 1: All pins are rated 2kV except for the VREF pin (Pin 5) which is typically rated at 800V. Note 2: The IC power dissipation in a typical application with VCC = 12V, switching frequency fSW = 250kHz, 50nc MOSFETs and RθJA = 115°C/W yields an operating junction temperature rise of approximately 52°C, and a junction tem- perature of 77°C with an ambient temperature of 25°C. Note 3: Guaranteed by design, not 100% tested in production. Electrical Characteristics: 0˚C < TA < 70˚C; 0˚C < TJ < 125˚C; 9V < VCC < 14V; 2.0V DAC Code (VID4 = VID3 =VID2 = VID1 = 0, VID0 = 1), CGATE(H) = CGATE(L) = 3.3nF, COFF = 390pF; Unless otherwise stated. VFB COMP COFF OFF TIME PWM COMP DISCHARGE COMP VOUT VREF VID0 VID1 VID2 VID3 VID4 DAC BANDGAP REFERENCE 1.10V EA CURRENT LIMIT 86mV 0.25V FAULT LATCH R S Q VCC OVP PWRGD Gnd GATE(L) GATE(H) VCCUVLO NONOVERLAP LOGIC Block Diagram

control method is illustrated in Figure 6. The out- put voltage is used to generate both the error signal and the ramp signal. Since the ramp signal is simply the output voltage, it is affected by any change in the output regard- less of the origin of that change. The ramp signal also con- tains the DC portion of the output voltage, which allows the control circuit to drive the main switch to 0% or 100% duty cycle as required. A change in line voltage changes the current ramp in the inductor, affecting the ramp signal, which causes the V 2TM control scheme to compensate the duty cycle. Since the change in inductor current modifies the ramp signal, as in current mode control, the V 2TM control scheme has the same advantages in line transient response. A change in load current will have an affect on the output voltage, altering the ramp signal. A load step immediately changes the state of the comparator output, which controls the main switch. Load transient response is determined only by the comparator response time and the transition speed of the main switch. The reaction time to an output load step has no relation to the crossover frequency of the error signal loop, as in traditional control methods. The error signal loop can have a low crossover frequency, since transient response is handled by the ramp signal loop. The main purpose of this ‘slow’ feedback loop is to provide DC accuracy. Noise immunity is significantly improved, since the error amplifier bandwidth can be rolled off at a low frequency. Enhanced noise immunity improves remote sensing of the output voltage, since the noise associated with long feedback traces can be effective- ly filtered. Line and load regulation are drastically improved because there are two independent voltage loops. A voltage mode controller relies on a change in the error signal to compen- sate for a deviation in either line or load voltage. This change in the error signal causes the output voltage to change corresponding to the gain of the error amplifier, which is normally specified as line and load regulation. A current mode controller maintains fixed error signal under deviation in the line voltage, since the slope of the ramp signal changes, but still relies on a change in the error signal for a deviation in load. The V 2TM method of control maintains a fixed error signal for both line and load varia- tion, since the ramp signal is affected by both line and load. Constant Off-Time To minimize transient response, the CS51313 uses a Constant Off-Time method to control the rate of output pulses. During normal operation, the Off-Time of the high side switch is terminated after a fixed period, set by the C OFF capacitor. Every time the VFB pin exceeds the COMP pin voltage an Off-Time is initiated. To maintain regula- tion, the V 2TM Control Loop varies switch On-Time. The PWM comparator monitors the output voltage ramp, and terminates the switch On-Time. Constant Off-Time provides a number of advantages. Switch duty Cycle can be adjusted from 0 to 100% on a pulse-by pulse basis when responding to transient condi- tions. Both 0% and 100% Duty Cycle operation can be maintained for extended periods of time in response to Load or Line transients. Programmable Output The CS51313 is designed to provide two methods for pro- gramming the output voltage of the power supply. A five bit on board digital to analog converter (DAC) is used to program the output voltage within two different ranges. The first range is 2.125V to 3.525V in 100mV steps, the sec- ond is 1.325V to 2.075V in 50mV steps, depending on the digital input code. If all five bits are left open, the CS51313 enters adjust mode. In adjust mode, the designer can choose any output voltage by using resistor divider feed- back to the V FB pin, as in traditional controllers. The CS51313 is specifically designed to meet or exceed Intel’s Pentium ® II specifications. Error Amplifier An inherent benefit of the V2TM control topology is that there is no large bandwidth requirement on the error amplifier design. The reaction time to an output load step has no relation to the crossover frequency, since transient response is handled by the ramp signal loop. The main purpose of this”slow”feedback loop is to provide DC accu- racy. Noise immunity is significantly improved, since the error amplifier bandwidth can be rolled off at a low fre- quency. Enhanced noise immunity improves remote sens- ing of the output voltage, since the noise associated with long feedback traces can be effectively filtered. The COMP pin is the output of the error amplifier and a capacitor to Gnd compensates the error amplifier loop. Additionally, through the built-in offset on the PWM Comparator non- inverting input, the COMP pin provides the hiccup timing for the Overcurrent Protection, the Soft Start function that minimizes inrush currents during regulator power-up and switcher output enable. Reference Voltage The CS51313 has a precision reference trimmed to 1.5% over temperature, which is externally available for use by other power supplies on the motherboard. For instance, the V REF pin can be used to configure an LDO controller that drives either a MOSFET or a bipolar transistor. The com- pensation criteria on this LDO controller is set by the dynamic performance requirement on the overall power supply. The following circuit demonstrates the typical con- nections required to implement an LDO controller using the CS51313 V REF pin. Figure 7: VREF used in an N-FET LDO regulator. The applications diagram shows a pair of linear regulators for V GTL and VCLOCK. The 1.23V VREF of the CS51313 is used as the reference for both regulators. The feedback External N-FET +3.3V CIN VREF 100K 0.5% 21.9K 0.5% CO +1.5V +12V Application Information: continued CS51313

Application Information: continued The CPU VCC(CORE) tolerance can be affected by any or all of the following reasons: 1) buck regulator output voltage setpoint accuracy; 2) output voltage change due to discharging or charging of the bulk decoupling capacitors during a load current tran- sient; 3) output voltage change due to the ESR and ESL of the bulk and high frequency decoupling capacitors, circuit traces, and vias; 4) output voltage ripple and noise. Budgeting the tolerance is left up to the designer who must take into account all of the above effects and provide a V CC(CORE) that will meet the specified tolerance at the CPU’s inputs. The designer must also ensure that the regulator compo- nent junction temperatures are kept within the manufac- turer’s specified ratings at full load and maximum ambient temperature. As computer motherboards become increas- ingly complex, regulator size also becomes important, as there is less space available for the CPU power supply. Step 2: Selection of the Output Capacitors These components must be selected and placed carefully to yield optimal results. Capacitors should be chosen to pro- vide acceptable ripple on the regulator output voltage. Key specifications for output capacitors are their ESR (Equivalent Series Resistance), and ESL (Equivalent Series Inductance). For best transient response, a combination of low value/high frequency and bulk capacitors placed close to the load will be required. In order to determine the number of output capacitors the maximum voltage transient allowed during load transi- tions has to be specified. The output capacitors must hold the output voltage within these limits since the inductor current can not change with the required slew rate. The output capacitors must therefore have a very low ESL and ESR. The voltage change during the load current transient is: OUT = ∆IOUT × ( + ESR + ), where ∆IOUT / ∆t = load current slew rate; ∆IOUT = load transient; ∆t = load transient duration time; ESL = Maximum allowable ESL including capacitors, circuit traces, and vias; ESR = Maximum allowable ESR including capacitors and circuit traces; t TR = output voltage transient response time. The designer has to independently assign values for the change in output voltage due to ESR, ESL, and output capacitor discharging or charging. Empirical data indicates that most of the output voltage change (droop or spike depending on the load current transition) results from the total output capacitor ESR. The maximum allowable ESR can then be determined according to the formula ESR MAX = , where ∆VESR = change in output voltage due to ESR (assigned by the designer). Once the maximum allowable ESR is determined, the number of output capacitors can be found by using the for- mula Number of capacitors = where ESRCAP = maximum ESR per capacitor (specified in manufacturer’s data sheet); ESR MAX = maximum allowable ESR. The actual output voltage deviation due to ESR can then be verified and compared to the value assigned by the design- er: ESR = ∆IOUT × ESRMAX Similarly, the maximum allowable ESL is calculated from the following formula: ESLMAX = , where ∆I/∆T = load current slew rate (as high as 20A/µs); ∆VESL = change in output voltage due to ESL. The actual maximum allowable ESL can be determined by using the equation: ESLMAX = , where ESLCAP = maximum ESL per capacitor (it is estimat- ed that a 10 × 12mm Aluminum Electrolytic capacitor has approximately 4nH of package inductance). The actual output voltage deviation due to the actual maxi- mum ESL can then be verified: ∆VESL = . The designer now must determine the change in output voltage due to output capacitor discharge during the tran- sient: CAP = , where ∆tTR = the output voltage transient response time (assigned by the designer); CAP = output voltage deviation due to output capaci- tor discharge; ∆I = Load step. ∆I × ∆tTR COUT ESLMAX × ∆I ESLCAP Number of output capacitors ∆VESL × ∆t ESRCAP ESRMAX ∆VESR ∆IOUT tTR COUT ESL CS51313

The total change in output voltage as a result of a load cur- rent transient can be verified by the following formula: ∆VOUT = ∆VESR + ∆VESL + ∆VCAP Step 3: Selection of the Duty Cycle, Switching Frequency, Switch On-Time (TON) and Switch Off-Time (TOFF) The duty cycle of a buck converter (including parasitic losses) is given by the formula: Duty Cycle = D = , where VOUT = buck regulator output voltage; VHFET = high side FET voltage drop due to RDS(ON); VL = output inductor voltage drop due to inductor wire DC resistance; V DROOP = droop (current sense) resistor voltage drop; VIN = buck regulator input voltage; VLFET = low side FET voltage drop due to RDS(ON). Step3a: Calculation of Switch On-Time The switch On-Time (time during which the switching MOSFET in a synchronous buck topology is conducting) is determined by: T ON = , where FSW = regulator switching frequency selected by the designer. Higher operating frequencies allow the use of smaller inductor and capacitor values. Nevertheless, it is common to select lower frequency operation because a higher fre- quency results in lower efficiency due to MOSFET gate charge losses. Additionally, the use of smaller inductors at higher frequencies results in higher ripple current, higher output voltage ripple, and lower efficiency at light load currents. Step 3b: Calculation of Switch Off-Time The switch Off-Time (time during which the switching MOSFET is not conducting) can be determined by: T OFF = − TON, The COFF capacitor value has to be selected in order to set the Off-Time, TOFF, above: COFF = , where 3980 is a characteristic factor of the CS51313; D = Duty Cycle. Step 4: Selection of the Output Inductor The inductor should be selected based on its inductance, current capability, and DC resistance. Increasing the induc- tor value will decrease output voltage ripple, but degrade transient response. There are many factors to consider in selecting the inductor including cost, efficiency, EMI and ease of manufacture. The inductor must be able to handle the peak current at the switching frequency without satu- rating, and the copper resistance in the winding should be kept as low as possible to minimize resistive power loss. There are a variety of materials and types of magnetic cores that could be used for this application. Among them are ferrites, molypermalloy cores (MPP), amorphous and powdered iron cores. Powdered iron cores are very com- monly used. Powdered iron cores are very suitable due to their high saturation flux density and have low loss at high frequencies, a distributed gap and exhibit very low EMI. The inductor value can be determined by: L = , where V IN = input voltage; VOUT = output voltage; tTR = output voltage transient response time (assigned by the designer); ∆I = load transient. The inductor ripple current can then be determined: L = , where ∆IL = inductor ripple current; VOUT = output voltage; TOFF = switch Off-Time; L = inductor value. The designer can now verify if the number of output capacitors from step 2 will provide an acceptable output voltage ripple (1% of output voltage is common). The for- mula below is used: L = , Rearranging we have: ESRMAX = , where ESRMAX = maximum allowable ESR; ∆VOUT = 1% × VOUT = maximum allowable output volt- age ripple ( budgeted by the designer ); L = inductor ripple current; VOUT = output voltage. The number of output capacitors is determined by: Number of capacitors = , where ESRCAP = maximum ESR per capacitor (specified in manufacturer’s data sheet). ESRCAP ESRMAX ∆VOUT ∆IL ∆VOUT ESRMAX VOUT × TOFF L (VIN − VOUT) × tTR Period × (1 − D) 3980 FSW Duty Cycle FSW VOUT + (VHFET + VL + VDROOP) VIN + VLFET − VHFET − VL Application Information: continued CS51313

The designer must also verify that the inductor value yields reasonable inductor peak and valley currents (the inductor current is a triangular waveform): I L(PEAK) = IOUT + , where IL(PEAK) = inductor peak current; IOUT = load current; ∆IL = inductor ripple current. IL(VALLEY) = IOUT − , where IL(VALLEY) = inductor valley current. Given the requirements of an application such as a buck converter, it is found that a toroid powdered iron core is quite suitable due to its low cost, low core losses at the switching frequency, and low EMI. Step 5: Selection of the Input Capacitors These components must be selected and placed carefully to yield optimal results. Capacitors should be chosen to pro- vide acceptable ripple on the input supply lines. A key specification for input capacitors is their ripple current rat- ing. The input capacitor should also be able to handle the input RMS current I IN(RMS). The combination of the input capacitors CIN discharges during the on-time. The input capacitor discharge current is given by: ICINDIS(RMS) = where ICINDIS(RMS) = input capacitor discharge current; IL(PEAK) = inductor peak current; IL(VALLEY) = inductor valley current. CIN charges during the off-time, the average current through the capacitor over one switching cycle is zero: ICIN(CH) = ICIN(DIS) × , where ICIN(CH) = input capacitor charge current; ICIN(DIS) = input capacitor discharge current; D = Duty Cycle. The total Input RMS current is: ICIN(RMS) = (ICIN(DIS)2 × D) + (ICIN(CH)2 × (1 − D)) The number of input capacitors required is then deter- mined by: NCIN = , where NCIN = number of input capacitors; ICIN(RMS) = total input RMS current; IRIPPLE = input capacitor ripple current rating (specified in manufacturer’s data sheets). The total input capacitor ESR needs to be determined in order to calculate the power dissipation of the input capac- itors: ESR CIN = , where ESRCIN = total input capacitor ESR; ESRCAP = maximum ESR per capacitor (specified in manufacturer’s data sheets); N CIN = number of input capacitors. Once the total ESR of the input capacitors is known, the input capacitor ripple voltage can be determined using the formula: V CIN(RMS) = ICIN(RMS) × ESRCIN, where VCIN(RMS) = input capacitor RMS voltage; ICIN(RMS) = total input RMS current; ESRCIN = total input capacitor ESR. The designer must determine the input capacitor power loss in order to ensure there isn’t excessive power dissipa- tion through these components. The following formula is used: P CIN(RMS) = ICIN(RMS)2 × ESRCIN where PCIN(RMS) = input capacitor RMS power dissipation; ICIN(RMS) = total input RMS current; ESRCIN = total input capacitor ESR. Step 6: Selection of the Input Inductor A CPU switching regulator, such as the one in a buck topology, must not disturb the primary +5V supply. One method of achieving this is by using an input inductor and a bypass capacitor. The input inductor isolates the +5V supply from the noise generated in the switching portion of the microprocessor buck regulator and also limits the inrush current into the input capacitors upon power up. The inductor’s limiting effect on the input current slew rate becomes increasingly beneficial during load transients. The worst case is when the CPU load changes from no load to full load (load step), a condition under which the highest voltage change across the input capacitors is also seen by the input inductor. The inductor successfully blocks the ripple current while placing the transient current require- ments on the input bypass capacitor bank, which has to initially support the sudden load change. The minimum inductance value for the input inductor is therefore: ESRCAP NCIN ICIN(RMS) IRIPPLE D 1 − D (IL(PEAK)2 + (IL(PEAK) × IL(VALLEY)) + IL(VALLEY)2 × D ∆IL ∆IL Application Information: continued CS51313

LIN = , where LIN = input inductor value; ∆V = voltage seen by the input inductor during a full load swing; (dI/dt) MAX = maximum allowable input current slew rate (0.1A/µs for a Pentium® II power supply). The designer must select the LC filter pole frequency so that at least 40dB attenuation is obtained at the regulator switching frequency. The LC filter is a double-pole net- work with a slope of −2, a roll-off rate of –40dB/dec, and a corner frequency: f C = , where L = input inductor; C = input capacitor(s). Step 7: Selection of the Switching FET FET Basics The use of the MOSFET as a power switch is propelled by two reasons: 1) Its very high input impedance; and 2) Its very fast switching times. The electrical characteristics of a MOS- FET are considered to be those of a perfect switch. Control and drive circuitry power is therefore reduced. Because the input impedance is so high, it is voltage driven. The input of the MOSFET acts as if it were a small capacitor, which the driving circuit must charge at turn on. The lower the drive impedance, the higher the rate of rise of V GS, and the faster the turn- on time. Power dissipation in the switching MOSFET consists of 1) conduction losses, 2) leakage losses, 3) turn-on switching losses, 4) turn-off switching losses, and 5) gate-transitions losses. The latter three losses are proportional to frequency. For the conducting power dissi- pation rms values of current and resistance are used for true power calculations. The fast switching speed of the MOSFET makes it indispensable for high-frequency power supply applications. Not only are switching power losses minimized, but also the maximum usable switching fre- quency is considerably higher. Switching time is indepen- dent of temperature. Also, at higher frequencies, the use of smaller and lighter components (transformer, filter choke, filter capacitor) reduces overall component cost while using less space for more efficient packaging at lower weight. The MOSFET has purely capacitive input impedance. No DC current is required. It is important to keep in mind the drain current of the FET has a negative temperature coeffi- cient. Increase in temperature causes higher on-resistance and greater leakage current. For switching circuits, V DS(ON) should be low to minimize power dissipation at a given ID, and VGS should be high to accomplish this. MOSFET switching times are determined by device capacitance, stray capacitance, and the impedance of the gate drive cir- cuit. Thus the gate driving circuit must have high momen- tary peak current sourcing and sinking capability for switching the MOSFET. The input capacitance, output capacitance and reverse-transfer capacitance also increase with increased device current rating. Two considerations complicate the task of estimating switching times. First, since the magnitude of the input capacitance, C ISS, varies with VDS, the RC time constant determined by the gate-drive impedance and CISS changes during the switching cycle. Consequently, computation of the rise time of the gate voltage by using a specific gate- drive impedance and input capacitance yields only a rough estimate. The second consideration is the effect of the “Miller” capacitance, C RSS, which is referred to as CDG in the following discussion. For example, when a device is on, V DS(ON) is fairly small and VGS is about 12V. CDG is charged to VDS(ON) − VGS, which is a negative potential if the drain is considered the positive electrode. When the drain is “off”, C DG is charged to quite a different potential. In this case the voltage across CDG is a positive value since the potential from gate-to-source is near zero volts and VDS is essentially the drain supply voltage. During turn-on and turn-off, these large swings in gate-to-drain voltage tax the current sourcing and sinking capabilities of the gate drive. In addition to charging and discharging C GS, the gate drive must also supply the displacement current required by C DG(IGATE = Cdg dVdg/dt). Unless the gate-drive impedance is very low, the VGS waveform commonly plateaus during rapid changes in the drain-to-source volt- age. The most important aspect of FET performance is the Static Drain-To-Source On-Resistance (R DS(ON)), which effects regulator efficiency and FET thermal management require- ments. The On-Resistance determines the amount of cur- rent a FET can handle without excessive power dissipation that may cause overheating and potentially catastrophic failure. As the drain current rises, especially above the con- tinuous rating, the On-Resistance also increases. Its posi- tive temperature coefficient is between +0.6%/C and +0.85%/C. The higher the On-Resistance the larger the conduction loss is. Additionally, the FET gate charge should be low in order to minimize switching losses and reduce power dissipation. Both logic level and standard FETs can be used. The refer- ence designs derive gate drive from the 12V supply, which is generally available in most computer systems and uti- lizes logic level FETs. Voltage applied to the FET gates depends on the applica- tion circuit used. Both upper and lower gate driver outputs are specified to drive to within 1.5V of ground when in the low state and to within 2V of their respective bias supplies when in the high state. In practice, the FET gates will be driven rail-to-rail due to overshoot caused by the capaci- tive load they present to the controller IC. Step 7a - Selection of the switching (upper) FET The designer must ensure that the total power dissipation in the FET switch does not cause the power component’s junction temperature to exceed 150°C. The maximum RMS current through the switch can be determined by the following formula: I RMS(H) = ,(IL(PEAK)2 + (IL(PEAK) × IL(VALLEY)) + IL(VALLEY)2 × D 2π LC (dI/dt)MAX Application Information: continued CS51313

IRMS(H) = maximum switching MOSFET RMS current; IL(PEAK) = inductor peak current; IL(VALLEY) = inductor valley current; D = Duty Cycle. Once the RMS current through the switch is known, the switching MOSFET conduction losses can be calculated: PRMS(H) = IRMS(H)2 × RDS(ON) where PRMS(H) = switching MOSFET conduction losses; IRMS(H) = maximum switching MOSFET RMS current; RDS(ON) = FET drain-to-source on-resistance The upper MOSFET switching losses are caused during MOSFET switch-on and switch-off and can be determined by using the following formula: P SWH = PSWH(ON) + PSWH(OFF) = , where PSWH(ON) = upper MOSFET switch-on losses; PSWH(OFF) = upper MOSFET switch-off losses; VIN = input voltage; IOUT = load current; tRISE = MOSFET rise time (from FET manufacturer’s switching characteristics performance curve); t FALL = MOSFET fall time (from FET manufacturer’s switching characteristics performance curve); T = 1/F SW = period. The total power dissipation in the switching MOSFET can then be calculated as: PHFET(TOTAL) = PRMSH + PSWH(ON) + PSWH(OFF), where PHFET(TOTAL) = total switching (upper) MOSFET losses; PRMSH = upper MOSFET switch conduction Losses; PSWH(ON) = upper MOSFET switch-on losses; PSWH(OFF) = upper MOSFET switch-off losses. Once the total power dissipation in the switching FET is known, the maximum FET switch junction temperature can be calculated: T J = TA + [PHFET(TOTAL) × RθJA], where TJ = FET junction temperature; TA = ambient temperature; PHFET(TOTAL) = total switching (upper) FET losses; RθJA = upper FET junction-to-ambient thermal resistance Step 7b: Selection of the synchronous (lower) FET The switch conduction losses for the lower FET can be cal- culated as follows: P RMSL = IRMS2 × RDS(ON) = [IOUT × (1 − D)]2 × RDS(ON), where PRMSL = lower MOSFET conduction losses; IOUT = load current; D = Duty Cycle; R DS(ON) = lower FET drain-to-source on-resistance. The synchronous MOSFET has no switching losses, except for losses in the internal body diode, because it turns on into near zero voltage conditions. The MOSFET body diode will conduct during the non-overlap time and the resulting power dissipation (neglecting reverse recovery losses) can be calculated as follows: P SWL = VSD × ILOAD × non-overlap time × FSW, where PSWL = lower FET switching losses; VSD = lower FET source-to-drain voltage; ILOAD = load current Non-overlap time = GATE(L)-to-GATE(H) or GATE(H)- to-GATE(L) delay (from CS51313 data sheet Electrical Characteristics section); F SW = switching frequency. The total power dissipation in the synchronous (lower) MOSFET can then be calculated as: PLFET(TOTAL) = PRMSL + PSWL, where PLFET(TOTAL) = Synchronous (lower) FET total losses; PRMSL = Switch Conduction Losses; PSWL = Switching losses. Once the total power dissipation in the synchronous FET is known the maximum FET switch junction temperature can be calculated: T J = TA + [PLFET(TOTAL) × RθJA], where TJ = MOSFET junction temperature; TA = ambient temperature; PLFET(TOTAL) = total synchronous (lower) FET losses; RθJA = lower FET junction-to-ambient thermal resistance. Step 8: Control IC Power Dissipation The power dissipation of the IC varies with the MOSFETs used, V CC, and the CS51313 operating frequency. The aver- age MOSFET gate charge current typically dominates the control IC power dissipation. The IC power dissipation is determined by the formula: P CONTROLIC = ICCVCC + PGATE(H) + PGATE(L), where PCONTROLIC = control IC power dissipation; ICC = IC quiescent supply current; VCC = IC supply voltage; PGATE(H) = upper MOSFET gate driver (IC) losses; PGATE(L) = lower MOSFET gate driver (IC) losses. The upper (switching) MOSFET gate driver (IC) losses are: PGATE(H) = QGATE(H) × FSW × VGATE(H), VIN × IOUT × (tRISE + tFALL) Application Information: continued CS51313

PGATE(H) = upper MOSFET gate driver (IC) losses; QGATE(H) = total upper MOSFET gate charge; FSW = switching frequency; VGATE(H) = upper MOSFET gate voltage. The lower (synchronous) MOSFET gate driver (IC) losses are: PGATE(L) = QGATE(L) × FSW × VGATE(L), where PGATE(L) = lower MOSFET gate driver (IC) losses; QGATE(L) = total lower MOSFET gate charge; FSW = switching frequency; VGATE(L) = lower MOSFET gate voltage. The junction temperature of the control IC is primarily a function of the PCB layout, since most of the heat is removed through the traces connected to the pins of the IC. Step 9: Slope Compensation Voltage regulators for today’s advanced processors are expected to meet very stringent load transient require- ments. One of the key factors in achieving tight dynamic voltage regulation is low ESR at the CPU input supply pins. Low ESR at the regulator output results in low out- put voltage ripple. The consequence is, however, that there’s very little voltage ramp at the control IC feedback pin (V FB) and regulator sensitivity to noise and loop insta- bility are two undesirable effects that can surface. The per- formance of the CS51313-based CPU V CC(CORE) regulator is improved when a fixed amount of slope compensation is added to the output of the PWM Error Amplifier (COMP pin) during the regulator Off-Time. Referring to Figure 12, the amount of voltage ramp at the COMP pin is dependent on the gate voltage of the lower (synchronous) FET and the value of resistor divider formed by R1and R2. V SLOPECOMP = VGATE(L) × ( ) × (1 − e) , where VSLOPECOMP = amount of slope added; VGATE(L) = lower MOSFET gate voltage; R1, R2 = voltage divider resistors; t = t OFF (switch off-time); τ = RC constant determined by C1 and the parallel com- bination of R1, R2 (Figure 12), neglecting the low driver output impedance The artificial voltage ramp created by the slope compensa- tion scheme results in improved control loop stability pro- vided that the RC filter time constant is smaller than the off-time cycle duration (time during which the lower MOS- FET is conducting). Step 10: Selection of Current Limit Filter Components The current limit filter is implemented by a 0.1µF ceramic capacitor across and two 510Ω resistors in series with the V FB and VOUT current limit comparator input pins. They provide a time constant τ = RC = 100µs, which enables the circuit to filter out noise and be immune to false triggering, caused by sudden and fast load changes. These load tran- sients can have slew rates as high as 20A/µs. Adaptive voltage positioning is used to help keep the out- put voltage within specification during load transients. To implement adaptive voltage positioning a “Droop Resistor” must be connected between the output inductor and output capacitors and load. This resistor carries the full load current and should be chosen so that both DC and AC tolerance limits are met. An embedded PC trace resis- tor has the distinct advantage of near zero cost implemen- tation. However, this droop resistor can vary due to three reasons: 1) the sheet resistivity variation caused by varia- tion in the thickness of the PCB layer; 2) the mismatch of L/W; and 3) temperature variation. 1) Sheet Resistivity For one ounce copper, the thickness variation is typically 1.26 mil to 1.48 mil. Therefore the error due to sheet resis- tivity is: = ±8%. 2) Mismatch due to L/W The variation in L/W is governed by variations due to the PCB manufacturing process. The error due to L/W mis- match is typically 1%. 3) Thermal Considerations Due to I 2 × R power losses the surface temperature of the droop resistor will increase causing the resistance to increase. Also, the ambient temperature variation will con- tribute to the increase of the resistance, according to the formula: R = R 20 [1+ α20(Τ−20)], where R20 = resistance at 20˚C; α =; T= operating temperature; R = desired droop resistor value. For temperature T = 50˚C, the % R change = 12%. Droop Resistor Tolerance Tolerance due to sheet resistivity variation ±8% Tolerance due to L/W error 1% Tolerance due to temperature variation 12% Total tolerance for droop resistor 21% In order to determine the droop resistor value the nominal voltage drop across it at full load has to be calculated. This voltage drop has to be such that the output voltage at full load is above the minimum DC tolerance spec: 0.00393 1.48 - 1.26 1.37 “Droop” Resistor for Adaptive Voltage Positioning and Current Limit -tτR2 R1 + R2 Application Information: continued CS51313

VDROOP(TYP) = . Example: for a 450MHz Pentium®II, the DC accuracy spec is 1.93 < VCC(CORE) < 2.07V, and the AC accuracy spec is 1.9V < VCC(CORE) < 2.1V. The CS51313 DAC output voltage is +2.001V < VDAC < +2.049V. In order not to exceed the DC accuracy spec, the voltage drop developed across the resistor must be calculated as follows: V DROOP(TYP) = = = 71mV. With the CS51313 DAC accuracy being 1%, the internal error amplifier’s reference voltage is trimmed so that the output voltage will be 25mV high at no load. With no load, there is no DC drop across the resistor, producing an out- put voltage tracking the error amplifier output voltage, including the offset. When the full load current is deliv- ered, a drop of -50mV is developed across the resistor. Therefore, the regulator output is pre-positioned at 25mV above the nominal output voltage before a load turn-on. The total voltage drop due to a load step is ∆V-25mV and the deviation from the nominal output voltage is 25mV smaller than it would be if there was no droop resistor. Similarly at full load the regulator output is pre-positioned at 25mV below the nominal voltage before a load turn-off. the total voltage increase due to a load turn-off is ∆V-25mV and the deviation from the nominal output voltage is 25mV smaller than it would be if there was no droop resis- tor. This is because the output capacitors are pre-charged to a value that is either 25mV above the nominal output voltage before a load turn-on or, 25mV below the nominal output voltage before a load turn-off . Obviously, the larger the voltage drop across the droop resistor (the larger the resistance), the worse the DC and load regulation, but the better the AC transient response. Current Limit The current limit setpoint has to be higher than the normal full load current. Attention has to be paid to the current rating of the external power components as these are the first to fail during an overload condition. The MOSFET continuous and pulsed drain current rating at a given case temperature has to be accounted for when setting the cur- rent limit trip point. Temperature curves on MOSFET manufacturers’ data sheets allow the designer to determine the MOSFET drain current at a particular V GS and TJ (junction temperature). This, in turn, will assist the designer to set a proper current limit, without causing device breakdown during an over- load condition. Let’s assume the full CPU load is 16A. The internal current sense comparator current limit voltage limits are: 77mV < V TH < 101mV. Also, there is a 21% total variation in RSENSE as discussed in the previous section. We compute the value of the current sensing element (embedded PCB trace) for the minimum current limit set- point: RSENSE(MIN) = RSENSE(TYP) × 0.79, RSENSE(MAX) = RSENSE(TYP) × 1.21, RSENSE(MAX) = = = 4.8mΩ. We select, RSENSE(TYP) = 3.3mΩ. We calculate the range of load currents that will cause the internal current sense comparator to detect an overload condition. Nominal Current Limit Setpoint From the overcurrent detection data in the electrical char- acteristics table: V TH(TYP) = 86mV, ICL(NOM) = = = 26A. Maximum Current Limit Setpoint From the overcurrent detection data in the electrical char- acteristics table: VTH(MAX) = 101mV, ICL(MAX)== = = 38.7A. Therefore, the range of load currents that will cause the internal current sense comparator to detect an overload condition through a 3.3mΩ embedded PCB trace is: 19.3A < I CL < 38.7A, with 26A being the nominal overload condition. Design Rules for Using a Droop Resistor The basic equation for laying an embedded resistor is: RAR = ρ × or R = ρ × , where A= W × t = cross-sectional area; ρ= the copper resistivity (µΩ-mil); L= length (mils); W = width (mils); t = thickness (mils). L (W × t) L A 101mV 3.3mΩ × 0.79 VTH(MAX) RSENSE(NOM) × 0.79 VTH(MAX) RSENSE(MIN) 86mV 3.3mΩ VTH(TYP) RSENSE(NOM) 77mV 16A VTH(MIN) ICL(MIN) +2.001V-1.93V 1.21 [VDAC(MIN)-VDC (MIN)] 1+RDROOP(TOLERANCE) VDAC(MIN)-VDC(MIN) 1+RDROOP(TOLERANCE) Application Information :continued CS51313

For most PCBs the copper thickness, t, is 35µm (1.37 mils) for one ounce copper; ρ = 717.86µΩ-mil. For a CPU load of 16A the resistance needed to create a 50mV drop at full load is: RDROOP = = = 3.1m Ω. The resistivity of the copper will drift with the temperature according to the following guidelines: Droop Resistor Length, Width, and Thickness The minimum width and thickness of the droop resistor should primarily be determined on the basis of the current- carrying capacity required, and the maximum permissible droop resistor temperature rise. PCB manufacturer design charts can be used in determining current- carrying capaci- ty and sizes of etched copper conductors for various tem- perature rises above ambient. For single conductor applications, such as the use of the droop resistor, PCB design charts show that for a droop resistor with a required current-carrying capacity of 16A, and a 45˚C temperature rise above ambient, the recom- mended cross section is 275 mil W × t = 275 mil2, where W = droop resistor width; t = droop resistor thickness. For 1oz. copper, t= 1.37 mils, therefore W = 201 mils = 0.201 in. R = ρ × , where R = droop resistor value; ρ = 0.71786mΩ-mil (1 oz. copper); L = droop resistor length; W = droop resistor width. R DROOP = 3.3mΩ. 3.3mΩ = 0.71786mΩ-mil × . Hence, L = 1265 mils = 1.265 in. In layouts where it is impractical to lay out a droop resistor in a straight line 1265 mils long, the embedded PCB trace can be “snaked” to fit within the available space. Thermal Considerations for Power MOSFETs In order to maintain good reliability, the junction tempera- ture of the semiconductor components should be kept to a maximum of 150°C or lower. The thermal impedance (junction to ambient) required to meet this requirement can be calculated as follows: Thermal Impedance = A heatsink may be added to TO-220 components to reduce their thermal impedance. A number of PC board layout techniques such as thermal vias and additional copper foil area can be used to improve the power handling capability of surface mount components. As a consequence of large currents being turned on and off at high frequency, switching regulators generate noise as a consequence of their normal operation. When designing for compliance with EMI/EMC regulations, additional components may be added to reduce noise emissions. These components are not required for regulator operation and experimental results may allow them to be eliminated. The input filter inductor may not be required because bulk filter and bypass capacitors, as well as other loads located on the board will tend to reduce regulator di/dt effects on the circuit board and input power supply. Placement of the power component to minimize routing distance will also help to reduce emissions. When laying out the CPU buck regulator on a printed cir- cuit board, the following checklist should be used to ensure proper operation of the CS51313. 1) Rapid changes in voltage across parasitic capacitors and abrupt changes in current in parasitic inductors are major concerns for a good layout. 2) Keep high currents out of sensitive ground connections. 3) Avoid ground loops as they pick up noise. Use star or single point grounding. 4) For high power buck regulators on double-sided PCBs a single ground plane (usually the bottom) is recommended. 5) Even though double sided PCBs are usually sufficient for a good layout, four-layer PCBs are the optimum approach to reducing susceptibility to noise. Use the two internal layers as the power and Gnd planes, the top layer for power connections and component vias, and the bot- tom layer for the noise sensitive traces. Layout Guidelines EMI Management TJ(MAX) - TA Power Thermal Management L 201 mils × 1.37 mils L W × t 50mV 16A 50mV IOUT Application Information: continued CS51313

6) Keep the inductor switching node small by placing the output inductor, switching and synchronous FETs close together. 7) The MOSFET gate traces to the IC must be as short, straight, and wide as possible. 8) Use fewer, but larger output capacitors, keep the capaci- tors clustered, and use multiple layer traces with heavy copper to keep the parasitic resistance low. 9) Place the switching MOSFET as close to the +5V input capacitors as possible. 10) Place the output capacitors as close to the load as possible. 11) Place the V FB,VOUT filter resistors (510 Ω) in series with the VFB and VOUT pins as close as possible to the pins. 12) Place the COFF and COMP capacitors as close as possi- ble to the COFF and COMP pins. 13) Place the current limit filter capacitor between the VFB and VOUT pins, as close as possible to the pins. 14) Connect the filter components of the following pins: VFB, VOUT, COFF, and COMP to the Gnd pin with a single trace, and connect this local Gnd trace to the output capaci- tor Gnd. 15) The “Droop” Resistor (embedded PCB trace) has to be wide enough to carry the full load current. 16) Place the V CC bypass capacitor as close as possible to the IC. Application Information: continued CS51313

RΘJC typ 28 ˚C/W RΘJA typ 115 ˚C/W D Lead Count Metric English Max Min Max Min 16L SO Narrow 10.00 9.80 .394 .386 Package Specification PACKAGE DIMENSIONS IN mm (INCHES) PACKAGE THERMAL DATA

Ordering Information

CS51313GDR16 16L SO Narrow (tape & reel) 20 © 1999 Cherry Semiconductor CorporationRev. 3/11/99 Cherry Semiconductor Corporation reserves the right to make changes to the specifications without notice. Please contact Cherry Semiconductor Corporation for the latest available information. CS51313 Surface Mount Narrow Body (D); 150 mil wide 0.33 (.013) 6.20 (.244) 5.80 (.228) 4.00 (.157) 3.80 (.150) 1.57 (.062) 1.37 (.054) D 0.25 (0.10) 0.10 (.004) 1.75 (.069) MAX 1.27 (.050) 0.40 (.016) REF: JEDEC MS-012 0.25 (.010) 0.19 (.008)