CS5127

CS5127 CHERRY

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Technical content

Features

3.3V CT SYNC COMP2 PGnd COMP1 ENABLE LGnd VFB1 VFB2 VREF VIN GATE1 GATE2 CS5127 C12, C13 2 x 680mF R9 IRL3103S R11 27k VFFB1 VFFB2 RT IRL3103S C16 100mF 1mF 18k 1N5821 C15 100mF 5mH C1, C2 2 x 680mF 5mH 330pF 2.8V C10, C11 2 x 680mF +5V 1mF 1N5821 C14 330pF 1540 1270 R10 20k 0.1mF 20k FMMT2222ACT 5V 12V C4, C5 2 x 680mF C17 330pF 20k + R7 2400 1500 0.1mF n Nonsynchronous Buck Design n V2ª Control Topology n 100ns Transient Loop Response n Programmable Oscillator Frequency n 30ns Typical Gate Rise and 10ns Fall Times (No Load) n Frequency Synchronization Input n ENABLE Input Controls Channel 2 Gate Driver n 5V/10mA Reference Output Package Option CS5127 Dual Output Nonsynchronous Buck Controller with Sync Function and Second Channel Enable CS5127

Description

The CS5127 is a fixed frequency dual output nonsynchronous buck controller. It contains circuitry for regulating two separate outputs. Each output channel contains a high gain error amplifier, a com- parator and latch, and a totem-pole output driver capable of providing DC current of 100mA and peak cur- rent in excess of 0.5A. A common oscillator controls switching for both channels, and a sync lead is provided to allow parallel supply operation or shifting of the switch- ing noise spectrum. An on-chip 5V reference is capable of providing as much as 10mA of current for exter- nal circuitry. The CS5127 also contains two undervoltage lockout circuits. The first lockout releases when V IN reaches 8.4V, while the second lockout ensures that VREF is higher than 3.6V. The outputs are held in a low state until both lock- outs have released. The controller is configured to utilize the V 2ª con- trol method to achieve the fastest possible transient response and best overall regulation. This dual controller is a cost-effective solu- tion for providing V CORE and VIO power solutions in computing applications using a single con- troller. The CS5127 will operate over an input voltage range of 9.4V to 20V and is available in a 16 lead wide body surface mount package. Applications Diagram

16 Lead SOIC Wide

12V, 5V to 2.8V @ 7A and 3.3V @ 7A for 233MHz Pentium¨ Processor with MMXª Technology V2 is a trademark of Switch Power, Inc. Pentium is a registered trademark and MMX is a trademark of Intel Corporation Rev. 11/3/98 Cherry Semiconductor Corporation

2000 South County Trail, East Greenwich, RI 02818

Tel: (401)885-3600 Fax: (401)885-5786 Email: info@cherry-semi.com Web Site: www.cherry-semi.com A Company ¨

Lead Symbol Lead Name VMAX VMIN ISOURCE ISINK PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Electrical Characteristics: 0¡C < TA < 70¡C; 0¡C < TJ < 125¡C; 9.4V < VIN < 20V; CT = 330 pF; RT = 27k½; unless otherwise stated. SYNC Oscillator Synchronization Input 5.5V -0.3V 5 mA 5 mA CT Oscillator Integrating Capacitor 5.5V -0.3V 1mA 1mA RT Oscillator Charge Current Resistor 5.5V -0.3V 1mA 1mA V FB1, VFB2 Voltage Feedback Inputs 5.5V -0.3V N/A N/A COMP1, COMP2 Error Amplifier Outputs 7.5V -0.3V 2mA 50mA V FFB1, VFFB2 PWM Ramp Inputs 5.5V -0.3V 1mA 1mA GATE1, GATE2 FET Gate Drive Outputs 20V -0.3V DC, 200mA DC, 200mA DC, -2.0V for 1A peak 1A peak t < 50ns (t < 100µs) (t < 100µs) LGnd Reference Ground and IC Substrate 0V 0V 25 mA N/A PGnd Power Ground 0V 0V 1A Peak, N/A 200mA DC ENABLE Channel 2 Enable 5.5V -0.3V 1mA N/A V REF Reference Voltage Output 5.5V -0.3V 150mA 5mA (short circuit) VIN Power Supply Input 20V -0.3V N/A 200mA DC, 1A peak (t < 100µs) n Reference Section VREF Output Voltage Room Temperature, 4.9 5.0 5.1 V IVREF = 1mA, VIN = 12V Line Regulation 1 20 mV Load Regulation 1 mA < I VREF < 10 mA 15 26 mV VREF Variation over Line, Load 4.85 5.15 V and Temperature Output Short Circuit Current 30 100 150 mA n Oscillator Section Oscillator Frequency Variation 175 210 245 kHz over Line and Temperature Maximum Duty Cycle 80 90 98 % Sync Threshold 0.8 1.6 2.4 V Sync Bias Current V SYNC = 2.4V 170 250 µA VSYNC = 5.0V 430 750 Sync Propagation Delay 230 ns

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Electrical Characteristics: 0¡C < TA < 70¡C; 0¡C < TJ < 125¡C; 9.4V < VIN < 20V; CT = 330 pF; RT = 27k½; unless otherwise stated. n Error Amplifiers VFB Reference Voltage V COMP = VVFB 1.245 1.275 1.300 V Input Bias Current V FB = 1.275V 0.1 1.0 µA Open Loop Gain 85 dB Unity Gain Bandwidth 1.0 MHz PSRR f = 120Hz 80 dB COMP Source Current V COMP = 3V, VVFB = 1.1V 0.9 1.3 2.0 mA COMP Sink Current V COMP = 1.2V, VVFB = 1.45V 10 16 24 mA n PWM Comparators VFFB Bias Current V FFB = 0 2.0 20 µA Propagation Delay V FFB rising to VGATE falling 100 250 ns Common Mode 2.9 3.3 V Maximum Input Voltage n ENABLE Lead ENABLE High Threshold channel 2 enabled 1.5 2.5 3.5 V ENABLE Bias Current V ENABLE = 0 100 250 400 µA n Gate Driver Outputs Output Low Saturation Voltage I GATE = 20 mA 0.1 0.4 V IGATE = 100 mA 0.25 2.50 V Output High Saturation Voltage I GATE = 20 mA 1.5 2.0 V IGATE = 100 mA 1.6 3.0 V Output Voltage under Lockout V IN = 6V, IGATE = 1 mA 0.1 0.2 V Output Rise Time no load 30 ns Output Fall Time no load 10 ns n Undervoltage Lockout Turn On Threshold 7.4 8.4 9.4 V Turn Off Threshold 6.8 7.8 8.8 V n Supply Current Start Up Current V IN = 6V 0.4 0.8 mA Operating Current V CT = 0V, no load 17.5 25 mA

PACKAGE LEAD # LEAD SYMBOL FUNCTION

16 Lead SO Wide

1 SYNC A pulse train on this lead will synchronize the oscillator. Sync threshold level is 2.4V. Synchronization frequency should be at least 10% higher than the reg- ular operating frequency. The sync feature is level sensitive. T The oscillator integrating capacitor is connected to this lead. 3R T The oscillator charge current setting resistor is connected to this lead. 4V FB1 The inverting input of the channel 1 error amplifier is brought out to this lead. The lead is connected to a resistor divider which provides a measure of the output voltage. The input is compared to a 1.275V reference, and channel 1 error amp output is used as the V 2ª PWM control voltage. 5 COMP1 Channel 1 error amp output and PWM comparator input. FFB1 This lead connects to the non-inverting input of the channel 1 PWM comparator. 7 GATE1 This lead is the gate driver for the channel 1 FET. It is capable of providing nearly 1A of peak current. 8 LGND This lead provides a ÒquietÓ ground for low power circuitry in the IC. This lead should be shorted to the PGND lead as close as possible to the IC for best operating results. 9 PGND This lead is the power ground. It provides the return path for the FET gate dis- charge. It should be shorted to the LGND lead as close as possible to the IC for best operating results. 10 GATE2 This lead is the gate driver for the channel 2 FET. See GATE1 lead description for more details. 11 V FFB2 This lead connects to the non-inverting input of the channel 2 PWM comparator. 12 COMP2 Channel 2 error amp output and PWM comparator input. 13 V FB2 Inverting input for the channel 2 error amp. See VFBI for more details.

14 ENABLE The regulator controlled by channel 2 may be turned on and off selectively by

the user. Pulling the ENABLE lead above 3.5V will turn channel 2 on. Setting the ENABLE lead voltage below 1.5V guarantees that channel 2 is off. 15 V REF This lead is the output of a ± 3% reference. This reference drives most of the on-chip circuitry, but will provide a minimum of 10 mA to external circuitry if needed. The reference is inherently stable and does not require a compensa- tion capacitor, but use of a decoupling capacitor will reduce noise in the IC. 16 V IN This lead is the power supply input to the IC. The maximum input voltage that can be withstood without damage to the IC is 20V.

The CS5127 is a dual power supply controller that utilizes the V2ª control method. Two nonsynchronous V2ª buck regulators can be built using a single controller IC. This IC is a perfect choice for efficiently and economically provid- ing core power and I/O power for the latest high-performance CPUs. Both switching regulators employ a fixed frequency architecture driven from a common oscillator circuit. The V 2ª method of control uses a ramp signal generated by the ESR of the output capacitors. This ramp is propor- tional to the AC current in the inductor and is offset by the DC output voltage. V 2ª inherently compensates for varia- tion in both line and load conditions since the ramp signal is generated from the output voltage. This differs from tra- ditional methods such as voltage mode control, where an artificial ramp signal must be generated, and current mode control, where a ramp is generated from inductor current. Figure 1: V2ª control diagram. The V2ª control method is illustrated in Figure 1. Both the ramp signal and the error signal are generated by the output voltage. Since the ramp voltage is defined as the output voltage, the ramp signal is affected by any change in the output, regardless of the origin of that change. The ramp signal also contains the DC portion of the output voltage, allowing the control circuit to drive the output switch from 0% to about 90% duty cycle. Changes in line voltage will change the current ramp in the inductor, affecting the ramp signal and causing the V 2ª control loop to adjust the duty cycle. Since a change in inductor current changes the ramp signal, the V2ª method has the characteristics and advantages of current mode control for line transient response. Changes in load current will affect the output voltage and thus will also change the ramp signal. A load step will immediately change the state of the comparator output that controls the output switch. In this case, load transient response time is limited by the comparator response time and the transition speed of the switch. Notice that the reac- tion time of the V 2ª loop to a load transient is not dependent on the crossover frequency of the error signal loop. Traditional voltage mode and current mode methods are dependent on the compensation of the error signal loop. The V 2ª error signal loop can have a low crossover fre- quency, since transient response is handled by the ramp signal loop. The ÒslowÓ error signal loop provides DC accuracy. Low frequency roll-off of the error amplifier bandwidth will significantly improve noise immunity. This also improves remote sensing of the output voltage, since switching noise picked up in long feedback traces can be effectively filtered. V 2ª line and load regulation are dramatically improved because there are two separate control loops. A voltage COMP VFB GATE VFFB PWM Comparator Reference Voltage Error Amplifier Error Signal Ramp Signal V2ª Control Method Block Diagram CT SYNC COMP2 COMP1 ENABLE LGND VFB2 VREF VIN GATE1 GATE2 VFFB1 VFFB2 RT PGND Error Amplifier 1.275V PWM Comparator Channel 2 Gate Driver Oscillator Reference Undervoltage Lockout Bandgap Voltage Reference VIN Undervoltage Lockout Channel 2 Gate Driver Error Amplifier +1.275V VFB1 PWM Comparator

The feedback (VFB) leads are connected to external resistor dividers to set the output voltage. The on-chip error ampli- fier is referenced to 1.275V, and the resistor divider values are determined by selecting the desired output voltage and the value of the divider resistor connected between the V FB lead and ground. Resistor R1 is chosen first based on a design trade-off of system efficiency vs. output voltage accuracy. Low values of divider resistance consume more current which decreas- es system efficiency. However, the V FB lead has a 1µA maximum bias current which can introduce errors in the output voltage if large resistance values are used. The approximate value of current sinking through the resistor divider is given by I V(FB) = The output voltage error that can be expected due to the bias current is given by Error Percentage = ´ 100% where R1 is given in ohms. For example, setting R1 = 5K yields an output voltage error of 0.39% while setting the feedback divider current at 255µA. Larger currents will result in reduced error. Figure 3: Feedback resistor divider. R2 can be sized according to the following formula once the desired output voltage and the value of R1 have been determined: R2 = R1 -1 There are many factors to consider when choosing the inductor. Maximum load current, core losses, winding losses, output voltage ripple, short circuit current, satura- tion, component height, EMI/EMC and cost are all variables the designer must consider. Inductance values between 1µH and 50µH are suitable for use with the CS5127. Low values within this range minimize the component size and improve transient response, but larger values reduce ripple current. Choosing the inductor value requires the designer to make some choices early in the design. Output current, output voltage and the input voltage range should be known in order to make a good choice. The input voltage range is bracketed by the maximum and minimum expected values of V IN. Most computer applica- tions use a fairly well-regulated supply with a typical output voltage tolerance on the order of ±5%. The values of V IN(MAX) and VIN(MIN) are used to calculate peak current and minimum inductance value, respectively. However, if the supply is well-regulated, these calculations may both be made using the typical input voltage value with very little error. Current in the inductor while operating in the continuous current mode (CCM) is defined as the load current plus the inductor ripple current: I L = IOUT + IRIPPLE The ripple current waveform is triangular, and the current is a function of the voltage across the inductor, the switch on-time and the inductor value. Switch on-time is the duty cycle divided by the operating frequency, and duty cycle can be defined as the ratio of V OUT to VIN, such that IRIPPLE = The peak current can be described as the load current plus half of the ripple current. Peak current must be less than the maximum rated switch current. This limits the maxi- mum load current that can be provided. It is also important that the inductor can deliver the peak current without saturating. I OUT(MAX) = ISWITCH(MAX) - Since the peak inductor current must be less than or equal to the peak switch current, the minimum value of induc- tance can be calculated: L MIN = The theoretical limit on load current transient response is a function of the inductor value, the load transient and the voltage across the inductor. In conventionally-controlled regulators, the actual limit is the time required by the con- trol loop. Conventional current-mode and voltage-mode control loops adjust the switch duty cycle over many oscil- lator periods, often requiring tens or even hundreds of Load Current Transient Response (VIN(MIN) - VOUT)VOUT f ´ VIN(MIN) ´ ISWITCH(MAX) (VIN(MAX) - VOUT)VOUT 2f ´ L ´ VIN(MAX) (VIN - VOUT)VOUT f ´ L ´ VIN Selecting the Inductor VOUT 1.275( COMP VFB GATE Output Driver 1.275V VOUT (1E - 6) ´ R1 1.275 1.275V Selection of Feedback Lead Divider Resistor Values CS5127 Applications Information

Applications Information: continued microseconds to return to a steady-state. V2ª control uses the ripple voltage from the output capacitor and a ÒfastÓ control loop to respond to load transients, with the result that the transient response of the CS5127 is very close to the theoretical limit. Response times are defined below. t RESPONSE(INCREASING) = tRESPONSE(DECREASING) = Note that the response time to a load decrease is limited only by the inductor value. Inductor current rating is an important consideration. If the regulated output is subject to short circuit or overcur- rent conditions, the inductor must be sized to handle the fault without damage. Sizing the inductor to handle fault conditions within the maximum DC current rating helps to ensure the coil doesnÕt overheat. Not only does this pre- vent damage to the inductor, but it reduces unwanted heat generated by the system and makes thermal management easier. Selecting an open core inductor will minimize cost, but EMI/EMC performance may be degraded. This is a tough choice, since there are no guidelines to ensure these com- ponents will not prove troublesome. Core materials influence the saturation current and satura- tion characteristics of the inductor. For example, a slightly undersized inductor with a powdered iron core may pro- vide satisfactory operation because powdered iron cores have a ÒsoftÓ saturation curve compared to other core materials. Small physical size, low core losses and high temperature operation will also increase cost. Finally, consider whether an alternate supplier is an important consideration. All of these factors can increase the cost of the inductor. For light load designs, the CS5127 will operate in discon- tinuous current mode (DCM). In this regime, external components can be smaller, since high power dissipation is not an issue. In discontinuous mode, maximum output current is defined as: I OUT(MAX) = where IPK is the maximum current allowed in the switch FET. Output capacitors are chosen primarily on the value of equivalent series resistance, because this is what deter- mines how much output ripple voltage will be present. Most polarized capacitors appear resistive at the typical oscillator frequencies of the CS5127. As a rule of thumb, physically larger capacitors have lower ESR. The capaci- torÕs value in µF is not of great importance, and values from a few tens of µF to several hundreds of µF will work well. Tantalum capacitors serve very well as output capaci- tors, despite their bad reputation for spectacular failure due to excessive inrush current. This is not usually an issue for output capacitors, because the failure is not associated with discharge surges. Ripple current in the output capaci- tor is usually small enough that the ripple current rating is not an issue. The ripple current waveform is triangular, and the formula to calculate the ripple current value is: I RIPPLE = and output ripple voltage due to inductor ripple current is given by: VRIPPLE(ESR) = A load step will produce an instantaneous change in output voltage defined by the magnitude of the load step, capacitor ESR and ESL. DV O = (DIO ´ ESD) + ESL A good practice is to first choose the output capacitor to accommodate voltage transient requirements and then to choose the inductor value to provide an adequate ripple voltage. Increasing a capacitorÕs value typically reduces its ESR, but there is a limit to how much improvement can be had. In most applications, placing several smaller capacitors in parallel will result in acceptable ESR while maintaining a small PC board footprint. A warning is necessary at this point. The V 2ª topology relies on the presence of some amount of output ripple voltage being present to provide the input signal for the ÒfastÓ control loop, and it is impor- tant that some ripple voltage be present at the lightest load condition in normal operation to avoid subharmonic oscil- lation. Externally generated slope compensation can be added to ensure proper operation. The V FFB lead is tied to the PWM comparatorÕs non-invert- ing input, and provides the connection for the externally-generated artificial ramp signal that is required whenever duty cycle is greater than 50%. Selecting the VFFB Lead Components DI DT (VIN - VOUT) ´ VOUT ´ ESR f ´ L ´ VIN (VIN - VOUT)VOUT f ´ L ´ VIN Selecting the Output Capacitor (IPK)2 f ´ L(VIN) 2VOUT ´ (VIN(MAX) - VOUT) Operating in Discontinuous Current Mode Other Inductor Selection Concerns L(ÆIOUT) VOUT L(ÆIOUT) (VIN - VOUT) ´ 0.85

discharge time is typically less than 10% of the charge time. External components CT and RT allow the switching frequency to be set by the user in the range between 10kHz and 500kHz. C T can be chosen first based on size and cost constraints. For proper operation over temperature, the value of R T should be chosen within the range from 20k½ to 40k½. Any type of one-eighth watt resistor will be ade- quate. Larger values of R T will decrease the maximum duty cycle slightly. This occurs because the sink current on the C T lead has an exponential relationship to the charge current. Higher charge currents will discharge the CT lead capacitor more quickly than lower currents, and a shorter discharge time will result in a higher maximum duty cycle. Once the oscillator frequency and a value of C T have been selected, the necessary value of RT can be calculated as fol- lows: RT = where fOSC is the oscillator frequency in hertz, CT is given in farads, and the value of RT is given in ohms. ESR effects are negligible since the charge and discharge currents are fairly small, and any type of capacitor is adequate for C As previously noted, the error amplifier does not con- tribute greatly to transient response, but it does influence noise immunity. The fast feedback loop input is compared against the COMP pin voltage. The DC bias to the V FFB pin may be provided directly from the output voltage, or through a resistor divider if output voltage is greater than 2.9V. The desired percentage value of DC accuracy trans- lates directly to the V FFB pin, and the minimum COMP pin capacitor value can be calculated: CCOMP = If fOSC = 200kHz, VFFB DC bias voltage is 2.8V and toler- ance is 0.1%, CCOMP = 28.6µF. This is the minimum value of COMP pin capacitance that should be used. It is a good practice to guard band the tolerance used in the calcula- tion. Larger values of capacitance will improve noise immunity, and a 100µF capacitor will work well in most applications. The type of capacitor is not critical, since the amplifier output sink current of 16mA into a fairly large value or wide range of ESR will typically result in a very small DC output voltage error. The COMP pin capacitor also deter- mines the length of the soft start interval. The input bypass capacitors minimize the ripple current in the input supply, help to minimize EMI, and provide a charge reservoir to improve transient response. The capac- itor ripple current rating places the biggest constraint on component selection. The input bypass capacitor network should conduct all the ripple current. RMS ripple current can be as large as half the load current, and can be calcu- lated as: I RIPPLE(RMS) =I OUT Peak current requirement, load transients, ambient operat- ing temperature and product reliability requirements all play a role in choosing this component. Capacitor ESR and the maximum load current step will determine the maxi- mum transient variation of the supply voltage during normal operation. The drop in the supply voltage due to load transient response is given as: ÆV = I RIPPLE(RMS) ´ ESR The type of capacitor is also an important consideration. Aluminum electrolytic capacitors are inexpensive, but they typically have low ripple current ratings. Choosing larger values of capacitance will increase the ripple current rating, but physical size will increase as well. Size con- straints may eliminate aluminum electrolytics fro consideration. Aluminum electrolytics typically have shorter operating life because the electrolyte evaporates during operation. Tantalum electrolytic capacitors have been associated with failure from inrush current, and man- ufacturers of these components recommended derating the capacitor voltage by a ratio 2:1 in surge applications. Some manufacturers have product lines specifically tested to withstand high inrush current. AVX TPS capacitors are one such product. Ceramic capacitors perform well, but they are also large and fairly expensive. At startup, output switching does not occur until two undervoltage lockouts release. The first lockout monitors the V IN lead voltage. No internal IC activity occurs until VIN lead voltage exceeds the VIN turn-on threshold. This threshold is typically 8.4V. Once this condition is met, the on-chip reference turns on. As the reference voltage begins to rise, a second undervoltage lockout disables switching until V REF lead voltage is about 3.5V. The GATE leads are held in a low state until both lockouts are released. As switching begins, the VFB lead voltage is lower than the output voltage. This causes the error amplifier to source current to the COMP lead capacitor. The COMP lead volt- age will begin to rise. As the COMP lead voltage begins to rise, it sets the threshold level at which the rising V FFB lead voltage will trip the PWM comparator and terminate switch conduction. This process results in a soft start inter- val. The DC bias voltage on V FFB will determine the final COMP voltage after startup, and the soft start time can be approximately calculated as: T SOFT START = VFFB ´ CCOMP ICOMP(SOURCE) Startup VOUT(VIN - VOUT) VIN2 Selecting the Input Bypass Capacitor (16mA)(TOSC) (VFFBDC Bias Voltage)(tolerance) Selecting the Compensation Capacitor 1.88 (fOSC)(CT) CS5127 Applications Information: continued

Applications Information: continued IC. This heat is transferred to the surface of the IC package, but a thermal gradient exists due to the thermal properties of the package molding compound. The magnitude of this thermal gradient is denoted in manufacturerÕs data sheets as Q JA , or junction-to-air thermal resistance. The on-chip junction temperature can be calculated if QJA , the air tem- perature at the ICÕs surface and the on-chip power dissipation are known: T J = TA + (QJA ´ P) TJ and TA are given in degrees centigrade, P is IC power dissipation in watts and QJA is thermal resistance in degrees centigrade per watt. Junction temperature should be calculated for all semiconductor devices to ensure they are operated below the manufacturerÕs maximum junction temperature specification. If any componentÕs temperature exceeds the manufacturerÕs maximum specification, some form of heatsink will be required. Heatsinking will improve the thermal performance of any IC. Adding a heatsink will reduce the magnitude of Q JA by providing a larger surface area for heat transfer to the sur- rounding air. Typical heat sinking techniques include the use of commercial heatsinks for devices in TO-220 pack- ages, or printed circuit board techniques such as thermal bias and large copper foil areas for surface mount pack- ages. When choosing a heatsink, it is important to break Q JA into several different components. QJA = QJC + QCS + QSA where all components of QJA are given in ¡C/W. QJC is the thermal impedance from the junction to the sur- face of the package case. This parameter is also included in manufacturerÕs data sheets. Its value is dependent on the mold compound and lead frames used in assembly of the semiconductor device in question. Q CS is the thermal impedance from the surface of the case to the heatsink. This component of the thermal impedance can be modified by using thermal pads or thermal grease between the case and the heat sink. These materials replace the air gap normally found between heatsink and case with a higher thermal conductivity path. Values of Q CS are found in catalogs published by manufacturers of heatsinks and thermal compounds. Finally, Q SA is the thermal impedance from the heatsink to ambient temperature. QSA is the important parameter when choosing a heatsink. Smaller values of QSA allow higher power dissipation without exceeding the maximum junction temperature of the semiconductor device. Values of Q SA are typically provided in catalogs published by heatsink manufacturers. The basic equation for selecting a heatsink is PD = where PD is on-chip power dissipation in watts, TJ is junc- tion temperature in ¡C, TA is ambient temperature in¡C, and thermal impedance QJC , QCS , and QSA are in¡C/W. All these quantities can be calculated or obtained from data sheets. The choice of a heatsink is based on the value of Q SA required such that the calculated power dissipation does not cause junction temperature to exceed the manu- facturerÕs maximum specification. Switching regulators generate noise a consequence of the large values of current being switched on and off in normal operation. Careful attention to layout of the printed circuit board will usually minimize noise problems. Layout guide- lines are provided in the next section. However, it may be necessary in some cases to add filter inductors or bypass capacitors to the circuitry to achieve the desired perfor- mance. The following guidelines should be observed in the layout of PC boards for the CS5127: 1. Connect the PGND lead to the external ground with a wide metal trace. 2. Connect both LGND and PGND together with a wide trace as close to the IC as possible. 3. Make all ground connections to a common ground plane with as few interruptions as possible. Breaks in the ground plane metal should be made parallel to an imaginary line between the supply connections and the load. 4. Connect the ground side of the COMP lead capacitors back to LGND with separate traces. 5. Place the V FFB lead capacitors as close to the VFFB leads as possible. 6. Place the 5V line bypass capacitors as close to the switch FETs as possible. 7. Place the output capacitor network as close to the load as possible. 8. Route the GATE lead signals to the FET gates with a metal trace at least 0.025 inches wide. 9. Use wide straight metal traces to connect between the 5V line and FETs, between FETs and inductors and between inductors and loads to minimize resistance in the high current paths. Avoid sharp turns, loops and long lengths. Layout Considerations EMI Management TJ - TA QJC + QCS + QSA CS5127

+5V +12V +5V 2.8V 3.3V 1540 +C8 1mF IRL3103S 680mF 2400 CS5127 SYNC1 CT2 RT3 VFB14 COMP1 VFFB1 GATE17 LGND8 VIN VREF 15 ENABLE VFB2 13 COMP2 VFFB2 11 GATE2 PGND 1N5821 IRL3103S 680mF 1500 C11 680mF C10 680mF +C3 1UF 5mH 1270 L1 5 mH 680mF 680mF 1N5821 C13 680mF C12 680UF C14 0.2mF R65 18K C15 0.01mF 3.3K 100K 390pF 24K 7pF C50 0.22mF 2N3906 R48 100K C15 0.1mF C24 0.01mF 2N3906 C16 0.22mF R11 2.2K R66 C17 0.2mF R10 C52 7pF +12V 2.8V 3.3V 1540 330PF C16 100mF C17 330PF 2400 CS5127 SYNC1 CT2 RT3 VFB1 COMP15 VFFB1 GATE17 LGND8 VIN VREF ENABLE 14 VFB2 COMP2 12 VFFB2 GATE2 10 PGND 09 1N5821 IRL3103S FMMT2222ACT 680mF C13 680mF 0.1mF 18KC15 100mF C14 330PF C10 680mF L2 5mH

1270 R10

+C3 10mF C12 680mFC11 680mF R11 20K 0.1mF 1N5818 1N5818 C18 0.1mF 50V R12 1N5248 Figure 15: CS5127 12V, 5V input to 2.8V @ 7A and 3.3V @ 7A Voltage Mode Control Application Circuit with External Soft Start. Figure 16: CS5127 12V only to 2.8V @ 7A and 3.3V @ 7A Application Circuit. Additional Application Circuits continued CS5127

Additional Application Circuits continued +5V 3.3V 680mF IRL3103S 680mF C17 330PF C12 CS5127 SYNC1 CT2 RT3 VFB14 COMP15 VFFB1 GATE17 LGND VIN VREF 15 ENABLE 14 VFB2 13 COMP2 12 VFFB2 11 GATE2 10 PGND 09 IRL3103S FMMT2222ACT R11 20K 1mF R66 R71 10K 0.1mF 0.1mF 1.50K R68 15k C13 680mF C14 330PF C10 680mF 20K 1N5821 1mF 1.54K R10 20K 5mH 330PF 5mF 1N5821 C16 100mF 1.27K +12V +12V +12V+5V 680mF 680mF 2.40K 18K C15 100mF RDROOP 2.8V R75 R76 1M1M C25 0.1mF R69 10K 2N2907 2N2907 LM2903 U4A LM2903 U4B R72 20K R74R73 R70 20K C11 680mF .008 R65 R67 15k 680mF R77 15K R78 15K RDROOP .008 + + 1KC24 0.1mF Figure 17: 200kHz, V2ª, 5V/12V input, 2.8V@ 7A and 3.3V @ 7A outputs with current limit. 2.8V 3.3V 1540 330PF C16 100mF C17 330pF 2400 CS5127 SYNC1 CT2 RT3 VFB1 COMP15 VFFB1 GATE17 LGND8 VIN VREF ENABLE 14 VFB2 COMP2 12 VFFB2 GATE2 10 PGND 09 1N5821 IRL3103S FMMT2222ACT 680mF C13 680mF 0.1mF 18KC15 100mF C14 330pF C10 680mF L2 10mH 0.1mF +5V +12V 2.5V 680mF 680mF +5V C18 47mF IRL3103S R18 2400 R17 2400 1mF 1mF U2A 1/2 LM358 Figure 18: CS5127 12V, 5V input to 2.8V @7A and 3.3V @ 7A Switching Regulator with External 1A, 2.5V Linear Output for Vclock.

24Rev. 11/3/98 © 1999 Cherry Semiconductor Corporation 1.27 (.050) BSC 7.60 (.299) 7.40 (.291) 10.65 (.419) 10.00 (.394) D 0.32 (.013) 0.23 (.009) 1.27 (.050) 0.40 (.016) REF: JEDEC MS-013 2.49 (.098) 2.24 (.088) 0.51 (.020) 0.33 (.013) 2.65 (.104) 2.35 (.093) 0.30 (.012) 0.10 (.004) Package Specification PACKAGE DIMENSIONS IN mm (INCHES) PACKAGE THERMAL DATA Thermal Data 16 Lead SOIC Wide RQJC typ 23 ûC/W RQJA typ 105 ûC/W D Lead Count Metric English Max Min Max Min 16 Lead SOIC Wide 10.50 10.10 .413 .398

Ordering Information

CS5127GDW16 16 Lead SOIC Wide CS5127GDWR16 16 Lead SOIC Wide (tape & reel) Surface Mount Wide Body (DW); 300mil wide Cherry Semiconductor Corporation reserves the right to make changes to the specifications without notice. Please contact Cherry Semiconductor Corporation for the latest available information. CS5127