CS5126

CS5124 CHERRY

Document overview

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Technical content

Features

I External Synchronization to Higher or Lower Frequency Oscillator (CS5126 Only) I Bias for Start up Circuitry (CS5124 Only) I Thermal Shutdown I Sleep On/Off Pin I Soft Start Timer I Leading Edge Blanking I Direct Optocoupler Interface I 90ns Propagation Delay I 35ns Driver Rise and Fall Times I Sleep Mode Package Options CS5124/6 High Performance, Integrated Current Mode PWM Controllers CS5124/6

Description

8 Lead SO Narrow

Cherry Semiconductor Corporation

2000 South County Trail, East Greenwich, RI 02818

Tel: (401)885-3600 Fax: (401)885-5786 Email: info@cherry-semi.com Web Site: www.cherry-semi.com A Company ® Rev. 3/12/99 Gnd UVLO 1VCC SYNC SS GATE ISENSE VFB CS5124 CS5126 48V to 5V, 1A flyback converter using the CS5124 The CS5124/6 is a fixed frequency current mode controller designed specifically for DC-DC converters found in the telecommunications industry. The CS5124/6 integrates many commonly required current mode power supply features and allows the power supply designer to realize substantial cost and board space savings. The product matrix is as follows: CS5124: 400kHz w/V BIAS Pin, 195mV first current sense threshold CS5126: 200kHz w/SYNC Pin, 335mV first current sense threshold The CS5124/6 integrates the follow- ing features: Internal Oscillator, Slope Compensation, Sleep On/Off, Under Voltage Lock Out, Thermal Shutdown, Soft Start Timer, Low Voltage Current Sense for Resistive Sensing, Second Current Threshold for Pulse by Pulse Over Current Protection, a Direct Optocoupler Interface and Leading Edge Current Blanking. The CS5124/6 has supply range of 7.7V to 20V and is available in 8 pin SO narrow package.

Pin Symbol Lead Name VMAX VMIN ISOURCE ISINK VCC VCC Power Input 20V -0.3V 1mA 1.5A Peak 200mA DC SYNC (CS5126) Clock Synchronization Input 20V -0.3V 1mA 1mA V BIAS (CS5124) V CC Clamp Output 20V -0.3V 1mA 1mA UVLO UVLO Shutdown Input 6V -0.3V 1mA 1mA SS Soft Start Capacitor Input 6V -0.3V 1mA 2mA V FB Voltage Feed Back Input 6V -0.3V 3mA 20mA ISENSE Current Sense Input 6V -0.3V 1mA 1mA GROUND Ground 0V 0V 1.5A peak 1mA 200mA DC GATE Gate Drive Output 20V -0.3V 1.5A Peak 1.5A Peak 200mA DC 200mA DC Lead Temperature Soldering: CS5124/6 Absolute Maximum Ratings PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Electrical Characteristics: -40°C ≤ TJ ≤ 125°C, -40°C ≤ TA ≤ 105°C, 7.60V ≤ VCC ≤ 20V, UVLO = 3.0V, ISENSE = 0V, CV(CC) = 0.33µF, CGATE = 1nF (ESR = 10Ω), CSS = 470pF CV(FB) = 100pF, unless otherwise stated. I General ICC Operating - VGATE not switching. 10 13 mA ICC at VCC Low V CC = 6V 500 750 µA ICC Sleep V UVL = 1V 210 275 µA I Low VCC Lockout VCC Turn-on Threshold Voltage 7.2 7.7 8.3 V VCC Turn-off Threshold Voltage 6.8 7.3 7.8 V VCC Hysteresis 350 425 500 mV I UVLO Sleep Threshold Voltage UVLO decreasing 1.5 1.8 2.3 V Sleep Threshold Voltage UVLO increasing 1.88 2.45 V Sleep Hysteresis 35 85 150 mV UVLO Turn-off (Note 1) 2.3 2.45 2.6 V Threshold Voltage UVLO Turn-on (Note 1) 2.50 2.63 2.76 V Threshold Voltage UVLO Hysteresis Turn-on – Turnoff (-40°C ≤ T J ≤ 100°C) 170 185 200 mV (Note 1) UVLO Hysteresis Turn-on – Turnoff (100°C ≤ TJ ≤ 125°C) 50 185 400 mV (Note 1) UVLO Input Bias Current -1 1 µA UVLO Clamp With UVLO sinking 1mA. 5 7.5 12 V

Electrical Characteristics: -40°C ≤ TJ ≤ 125°C, -40°C ≤ TA ≤ 105°C, 7.60V ≤ VCC ≤ 20V, UVLO = 3.0V, ISENSE = 0V, CV(CC) = 0.33µF, CGATE = 1nF (ESR = 10Ω), CSS = 470pF CV(FB) = 100pF, unless otherwise stated. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT I VCC Clamp and BIAS Pin CS5124 Only. Connect an NFET as follows: BIAS = G, V CC = S, VIN = D. VCC Clamp Voltage 36V ≤ VIN ≤ 60V, 220nF ≤ 7.275 7.9 8.625 V CSS ≤ 500nF, R = 500k BIAS Minimum Voltage Measure Voltage on BIAS with: 1.6 2.8 4 V 10V ≤ VCC ≤ 20V and 50µA ≤ IBIAS ≤ 1mA BIAS Clamp With BIAS pin sinking 1mA 12 15 20 V I 200kHz Oscillator CS5126 Only Operating Frequency 175 200 225 kHz Max Duty Cycle Clamp 78 82.5 85 % Slope Compensation 12 18 23 mV/µs (Normal operation) Slope Compensation (Synchronized operation) (Note 1) 7 12 16 mV/µs SYNC Input Threshold Voltage 1 2 3 V SYNC Input Impedance Measured with SYNC = 1V &10V 50 120 230 k Ω I 400kHz Oscillator CS5124 Only Operating Frequency 360 400 440 kHz Max Duty Cycle Clamp 80.0 82.5 85.0 % Slope Compensation 15 21 26 mV/µs I Soft Start Soft Start Charge Current 7 10 13 µA Soft Start Discharge Current 0.5 10.0 mA V SS Voltage when VFB VFB = 300mV 1.40 1.62 1.80 V Begins to Rise Peak Soft Start Charge Voltage 4.7 4.9 V Valley Soft Start Discharge Voltage 200 275 400 mV I Current Sense CS5124 Only First Current Sense Threshold At max duty cycle. 170 195 215 mV Second Current Sense Threshold 250 275 315 mV I SENSE to GATE Prop. Delay 0 to 700mV pulse into I SENSE 60 90 130 ns (after blanking time) Leading Edge Blanking Time 0 to 400mV pulse into I SENSE 90 130 180 ns Internal Offset (Note 1) 60 mV I Current Sense CS5126 Only First Current Sense Threshold At max duty cycle 300 335 360 mV Second Current Sense 485 525 575 mV Threshold I SENSE to GATE Prop. Delay 0 to 800mV pulse into I SENSE 60 90 130 ns (after blanking time) Leading Edge Blanking Time 0 to 550mV pulse into I SENSE 110 175 210 ns Internal Offset (Note 1) 125 mV

PACKAGE LEAD # LEAD SYMBOL FUNCTION CS5124/6 Electrical Characteristics: -40°C ≤ TJ ≤ 125°C, -40°C ≤ TA ≤ 105°C, 7.60V ≤ VCC ≤ 20V, UVLO = 3.0V, ISENSE = 0V, CV(CC) = 0.33µF, CGATE = 1nF (ESR = 10Ω), CSS = 470pF CV(FB) = 100pF, unless otherwise stated. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 11 V CC VCC Power Input Pin. 2 - BIAS V CC Clamp Output Pin. This pin will control the gate of an N-channel MOS- FET that in turn regulates VCC. This pin is internally clamped at 15V when the IC is in sleep mode. - 3 SYNC Clock Synchronization Pin. A positive edge will terminate the current PWM cycle. Ground this pin when it is not used. 3 2 UVLO Sleep and under voltage lockout pin. A voltage greater than 1.8V causes the chip to "wake up" however the GATE remains low. A voltage greater than 2.6V on this pin allows the output to switch. 4 4 SS Soft Start Capacitor Pin. A capacitor placed between SS and GROUND is charged with 10µA and discharged with 10mA. The Soft Start capacitor con- trols both soft-start time and hiccup mode frequency. 55 V FB Voltage Feedback Pin. The collector of an optocoupler is typically tied to this pin. This pin is pulled up internally by a 4.3kΩ resistor to 5V and is clamped internally at 2.9V(2.65V). If VFB is pulled > 4V, the oscillator is disabled and GATE will stay high. If the VFB pin is pulled < 0.49V, GATE will stay low. 66 I SENSE Current Sense Pin. This pin is connected to the current sense resistor on the primary side. If VFB is floating, the GATE will go low if ISENSE = 195mV (335mV). If ISENSE > 275mV (525mV), Soft Start will be initiated. 7 7 GATE Gate Drive Output Pin. Capable of driving a 3nF load. GATE is nominally clamped to 13.5V. 8 8 Gnd Ground Pin. I Voltage Feedback VFB Pull-up Res. 2.9 4.3 8.1 k Ω VFB Clamp Voltage CS5124 Only 2.63 2.90 3.15 V VFB Clamp Voltage CS5126 Only 2.40 2.65 2.90 V VFB Fault Voltage Threshold 460 490 520 mV I Output Gate Drive Maximum Sleep V CC = 6.0V, IOUT = 1mA 1.2 2.0 V Pull-down Voltage GATE High (AC) Series resistance < 1 Ω (Note 1) V CC-1 V CC-0.5 V GATE Low (AC) Series resistance < 1 Ω (Note 1) 0.0 0.5 V GATE High Clamp Voltage V CC = 20V 11.0 13.5 16.0 V Rise Time Measure GATE rise time, 45 65 ns 1V < GATE < 9V; VCC =12V Fall Time Measure GATE fall time, 25 55 ns 9V > GATE > 1V; VCC = 12V I Thermal Shutdown Thermal Shutdown Temperature (Note 1) (GATE low) 135 150 165 °C Thermal Enable Temperature (Note 1) (GATE switching) 100 125 150 °C Thermal Hysteresis (Note 1) 15 25 35 °C Notes 1. Not tested in production. Specification is guaranteed by design.

{2.65V} 2.90V V5REF GATE ÷ VFB ISENSE VCC 2.62 V/2.45V 1.91 V/1.83V REMOTE (SLEEP) COMP SS VCC UVLO COMP 7.7 V/7.275V -LINE AMP (CS5124 ONLY) 2.9 R R 2.0V SS COMP 275mV V V V V 1.32V V {525mV} 275mV {125mV} 60mV DRIVER 490mV VFB COMP PWM COMP 2ND ICOMP +LINE UVLO COMP RESET DOMAIN 4500Ω BIAS UVLO V5REF R Q S 1000Ω BLANKING 10µA V5REF V5REF V BLANK VCC V V TSHUT V R QS SS AMP V {85 mV/us} 170mV us {1/5} OSC RAMP ENABLE VCC VREF = 5V VREFOK SYNC {CS5126 ONLY} DIS R QS SET DOMAIN SOFT START LATCH 150°C/125°C Gnd Theory of Operation Powering the IC VCC can be powered directly from a regulated supply and requires 500µA of start-up current. The CS5124/6 includes a line bias pin (BIAS) that can be used to control a series pass transistor for operation over a wide input volt- age. The BIAS pin will control the gate voltage of an N- channel MOSFET placed between V IN and VCC to regulate VCC at 8V. VCC and UVLO Pins The UVLO pin has three different modes; low power shut- down, Line UVLO, and normal operation. To illustrate how the UVLO pin works; assume that V IN, as shown in the application schematic, is ramped up starting at 0V with the UVLO pin open. The SS and I SENSE pins also start at 0V. While the UVLO is below 1.8V, the IC will remain in a low current sleep mode and the BIAS pin of the CS5124 is inter- nally clamped to a maximum of 15V. When the voltage on the UVLO pin rises to between 1.8V and 2.6V the reference for the V CC UVLO is enabled and VCC is regulated to 8V by the BIAS pin (CS5124 only), but the IC remains in a UVLO state and the output driver does not switch. When the UVLO pin exceeds 2.6V and the V CC pin exceeds 7.7V, the GATE pin is released from a low state and can begin switching based on the comparison of the I SENSE and VFB pins. The Soft Start capacitor begins charging from 0V at 10µA. As the capacitor charges, a buffered version of the capacitor voltage appears on the VFB pin and the VFB volt- age begins to rise. As VFB rises the duty cycle increases until the supply comes into regulation. Soft Start Soft Start is accomplished by clamping the VFB pin 1.32V below the SS pin during normal start up and during restart after a fault condition. When the CS5124/6 starts, the Soft Start capacitor is charged from a 10µA source from 0V to 4.9V. The V FB pin follows the Soft Start pin offset by –1.32V until the supply comes into regulation or until the Soft Start error amp is clamped at 2.9V (2.65V for the CS5126). During fault conditions the Soft Start capacitor is dis- charged at 10mA. Fault Conditions The CS5124/6 recognizes the following faults: UVLO off, Thermal Shutdown, V REF(OK), and Second Current Threshold. Once a fault is recognized, fault latch F2 is set and the IC immediately shuts down the output driver and discharges the Soft Start capacitor. Soft Start will begin only after all faults have been removed and the Soft Start capacitor has been discharged to less than 0.275V. Each fault will be explained in the following sections.

Theory of Operation: continued

Application Information

Under Voltage Lockout (UVLO) The UVLO pin is tied to typically the midpoint of a resis- tive divider between VIN and GROUND. During a start up sequence, this pin must be above 2.6V in order for the IC to begin normal operation. If the IC is running and this pin is pulled below 1.8V, F2 shuts down the output driver and discharges the Soft Start capacitor in order to insure proper start-up. If the UVLO pin is pulled high again before the Soft Start capacitor discharges, the IC will complete the Soft Start discharge and, if no other faults are present, will immediately restart the power supply. If the UVLO pin stays low, then it will enter either the low current sleep mode or the UVLO state depending on the level of the UVLO pin. Thermal Shutdown If the IC junction temperature exceeds approximately 150°C the thermal shutdown circuit sets F2, which shuts down the output driver and discharges the Soft Start capacitor. If no other faults are present the IC will initiate Soft Start when the IC junction temperature has been reduced by 25°C. V REF(OK) VREF(OK) is an internal monitor that insures the internal regulator is running before any switching occurs. This function does not trip the fault comparator like the other fault functions. To insure that Soft Start will occur at low line conditions the UVLO divider should be set up so that the V CC UVLO comparator turns on before the LINE UVLO comparator. Second Threshold Comparator Since the maximum dynamic range of the ISENSE signal in normal operation is 195mV (335mV for the CS5126), any voltage exceeding this threshold on the I SENSE pin is con- sidered a fault and the PWM cycle is terminated. The 2nd I COMP compares the ISENSE signal with a 275mV (525mV for the CS5126) threshold. If the ISENSE voltage exceeds the second threshold, F2 is set, the driver turns off, and the soft-start capacitor discharges. After the Soft Start capacitor has discharged to less than 0.275V Soft Start will begin. If the fault condition has been removed the supply will oper- ate normally. If the fault remains the supply will operate in hiccup mode until the fault condition is removed. V FB Comparator The VFB comparator detects when the output voltage is too high. When the regulated output voltage is too high, the feedback loop will drive V FB low. If VFB is less than 0.49V the output of the VFB comparator will go high and shut the output driver off. Oscillator The internally trimmed, 400kHz (CS5124) or 200kHz (CS5126) provides the slope compensation ramp as well as the pulse for enabling the output driver. PWM Comparator and Slope Compensation The CS5124/6 provides a fixed internal slope compensa- tion ramp that is subtracted from the feedback signal. The pwm comparator compares peak primary current to a por- tion of the difference of the feedback voltage and slope compensation ramp. The 170mV/µs (85mV/µs for the CS5126) slope compensation ramp is subtracted from the voltage feedback signal internally. The difference signal is then divided by ten (five for the CS5126) before the PWM comparator to provide high noise rejection with a low volt- age across the current sense network. (The effective ramp is 21mV/µs for the CS5124, and 18mV/µs for the CS5126). A 60mV (125mV for the CS5126) nominal offset on the pos- itive input to the PWM comparator allows for operation with the I SENSE pin at, or even slightly below Gnd. A 4.3kΩ pull-up resistor internally connected to a 5V nomi- nal reference provides the bias current to for an opto-cou- pler connection to the V FB pin. UVLO and Thermal Shutdown Interaction The UVLO pin and thermal shutdown circuit share the same internal comparator. During high temperature opera- tion (T J >100°C) the UVLO pin will interact with the ther- mal shutdown circuit. This interaction increases the turn- on threshold (and hysteresis) of the UVLO circuit. If the UVLO pin shuts down the IC during high temperature operation, higher hysteresis (see hysteresis specification) might be required to enable the IC. BIAS Pin (CS5124 Only) The bias pin can be used to control V CC as shown in the main application diagram. In order to provide adequate phase margin for the bias control loop, the pole created by the series pass transistor and the V CC bypass capacitor should be kept above 10kHz. The frequency of this pole can be calculated by Formula (1). Pole Frequency = (1) Transconductance of pass Transistor 2 × π × CV(CC)

Application Information: continued CS5124/6 A large negative dv/dt on the power MOSFET drain will couple current into the gate driver through the gate to drain capacitance. If this current is kept within absolute maximum ratings for the GATE pin it will not damage the IC. However if a high negative dv/dt coincides with the start of a PWM duty cycle, there will be small variations in oscillator frequency due to current in the controller sub- strate. If required, this can be avoided by choosing the transformer ratio and reset circuit so that a high dv/dt does not coincide with the start of a PWM cycle, or by clamping the negative voltage on the GATE pin with a schottky diode First Current Sense Threshold During normal operation the peak primary current is con- trolled by the level of the V FB pin (as determined by the control loop) and the current sense network. Once the sig- nal on the I SENSE pin exceeds the level determined by VFB pin the pwm cycle terminates. During high output currents the V FB pin will rise until it reaches the VFB clamp. The first current sense threshold determines the maximum signal allowed on the I SENSE pin before the PWM cycle is termi- nated. Under this condition the maximum peak current is determined by the V FB Clamp, the slope compensation ramp, the PWM comparator offset voltage and the PWM on time. The nominal first current threshold varies with on time and can be calculated from Formulas (2) & (3) below. CS5124 1st Threshold = – 60mV (2) CS5126 1st Threshold = – 125mV (3) When the output current is high enough for the I SENSE pin to exceed the first threshold, the pwm cycle terminates early and the converter begins to function more like a cur- rent source. The current sense network must be chosen so that the peak current during normal operation does not exceed the first current sense threshold. Second Current Sense Threshold The second threshold is intended to protect the converter from over-heating by switching to a low duty cycle mode when there are abnormally high fast rise currents in the converter. If the second current sense threshold is tripped, the converter will shut off and restart in Soft Start mode until the high current condition is removed. The dead time after a second threshold over-current condition will pri- marily be determined by the time required to charge the Soft Start cap from 0.275V nominal to 1.32V. The second threshold will only be reached when a high dv/dt is present at the current sense pin. The signal must be fast enough to reach the second threshold before the first threshold turns off the driver. This will normally hap- pen if the forward inductor saturates or when there is a shorted load. Excessive filtering of the current sense signal, a low value current sense resistor, or even an inductor that does not saturate during heavy output currents can prevent the sec- ond threshold from being reached. In this case the first cur- rent sense threshold will trip during each cycle of high out- put current conditions. The first threshold will limit output current but some components, especially the output rectifi- er, can overheat due to higher than normal average output current. Slope Compensation Current mode converters operating at duty cycles in excess of 50% require an artificial ramp to be added to the current waveform or subtracted from the feedback waveform. For the current loop to be stable the artificial ramp must be equivalent to at least 50% of the inductor current down slope and is typically chosen between 75 % to 100% of the inductor down current down slope. To choose an inductor value such that the internal slope compensation ramp will be equal to a certain fraction of the inductor down current slope use the Formula (4). × (V OUT + VRECTIFIER) ×× RI(SENSE) × Slope Value Factor = Inductor Value (H) (4) Calculating the nominal inductor value for an artificial ramp equivalent to 100% of the current inductor down slope at CS5126 nominal conditions, a 5V output, a 200mΩ current sense resistor and a 4:1 transformer ratio yields To check that the slope compensation ramp will be greater than 50% of the inductor down under all conditions, sub- stitute the minimum internal slope compensation value and use 0.5 for the slope compensation value. Then check that the actual inductor value will always be greater than the inductor value calculated. During synchronized operation of the CS5126 the slope compensation ramp is reduced by 33%. If the CS5126 will 20mV/µs NSECONDARY NPRIMARY Internal Ramp 2.65V – 85mV/µs × TON 2.9V – 170mV/µs × TON

be used in synchronized operation, the inductor value should be recalculated to work with the slope compensa- tion ramp reduced to 67% of the normal value. Powering the CS5124/6 from a Transformer Winding There are numerous ways to power the CS5124/6 from a transformer winding to enable the converter to be operated at high efficiency over a wide input range. Two ways are shown in the application circuits. The CS5124 application circuit (main application diagram) is a flyback converter that uses a second flyback winding to power V CC. R4 improves VCC regulation with load changes by snubbing the turn off spike. Once the turn off spike has subsided the voltage of this winding is voltage proportional to the voltage on the main flyback winding. This voltage is regulated because the main winding is clamped by the regulated output voltage. In the CS5126 application circuit (below) an extra winding is added to the forward inductor to power V CC. This wind- ing is phased to conduct during the off time of the forward converter and performs the same function as the flyback winding above. A flyback winding from a forward transformer can also be used to power VCC. Ideally the transformer volt-second product of a forward converter would be constant over the range of line voltages and load currents; and the trans- former inductance could be chosen to store the required level of energy during each cycle to power V CC. Even though the flyback energy is not directly regulated it would remain constant. Unfortunately in a real converter there are many non-ideal effects that degrade regulation. Transformer inductance varies, converter frequency varies, energy stored in primary leakage inductance varies with output current, stray transformer capacitances and various parasitics all effect the level of energy available for V CC. If too little energy is provided to VCC, the bootstrapping cir- cuit must provide power and efficiency will be reduced. If too much energy is provided V CC rises and may damage the controller. If this approach is taken the circuit must be carefully designed and component values must be con- trolled for good regulation. Application Information: continued Additional Application Diagram VCC UVLO SS Gnd GATE IS VFB 0.2Ω 1/4W IRF634 17.4k 1.5µF, 100VC3 0.2µF, 100V 10µH 36-75VIN 39k C12 .01µF .01µF 30.1k 47µF ISOLATED RTN 5VOUT ENABLE 48VRTN C10 1000pF C11 0.1µF TPS5908 10.0k SYNC 1.5µF, 100V SYNC CS5126 200k MMBD6100L 1µF, 25V 390pF C8 47µF 11V R10 10k 10k C4 1000pF F2T493 MBRB2060CT CTX15-14527CTX15-14526 48V to 5V, 5A forward converter using the CS5126

10 © 1999 Cherry Semiconductor CorporationRev. 3/12/99 Part Number Description CS5124XD8 8 Lead SO Narrow CS5124XDR8 8 Lead SO Narrow (tape & reel) CS5126XD8 8 Lead SO Narrow CS5126XDR8 8 Lead SO Narrow (tape & reel) Thermal Data 8L SO Narrow RΘJC typ 45 ˚C/W RΘJA typ 165 C/W D Lead Count Metric English Max Min Max Min 8 Lead SO Narrow 5.00 4.80 .197 .189 Package Specification PACKAGE DIMENSIONS IN mm (INCHES) PACKAGE THERMAL DATA

Ordering Information

Cherry Semiconductor Corporation reserves the right to make changes to the specifications without notice. Please contact Cherry Semiconductor Corporation for the latest available information. Surface Mount Narrow Body (D); 150 mil wide 0.33 (.013) 6.20 (.244) 5.80 (.228) 4.00 (.157) 3.80 (.150) 1.57 (.062) 1.37 (.054) D 0.25 (0.10) 0.10 (.004) 1.75 (.069) MAX 1.27 (.050) 0.40 (.016) REF: JEDEC MS-012 0.25 (.010) 0.19 (.008)