CPS-8

CPS-8 RENESAS

Document overview

• Manufacturer or author: Integrated Device Technology
• PDF pages: 48

Technical content

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1 Device Overview

The CPS-8, device number IDT80KSW0003, is a serial RapidIO (sRIO) switch whose functionality is central to routing packets for distribution among DSPs, processors, FPGAs, other switches, or any other sRIO-based devices. It may also be used in serial RapidIO backplane switching. The CPS-8 supports serial RapidIO packet switching (unicast, multicast, and an optional broadcast) from any of its 8 input ports to any of its 8 output ports.

2 Features

– 8 bidirectional serial RapidIO (sRIO) lanes v 1.3 – Port Speeds selectable: 3.125Gbps, 2.5Gbps, or 1.25Gbps – All lanes support short haul or long haul reach for each PHY speed – Configurable port count to up to eight 1x ports, two 4x ports, or 4 1x and 1 4x ports – Lanes can be configured as individual non-redundant 1x ports, as part of a redundant 1x port, or as part of a 4x port – Support for two separate port rates for each quad – Supports standard 4 levels of priority – Error management support u Interfaces - I2C – Provides I2C port for maintenance and error reporting – Master or Slave Operation – Master allows power-on configuration from external ROM – Master mode configuration with external image compressing and checksum u Performance – 20 Gbps of peak switching bandwidth – Non-blocking data flow architecture within each sRIO priority – Very low latency for all packet length and load condition – Internal queuing buffer and retransmit buffer – Standard receiver based physical layer flow control u Features – Configurable for Cut Through or Store And Forward data flow – Device configurable through any of sRIO ports, I2C, or JTAG – Packet Trace. Each port provides the ability to match the first 160 bits of any packet against up to 4 programmable comparison values to copy the packet to a programmable output trace port – Packet Filter. Each port also provides the ability to filter the packet based on comparisons against these same 4 programmable values mentioned above – Supports up to 10 simultaneous multicast masks – Broadcast support – Port Loopback Debug Feature – Software assisted error recovery, supporting hot swap – Ports may be individually turned off to reduce power – PMON counters for monitor and diagnostics. Per input port and output port counters – SerDes physical diagnostic registers – Embedded PRBS generation and detection with programmable poly- nomials support Bit Error Rate (BER) testing – 0.13um technology – Low power dissipation – Full JTAG Boundary Scan Support (IEEE1149.1 & 1149.6) – Package: 324-ball grid array, 19mm x 19mm, 1.0mm ball pitch

3 Block Diagram

pidIO® Switch Serial RapidIO Switch sRIO Enhanced Quad (up to 4 ports) sRIO Enhanced Quad (up to 4 ports) Ln0 Ln1 Ln2 Ln3 Ln4 Ln5 Ln6 Ln7 Mai ntenance Er r or Management Confi gurationJTAG I 2 C

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4 Device Description

The CPS-8 is optimized for DSP cluster applic ations at board level. Its main function is to have a backplane interface which ca n connect to a back- plane switch or directly to multiple RF cards. On the line card side it can also connect to multiple ports. It supports up to 8 ports which are configurable as line card, or backplane ports. It is an end-point free (switch) device in an sRIO network. The CPS-8 receives packets from up to 8 ports. The CPS offers full support for normal switching as well as enhanced functions: 1) Normal S witching: All packets are switched in accordance with standard serial RapidIO specifications, with packet destination IDs determining how the packet is routed. Three major options exist within this category: a. Multicast: If a Multicast ID is received, the CPS-8 performs a multicast as defined in the sRIO multicast registers. b. Unicast: All o ther operations are performed as specified in sRIO. c. Ma intenance packets: As specified by sRIO. The sRIO Switch supports a peak throughput of 20 Gbps which is the line rate for 8 ports in 1x configuration, each at 2.5 Gbps (3.125 Gbps minus the sRIO-defined 8b10b encoding), and switches dynamically in accordance with the packet headers and priorities. 2) En hanced functions Enhanced features are provided for support of system debug. These features which are opti onal for the user consist of two major functions: a. P acket Trace: The Packet Trace feature provides at-speed checking of the first 160 bits (header plus a portion of any payload) of every incom- ing packet against user-defined com parison register values. The trace feature is available on all serial RapidIO ports, each ac ting indepen- dently from one another. If the trace feature is enabled for a given port, every incoming packet is checked for a match against up to four comparison registers. In the event of a match, either of two possible user defined actions may take place: i) not only does the packet route normally through the switch to its appropriate destination port, but this same packet is replicated and sent to a “trace port.” The trace port itself may be any of the standard serial RapidIO ports. The port us ed for the trace port is defined by the user through simple register configuration. ii) th e packet is dropped. If there is no match, the packets route normally through the switch with no action taken. The Packet Trace feature can be used during system bring-up and prototyping to identify particular packet types of interest to the user. It might be used in security applications, where packets must be checked for either correct or incorrect tags in either of the header or payload. Identi- fied (match) packets are then routed to the trace port for receipt by a host processor, which can perform an intervention at the software level. b. Port Loopba ck: The CPS-8 offers internal loopback for each port that may be used for system debug of the high speed sRIO por ts. By enabling loopback on a given port, packets sent to the port’s receiver are immediatel y looped back at the physical layer to the transmitter - bypassing the higher logical or transport layers. Broadcast: Each multicast mask can be configured so that the source port is included among the destination ports for that multicast operation. The CPS-8 can be programmed through any one or combination of sRIO, I 2C, or JTAG. Note that any sRIO port may be used for programming. The CPS-8 can also configure itself on power-up by reading directly from ROM over I2C in master mode.

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5 Applications

Central switch based wireless processing Figure 2 Application Overview Note: The CPS-8 provides direct support for backplane connecti ons using the serial RapidIO standard. The addition of an appropriate bridge (e.g., CPRI  sRIO) allows for further backplane flexibility, accommodat ing designs based on a wide range of standards such as CPRI, OBSAI, GbE or PCIe. In a macro wireless station, a switch-based raw data combinat ion and distribution architecture is widely adopted. Switch based architecture provides high flexibility and high resource efficiency. The raw data from the Radio Unit is di stributed to one or more processing cards by unicast or multicast. Aggregating raw data from processing cards to a bufferless chain can be done by a fast non-blocking switch. Media Gateway and general processing Note: The CPS-8 provides direct support for backplane connections using the serial RapidIO standard. Though SAR and RTP is usually processed by NP/Processor, DSP is more efficient for TDM conversion and compression. A low jitter switch enables the full utilization of DSP processing power. Priority support, fast switching, and multicasting will differentiate class of traffic to provide QoS.

6 Functional Overview

IDT’s CPS-8 is optimized for either board- level DSP/ASIC cluster applications or m odule-level distributed processing applicatio n. Up to 8 serial or long haul. The CPS-8 switch has a sustained 20Gbps bandwidth. Also three major options exist within this category: a. Multicast: If a Multicast ID is received, the CPS-8 performs a multicast as defined by the devic e’s configurable sRIO multicast mask registers. Also optional for broadcast. b. Unicast: All other operations are performed as specified in sRIO. Maintenance packets: As specified in sRIO. The CPS-8 supports a “Store and Forward” and an optional “Cut Through” packet forward methodology. Refer to “CPS-8 User Manual” for details. The CPS-8 can be programmed through a CPU or a DSP connected to one of the sRIO ports of the device or with a CPU connected to an I2C or JTAG bus. It can also work along with a I2C configuration memory. This option is added to allow the CPS-8 to work in “remote stand alone” mode. 80KSW 0003 Seri al Rapi dI O DSPDSP CPU To/ From TDM based To/ From IP based W AN/Publ i c

4 of 47 March 31, 2008 IDT80KSW0003 Datasheet Each sRIO port provides a packet trace capability. For any pa cket received by a port, a comparison between the first 160 bits a nd up to four configu- rable values can be performed. A match against any of these parameters will result in a copy of the packet and a route of the packet to a configurable ouput port. This feature can be used as a tact ical function to track user data or in a debug environment to test how specific p ackets are moving through the platform. Each sRIO port also provides a packet filter capability. For any packet received by a port, a comparison between the first 160 bits and up to the same four configurable values mentioned above can be performed. A match against any of these parameters will result in the packet being filtered.

7 Interface Overview

Figure 3 Diagram of the CPS-8 Interfaces sRIO Ports The sRIO interfaces are the main communica tion ports on the chip. These ports are compli ant with the serial RapidIO v. 1.3 spec ifications. Please refer to the serial RapidIO specifications for full detail [2-10]. The device provides 8 differential dual simplex transceivers dedicated to sRIO I/O. These can be independently configured to run in various configura- tions as 1x- or 4x-ports. The CPS-8 supports a maximum of 2 times 4x-ports, or 8 times 1x-ports, as well as 4 1x and 1 4x ports. The device has a proprietary implementation which we refer to as an “Enhanced Quad.” An Enhanced Quad can be operated in standard sRIO mode like the standard quads. Additionally the Enhanced Quad can be register-configured to run as 4 independent 1x-ports - any of which can be enabled at a given time. In this manner, the user has the flexibility to us e one, multiple, or all four lanes in 1x-mode. For example, lan es 0 - 3 are programmable into one 4x- or four 1x-ports. This is unlike the standard sRIO port implementation that, when configured as a 1x-port, renders the remaining 3 possible connections unused. The device control of each of lane parameter s (data rate, transmitter pre-emphasis, dr ive strength) can be separately configured, such that the char- acteristics for lanes 0 and 1 can be different from those for lanes 2 and 3 in one quad. The ability to control reset and initi alization of lanes 0 and 1 versus lanes 2 and 3 separately is also provided. So each 2 lanes (lanes 0, 1 and lanes 3,4) at the granularity of the half quad can be programmed to run independently at 1.25, 2.5, or 3.125Gbps and handle long or short haul serial transmission per RIO serial specification. IDT CPS-8

8 Differential sRIO Lanes

1.25, 2.5, or 3.125 Gbps I2C Interface 400KHz JTAG Interface RST REF_CLK IRQ Rext SPD[1:0]

5 of 47 March 31, 2008 IDT80KSW0003 Datasheet I2C Bus This interface may be used as an alternative to the standard sRIO or JTAG ports to program the chip and to check the status of registers - including the error reporting registers. It is fully compliant with the I2C specification, it supports master mode and slave mode, also supports both Fast-mode and Standard-mode buses [1]. Refer to the “I2C” section for full detail. JTAG TAP Port This TAP interface is IEEE1149.1 (JTAG) and 1149.6 (AC Extest) compliant [10, 11]. It may also be used as an alternative to the standard sRIO or I2C ports to program the chip and to check the status of register s - including the error reporting registers. It has 5 pins. Refer to the JTAG chapter for full detail. Interrupt (IRQ) An interrupt output is provided in suppor t of Error Management functionality. This output may be used to flag a host processor in the event of error conditions within the device. Refer to the Error Handling chapter for full detail. Reset A single Reset pin is used for full reset of the CPS-8, including setting all registers to power-up defaults. Refer to the Reset & Initialization chapter for full detail. Clock The single system clock (REF_CLK+ / -) is a 156.25MHz differential clock. Rext (Rextn & Rextp) These pins are used to establish the drive bi as on the SerDes output. An external bias resistor is required. The two pins must be connected to one another with a 12k Ohm resistor. This provides CML driver stability across process and temperature. SPD[1:0] Speed Select Pins. These pins define the sRIO port speed at RESET for all ports. The RESET setting may be overridden by subsequent programming before power-up.

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8 Absolute Maximum Ratings(1)

Table 1 Absolute Maximum Rating NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these o r any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to abso lute maximum rating conditions for extended periods may affect reliability. 2. This is a ste ady-state DC parameter that applies after the power supply has reached its nominal operating value. Power sequencing is not necessary; however, the voltage on any Input or I/O pin cannot exceed its corresponding supply volta ge during power supply ramp up. 3. Ambient Temperature under DC Bias. No A C Conditions. Symbol Rating Commercial & Industrial Unit VTERM (VDD3)V DD3 Terminal Voltage with Respect to GND -0.5 to 3.6 V VTERM (2) (VDD3-supplied inter faces) Input or I/O Terminal Voltage with Respect to GND -0.3 to V DD3+0.3 V VTERM (VDD)V DD Terminal Voltage with Respect to GND -0.5 to 1.5 V VTERM (2) (VDD-supplied inter faces) Input or I/O Terminal Voltage with Respect to GND -0.3 to V DD+0.3 V VTERM (VDDS)V DDS Terminal Voltage with Respect to GNDS -0.5 to 1.5 V VTERM (2) (VDDS-supplied inter faces) Input or I/O Terminal Voltage with Respect to GNDS -0.3 to V DDS+0.3 V VTERM (VDDA)V DDA Terminal Voltage with Respect to GNDS -0.5 to 1.5 V VTERM (2) (VDDA-supplied inter faces) Input or I/O Terminal Voltage with Respect to GNDS -0.3 to V DDA+0.3 V TBIAS (3) Temperature Under Bias -55 to +125 C TSTG Storage Temperature -65 to +150 C TJN Junction Temperature +125 C IOUT (For VDD3 = 3.3V) DC Output Current 30 mA IOUT (For VDD3 = 2.5V) DC Output Current 30 mA

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9 Recommended Temperature and Operating Voltage1

Table 2 Recommended Temperature and Operating Voltage NOTES: 1. Power sequencing is not necessary; however, the voltage on any Input or I/O pin cannot exceed its corresponding supply volt age during power supply ramp up. The device is not sensitive to supply rise and fall times, and thus these are not specified. 2. VDD3, VDDA, and VDDS share a common ground (GNDS). Core supply and ground are VDD and GND respectively. 3. VDD3 may be operated at either 3.3V or 2.5V simply by providing that supply voltage. Fo r those interfaces operating on this supply, this datasheet provides input and output specifications at each of these voltages. 4. VDDS & VDDA may be tied to a common power plane. VDD (core, digital supply) should have its own supply and plane.

10 AC Test Conditions

Ground(2) Supply Voltage(4) Commercial 0C to 70C GND = 0V GNDS = 0V VDD = 1.2 +/- 5% VDDS = 1.2 +/- 5% or 2.5V +/- 100mV VDDA = 1.2 +/- 5% Industrial -40C to 85C GND = 0V GNDS = 0V VDD = 1.2 +/- 5% VDDS = 1.2 +/- 5% or 2.5V +/- 100mV VDDA = 1.2 +/- 5% Input Pulse Levels GND to 3.0V / GND to 2.4V Input Rise / Fall Times 2ns Input Timing Refer- ence Levels 1.5V / 1.25V Output Reference Levels 1.5V / 1.25V Output Load Figures 4 Table 3 AC Test Conditions (VDD3=3.3V / 2.5V): JTAG, I2C, RST

8 of 47 March 31, 2008 IDT80KSW0003 Datasheet Figure 4 AC Output Test Load (JTAG) Figure 5 AC Output Test Load (IRQ) NOTE: The IRQ pin is an open-drain driver. IDT recommends a weak pull-up resistor (2-10k Ohm) be placed on this pin to VDD3. Figure 6 AC Output Test Load (I2C) NOTE: The SDA and SCL pins are open-drain drivers. Refer to the Philips I2C specification [1] for appropriate selection of pull-up resistors for each.

50 OhmDATAout

10pF (TESTER)

50 Ohm

1.5V / 1.25V IRQ 400pF (max) 2–10k Ohm 3.3V / 2.5V SDA, SCL 400pF (max) 2k Ohm 3.3V / 2.5V

9 of 47 March 31, 2008 IDT80KSW0003 Datasheet Figure 7 sRIO Lanes Test Load The characteristic impedance Z0 should be designed for 100 Ohms. An inline capacitor C1 and C2 at each input of the receiver provides AC-coupling and a DC-block. The IDT recommended and test value is 100nF for eac h. Thus, any DC bias different ial between the two devices on the link is negated. The differential input resistance at the receiver is des igned to be 100 Ohms (per sRIO specification). Thus, R1 and R2 are 50 Ohms each. Note that VBIAS is the internal bias voltage of the device’s receiver.

11 Device Performance Figures

The following table lists the CPS-8’s performance figure. Figures provided here are guaranteed by design and characterization, but are not production tested. Table 4 80KSW0003 Performance Figures NOTES: 1. Values are guaranteed by characterization, but are not production tested. 2. For those specifications associated wi th an sRIO transaction, it should be noted t hat the upper limit to a specification may be dictated by sRIO priority handling. For example, a maintenance read packet having lower priority may be held off until higher priority packets in queue are serviced. The user should take into consideration this additional priority-induced delay w hen examining these specifications. I 2C and JTAG configuration register access transactions are always deterministic and follow these specifications identically. 3. “Cycles” refer to internal core clock cycles which are two times the external reference clock (REF_CLK) frequency = 312.5 MHz. Description Min Typ Max Units Comments Switch Throughput (Peak) - - 20 Gbps Switch Throughput (Sustained) - 17 - Gbps Value shown is for device configured for 2 4X ports, each running at 3.125Gbps, 276 byte packets at priority 0. Please contact IDT technical support for figures related to a specific usage case and traffic conditions. Switch Latency Jitter (70% switch load) 2 -6 0 - n s Latency Jitter for the switch lock is the sum of the Physical layer jitter plus one maintenance packet of contention delay for a given output port. Worst case for the physical layer is the jitter caused by the port sync process. This requires 6 32-bite control symbols plus 2 cycles times the port rate. The figures shown here are for priority 2 packets under 70% switch loading with an even mix of packets of each priority. It assumes that no maintenance packets contend on the output port. Soft Reset to Receipt of Valid Packets - - 26 us This in cludes reset time as well as link establishment. Hard Reset to Receipt of Valid Packets - - 26 us This in cludes reset time as well as link establishment. Multicast Map Update Delay 25 - 2000 cycles Tx TXP TXN Rx RXP RXN Vbias

10 of 47 March 31, 2008 IDT80KSW0003 Datasheet Switch Latency in “Store-and-Forward” mode Table 5 Switch Latency Table (Store-and-Forward mode) 1) Values are guaranteed by characterization, but are not production tested. 2) For those specifications associated wi th an sRIO transaction, it should be noted t hat the upper limit to a specification may be dictated by sRIO priority handling. For example, a maintenance read packet having lower priority may be held off until higher priority packets in queue are serviced. The user should take into consideration this additional priority-induced delay when examining these specifications. I2C and JTAG transactions are always deterministic and follow these specifications identically. 3) Switch latency is a statistical functi on, which typically increases with increas ed traffic loading on the switch. Values sho wn in Table 5 are for single input port to single output port with matching input and out put port rates in “Store-and-Forward” mode, no other switch loading. The switch latency in “Store-and-Forward” packet forward methodology is also a strong function of po rt rate. For specific values under oth er specific applica- tion usage scenarios and traffic conditions, please contact IDT technical support. Switch Latency in “Cut-Through” mode Table 6 Switch Latency Table (Cut-Through mode) 1) Values shown in Table 6 are typical for single input port to single output port with matching input and output port rates in “Cut-Through” mode, no other switch loading. For specific values under other specific application usage scenarios and traffic conditions, please contact IDT technical support. Note: In "Store-and-Forward" mode and "Cut-Through" mode when trace and filter are enabled at the same time, the latency for packets sent to the trace port will increase by the time taken to send 20 bytes into the port ([20 bytes * 8 ] * 1/[port_speed * 0.8]). The latency for other traffic flow will be unaffected. Pay Load Size 1.25GHz 2.5GHz 3.125GHz 1X 4X 1X 4X 1X 4X

8 Byte 456 ns 343 ns 277 ns 225 ns 246 ns 209 ns

16 Byte 517 ns 360 ns 311 ns 231 ns 267 ns 213 ns

32 Byte 652 ns 435 ns 375 ns 272 ns 320 ns 239 ns

64 Byte 902 ns 500 ns 501 ns 305 ns 422 ns 263 ns

128 Byte 1425 ns 722 ns 757 ns 417 ns 630 ns 352 ns

256 Byte 2451 ns 1071 ns 1273 ns 590 ns 1035 ns 492 ns

Control Symbol 115 ns 105 ns 60 ns 55 ns 50 ns 45 ns Pay Load Size 1.25GHz 2.5GHz 3.125GHz 1X 4X 1X 4X 1X 4X

8 Byte 366 ns 322 ns 244 ns 216 ns 208 ns 199 ns

16 Byte 363 ns 324 ns 234 ns 215 ns 206 ns 197 ns

32 Byte 365 ns 316 ns 232 ns 215 ns 205 ns 198 ns

64 Byte 365 ns 318 ns 234 ns 219 ns 204 ns 198 ns

128 Byte 372 ns 314 ns 233 ns 217 ns 210 ns 196 ns

256 Byte 371 ns 312 ns 238 ns 216 ns 205 ns 195 ns

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12 Typical Power Figures

Typical power draw for the 80KSW0003 is approximately 2.3W total for all ports enabled as 2 4x @ 3.125G under 50% switch load. The following table provides power figures on a per-block basis. An estimate of the device power figure for a given application usage can be determined by using the “CPS Power Calculator” modeling tool available on www.IDT.com Table 7 Typical Power Figures Condition: VDD = 1.2V, VDDS = 1.2V, VDDA = 1.2V, VDD3 = 3.3V @ Room temperature 25oC temperature and process range. Description Type Units Supply Comments SerDes 1x @ 1.25G 45 mW V DDS, VDDA Analog SerDes power consumption (VDDS and VDDA). This does not include the sRIO quad power consumption. SerDes 1x @ 2.5G 60 mW V DDS, VDDA Analog SerDes power consumption (VDDS and VDDA). This does not include the sRIO quad power consumption. SerDes 1x @ 3.125G 75 mW V DDS, VDDA Analog SerDes power consumption (VDDS and VDDA). This does not include the sRIO quad power consumption. SerDes 4x @ 1.25G 200 mW V DDS, VDDA Analog SerDes power consumption (VDDS and VDDA). This does not include the sRIO quad power consumption. SerDes 4x @ 2.5G 220 mW V DDS, VDDA Analog SerDes power consumption (VDDS and VDDA). This does not include the sRIO quad power consumption. SerDes 4x @ 3.125G 245 mW V DDS, VDDA Analog SerDes power consumption (VDDS and VDDA). This does not include the sRIO quad power consumption. JTAG Block Enable 100 mW V DD, VDD3 Configuration Register Access only. Max interface speed(10MHz). I2C Block Enable 20 mW V DD, VDD3 Configuration Register Access only. Max interface speed (400KHz). Switch Block (max traffic) 209 mW V DD Switch block only. All ports enabled and sending traffic at max aggre- gate throughput for the switch block. Standby Power @1.25G 1258 mW V DD Part powered up, reset, all links up (reset configuration), no traffic Standby Power @1.25G 214 mW V DD3 Part powered up, reset, all links up (reset configuration), no traffic Standby Power @1.25G 268, 191 mW V DDS, VDDA Part powered up, reset, all links up (reset configuration), no traffic Quiescent Power 1200 mW V DD Minimum possible operational power draw. All ports disable, I2C and JTAG signals static. Quiescent Power 214 mW V DD3 Minimum possible operational power draw. All ports disable, I2C and JTAG signals static. Quiescent Power 37,32 mW V DDS, VDDA Minimum possible operational power draw. All ports disable, I2C and JTAG signals static. Reset Power 324 mW V DD Peak power during RESET of the device. Reset Power 210 mW V DD3 Peak power during RESET of the device. Reset Power 35, 27 mW V DDS, VDDA Peak power during RESET of the device. Peak sustained Power 1639 mW V DD All sRIO ports enabled at maximum speed, maximum traffic to the switch. Peak sustained Power 214 mW V DD3 All sRIO ports enabled at maximum speed, maximum traffic to the switch. Peak sustained Power 354, 244 mW V DDS, VDDA All sRIO ports enabled at maximum speed, maximum traffic to the switch

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13 I2C-Bus

The CPS-8 is compliant with the I2C specification [1]. This specification provides all functional detail and electrical specifications associated with the I2C bus. This includes signaling, addressing, arbitration, AC timing, DC specifications, and other details. The I2C bus is comprised of Serial Data (SDA) and Serial Clock (SCL) pins. It can be used to attach a CPU or a configuration memory. The I2C interface supports Fast/Standard (F/S) mode (400/ 100 kHz). I2C master mode and slave mode The CPS-8 device supports both master mode and slave mode. It’s selected by MM static configuration pin. Refer to following for signaling and operation. I2C Device Address The device address for the CPS-8 is fully pin-defined by 10 external pins while in slave mode. This provides full flexibility in defining the slave address to avoid conflicting with other I2C devices on a given bus. The CPS-8 may be operated as either a 10-bit addressable device or a 7-bit addressable device based on another external pin, address select (ADS). If the ADS pin is tied to Vdd, then the CPS-8 operates as a 10-bit addressable device and the device address will be defined as ID[9:0]. If the ADS pin is tied to GND, then the CPS-8 operates as a 7-bit addressable device with the device address defined by ID[6:0]. The addressing mode must be established at power-up and remain static throughout operation. Dynamic changes will result in undetermined behavior. Table 8 I2C static address selection pin configuration All of the CPS-8’s registers are addressable through I2C. These registers are accessed via 22-bit addresses and 32-bit word boundaries though standard reads and writes. These registers may also be accessed through the sRIO and JTAG interfaces. Signaling Communication with the CPS-8 on the I2C bus follows these three cases: 1) Suppose a master device wants to send information to the CPS-8: – Master device addresses CPS-8 (slave) – Master device (master-transmitter), sends data to CPS-8 (slave- receiver) – Master device terminates the transfer 2) If a master d evice wants to receive information from the CPS-8: – Master device addresses CPS-8 (slave) – Master device (master-receiver) receives data from CPS-8 (slave- transmitter) – Master device terminates the transfer. Pin I2C Address Bit (pin_addr) ID0 0 ID1 1 ID2 2 ID3 3 ID4 4 ID5 5 ID6 6 ID7 7 (don’t care in 7-bit mode) ID8 8 (don’t care in 7-bit mode) ID9 9 (don’t care in 7-bit mode)

13 of 47 March 31, 2008 IDT80KSW0003 Datasheet 3) If CPS-8 polls configuration image from external memory – CPS-8 addresses the memory. – Memory transmits the data. – CPS-8 gets the data. All signaling is fully compliant with I2C. Full detail of signaling can be found in the Philips I2C specification [1]. Standard signalling and timing waveforms are shown below. Interfacing to Standard-, Fast-, and Hs-mode Devices The CPS-8 supports Fast / Standard (F/S) modes of operation. Per I2C specification, in mixed speed communication the CPS-8 supports Hs- and Fast-mode devices at 400 kbit/s, and Standard-mode devices at 100 kbit/s. Please refer to the I2C specification for detail on speed negotiation on a mixed speed bus. CPS-8 Specific Memory Access (Slave mode) There is a CPS-8 specific I2C memory access implementation. This implementation is fully I2C compliant. It requires the memory address to be explicitly specified during writes. This provides directed memory accesses through the I2C bus. Subsequent reads always begin at the address specified during the last write. The write procedure requires the 3-Bytes (22-bits) of memory address to be provided following the device address. Thus, the following are required: device address – one or two bytes depending on 10-bit / 7-bit addressing, memory address – 3 bytes yielding 22-bits of memory address, and a 32- bit data payload – 4 byte words. To remain consistent with sRIO standard maintenance packet memory address convention, the I2C memory address provided must be the 22MSBs. Since I2C writes to memory apply to double words (32-bits), the 2 LSBs are DON’T CARE as the LSBs correspond to word and byte pointers. The read procedure has the memory address section of the transfer removed. Thus, to perform a read, the proper access would be to perform a write operation and issue a repeated start after the acknowledge bit following the third byte of memory address. Then, the master would issue a read command selecting the CPS-8 through the standard device address procedure with the R/W bit high. Note that in 10-bit device address mode (ADS=1), only the two MSBs need be provided during this read. Data from the previously loaded address would immediately follow the device address protocol. It is possible to issue a stop or repeated start anytime during the write data payload procedure, but must be before the final acknowledge (i.e. canceling the write before the actual write operation is completed and performed). Also, the master would be allowed to access other devices attached to the I 2C bus before returning to select the CPS-8 for the subsequent read operation from the loaded address. Figures Figure 8 Write protocol with 10-bit Slave Address (ADS =1). I2C writes to memory align on 32-bit word boundaries, thus the 22 address MSBs must be provided while the 2 LSB’s associated with word and byte pointers are DON’T CARE and are therefore not transmitted. 5686 d 05 Device Address [9:8] 11110 0 AA A A A Memory Address [21:16] R/W Bit (R=1, W=0) 81 7 2 6 3 5 4 4 Memory address loaded is mem_addr[21:0] XX A 000 Device Address [7:0] Memory Address [15:8] Memory Address [7:0] Data Word #1 MSB Byte Incoming data will be written to mem_addr[21:0]

14 of 47 March 31, 2008 IDT80KSW0003 Datasheet Figure 9 Read Protocol with 10-bit Slave Address (ADS=1) Figure 10 Write protocol with 7-bit Slave Address (ADS=0). I2C writes to memory align on 32-bit word boundaries, thus the 22 address MSBs must be provided while the 2 LSB’s associated with word and byte pointers are DON’T CARE and are therefore not transmitted. Figure 11 Read protocol with 7-bit Slave Address (ADS=0) CPS-8 configuration and image (Master mode) There is both a power up master and a command master mode. If powered up in master mode, the CPS-8 polls configuration image from external memory after the device reset sequence has completed. Once the device has completed its configuration sequence, it will revert to slave mode. Through a configuration register write, the device can be commanded to enter master mode, which provides more configuration sequence flexibility. Refer to “CPS-8 User Manual” for details. Note that the ADS and ID pins will all run off the core (1.2V) power supply, and these pins are required to be fixed during operation. Thus, these pins must be statically tied to the 1.2V supply or GND. Tables 9 through 11 below list the SDA and SCL electrical specifications for F/S-mode I2C devices: Device Address [9:8] 1 1110 1 AA A A A Data Word #1 MSB Byte Data Word #1 Byte #2 Data Word #1 Byte #3 Data Word #1 LSB Byte R/W Bit (R=1, W=0) 81 7 2 6 3 5 4 4 Data output is from base mem_addr[21:0] Device Address [6:0]

0 AA A A A

[21:16] R/W Bit (R=1, W=0) 81 7 26 35 44 Memory address loaded is mem_addr[21:0] XX A 000 Memory Address [15:8] Memory Address [7:0] Data Word #1 MSB Byte Incoming data will be written to mem_addr[21:0] Data Word #1 Byte #2 R/W Bit (R=1, W=0) A 2617 Device Address [6:0] A A 1 A Data Word #1 MSB Byte Data Word #1 Byte #2 Data Word #1 Byte #3 Data Word #1 LSB Byte Data output is from base mem_addr[21:0]

15 of 47 March 31, 2008 IDT80KSW0003 Datasheet At recommended operating conditions with VDD3 = 3.3V ± 5% Table 9 I2C SDA & SCL DC Electrical Specifications At recommended operating conditions with VDD3 = 2.5V ± 100mV Table 10 I2C SDA & SCL DC Electrical Specifications Parameter Symbol Min Max Unit Input high voltage level V IH 0.7 x V DD3 V DD3 (MAX)+ 0.5 V Input low voltage level V IL -0.5 0.3 x V DD3 V Hysteresis of Schmitt trigger inputs: Vhys 0.05 x V DD3 - Low level output voltage V OL 0 0.2 x V DD3 V Output fall time from VIH(MIN) to VIL(MAX) with a bus capacitance from 10pF to 400pF tOF 20 + 0.1 x C b 250 ns Pulse width of spikes which must be suppressed by the input filter tSP 0 50 ns Input current each I/O pin (input voltage is between 0.1 x VDD3 and 0.9 x VDD3 (MAX) ) II -10 10 uA Capacitance for each I/O pin C I - 10 pF Parameter Symbol Min Max Unit Input high voltage level V IH 0.7 x V DD3 V DD3(MAX) + 0.1 V Input low voltage level V IL -0.5 0.3 x V DD3 V Hysteresis of Schmitt trigger inputs: Vhys 0.05 x V DD3 - Low level output voltage V OL 0 0.2 x V DD3 V Output fall time from VIH(MIN) to VIL(MAX) with a bus capacitance from 10pF to 400pF tOF 20 + 0.1 x C b 250 ns Pulse width of spikes which must be suppressed by the input filter tSP 0 50 ns Input current each I/O pin (input voltage is between 0.1 x VDD3 and 0.9 x VDD3 (MAX)) II -10 10 uA Capacitance for each I/O pin C I - 10 pF

16 of 47 March 31, 2008 IDT80KSW0003 Datasheet Table 11 Specifications of the SDA and SCL bus lines for F/S-mode I2C -bus devices NOTES: 1. For more information, see the I2C-Bus specification by Philips Semiconductor [1]. 2. A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHMIN of the SCL signal) to bridge the undefined region of the falling edge of SCL. 3. The maximum t HD;DAT has only to be met if the device does not stretch the LOW period (tLOW) of the SCL signal. 4. A Fast-mode I 2C-bus device can be used in a Standard-mode I 2C-bus system, but the requirement t SU;DAT > 250 ns must then be met. This will automatically be the case if the device does not stretch the LO W period of the SCL signal. If such a device does stretch the LO W period of the SCL signal, it must output the next data bit to the SDA line tRMAX + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus specification) before the SCL line is released. Signal Symbol Reference Edge Standard Mode Fast Mode Unit Min Max Min Max I2C(1,4) SCL f SCL none 0 100 0 400 kHz tHD;STA 4.0 — 0.6 — s tR — 1000 — 300 s tF — 300 — 300 s SDA(2,3) tSU;DAT SCL rising 250 — 100 — s tHD;DAT 03 . 4 50 0 . 9 s tR — 1000 10 300 s tF — 300 10 300 s Start or repeated start condition tSU;STA SDA falling 4.7 — 0.6 — s tSU;STO 4.0 — 0.6 — s Stop condition t SU;STO SDA rising 4.0 — 0.6 — s Bus free time between a stop and start condi- tion tBUF 4.7 — 1.3 — s Capacitive load for each bus line Cb — 400 — 400 pF

17 of 47 March 31, 2008 IDT80KSW0003 Datasheet I2C Timing Waveforms Figure 12 I2C Timing Waveforms

14 Interrupt (IRQ) Electrical Specifications

At recommended operating conditions with VDD3 = 3.3V ± 5% Table 12 IRQ Electrical Specifications (VDD3 = 3.3V ± 5%) tSU;STO tHD;STA tSU;STA tSU;DAT tHD;DAT tHIGH tHD;STA tLOW SDA SCL tBUF Parameter Symbol Min Max Unit Low level output voltage (I OL = 4mA, V DD3 = Min.) VOL 0 0.4 V Output fall time from V IH(min) to VIL(max) with a bus capacitance from 10pF to 400pF tOF - 25 ns Input current each I/O pin (input voltage is between 0.1 x V DD3 and 0.9 x V DD3 (max)) II -10 10 uA Capacitance for IRQ C I - 10 pF

18 of 47 March 31, 2008 IDT80KSW0003 Datasheet At recommended operating conditions with VDD3 = 2.5V ± 100mV Table 13 IRQ Electrical Specifications (VDD3 = 2.5V ± 100mV) Figure 13 IRQ Timing Diagram The IRQ pin is an open-drain driver. IDT recommends a weak pull-up resistor (2-10k Ohm) be placed on this pin to VDD3. The IRQ pin goes active low when any special error filter error flag is set, and is cleared when all error flags are reset. Please refer to the device user’s manual for full detail.

15 Serial RapidIO Ports

The CPS-8’s SERDES are in full compliance to the RapidIO AC specifications for the LP-Serial physical layer [5]. This section provides those specifications for reference. The electrical specifications cover both single and multiple-lane links. Two transmitters (short run and long run) and a single receiver are specified for each of three baud rates, 1.25, 2.50, and 3.125 GBaud. Two transmitter specifications allow for solutions ranging from simple chip-to-chip interconnect to driving two connectors across a backplane. A single receiver specification is given that will accept signals from both the short run and long run transmitter specifications. The short run transmitter setting should be used mainly for chip-to-chip connections on either the same printed circuit board or across a single connector. This covers the case where connections are made to a mezzanine (daughter) card. The minimum swings of the short run specification reduce the overall power used by the transceivers. The long run transmitter specifications use larger voltage swings that are capable of driving signals across backplanes. This allows a user to drive signals across two connectors and a backplane. The CPS-8 can drive beyond the specification distance of at least 50 cm at all baud rates. Please use IDT’s Simulation Kit IO models to determine reach and signal quality for a given PCB design. Parameter Symbol Min Max Unit Low level output voltage (IOL = 2mA, VDD3 = Min.) VOL 0 0.4 V Output fall time from VIH(min) to VIL(max) with a bus capacitance from 10pF to 400pF tOF - 25 ns Input current each I/O pin (input voltage is between 0.1 x VDD3 and 0.9 x VDD3 (max)) II -10 10 uA Capacitance for IRQ C I - 10 pF

19 of 47 March 31, 2008 IDT80KSW0003 Datasheet Signal Definitions LP-Serial links uses differential signaling. This section defines terms used in the description and specification of differential signals. Differential Peak- Peak Voltage of Transmitter or Receiver shows how the signals ar e defined. The figure shows wave forms for either a transmitter output (TD and TD) or a receiver input (RD and RD). Each signal swings between A Volts and B Volts where A > B. Using these waveforms, the definitions are as follows: 1. The transmitter output signals and the receiver input signals TD, TD , RD and RD each have a peak-to-peak swing of A - B Volts 2. The differential output signal of the transmitter, V OD, is defined as VTD-VTD. 3. The differential input signal of the receiver, V ID, is defined as VRD-VRD. 4. The differential output signal of the trans mitter and the differential input signal of the receiver each range from A - B to -(A - B) Volts. 5. The peak value of the differential trans mitter output signal and the differential receiver input signal is A - B Volts 6. The peak-to-peak value of the differential transmitter output signal and the differential receiver input signal is 2 * (A - B) Volts Figure 14 Differential Peak-Peak Voltage of Transmitter or Receiver To illustrate these definitions using real values, consider the case of a CML (Current Mode Logic) transmitter that has a common mode voltage of 2.25 V and each of its outputs, TD and TD, has a swing that goes between 2.5V and 2.0V. Using these values, the peak-to-peak voltage swing of the signals TD and TD is 500 mV p-p. The differential output signal ranges between 500 mV and -500 mV. The peak differential voltage is 500 mV. The peak-to-peak differential voltage is 1000 mV p-p. Equalization With the use of high speed serial links, the interconnect media will cause degradation of the signal at the receiver. Effects such as Inter-Symbol Interference (ISI) or data dependent jitter are produced. This loss can be large enough to degrade the eye opening at the receiver beyond what is allowed in the specification. To negate a portion of these effects, equalization can be used. The equalization technique implemented in the CPS-8 is Pre-emphasis on the transmitter (under register control). Explanatory Note on Transmitter and Receiver Specifications AC electrical specifications are given for transmitter and receiver. Long run and short run interfaces at three baud rates (a total of six cases) are described. The parameters for the AC electrical specifications are guided by the XAUI electrical interface specified in Clause 47 of IEEE 802.3ae-2002. XAUI has similar application goals to serial RapidIO. The goal of this standard is that electrical designs for serial RapidIO can reuse electrical designs for XAUI, suitably modified for applications at the baud intervals and reaches described herein. Transmitter Specifications LP-Serial transmitter electrical and timing specifications are stated in the text and tables of this section. A Volts B Volts TD or RD TD or RD Differential Peak-Peak = 2 * (A – B)

20 of 47 March 31, 2008 IDT80KSW0003 Datasheet The differential return loss, S11, of the transmitter in each case shall be better than -10 dB for (Baud Frequency)/10 < Freq(f) < 625 MHz, and -10 dB + 10log(f/625 MHz) dB for 625 MHz <= Freq(f) <= Baud Frequency The reference impedance for the differential return loss measurements is 100 Ohm resistive. Differential return loss includes contributions from on- chip circuitry, chip packaging and any off-chip components related to the driver. The output impedance requirement applies to all valid output levels. The CPS-8 satisfies the specification requirement that the 20%-80% rise/fall time of the transmitter, as measured at the transmitter output, in each case has a minimum value 60 ps. Similarly the timing skew at the output of an LP-Serial transmitter between the two signals that comprise a differential pair does not exceed 25 ps at 1.25 GB, 20 ps at 2.50GB and 15 ps at 3.125 GB. Table 14 Short Run Transmitter AC Timing Specifications - 1.25 GBaud Table 15 Short Run Transmitter AC Timing Specifications - 2.5 GBaud Symbol Parameter Range Unit Notes Min Max VO Output Voltage -0.40 2.30 Volts Voltage relative to COM- MON of either signal com- prising a differential pair. V DIFF PP Differential Output Voltage 500 1000 mV p-p JD Deterministic Jitter - 0.17 UI p-p JT Total Jitter - 0.35 UI p-p SMO Multiple Output Skew - 1000 ps Skew at the transmitter output between lanes of a multilane link UI Unit Interval 800 800 ps +/- 100 ppm Symbol Parameter Range Unit Notes Min Max VO Output Voltage -0.40 2.30 Volts Voltage relative to COM- MON of either signal com- prising a differential pair. VDIFF PP Differential Output Voltage 500 1000 mV p-p JD Deterministic Jitter - 0.17 UI p-p JT Total Jitter - 0.35 UI p-p SMO Multiple Output Skew - 1000 ps Skew at the transmitter output between lanes of a multilane link UI Unit Interval 400 400 ps +/- 100 ppm

21 of 47 March 31, 2008 IDT80KSW0003 Datasheet Table 16 Short Run Transmitter AC Timing Specifications - 3.125 GBaud Table 17 Long Run Transmitter AC Timing Specifications - 1.25 GBaud Symbol Parameter Range Unit Notes Min Max VO Output Voltage -0.40 2.30 Volts Voltage relative to COM- MON of either signal com- prising a differential pair. VDIFF PP Differential Output Voltage 500 1000 mV p-p JD Deterministic Jitter - 0.17 UI p-p JT Total Jitter - 0.35 UI p-p SMO Multiple Output Skew - 1000 ps Skew at the transmitter output between lanes of a multilane link UI Unit Interval 320 320 ps +/- 100 ppm Symbol Parameter Range Unit Notes Min Max VO Output Voltage -0.40 2.30 Volts Voltage relative to COM- MON of either signal com- prising a differential pair. VDIFF PP Differential Output Voltage 800 1600 mV p-p JD Deterministic Jitter - 0.17 UI p-p JT Total Jitter - 0.35 UI p-p SMO Multiple Output Skew - 1000 ps Skew at the transmitter output between lanes of a multilane link UI Unit Interval 800 800 ps +/- 100 ppm

22 of 47 March 31, 2008 IDT80KSW0003 Datasheet Table 18 Long Run Transmitter AC Timing Specifications - 2.5 GBaud Table 19 Long Run Transmitter AC Timing Specifications - 3.125 GBaud For each baud rate at which an LP-Serial transmitter is specified to operate, the output eye pattern of the transmitter falls entirely within the unshaded portion of the Transmitter Output Compliance Mask shown in Transmitter Output Compliance Mask (Figure 15) with the parameters specified in Transmitter Differential Output Eye Diagram Parameters (Table 17) when measured at the output pins of the device and the device is driving a 100 Ohm +/- 5% differential resistive load. The specification allows the output eye pattern of a LP-Serial transmitter that implements pre-emphasis (to equalize the link and reduce inter-symbol interference) to only comply with the Transmitter Output Compliance Mask when pre-emphasis is disabled or minimized. Symbol Parameter Range Unit Notes Min Max VO Output Voltage -0.40 2.30 Volts Voltage relative to COM- MON of either signal com- prising a differential pair. VDIFF PP Differential Output Voltage 800 1600 mV p-p JD Deterministic Jitter - 0.17 UI p-p JT Total Jitter - 0.35 UI p-p SMO Multiple Output Skew - 1000 ps Skew at the transmitter output between lanes of a multilane link UI Unit Interval 400 400 ps +/- 100 ppm Symbol Parameter Range Unit Notes Min Max VO Output Voltage -0.40 2.30 Volts Voltage relative to COM- MON of either signal com- prising a differential pair. VDIFF PP Differential Output Voltage 800 1600 mV p-p JD Deterministic Jitter - 0.17 UI p-p JT Total Jitter - 0.35 UI p-p SMO Multiple Output Skew - 1000 ps Skew at the transmitter output between lanes of a multilane link UI Unit Interval 320 320 ps +/- 100 ppm

23 of 47 March 31, 2008 IDT80KSW0003 Datasheet Figure 15 Transmitter Output Compliance Mask Table 20 Transmitter Differential Output Eye Diagram Parameters Receiver Specifications LP-Serial receiver electrical and timing specifications are stated in the text and tables of this section. The receiver input impedance results in a differential return loss better than 10 dB and a common mode return loss better than 6 dB from 100 MHz to (0.8)*(Baud Frequency). This includes contributions from on-chip circuitry, the chip package and any off-chip components related to the receiver. AC coupling components are included in this requirement. The reference impedance for return loss measurements is 100 Ohm resistive for differential return loss and 25 Ohm resistive for common mode. Transmitter Setting V DIFFmin (mV) V DIFFmax (mV) A (UI) B (UI) 1.25 GBaud Short Range 250 500 0.175 0.39 1.25 GBaud Long Range 400 800 0.175 0.39 2.5 GBaud Short Range 250 500 0.175 0.39 2.5 GBaud Long Range 400 800 0.175 0.39 3.125 GBaud Short Range 250 500 0.175 0.39 3.125 Gbaud Long Range 400 800 0.175 0.39 VDIFFmax VDIFFmin -VDIFFmax -VDIFFmin 0A B 1 - A 1 - B 1 Time in UI Transmitter Differential Output Voltage

24 of 47 March 31, 2008 IDT80KSW0003 Datasheet Table 21 Receiver AC Timing Specifications - 1.25 GBaud NOTE: 1. Total jitter is composed of three components, deterministic jitter, random jitter and single frequency sinusoidal jitter. The sinusoidal jitter may have any amplitude and frequency in the unshaded region of Figure 16. The sinusoidal jitter component is included to ensure margin for low frequency jitter, wander, noise, crosstalk and other variable system effects. Table 22 Receiver AC Timing Specifications - 2.5 GBaud NOTE: 1. Total jitter is composed of three components, deterministic jitter, random jitter and single frequency sinusoidal jitter. The sinusoidal jitter may have any amplitude and frequency in the unshaded region of Figure 16. The sinusoidal jitter component is included to ensure margin for low frequency jitter, wander, noise, crosstalk and other variable system effects. Symbol Parameter Range Unit Notes Min Max VIN Differential Input Voltage 200 1600 mV p-p Measured at receiver JD Deterministic Jitter Tolerance 0.37 - UI p-p Measured at receiver JDR Combined Deterministic and Random Jitter Tolerance 0.55 - UI p-p Measured at receiver JT Total Jitter Tolerance(1) 0.65 - UI p-p Measured at receiver SMI Multiple Input Skew - 24 ns Skew at the receiver input between lanes of a multi- lane link BER Bit Error Rate 10 -12 UI Unit Interval 800 800 ps +/- 100 ppm Symbol Parameter Range Unit Notes Min Max VIN Differential Input Voltage 200 1600 mV p-p Measured at receiver JD Deterministic Jitter Tolerance 0.37 - UI p-p Measured at receiver JDR Combined Deterministic and Random Jitter Tolerance 0.55 - UI p-p Measured at receiver JT Total Jitter Tolerance(1) 0.65 - UI p-p Measured at receiver SMI Multiple Input Skew - 24 ns Skew at the receiver input between lanes of a multi- lane link BER Bit Error Rate 10 -12 UI Unit Interval 400 400 ps +/- 100 ppm

25 of 47 March 31, 2008 IDT80KSW0003 Datasheet Table 23 Receiver AC Timing Specifications - 3.125 GBaud NOTE: 1. Total jitter is composed of three components, deterministic jitter, random jitter and single frequency sinusoidal jitter. The sinusoidal jitter may have any amplitude and frequency in the unshaded region of Figure 16. The sinusoidal jitter component is included to ensure margin for low frequency jitter, wander, noise, crosstalk and other variable system effects. Figure 16 Single Frequency Sinusoidal Jitter Limits Symbol Parameter Range Unit Notes Min Max VIN Differential Input Voltage 200 1600 mV p-p Measured at receiver JD Deterministic Jitter Tolerance 0.37 - UI p-p Measured at receiver JDR Combined Deterministic and Random Jitter Tolerance 0.55 - UI p-p Measured at receiver JT Total Jitter Tolerance(1) 0.65 - UI p-p Measured at receiver SMI Multiple Input Skew - 22 ns Skew at the receiver input between lanes of a multi- lane link BER Bit Error Rate 10 -12 UI Unit Interval 320 320 ps +/- 100 ppm

26 of 47 March 31, 2008 IDT80KSW0003 Datasheet Receiver Eye Diagrams For each baud rate at which an LP-Serial receiver is specified to operate, the receiver meets the corresponding Bit Error Rate specification (Receiver AC Timing Specifications - 1.25 GBaud, Receiver AC Timing Specif ications - 2.5 GBaud, and Receiver AC Timing Specifications - 3 .125 GBaud ) when the eye pattern of the receiver test signal (exclusive of sinusoidal jitter) falls ent irely within the unshaded portion of the Receiver Input Compliance Mask shown in (Figure 17) with the parameters specifi ed in Receiver Input Compliance Mask Parameters exclusive of Si nusoidal Jitter. The eye pattern of the receiver test signal is measured at the input pins of the receiving devic e with the device replaced with a 100 Ohm +/- 5% differential resistive load. Figure 17 Receiver Input Compliance Mask Table 24 Receiver Input Compliance Mask Parameters exclusive of Sinusoidal Jitter Receiver Rate V DIFFmin (mV) V DIFFmax (mV) A (UI) B (UI) 1.25 GBaud 100 800 0.275 0.400 2.5 GBaud 100 800 0.275 0.400 3.125 GBaud 100 800 0.275 0.400 VDIFFmax VDIFFmin -VDIFFmax -VDIFFmin

0 AB 1 - A 1 - B 1

Receiver Differential Input Voltage

27 of 47 March 31, 2008 IDT80KSW0003 Datasheet

16 Reference Clock

The differential reference clock (REF_CLK+/-) is used to generate the sRIO PHY and internal clocks used in the CPS-8. Reference Clock Electrical Specifications The reference clock is 156.25 MHz, and is AC-coupled with the following electrical specifications: Figure 18 REF_CLK Representative Circuit Table 25 Input Reference Clock Jitter Specifications The reference clock wander should not be more than 100ppm (for 156.25 MHz, this is +/-15.625 KHz). This requirement comes from the sRIO specification that outgoing signals from separate links which belong to the same port should not be separated more than 100ppm. Note that the series capacitors are discretes that must be plac ed external to the device’s receivers. All other elements are as sociated with the input structure internal to the device. VBIAS is generated internally. Name Description Min Nom Max Units REF_CLK REF_CLK clock running at 156.25Mhz -100 ---- +100 ppm Phase Jitter (rms) Phase Jitter (rms) (1MHz - 20MHz) ---- ---- 2p s tDUTY_REF REF_CLK duty cycle 40 50 60 % tRCLK/tFCLK Input signal rise/fall time (20%-80%) 200 500 650 ps vIN_CML Differential peak-peak REF_CLK input swing 400 ---- 2400 mV RL_CLK Input termination resistance 40 50 60 ohm LI_CLK Input inductance ----- ----- 4n H CI_CLK Input capacitance ----- ----- 5p F 5686 drw07 REF_CLK_P REF_CLK_N REF_CLK LI,C L K CI,C L K VBIAS,C L K LI,C L K CI,C L K RL,CLK RL,CLK

28 of 47 March 31, 2008 IDT80KSW0003 Datasheet

17 JTAG Interface

Description

The CPS-8 offers full JTAG (Boundary Scan) support for both its slow speed and high speed pins. This allows “pins-down” testing of newly manufac- tured printed circuit boards as well as tr oubleshooting of field returns. The JTAG TAP interface also offers an alternative met hod for Configuration Register Access (CRA) (along with the sRIO and I2C ports). Thus this port may be used for programming the CPS-8’s many registers. Boundary scan testing of the AC-coupled IOs is performed in accordance with IEEE 1149.6 (AC Extest). IEEE 1149.1 (JTAG) & IEEE 1149.6 (AC Extest) Compliance scan cells are on the same chain. No additional control cells are provided for independent selection of negative and/or positive terminals of the TX- or RX-pairs. System Logic TAP Controller Overview The system logic utilizes a 16-state, six- bit TAP controller, a four-bit instruction register, and five dedicated pins to perfo rm a variety of functions. The primary use of the JTAG TAP Controller state machine is to allow the five external JTAG control pins to control and access the CPS-8's many external signal pins. The JTAG TAP Controller can also be used for identifying the device part number. The JTAG logic of the CPSCPS is depicted in the figure below. Figure 19 Diagram of the JTAG Logic Bypass Register Instruction Register Decoder 4-Bit Instruction Register Tap Controller m u x m u x Device ID Register Boundary Scan Register TDI TMS TCK TRST TDO

29 of 47 March 31, 2008 IDT80KSW0003 Datasheet Signal Definitions JTAG operations such as Reset, State-transition control and Clock sampling are handled through the signals listed in the table below. A functional overview of the TAP Controller and Boundary Scan registers is provided in the sections following the table. The system logic TAP controller transitions from state to state, according to the value present on TMS, as sampled on the risin g edge of TCK. The Test-Logic Reset state can be reached either by asserting TRST or by applying a 1 to TMS for five consecutive cycles of TCK. A state diagram for the TAP controller appears in Figure 20. The value next to state represent the value that must be applied to TMS on the next rising edge of TCK, to transi- tion in the direction of the associated arrow. Figure 20 State Diagram of the CPS-8’s TAP Controller Pin Name Type Description TRST Input JTAG RESET Asynchronous reset for JTAG TAP controller (internal pull-up) TCK Input JTAG Clock Test logic clock. JTAG_TMS and JTAG_TDI are sampled on the rising edge. JTAG_TDO is output on the falling edge. TMS Input JTAG Mode Select. Requires an external pull-up. Controls the state transitions for the TAP controller state machine (internal pull-up) TDI Input JTAG Input Serial data input for BSC chain, Instruction Register, IDCODE register, and BYPASS register (internal pull-up) TDO Output JTAG Output Serial data out. Tri-stated except when shifting while in Shift-DR and SHIFT-IR TAP controller states. Table 26 JTAG Pin Descriptions Test- Logic Reset Run-Test/ Idle Select- DR-Scan Capture-DR Shift-DR Exit1 -DR Pause-DR Exit2-DR Select- IR-Scan Capture-IR Shift-IR Exit1-IR Pause-IR Exit2-IR Update-DR Update-IR 110 00

32 of 47 March 31, 2008 IDT80KSW0003 Datasheet The Instruction Register contains four shift-register-based cells that can hold instruction data. This register is decoded to p erform the following func- tions: – To select test data registers that may operate while the instruction is current. The other test data registers should not interfere with chip oper- ation and selected data registers. – To define the serial test data register path used to shift data between TDI and TDO during data register scanning. The Instruction Register is comprised of 4 bits to decode instructions, as shown in the table below. EXTEST The external test (EXTEST) instruction is used to control t he boundary scan register, once it has been initialized using the SA MPLE/PRELOAD instruction. Using EXTEST, the user can then sample inputs from or load values onto the external pins of the CPS-8. Once this instruction is selected, the user then uses the SHIFT-DR TAP controller state to shift values into the boundary scan chai n. When the TAP controller pass es through the UPDATE-DR state, these values will be latched onto the output pins or into the output enables. Instruction Definition OPcode [3:0] EXTEST Mandatory instruction allowing the testing of board level interconnections. Data is typically loaded onto the latched parallel outputs of the boundary scan shift register using the SAMPLE/PRELOAD instruction prior to use of the EXTEST instruction. EXTEST will then hold these values on the outputs while being executed. Also see the CLAMP instruction for similar capability. 0000 SAMPLE/ PRELOAD Mandatory instruction that allows data values to be loaded onto the latched parallel output of the boundary-scan shift register prior to selection of the other boundary-scan test instruction. The Sample instruction allows a snap- shot of data flowing from the system pins to the on-chip logic or vice versa. 0001 IDCODE Provided to select Device Identific ation to read out manufacturer’s identity, part, and version number. 0010 HIGHZ Tri-states all output and bidirectional boundary scan cells. 0011 CLAMP Provides JTAG user the option to bypass the part’s JTAG controller while keeping the part outputs controlled similar to EXTEST. 0100 EXTEST_PULSE AC Extest instruction implemented in accordance with the requirements of the IEEE std. 1149.6 specification. 0101 EXTEST_TRAIN AC Extest instruction implemented in accordance with the requirements of the IEEE std. 1149.6 specification. 0110 RESERVED Behaviorally equivalent to th e BYPASS instruction as per the IEEE std. 1149.1 specification. However, the user is advised to use the explicit BYPASS instruction. 0111 — 1001 CONFIGURA- TION REGIS- TER ACCESS (CRA) CPS-8-specific opcode to allow reading and writing of the configuration regis- ters. Reads and writes must be 32-bits. See further detail below. 1010 PRIVATE For internal use only. Do not use. 1011 — 1100 RESERVED Behaviorally equivalent to th e BYPASS instruction as per the IEEE std. 1149.1 specification. However, the user is advised to use the explicit BYPASS instruction. 1101 PRIVATE For internal use only. Do not use. 1110 BYPASS The BYPASS instruction is used to truncate the boundary scan register as a single bit in length. 1111 Table 27 Instructions Supported By CPS-8’s JTAG Boundary Scan

33 of 47 March 31, 2008 IDT80KSW0003 Datasheet SAMPLE/PRELOAD The sample/preload instruction has a dual use. The primary us e of this instruction is for preloading the boundary scan register prior to enabling the EXTEST instruction. Failure to preload will result in unknown random data being driven onto the output pins when EXTEST is selected. The secondary function of SAMPLE/PRELOAD is for sampling the system state at a particular moment. BYPASS The BYPASS instruction is used to truncate the boundary scan register to a single bit in length. During system level use of the JTAG, the boundary scan chains of all the devices on the board are connected in series. In order to faci litate rapid testing of a given device, al l other devices are put into BYPASS mode. Therefore, instead of having to shift 46 times to get a value through the CPS-8, the user only needs to shift one time to get the value from TDI to TDO. When the TAP controller passes through the CAPTURE-DR state, the value in the BYPASS register is updated to be 0. If the device being used does not have an IDCODE register, then the BYPASS instruction will automatically be selected into the instruction register whenever the TAP controller is reset. Theref ore, the first value that will be shifted out of a device without an IDCODE registe r is always 0. Devices such as the CPS-8 that include an IDCODE register will automatically load the IDCODE instruction when the TAP controller is reset, and they will shift out an initial value of 1. This is done to allow the user to easily distinguish between devices having IDCODE registers and those that do not. CLAMP This instruction, listed as optional in the IEEE 1149.1 JTAG Specifications, allows the boundar y scan chain outputs to be clamp ed to fixed values. When the clamp instruction is issued, the scan chain will bypass the CPS-8 and pass through to devices further down the scan chain. IDCODE The IDCODE instruction is automatically loaded when the TAP c ontroller state machine is reset either by the use of the TRST signal or by the appli- cation of a ‘1’ on TMS for five or more cycles of TCK as per the IEEE Std 1149.1 specification. The least significant bit of this value must always be 1. Therefore, if a device has a ID CODE register, it will shift out a 1 on the first shift if it is brought directly to the SHIFT-D R TAP controller state after the TAP controller is reset. The board- level tester can then examine this bit and determine if the device contains a DEVICE_ID register (the first bit is a 1), or if the device only contains a BYPASS register (the first bit is 0). However, even if the device contains an IDCODE register, it must also contain a BYPASS register. The only difference is that the BYPASS register will not be the default register selected during the TAP controller rese t. When the IDCODE instruction is active and the TAP control ler is in the Shift-DR state, the thirty-two bit value that will be shifted out of the device-ID register is 0x0035C067. EXTEST PULSE This IEEE 1149.6 instruction applies only to the AC-coupled pins. A ll DC pins will perform as if the IEEE Std 1149.1 EXTEST ins truction is operating whenever the EXTEST_PULSE instruction is effective. Bit(s) Mnemonic Description R/W Reset 0 reserved reserved 0x1 R 1 11:1 Manuf_ID Manufacturer Identity (11 bits) IDT 0x33 R0 x 3 3 27:12 Part_number Part Number (16 bits) This field identifies the part number of the processor derivative. For the CPS-8 this value is: 0x35C Ri m p l . dep. 31:28 Version Version (4 bits) This field identifies the version number of the processor deriva- tive. For the CPS-8, this value is 0x0035C067 Ri m p l . dep. Table 28 System Controller Device Identification Register Version Part Number Vendor ID LSB 0000 0000|0011|0101|1100 0000|0110|011 1 Table 29 System Controller Device ID Instruction Format

34 of 47 March 31, 2008 IDT80KSW0003 Datasheet The EXTEST_PULSE instruction enables edge- detecting behavior on signal paths containing AC pins, where test receivers reconstru ct the original waveform created by a driver even when signals decay due to AC-coupling. As the operation name suggests, enabling EXTEST_PULSE causes a pulse to be issued which can be detected even on AC-coupled receivers. Refer to the IEEE Std 1149.6 for full details. Below is a short synopsis. If enabled, the output signal is forced to the value in its associated Boundary-Scan Register data cell for its driver (true and inverted values for a differ- ential pair) at the falling edge of TCK in the Update-IR and U pdate-DR TAP Controller states. The output subsequently transitio ns to the opposite of that state (an inverted state) on the first falling edge of TCK t hat occurs after entering the Run-Test/Idle TAP Controller sta te. It then transitions back again to the original state (a noninverted state) on the first falling edge of TCK after leaving the Run-Test/Idle TAP Controller state. EXTEST TRAIN This IEEE 1149.6 instruction applies only to the AC-coupled pins. A ll DC pins will perform as if the IEEE Std 1149.1 EXTEST ins truction is operating whenever the EXTEST_PULSE instruction is effective. The EXTEST_TRAIN instruction enables edge-detecting behavior on signal paths containing AC pins, wher e test receivers reconstru ct the original waveform created by a driver even when signals decay due to AC-coupling. As the operation name suggests, enabling EXT EST_TRAIN causes a pulse train to be i ssued which can be detected even on AC-couple d receivers. Once in an enabled state, the train will be sent continuously in response to the TCK clock. No other signaling is required to g enerate the pulse train while in this state. Refer to the IEEE Std 1149.6 for full details. Below is a short synopsis. First, the output signal is forced to the state matching the val ue (a noninverted state) in its associated Boundary-Scan Regist er data cell for its driver (true and inverted values for a differential pair), at the fall ing edge of TCK in update-IR. Then the output signal transitions to the opposite state (an inverted state) on the first falling edge of TCK that occurs after entering the Run-Test/Idle TAP Controller state. While remaining in this state, the output signal will continue to invert on every falling edge of TCK, thereby generating a pulse train. RESERVED Reserved instructions are not implemented, but default to a BYPASS mode. IDT recommends using the standard BYPASS opcode rather than RESERVED opcodes if BYPASS functionality is desired. PRIVATE Private instructions implement various test modes used in the device manufacturing process. The user should not enable these instructions. Usage Considerations As previously stated, there are internal pull-ups on TRST, TMS, and TDI. However, TCK also needs to be driven to a known value. It is best to either drive a zero on the TCK pin when it is not being used or to use an external pull-dow n resistor. In order to guarantee that the JTAG does not interfere with normal system operation, the TAP controller should be forced into the Test-Logic-Reset controller state by continuously holding TRST low and/or TMS high when the chip is in normal operation. If JTAG will not be used, externally pull-down TRST low to disable it. JTAG Configuration Register Access As previously mentioned, the JTAG port may be used to read and write to the CPS-8’s configuration registers. The same JTAG instruction (4b1010) is used for both writes and reads.

35 of 47 March 31, 2008 IDT80KSW0003 Datasheet Writes during Configuration Register Access A write is performed by shifting the CRA OPcode into the Instru ction Register (IR), then shifti ng in first a read / write selec t bit, then both the 22-bit target address and 32-bit data into the Data Register (DR). When bit 0 of the data str eam is 0, data shifted in after the addre ss will be written to the address specified in jtag_config_addr. The TDO pin will transmit all 0s. See the figure below for the associated timing diagram. Figure 25 Implementation of write during configuration register access Bits Field Name Size Description 0 jtag_config_wr_n 1 1 – read configuration register 0 – write configuration register Bits Field Name Size Description [22:1] jtag_config_addr 22 Starting address of the memory mapped configuration regis- ter. 22 address bits map to a unique double-word aligned on a 32-bit boundary. This provides accessibility to and is consis- tent with the sRIO memory mapping. [54:23] jtag_config_data 32 Reads: Data shifted out (one 32-bit word per read) is read from the configuration register at address jtag_config_addr. Writes: Data shifted in (one 32-bit word per write) is written to the configuration register at address jtag_config_addr. Table 30 Data stream for JTAG Configuration Register Access mode Shift_dr Capture _dr Shift_drPause_dr Exit1_dr Exit2_dr Update_drExit1_dr Exit2_dr Pause_dr Select_dr_scan TAP controller state TDO ZZ Z Internal address Address Internal data Data Address DataTDI

36 of 47 March 31, 2008 IDT80KSW0003 Datasheet Reads during Configuration Register Access Reads are much like writes except that target data is not prov ided. When bit 0 of the data stream is 1, data shifted out will b e read from the address specified in jtag_config_addr. TDI will not be used after the address is shifted in. As a function of read latency in the architecture, the first 16 bits will be 0’s and must be ignored. The following bits will contain the actual register bits. Figure 26 Implementation of read during configuration register access At recommended operating conditions with VDD3 = 3.3V ± 5% Table 31 JTAG DC Electrical Specifications (VDD3 = 3.3V ± 5%) Shift_dr Capture_dr Shift_drPause_dr Exit1_dr Exit2_dr Update_drExit1_dr Exi t2_dr Pause_dr Sel ect _dr _scan TAP contro lle r state TDI Address TDO ZZ Z Dat a Read latency Dat a 1 Inter nal address Address Internal data Dat a Parameter Symbol Min Max Unit 3.3V Supply Voltage V DD3 3.15 3.45 V Ground V SS 0 0 V Input high voltage level V IH 2.0 V DD3(max) + 0.15 V Input low voltage level V IL -0.3 0.8 V Output Low Voltage (IOL = 4mA, VDD3 = Min.) V OL - 0.4 V Output High Voltage (IOH = -4mA, VDD3 = Min.) VOH 2.4 - V Input current for JTAG pins (input voltage is between 0.1 x VDD3 and 0.9 x VDD3 (max)) ILI -30 30 uA Capacitance for each Input pin C IN - 8 pF Capacitance for each I/O or Output pin C OUT - 10 pF

37 of 47 March 31, 2008 IDT80KSW0003 Datasheet At recommended operating conditions with VDD3 = 2.5V ± 100mV Table 32 JTAG DC Electrical Specifications (VDD3 = 2.5V ± 100mV ) Table 33 JTAG AC Electrical Specifications NOTES: 1. Guaranteed by design. 2. Refer to AC Electrical Test Conditions stated earlier in this document. 3. JTAG operations occur at one speed (10MHz). The base device may run at any speed specified in this datasheet. Parameter Symbol Min Max Unit 2.5V Supply Voltage V DD3 2.4 2.6 V Ground V SS 0 0 V Input high voltage level V IH 1.7 V DD3(max) + 0.1 V Input low voltage level V IL -0.3 0.7 V Output Low Voltage (IOL = 2mA, VDD3 = Min.) V OL - 0.4 V Output High Voltage (IOH = -2mA, VDD3 = Min.) VOH 2.0 - V Input current for JTAG pins (input voltage is between 0.1 x VDD3 and 0.9 x VDD3 (max) ILI -30 30 uA Capacitance for each Input pin C IN - 8 pF Capacitance for each I/O or Output pin C OUT - 10 pF 80KSW0003 Symbol Parameter Min. Max. Units tJCYC JT AG Clock Input Period 100 ____ ns tJCH JT AG Clock HIGH 40 ____ ns tJCL JT AG Clock Low 40 ____ ns tJR JTAG Clock Rise Time ____ 3(1) ns tJF JT AG Clock Fall Time ____ 3(1) ns tJRST JT AG Reset 50 ____ ns tJRSR JT AG Reset Recovery 50 ____ ns tJCD JTAG Data Output ____ 25 ns tJDC JTAG Data Output Hold 0 ____ ns tJS JT AG Setup 15 ____ ns tJH JT AG Hold 15 ____ ns 5686 tbl 02b

38 of 47 March 31, 2008 IDT80KSW0003 Datasheet JTAG Timing Waveforms Figure 27 JTAG Timing Specifications NOTES: 1. Device inputs = All device inputs except TDI, TMS, and TRST. 2. Device outputs = All device outputs except TDO.

18 Reset & Initialization

The CPS-8 does not require specific power sequencing between any of the core and I/O supplies. Reset Pin and Timing Figure 28 Reset Timing To reset the device, first reset signal has to be de-asserted (Reset Low), and it is asserted after 5 REF_CLK cycles. 4096 REF_CLK cycles later, the device completes the reset process. Once completed, access to the CPS-8 from any and all interfac es is possible and the CPS-8 i s fully functional. Control and data traffic will not be accepted by the CPS-8 until this process is fully completed. TCK Device Inputs(1)/ TDI/TMS Device Outputs(2)/ TDO TRST tJCD tJDC tJRST tJS tJH tJCYC tJRSR tJF tJCL tJR tJCH 5686 drw 08 RST 5 REF_CLK Cycles 4096 REF_CLK Cycles

39 of 47 March 31, 2008 IDT80KSW0003 Datasheet Table 34 CPS-8 Reset Port Configuration Speed Select (SPD[1:0]) There are 2 port speed select pins. These pins are used to chose the initial speed on sRIO ports. The selection table is given below: Table 35 Port Speed Selection Pin Values At power-up the CPS-8 is configured as with 8 non-redundant 1x ports. All ports are configured with each link running at 1.25, 2.5, or 3.125 Gbps (depending on the SPD[1:0] pins). An end-point connected to the CPS-8 can then reprogram all the ports to the desired configuration. All ports are configured as long run at start up because it will allow the port to communicate to either a short run or long run port on the CPU. Initialization of sRIO Switching At the initialization all values in the route table are programmed as default route. But the CPS-8 accepts maintenance packets. These maintenance packets may be used to configure the CPS-8. Lane# Quad# Quad Type Default on Reset 1x-Ports Only Port Numbering 4x-Ports Only Port Numbering

0 Enhanced Enhanced

1 Enhanced Enhanced

Value on the Pins (SPD1, SPD0) Ports Rate 00 1.25Gbps 01 2.5Gbps 10 3.125Gbps

11 Reserved

40 of 47 March 31, 2008 IDT80KSW0003 Datasheet

19 Pinout & Pin Listing

Figure 29 80KSW0003 Pinout (TOP VIEW)

41 of 47 March 31, 2008 IDT80KSW0003 Datasheet Pin Summary Pin Name Function Supply / Interface Pin Function Description ADS I 2C( V DD, GND) / CMOS Input I 2C address width select. Set ADS = GND for 7-bit CPS-8 slave address. ADS = Vdd for 10-bit. NOTE: SUPPLY / LEVELS REQUIREMENTS ARE UNIQUE FROM THE OTHER I2C PINS. DNC Do Not Connect. This pin should be left FLOATING. It should not be connected to any other signal or power rail. GND Digital Ground (CMOS) Digital GND. All pins must be tied to single potential power supply ground plane. GNDS Analog Ground (CMOS) Analog GND. All pins must be tied to single potential ground sup- ply plane. ID0 - ID9 I 2C( V DD, GND) / CMOS Input I 2C Slave ID addresses. This should be set statically to Vdd or GND at power-up. NOTE: SUPPLY / LEVELS REQUIREMENTS ARE UNQUE FROM THE OTHER I2C PINS. NC Not connected MM I 2C CMOS Input Select the I 2C Mater or Slave mode. Logic high for Master mode IRQ Interrupt (V DD3, GND) / CMOS Output This is an interrupt output pin whose value is given by the Error Management Block. REF_CLK +/- SERDES Clock (V DD, GND) / Differential Input Differential input clock. This clock is used as the 156.25 MHz refer- ence for standard SERDES operation. REXTN, REXTP Rext External bias resistor. Rextn must be connected to Rextp with a 12k Ohm resistor. This establishes the drive bias on the SERDES output. This provides CML driver stability across process and tem- perature. RST Reset (V DD3, GND) / CMOS Input CPS-8 Global Reset. Sets all internal registers to default values. Resets all PLLs. Resets all port configurations. This is a HARD Reset. RX0+/- to RX7+/- sRIO Receive (V DDS, GNDS) / RIO Differential Input Differential receiver inputs, Lanes 0 to 7 SCL I 2C( V DD3, GND) / CMOS IO I 2C Clock. SDA I 2C( V DD3, GND) / CMOS IO I 2C Serial Data IO. Data direction is determined by the I2C Read/ Write bit. See I2C section for further detail. SPD[1:0] SPD (V DD, GND) / CMOS Input Speed Select Pins. Thes e pins define sRIO port speed at RESET for all ports. The RESET setting may be overridden by subsequent programming of the QUAD_CTRL register. SPD[1:0] = {00 = 1.25G, 01 = 2.5G, 10 = 3.125G, 11 = RESERVED}. These pins must remain STATICALLY BIASED before power-up. TCK JTAG (V DD3, GND) / CMOS Input JTAG Tap Port Clock TDI JTAG (V DD3, GND) / CMOS Input JTAG Tap Port Input TDO JTAG (V DD3, GND) / CMOS Output JTAG Tap Port Output TMS JTAG (V DD3, GND) / CMOS Input JTAG Tap Port Mode Select TRST JTAG (V DD3, GND) / CMOS Input JTAG Tap Port Asynchronous Reset TX0+/- to TX7+/- sRIO Transmit (VDDS, GNDS) / RIO Differential Output Differential transmitter outputs, Lanes 0 to 7 Table 36 Pin Summary (Alphabetical)

42 of 47 March 31, 2008 IDT80KSW0003 Datasheet Package Physical & Thermal Specifications Dimensions: 19 x 19 mm Ball Count: 324 Ball Diameter: 0.6mm Ball Pitch: 1.0mm Estimated Theta J Estimated Theta JC = 0.2 C/W VDD 1.2V Digital Power (CMOS) Digital VDD. All pins must be tied to single potential power supply plane. VDD3 3.3V Digital Power (CMOS) Digital Interface VDD. All pins must be tied to single potential power supply plane. VDDA Analog Power (CMOS) Analog power. VDDS & VDDA may be tied to a common power plane. VDD (core, digital supply) should have its own supply and plane. V DDS SERDES Power (CMOS) Analog power for TX/RX pairs. VDDS & VDDA may be tied to a common power plane. VDD (core, digital supply) should have its own supply and plane. Pin Name Function Supply / Interface Pin Function Description Table 36 Pin Summary (Alphabetical)

43 of 47 March 31, 2008 IDT80KSW0003 Datasheet Figure 30 AR-324 (19 x 19 mm) Package Drawing 1 of 2

44 of 47 March 31, 2008 IDT80KSW0003 Datasheet Figure 31 AR-324 (19 x 19 mm) Package Drawing 2 of 2

45 of 47 March 31, 2008 IDT80KSW0003 Datasheet

22 References & Standards

[1] “The I 2C-BUS Specification”, version 2.1, January 2000, Philips [2] RapidIO Interconnect Specification, Part I: Input/Output Logi cal Specification, Rev. 1.3, 06/2005, RapidIO Trade Association [3] RapidIO Interconnect Specification, Part II: Message Passing Logical Specification, Rev. 1.3, 06/2005, RapidIO Trade Association [4] RapidIO Interconnect Specification, Part III: Common Transpor t Specification, Rev. 1.3, 06/2005, RapidIO Trade Association [5] RapidIO Interconnect Specification, Part VI: Physical Layer 1x/4x LP-Serial Specification, Rev. 1.3, 06/2005, RapidIO Trade Association [6] RapidIO Interconnect Specification, Part VII: System and Device Inter-operability Specificati on, Rev. 1.3, 06/2005, RapidIO Trade As sociation [7] RapidIO Interconnect Specification, Part VIII: Error Management Extensions Specification, Rev. 1.3, 06/2005, RapidIO Trade Association [8] RapidIO Interconnect Specification, Part IX: Logic Layer Flow Control Extensions Specification, Rev. 1.0, 06/2005, RapidIO Trade As sociation [9] RapidIO Interconnect Specification, Annex I: Software/System Bring Up Specification, Rev. 1.3, 06/2005, RapidIO Trade Association [10] IEEE Std 1149.1-2001 IEEE Standard Test Access Port and Boundary-Scan Architecture [11] IEEE Std 1149.6-2003 IEEE Standard for Boundary-Scan Testing of Advanced Digital Networks

46 of 47 March 31, 2008 IDT80KSW0003 Datasheet March 24, 2008: Revision 0. Initial Release. XXXXX AA Device Type Package Process/ Temperature Range Blank I Commercial (0°C to+70°C) Industrial (-40°C to+85°C) AR 80KSW0003 324-Pin RoHS Compliant FCBGA Central Packet Switch

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