CF003 ETC1

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e q ae _. = CF003 Series GaAs A e 4 % Bis Pseudomorphic aay O Low Noise Figure: 1.0 dB at 12 GHz A ee High Gain: 10 dB at 12 GHz ee A Pyqp Power: +22 dBm at 12 GHz A CO aa oN Gq . . a N

1 Wide Dynamic Range Oe

a Active Layers Include: A 4 a | Pseudomorphic HEMT, Ce Epitaxial and Ion Implanted a a Pee, Wafer Qualification Procedure he [| or & Customer Wafer Selection Available . = Celeritek CF003 Series Chips A ‘ Celeritek CF003 Series chips are GaAs-based i transistors which include the CF003-01, CF003-02 and iy CF003-03 models. They are 600 um gate width transistors Lea. with sub half-micron gate length and Celeritek’s proprietary A r. Silicon Nitride passivation. li me, Celeritek’s Wafer Qualification Procedure for CFO03 a ee oa Series FETs consists of DC, RF and reliability testing of both aa 4 individual die and generic 6 to 18 GHz amplifier modules. i a The CF003-01, with it’s unique straight gate design, a ae provides high gain and medium output power. It is suitable in ve eae narrow- and wide-band amplifier applications up to 26 GHz. _ s (i The CF003-03 provides low-noise and wide dynamic z < thes bites range up to 26 GHz. It is suitable for narrow- and wide-band sat a | 7 amplifiers. Superior gi also makes this model useful for high 7. a oe gain feed back amplifiers. Its rugged construction allows it to ee a fi withstand the same input power as conventional MESFETs. aan oe : : oo All CF003 Series devices are available in chip form ee ET eed and are suitable for airborne, shipboard and ground-based Bee ee ee equipment. Screening includes MIL-STD-750 Class B. Class S : 2 ee eS eee and commercial screening. These devices are also available in “hea eee packaged form. Please consult the CFB003 Series and CFC003 ° Series data sheets or contact the factory for further information. ‘ ech [157]

Specifications (T 4 = 25°C) CF003-01 CF003-02 CF003-03 lon Pseudomorphic Active Layer Implanted HEMT Frequency Symbol | Parameters and Conditions (GHz) Min Typ Max Min’ Typ Max Min’ Typ Max NFopt Optimum Noise Figure 12.0 dB 18 26 14 2.0 1.0 1.4 Vpg = 3.0 V, Ipg = 30 mA Vpg = 3.0 V ing = 30 mA 1So4!? 50 Ohm Insertion Gain 2.0 dB 16.0 17.0 18.0 18.0 oB 3.0 40 5.0 Pigp_ | Power Output @ 1 dB GC 12.0 22.0 20.0 Vpg = 6.0 V, Ipg = 80 mA Im Transconductance mS 120 150 180 Vps = 3.0 V, Vag = 0 V Ipgg_| Drain Current mA | 120 180 240 | 120 180 240 | 120 180 240 Vps = 3.0 V, Veg =0V Vps = 3.0 V, Ipg = 1 mA Igp = 100 pA Absolute Maximum Ratings Chip Outline Drawing Parameter Symbol Ratings Drain-Source Voltage Vps 8v + 7201283. ————-—-+ | 50/2.0--| Gate-Source Voltage Ves -5V oe Drain Current Ips Ipss 502.0 OD ee & | Continuous Dissipation Pr 1600 mw saben ae: al 250/9.8 Channel Temperature Tou 175°C Se) er ee H Storage Temperature Tste -65°C to +175°C. J b- 502.0 _ C 50/20 i | 100/3.9 Typical Noise Parameters - CF003-03 Vps= 3.0V, Ipg= 30mA CFO03 CHIP (UNITS IN MICRONS/MILS) eo THICKNESS: 110 MICRONS/4.3 MILS Frequency NFopt Ga ‘Gamma opt Rni50 (GHz) (a8) (dB) (Mag) __(Ang) 20 0.38 188 0.84 ¥ 3.28 Die Attach and Bonding Procedures . . . . a Die Attach: Conductive epoxy or eutectic die attach is 80 0.62 136 038 Hy 6.18 recommended. For eutectic die attach: Preform: AuSn (80%. 10.0 0.86 11.1 048 «114 0.09 Au, 20% Sn); Stage Temperature: 290°C, +5°C; Handling 18-0 122 33 oe ara 0.04 stressed); Thermocompression bonding is preferred over 20.0 146 0 74 053-135 0.14 Stage Temperature: 250°C; Bond Tip Temperature: 150°C; Bonding Tip Pressure: 18 to 40 gms depending on size of wire. — ET [158 ]

Typical Performance (T ‘A = 25°C) NOISE FIGURE AND associateD GAIN vs FREQUENCY NOISE FIGURE AND ASSOCIATED GAIN vs Ing x Vps = 3, Ipg = 30 mA 08 4 Pog na een ote 2e co | DNA aT ees Z10 TP <1 ws 3 of SS <A 8 z Peele USER) a “TTT TET TTT % 4 6 8 10 20 26 %0 20 30 40 50 60 70 80 90 100110 120 130 FREQUENCY, GHz Ipg, mA S2q AND MSG vs FREQUENCY at LOW NOISE BIAS So AND MSG vs Focauceicy at POWER BIAS

05 Vps = 3V, Ing = 30 mA Vps = 6 V, Ipg = 80 mA

g a uso | a ot TTP AN a | [TP SAY 2 4 6 8 10 20 26 2 4 6 8 10 20 26 FREQUENCY, GHz FREQUENCY, GHz S41 AND Spo vs FREQUENCY at LOW NOISE BIAS S41 AND Spo vs FREQUENCY at POWER BIAS Vps =3V, Ipg = 30 mA ios =6 V, Ipg = 80 mA j50 j50 j100 ae A j100 j10 Le SN j10 MS SAN ANE] (NRE “AD LF RO -j50 -j50 FREQUENCY 2.0 to 26.0 GHz FREQUENCY 2.0 to 26.0 GHz PEL EDPItTrew OS a 5 a=aze [159

Typical Scattering Parameters, Common Source (S-Parameters Include Bonding Wire Parasitics) CF003-01 at Power Bias Vps =6 V, Ipg = 80 mA Frequency SH So4 Si2 Soo « MSG (GHz) (Mag) (Ang) (dB) (Mag) (Ang) (dB) (Mag) _(Ang) (Mag) (Ang) (dB) CF003-03 at Low Noise Bias Vos = 3; Ipg = 30 mA Frequency S44 Sai St2 S22 K MSG (GHz) __(Mag)_(Ang)_(@B)_(Mag)_ (Ang) _(dB)_(Mag)_(Ang)___(Mag)_(Ang) (GB) Device Model Wafer Qualification c Procedure ‘CFO03-01 _CFO03-03 ta Ra | od Rg res Parameters !DS=80mA IDS=30mA Units C, Cas 100% Visual Insp. ty 21 020. nH 9s em(t) Rg 0.50 050 a im Sample Chip) NF, Power, Cog 0.088 0.068 pF Gm 134 158 mS. ‘Sample Circuit | ne. power, Gain, t 28 23 ps Rs Performance Tests | yswR Cog 08 015 pF 6-18 Giz Module Ras 87 92 Q Rg 0.67 0.67 Q Ls Power Blast & lg 021 022 0 nH Assesment | Burn-in fs a teem 80% of tested samples must meet ts o4 oo me ° specifications for wafer acceptance

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Santa Clara, California 95054 (408) 986-5060 Fax: (408) 986-5095 3-91 Specifications subject to change Wan Sasa 1 OS [160]