CCE4503 RENESAS

Document overview

  • Manufacturer or author: Provided By www.digicamel.com(free datasheet download site)
  • PDF pages: 17

Technical content

Datasheet sections

  • 1.1 Block Diagram
  • 2.1 Pin Assignment
  • 2.2 Pin Descriptions
  • 2.3 Pin Type Definition
  • 3.1 Absolute Maximum Ratings
  • 3.2 ESD Ratings
  • 3.3 Recommended Operating Conditions
  • 3.4 Electrical Characteristics
  • 3.5 Thermal Characteristics
  • 4.1 Output Stage
  • 4.2 Current limit and slew rate configuration
  • 4.3 Automatic Recovery
  • 4.4 Wake-up detection
  • 4.5 Error output handling
  • 4.6 Overtemperature detection
  • 4.7 Allowed Reverse polarity connections
  • 5.1 Package Outlines
  • 5.2 Tape and Reel Information
  • 5.3 Soldering Information

Features

■ IO-Link Compliant Transceiver ■ One IO-Link channel with up to 250 mA permanent driving current ■ 350 mA peak (typ.) ■ Configurable PNP-, NPN- and ■ Push-Pull mode ■ Configurable current limit ■ Configurable slew rate limitation for optimized EMC ■ Wake-up detection ■ Small DFN 10-pin package ■ 3 LDO Options with up to 20 mA ■ 3.3V LDO output ■ 5V LDO output ■ External LDO ■ Reverse-polarity protection ■ Overcurrent detection ■ Undervoltage detection ■ Overtemperature detection

Applications

■ IO-Link Sensors ■ IO-Link Actuators ■ High voltage level shifter ■ Industrial automation Figure 1. Application Diagram

R15DS0024ED0204 Rev.2.5 Jan 25, 2023 Page 3 1. Overview

1.1 Block Diagram

3.3V / 5V Logic Core Protection Protection Protection HV-Driver Diagnostics CCE4503 On Chip Oscillator I/O-Link RX CQ /over temp /over current /under voltage NWUP TXEN TXD ILIM RXD NERR VDD Figure 2: Block Diagram

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2.1 Pin Assignment

Figure 3: DFN10 Pinout Diagram (Top View)

2.2 Pin Descriptions

Pin Number Pin Name Type Rest State Description 1 VDD PWR 3.3V - 5V Supply Voltage Input / Output

2 NERR OD High-Z Error Output (Overcurrent detection, Undervoltage

detection, Overtemperature detection

3 RXD DO Channel signal output

4 TXD DI, PU Channel signal input

5 TXEN DI, PD Channel driver enable

6 ILIM AI Current Limit configuration

7 L- PWR Ground supply (IO-Link)

8 CQ DIO IO-Link data

9 L+ PWR Positive supply (IO-Link)

10 NWUP OD High-Z Wake-up detection (Channel short detection)

PAD Thermal Pad GND Thermal Pad, connect to VSS or leave open

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2.3 Pin Type Definition

OD Digital Output open drain PU Pull-up resistor (fixed) PD Pull-down resistor (fixed) PWR Power AI Analog input AO Analog output AIO Analog input/output BP Back drive protection SPU Switchable pull-up resistor SPD Switchable pull-down resistor GND Ground

R15DS0024ED0204 Rev.2.5 Jan 25, 2023 Page 6 3. Characteristics

3.1 Absolute Maximum Ratings

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions can adversely impact product reliability and result in failures not covered by warranty. Parameter Conditions Name Min Max Unit Supply Voltage Static, referenced to VL- VL+ - VL- -40 40 V Supply Voltage Dynamic (t ≤ 100 µs) VL+ - VL-_pulse -42 42 V Operating Temperature Ambient temperature Tamb -40 +125 °C Storage Temperature Tstorage -55 +175 °C Junction Temperature Tj -40 +150 °C Voltage at pin CQ Referenced to VL-: VCQ - VL- VCQ,max VL- VL+ V Voltage at all other pins Referenced to VL- VIOmax -0.7 VDD + 0.7 V Logic Level Supply Voltage VDDmax 6 V Output current At pin RXD, NWUP, NERR IOutMax -5 5 mA

3.2 ESD Ratings

ESD Model/Test Rating Unit Human Body Model (Tested per JS-001-2012 HBM) 4 (81) kV ESD Contact Discharge (Tested per IEC61000-4-2)2 16 kV Surge (Tested per IEC61000-4-5, adapted to 500 Ω 1.2/50 μs)4 0.8 (55) kV Latch-Up (Tested per JESD78E; Class 1 & 2) 100 mA

1 Higher Rating for L+, L- and CQ

2 Valid for L+, L- and CQ

3 Valid for L+, L- and CQ

4 Valid for L+, L- and CQ; 100 nF between L+ and L-, 1 µF between VDD and GND

5 Up to 5 kV with TVS Diodes (e.g. SMAJ33A) connected between L+, L- and CQ (higher Voltages have not been tested)

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3.3 Recommended Operating Conditions

Parameter Conditions Pin Name Min Typ Max Unit Main Supply Voltage 7, 9 VL+ 7 36 V Supply Voltage Ripple Fripple = DC … 100kHz VL+ > 12 V 9 ∆VL+ 1 V Voltage CQ Receiver mode 8 VCQ_MAX VL- VL+ V Logic Level Supply Voltage External Supply 1 VDD 3 5.5 V LDO Output Current 3.3V LDO or 5V LDO, VL+ ≤ 24V

1 IVDD 20 mA

ILIM External Resistor To L- 6 RILIM 0 100 kΩ LDO External Capacitor To L- 1 CLDO 0.8 1 1.2 µF

3.4 Electrical Characteristics

3.4.1. Input / Output CQ Parameter Conditions Pin Name Min Typ Max Unit Output voltage low level active pull down, IOL=-200mA 8 VOL 0 1.5 V Output voltage high level active pull up, IOH=+200mA 8 VOH VL+ - 1.5 VL+ V Leakage current input enabled 0 ≤ VCQ ≤ VL+ - 0.1 V

8 Ileak -2 2 µA

Current of CQ channel 8 ICQmax -250 250 mA Output source current limit RILIM = 0 or hZ RILIM = 100 kΩ

8 IlimP 300

Output sink current limit RILIM = 0 or hZ RILIM = 100 kΩ

8 IlimN -400

-70 -350 -50 -300 -35 mA Load capacitance 8 CL 5 nF Inductive load 8 LLoad 1.5 H Output rise/fall time (20% to 80%) Open load, RILIM = 0 or hZ 8 tr,f 869 ns Switch On Time 8 tDLY_LH 4 µs Switch Off Time 8 tDLY_HL 4 µs

R15DS0024ED0204 Rev.2.5 Jan 25, 2023 Page 8 Short circuit detection time

8 TSHORT 300 µs

Short circuit disable time RILIM ≠ hZ 8 TSHORT_DIS 15 ms Wake-up detection time 8 TWAKE 40 80 100 µs Input threshold high level 8 VIH 10.5 11.75 13 V Input threshold low level 8 VIL 8 9.75 11.5 V Hysteresis between input thresholds high and low

8 VHyst 2 V

3.4.2. Digital I/O Parameter Conditions Pin Name Min Typ Max Unit Input Input Voltage LOW VDD = 3.3 V 4, 5 VIN_L_3V3 1 V Input Voltage HIGH VDD = 3.3 V 4, 5 VIN_H_3V3 2.3 V Input Voltage LOW VDD = 5.0 V 4, 5 VIN_L_5V 1.5 V Input Voltage HIGH VDD = 5.0 V 4, 5 VIN_H_5V 3.5 V Input Pull-Up current VDD - VSS = 5.0 V, Vpin=0V 4, 5 IPU_5V 3 30 110 µA Input Pull-Down current VDD - VSS = 5.0 V, Vpin=5.0V 4, 5 IPD_5V -110 -30 -3 µA Input Voltage LOW VDD = 3.3 V 4, 5 VIN_L_3V3 1 V Output Output Voltage LOW VDD - VSS = 3.3 V IOUT_LOW = 2 mA 2, 3, 10 VOUT_L 0.7 V VDD - VSS = 5.0 V IOUT_LOW = 2 mA 2, 3, 10 VOUT_L 0.8 V Output Voltage HIGH VDD - VSS = 3.3 V IOUT_HIGH = 2 mA 3 VOUT_H 2.6 V VDD - VSS = 5.0 V IOUT_HIGH = 2 mA 3 VOUT_H 4.2 V

R15DS0024ED0204 Rev.2.5 Jan 25, 2023 Page 9 3.4.3. 3.3V / 5V Voltage Regulator Parameter Conditions Pin Name Min Typ Max Unit Output Voltage VDD 3.3V Regulator 1 VDD3V3 3.0 3.3 3.6 V 5V Regulator 1 VDD5V 4.5 5 5.5 V Voltage Drop Load Current = 20 mA 1 VDO 2 V Output Current VDD 1 IVDD 20 mA Line regulation IOUT = 1 mA VL+ = 24 V

1 REG 2 mV/V

Load regulation DC current up to 20 mA VL+ = 24 V 1 1 % Power Supply rejection ratio 100 kHz, IOUT = 20 mA 1 PSRR 40 dB Power-On Threshold Only applies to the driver without LDO (CCE4503- 0V) 1 VRST 2.7 3.0 V Undervoltage lockout voltage (VL+)

1 VL+,min 6 V

voltage (VDD)

1 VDD,min 3 V

Start-up time 1 5 µs

3.5 Thermal Characteristics

Parameter Description Conditions Min Typ Max Unit TALARM_H Alarm temperature (higher threshold) 150 165 180 °C TALARM_L Alarm temperature (lower threshold) 140 155 170 °C TWARNING Warning temperature (higher threshold) 125 140 155 °C Rtja Thermal resistance (junction to ambient) 30 K/W 4. Electrical Specifications CCE4503 is a fully reverse polarity protected IO-Link slave device with one IO-Link channel. The system consists of a high voltage output stage with integrated overcurrent protection, a high voltage input stage with a spike-tolerant filter, a logic core with UART interface, an internal oscillator and an optional LDO. The LDO output voltage is factory programmed and needs to be specified with the order. To simplify the IO -Link protocol handling, a wake-up detection and automatic recovery function are implemented. Additional advance protection features such as overtemperature detection and undervoltage detection ensure robust functionality in industrial applications. All pins are ESD-protected.

4.1 Output Stage

into an inactive low-power state. setting TXD low and using TXEN as control pin. Table 1. Output stage truth table

4.2 Current limit and slew rate configuration

automatic recovery disabled.

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4.3 Automatic Recovery

If a short is detected, the output stage is automatically disabled after the time tSHORT. The automatic recovery function enables the output again after tSHORT_DIS and checks if the overcurrent is still present (see Figure 4). Channel enabled Channel automatically disabled Channel disabled Overcurrent detected Set TXEN = 1 Reset after tshort_dis Set TXEN = 0 Figure 4: Automatic recovery

4.4 Wake-up detection

An overcurrent pulse of tWAKE will be detected as wake-up pulse. When a wake-up pulse is detected, the output of NWUP will switch from high impedance to low until TXEN is toggled by the microcontroller. An overcurrent pulse > tWAKE will be detected as overcurrent fault condition. An overcurrent pulse < tWAKE will not be detected.

4.5 Error output handling

The error output NERR combines the indication of three error sources and will be tied low if any fault condition is detected. The following error sources are indicated by NERR: ■ Overtemperature ■ Undervoltage ■ Overcurrent The overtemperature and undervoltage detections are combinational outputs and keep the NERR signal low as long as the error is present. The overcurrent detection is latched and will be reset when the CCE4503 leaves the transmit mode (TXEN = 0).

4.6 Overtemperature detection

The overtemperature detection detects 3 thresholds: ■ At TWARNING the output of NERR will be tied low. This is a combinational signal and cannot be reset by the MCU. It will be reset once the temperature drops below TWARNING. ■ At TALARM_H, the chip will switch off the outputs. This cannot be reset by the MCU. ■ When the temperature drops again below TALARM_L, the output is released and can be controlled by TXEN and TXD.

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4.7 Allowed Reverse polarity connections

The CCE4503 is designed to handle all possible permutations of reverse polarity.

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5.1 Package Outlines

Figure 5: DFN10 Package Outline Drawing

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5.2 Tape and Reel Information

Figure 6: Tape and Reel Information

5.3 Soldering Information

Refer to the IPC/JEDEC standard J-STD-020 for relevant soldering information. This document can be downloaded from http://www.jedec.org.

R15DS0024ED0204 Rev.2.5 Jan 25, 2023 Page 15 6. Ordering Information The ordering number consists of the part number followed by a suffix (shown as "xx") indicating the LDO option. For details and availability, please consult your Renesas Electronics local sales representative. Table 3: Ordering Information Part Number Package Size (mm) Shipment Form Pack Quantity CCE4503 xx LDO DFN10 3 x 3 T&R 4000 Part Number Legend: 7. Application Information The CCE4503 may need to be connected to some external components depending on the desired operating environment: ■ If an LDO is selected (5V or 3.3V), a 1 µF capacitor from VDD to L- must be provided by the customer ■ Outputs NERR and NWUP are open-drain outputs. Usually, the internal pull-up resistors of the MCU can be used. If no pull-up resistors can be configured, the customer needs to connect external resistors. ■ A resistor RLIM may be used to set the overcurrent limit and slew rate. For maximum slew rate and overcurrent limit, the pin can be connected to VSS or left open. Figure 7: CCE4503 application

R15DS0024ED0204 Rev.2.5 Jan 25, 2023 Page 16 8. Revision History Revision Date Description 2.5 25-Jan-2023 Corrected formatting of document Added Chapter ESD Ratings 2.4 06-Dec-2022 Updated to Renesas Added Tape and Reel Information 2.3 23-Jul-2020 Changed Ordering Information 2.2 27-May-2020 Corrected Electrical Characteristics 2.1 26-May-2020 Corrected Error! Reference source not found. Added Errata sheet note 2.0 20-Feb-2020 Initial version. Preliminary

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