FAN54005 ONSEMI
Document overview
- Manufacturer or author: Provided By digicamel.com
- PDF pages: 32
Technical content
Features
- Fully Integrated, High−Efficiency Charger for Single−Cell Li−Ion and Li−Polymer Battery Packs
- Charge V oltage Accuracy: ±0.5% at 25°C Charge V oltage Accuracy: ±1% from 0 to 125°C
- Supports 200 mA to 1.45 A Systems 95% Efficiency for 200 mA−Hour Batteries 94% Efficiency for 500 mA−Hour Batteries 90% Efficiency for 1.0 A−Hour Batteries
- ±5% Input Current Regulation Accuracy
- ±5% Charge Current Regulation Accuracy
- 20 V Absolute Maximum Input V oltage
- 6 V Maximum Input Operating V oltage
- Charge Parameters Programmable through High−Speed I2C Interface (3.4 Mb/s) with Fast Mode Plus Compatibility ♦ Input Current ♦ Fast−Charge / Termination Current ♦ Charger V oltage ♦ Termination Enable
- 3 MHz Synchronous Buck PWM Controller with Wide Duty Cycle Range
- Small Footprint 1 /C0109H External Inductor
- Safety Timer with Reset Control
- 1.8 V Regulated Output from VBUS for Auxiliary Circuits
- Dynamic Input V oltage Control Automatically Reduces Charging Current with Weak Input Sources
- Low Reverse Leakage to Prevent Battery Drain to VBUS
- 5 V , 500 mA Boost Mode for USB OTG for 3.0 V to
4.5 V Battery Input
- Available in a 1.96 x 1.87 mm, 20−bump, 0.4 mm Pitch
Applications
- Wireless Speakers, Headphones
- Cell Phones, Gaming Devices
- Toys, Drones, Digital Cameras
- IoT Devices
- E−Cigs, Vapes
ORDERING INFORMATION
Part Number Temperature Range Package PN Bits: IC_INFO[4:2] Packing† FAN54005UCX −40°C to +85°C 20−Bump, Wafer−Level Chip−Scale Package (WLCSP), 0.4 mm Pitch, 1.96 x 1.87 mm
101 Tape and Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. www.onsemi.com WLCSP
20 BALL
Figure 3. WLCSP−20 Pin Assignments Table 2. PIN DEFINITIONS A1, A2 VBUS Charger Input Voltage and USB−OTG output voltage. Bypass with a 1 /C0109F capacitor to PGND. A3 NC No Connect. No external connection is made between this pin and the IC’s internal circuitry. A4 SCL I2C Interface Serial Clock. This pin should not be left floating. high−voltage input switch. Bypass with a minimum of 4.7 /C0109F, 6.3 V capacitor to PGND. B4 SDA I2C Interface Serial Data. This pin should not be left floating. C1−C3 SW Switching Node. Connect to output inductor. C4 STAT Status. Open−drain output indicating charge status. The IC pulls this pin LOW when charging. of CMID should be as short as possible. sense current into the battery. Bypass this pin close to RSNS with a 0.1 /C0109F capacitor to PGND. ters. When this pin is HIGH, the 15−minute timer is reset. This pin does not affect the 32−second timer. up to 2 mA of DC load current. E4 VBAT Battery Voltage. Connect to the positive (+) terminal of the battery pack and close to RSNS.
Table 3. ABSOLUTE MAXIMUM RATINGS should not be assumed, damage may occur and reliability may be affected.
- SW only: Switching transients of −0.7 V, minimum, with duration <20 nsec, are acceptable.
Table 4. RECOMMENDED OPERATING CONDITIONS the Recommended Operating Ranges limits may affect device reliability. Table 5. THERMAL PROPERTIES given ambient temperature TA. For measured data, see Thermal Regulation and Protection.
Table 6. ELECTRICAL SPECIFICATIONS VBUS = 5.0 V; HZ_MODE; OPA_MODE = 0; (Charge Mode); SCL, SDA, OTG = 0 or 1.8 V; and typical values are for TJ = 25°C.
1.8 V LINEAR REGULATOR
VBUS = 5.0 V; HZ_MODE; OPA_MODE = 0; (Charge Mode); SCL, SDA, OTG = 0 or 1.8 V; and typical values are for TJ = 25°C.
VBUS = 5.0 V; HZ_MODE; OPA_MODE = 0; (Charge Mode); SCL, SDA, OTG = 0 or 1.8 V; and typical values are for TJ = 25°C. performance may not be indicated by the Electrical Characteristics if operated under different conditions.
- Negative current is current flowing from the battery to GND (discharging the battery).
- Q2 always turns on for 60 ns, then turns off if current is below I
- Guaranteed by design; not tested in production.
- This tolerance (%) applies to all timers on the IC, including soft −start and deglitching timers.
Table 7. I2C TIMING SPECIFICATIONS Guaranteed by design, VBAT ≥ 2.5 V if valid VBUS not present.
Unless otherwise specified, circuit of Figure 1, RSNS = 68 m/C0087, VOREG = 4.2 V, VBUS = 5.0 V, and TA = 25°C.
4.7 VBUS
5.0 VBUS
5.5 VBUS
Figure 6. Battery Charge Current vs. VBUS with Figure 7. Battery Charge Current vs. VBUS with Figure 8. Charger Efficiency, No Figure 9. Charger Efficiency vs. VBUS, Figure 10. Auto−Charge Startup at VBUS Plug−in, Figure 11. Auto−Charge Startup at VBUS Plug−in,
Unless otherwise specified, circuit of Figure 1, RSNS = 68 m/C0087, VBAT = 3.6 V, and TA = 25°C.
3.0 VBAT
3.6 VBAT
4.2 VBAT
Figure 21. Efficiency vs. VBAT Figure 22. Efficiency Over−Temperature Figure 23. Output Regulation vs. VBAT Figure 24. Output Regulation Over−Temperature Figure 25. Quiescent Current
Unless otherwise specified, circuit of Figure 1, RSNS = 68 m/C0087, VBAT = 3.6 V, and TA = 25°C. Figure 26. Boost PWM Waveform Figure 27. Boost PFM Waveform Figure 28. Output Ripple vs. VBAT Figure 29. Output Ripple vs. Temperature Figure 30. Startup, 3.6 VBAT, 44 /C0087 Load, Additional Figure 31. VBUS Fault Response, 3.6 VBAT
Unless otherwise specified, circuit of Figure 1, RSNS = 68 m/C0087, VBAT = 3.6 V, and TA = 25°C. Figure 32. Load Transient, 5−155−5 mA, tR=tF=100 ns Figure 33. Load Transient, 5 −255−5 mA, tR=tF=100 ns
Table 8. OREG BITS (REG 02[7:2]) vs. CHARGER Table 9. PROGRAMMABLE CHARGING PARAMETERS
- The battery voltage falls below VOREG – VRCH
- VBUS Power on Reset (POR)
- CE or HZ_MODE is reset through I2C write to CONTROL1 (REG 01) register. Charge Current Limit (IOCHARGE) Charge current limit is established by regulating the voltage across RSNS (VRSNS) to the value controlled by the IOCHARGE bits. Select RSNS in the range of 68 m/C0087 < RSNS < 180 m/C0087. Charge current is further limited by the IO_LEVEL (Reg 05[5]) bit by default (IO_LEVEL=1). When IOLEVEL=1, the voltage across R SNS is limited to 34.0 mV . When IO_LEVEL=0 charge current is limited by the IOCHARGE bits.
Table 10. IOCHARGE CURRENT AS FUNCTION OF Table 11. ITERM CURRENT AS FUNCTION OF ITERM
VBUS OVP fault or a VRCH recharge initiation). and other non−compliant chargers are rejected. Section references Figure 39. timer (t15MIN). When this times out, charging is terminated. t15MIN timer, which in turn starts a 32−second timer (t32S). Setting the TMR_RST bit (REG 00[7]) resets the t32S timer. prevents overcharge if the host fails to reset the t32S timer. programmed by the IINLIM bits (REG 01[7:6]). Table 12. INPUT CURRENT LIMIT
11 No limit
Figure 36. Charger VBUS POR
Figure 37. Charge Mode
Table 13. VSP AS FUNCTION OF VSP BITS (REG 05[2:0]) register is locked until VBAT falls below VSHORT. Table 14. ISAFE (IOCHARGE Limit) AS FUNCTION OF Table 15. VSAFE (VOREG Max. Limit) AS FUNCTION the die cools to about 120°C. difference between the die temperature and ambient. Table 16. EVALUATION BOARD MEASURED /C0113JA
current is disabled by body switching Q1.
- Pulses the STAT pin, sets the STAT bits to 11, and
suspended USB port or a low−current−capable OTG device.
- Sets the FAULT bits to 001, sets the STAT bits to
11, and pulses the STAT pin. is cleared and charging resumes after VBUS is revalidated. bits to 100, sets the STAT bits to 11, and pulses the STAT pin. the battery is present and the IC sets the FAULT bits to 000.
- Sets the registers to their default values.
- Sets the FAULT bits to 111.
- Resumes charging with default values after tINT.
start. To avoid this behavior, use the following sequence.
- Set the OTG pin HIGH. When VBUS is plugged
- Program the Safety Register.
- Set OREG to the desired value (typically 4.18).
- Reset the IO_LEVEL bit, then set IOCHARGE.
and provides a fault indicator for interrupt driven systems. Table 17. STAT PIN FUNCTION
0 X OPEN
1 Charging LOW
in Charge Mode. See Table 18 for details. Table 18. FAULT STATUS BITS DURING CHARGE MODE Setting the RESET bit clears all registers (except Safety). Table 19. DISABLE PIN AND CE BIT FUNCTIONALITY charging, the t15MIN timer is reset. operational mode of the charger. Table 20. OPERATION MODE CONTROL
0 X 1 Charge Configure
1 X X High Impedance
Table 21. ENABLING BOOST
1 ACTIVE X X Enabled
0 X 1 X Disabled
1 ACTIVE 1 1 Disabled
0 ACTIVE 0 0 Disabled
POR or reading REG00 clears the fault condition. appears as a constant output resistance. seen in Figure 32 and Figure 40. Figure 40. Output Resistance (ROUT)
bottom of its output voltage ripple at 5.07 V in PFM Mode. Table 22. BOOST PWM OPERATING STATES 560 /C0109s, a FAULT state is initiated. is closed and the current limit is set to 100%. 384 /C0109s period, a fault state is initiated. frequency reasonably constant in CCM. actual output voltage is greater than the regulation point.
- The power stage is in High−Impedance Mode.
- The FAULT bits (REG 00[2:0]) are set per
Table 23. FAULT BITS DURING BOOST MODE 1 0 0 N/A: This code does not appear. 1 1 0 Timer fault; all registers reset. 1 1 1 N/A: This code does not appear. Figure 41. Boost Response Attempting to Start into through I 2C by setting the DIS_VREG bit (REG 05[6]).
Table 25. BIT DEFINITIONS FOR FIGURE 46 AND FIGURE 47 A ACK. The slave drives SDA to 0 to acknowledge the preceding packet. A NACK. The slave sends a 1 to NACK the preceding packet.
1 A Data A
Figure 46. Write Transaction Figure 47. Read Transaction The nine FAN54005 user−accessible registers are defined in Table 26. Table 26. I2C REGISTER ADDRESS
Table 27. REGISTER BIT DEFINITIONS This table defines the operation of each register bit for all IC versions. Default values are in bold text.
7 TMR_RST OTG 1 W Writing a 1 resets the t32S timer; writing a 0 has no effect
6 EN_STAT 0 R/W Prevents STAT pin from going LOW during charging; STAT pin still pulses to enunciate
1 Enables STAT pin LOW when IC is charging
01 Charge in progress
10 Charge done
11 Fault
3 BOOST 0 R IC is not in Boost Mode
1 IC is in Boost Mode
3 TE 0 R/W Disable charge current termination
1 Enable charge current termination
1 HZ_MODE 0 R/W Not High−Impedance Mode See Table 21
1 High−Impedance Mode
0 OPA_MODE 0 R/W Charge Mode
1 Boost Mode
1 OTG_PL 0 R/W OTG pin active LOW
1 OTG pin active HIGH
0 OTG_EN 0 R/W Disables OTG pin
1 Enables OTG pin
7 RESET 1 W Writing a 1 resets charge parameters, except the Safety register (REG 06), to their de-
This table defines the operation of each register bit for all IC versions. Default values are in bold text.
3 Reserved 1 R Unused
7 Reserved 0 R Unused
5 IO_LEVEL 0 R/W Output current is controlled by the IOCHARGE bits
1 Output current control is limited to 34 mV across RSNS
4 SP 0 R DIVC is not active (VBUS is able to stay above VSP)
1 DIVC has been detected and VBUS is being regulated to VSP
3 EN_LEVEL 0 R DISABLE pin is LOW
1 DISABLE pin is HIGH
7 Reserved 0 R Bit disabled and always returns 0 when read back
7 ITERM_CMP R ITERM comparator output, 1 when VRSENSE > See Table 11
6 VBAT_CMP R Output of VBAT comparator
5 LINCHG R 30 mA linear charger ON
4 T_120 R Thermal regulation comparator; when=1 and T_145=0, the charge current is limited to
3 ICHG R 0 indicates the IOCHARGE loop is controlling the battery charge current
2 IBUS R 0 indicates the IBUS (input current) loop is controlling the battery charge current
1 VBUS_VALID R 1 indicates VBUS has passed validation and is capable of charging
0 CV R 1 indicates the constant−voltage loop (OREG) had been active at least once since the
maximized to improve thermal performance if possible. Figure 48. PCB Layout Recommendations The table below pertains to the MOD information on the following page. ON Semiconductor is licensed by the Philips Corporation to use the I2C bus protocol.
WLCSP20 1.96x1.87x0.586 CASE 567SL ISSUE O DATE 30 NOV 2016 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. 98AON16608GDOCUMENT NUMBER: DESCRIPTION: Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1WLCSP20 1.96x1.87x0.586 © Semiconductor Components Industries, LLC, 2019 www.onsemi.com
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