BT8510

BT8510 ETC1

Document overview

• Manufacturer or author: Provided By www.digicamel.com(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 78

Technical content

ie? ae ee) Product Description Sy —. Features and Modes of Operation This specification describes the Bt8510 E1 (often called CEPT or DS1A) frame synchronization, signal generation, and recovery circuit for application in digital terminal interfaces operating at 2.048 Mb/s. Applications for this device include digital cross-connect systems, digital loop concentrators, DCME equipment, cus- tomer premise multiplexers, network managers, and PBXs. The circuit operates with Integrated Services Digital Network (ISDN) primary rate digital streams operating at a data rate of 2.048 Mb/s according to ITU-T Recommendation G.703. The El framer is designed to meet the basic requirements of ITU-T Recom- mendation G.704. It can be used in the development of equipment to conform The physical line interface is included on-chip, accommodating both 75 ohm and 120 ohm cables. Data and clock can be recovered from received signals with up to —12 dB (120 ohm cables) and -15 dB (75 ohm cables) of attenuation. The analog circuits in the physical line interface may be powered-down if unused. Digital logic-level inputs and outputs are also provided for this case. For ISDN applications, additional functions are provided to meet the require- ments of ITU-T 1.431, 1.604 and G.962. These functions include LAPD format- ting in Time Slot 16 (TS16), full access to the Sa bits on a multiframe basis, line loopback, per-DSO loopbacks, idle code word insertion, and comprehensive CRC-4 functions. An off-line framer is provided in the receiver. The framer has an average reframe time to the Frame Alignment Signal (FAS) of about 1 ms. Separate multi- frame synchronization circuits are provided in the receiver for recovery of received Channel Associated Signaling (CAS) and the CRC-4 multiframe signals. CRC-4 error checking is performed and Far-End Block Error (FEBE) bits are transmitted in accordance with G.706 if these modes are enabled. Through an 8-bit parallel interface, an external microprocessor or microcon- troller can monitor all status conditions, provide configuration control, and access signaling and PCM data. The processor interface uses a multiplexed address/data bus, and can be directly connected to Intel 8051 and Motorola 68HC11 microcon- trollers, without glue logic. eee Brooktree* 1 @ 7811073 0033241 410

Product Description Bt8510 & Features and Modes of Operation Individual 16-byte buffers are provided for both transmit and receive data in Time Slot 16 (one 16-byte buffer per direction). In CAS mode, this corresponds to a full multiframe. In LAPD mode, this may only be a partial message (multi- frame synchronization is irrelevant). LAPD flag generation and detection (idle and abort bytes), FCS generation and checking, and zero stuffing and removal are provided. General-purpose unformatted data may be processed through the TS16 buffers including Common Channel Signaling (CCS). The Bt8510 provides for both transmit and receive synchronization to a multi- frame reference. To enable received signal synchronization to a single clock ref- erence, the receive circuitry provides slip buffers and signaling reinsertion. The slip buffer removes all input jitter because slip buffer outputs are synchronized to ; the local system clock. Signaling freeze is provided during an out-of-frame or -multiframe synchronization condition. This prevents updating of the received signaling bit register from TS16, unless framing is valid. An optional short-delay mode allows specialized use of the slip buffer for delay-sensitive applications such as wireless communication systems. . Fixed PCM idle codes can be optionally inserted in the transmitted PCM data stream from a buffer that is loaded by the host processor. Each of the 32 time slots in the E1 signal has a corresponding control word that allows the transmitted PCM to be set on a DSO basis. This feature may also be used to insert errors in the transmitted framing pattern, CAS or CCS can be inserted via a 16-byte register that is optionally inserted into TS16, passed through from the Transmit PCM In pin (XPCMD), or inserted serially onto an external pin (XSIGI). This per-channel control word is also used to control the transmit time slot indication signal (XINDY). Received CAS is recovered from TS16 and loaded into the receive TS16 sig- naling buffer. This buffer has two multiframes of memory that allow the old sig- naling information to be retained in the event of an out-of-frame or multiframe synchronization condition. Signaling data is provided on an external pin (SLPSIGO) and also multiplexed in the full rate stream as it is received (it may also be read via the microprocessor port). PCM insertion of a fixed data pattern is also provided in the receive PCM stream on a DSO basis. Receive data and signaling insertion can be similarly pro- vided on a per-channel basis. The Alarm Indication Signal (AIS) consisting of all-ones may be inserted on the full E1 signal or in TS16 only.

2 Brooktree*

M@@ 7811073 0033242 357 mm

Table 1. B18510 Pin Assignments .

4 Brooktree*

Figure 2. Bt8510 Functional Pinout

Table 2. Hardware Signal Definitions (1 of 4) falling edge of the transmit clock, XCKI. resulting multiframe timing will be indicated by XSYNCO. slot 16 signaling buffer (TXTS16;0xF0-OxFF). Positive Out positive bipolar data input of an external line interface circuit. Negative Out negative bipolar data input of an external line interface circuit. Positive Out pin drives a transformer through a series resistor. Negative Out pin drives a transformer through a series resistor. grounded, XSYNCO will free-run at a multiframe rate. Indicator Transmit Per-Channel Control Registers [TXCR;0x10—Ox1F]..

6 Brooktree’

Table 2. Hardware Signal Definitions (2 of 4) edges of RCKO. No insertion or buffering options are available. input clock (RCKI) is repeated. beginning of each 256-bit frame. bipolar pulses detected by the receiver. pulses detected by the receiver. analog interface is disabled, this input should be tied to Vpp. analog interface is disabled, this input should be tied to Vp. active. This signal is real-time and unlatched.

Table 2. Hardware Signal Definitions (3 of 4) available for delay-sensitive applications. g provide timing for SLPPCMO. a multiframe timing will be indicated by SLPSYNCO.

3 SLPSYNCO | Slip Buffer Sync Out The rising edge indicates the position of TSO in frame 0 of the

multiframe in the slip buffer PCM output, SLPPCMO. multiframe, this output can be ignored. Indicator Receive Per-Channel Control Register [RXCR;0x00-Ox0F]. onto the multiplexed address/data bus. 3 low, only the control and status registers can be accessed. = any activity on the microprocessor bus.

8 Brooktree*

Table 2. Hardware Signal Definitions (4 of 4) connection to the SYSCKI input. must be in the range of 8.0 MHz to 20.0 MHz. nected to SYSCKI, if desired. clock for the transmitter or slip buffer, as desired. be tied low for normal operation.

3 INIT Initialization Active-high input that initializes the internal circuitry to a known

device testing. It is normally three-stated unless ATEST is high. 38 Seven pins are provided for ground.

PAGE (S) INTENTIONALLY BLANK M@™ 7811073 0033250 423 mm io

he . = gs ee) Functional Description - 3 ie Overview A block diagram of the Bt8510 El transceiver is shown in Figure 3 and consists of three major sections: receiver, slip buffer and transmitter. The receiver is comprised of the analog receiver, the timing recovery circuit, the HDB3 decoder and the framer which recovers synchronization and detects alarms and errors. The receive bipolar input data can be obtained from either an external Line Interface Unit (LIU) chip, or by using the internal analog receiver and the timing recovery circuit which consists chiefly of a Digital Phase Locked Loop (DPLL). The analog receiver uses adaptive decision levels to allow for up to 15 dB of cable loss. After clock and data have been recovered, HDB3 decoding is performed to remove zero-code suppres- sion and to convert the bipolar data into a single unipolar data stream. The resulting serial data is then checked by the framer for the G.704 Frame Alignment Signal (FAS), the G.732 Channel Associated Signaling (CAS) multiframe, and the G.706 CRC-4 multiframe, if present. Errors and alarm status are reported in registers accessible by the micropro- cessor. Data in time slot 16 (TS16) is routed to the receive TS16 buffer (RXTS16;0x80-0x9F) for microprocessor access to CAS/CCS signaling bits or for processing of message-oriented signaling by the internal LAPD receiver. The recovered serial data stream is made available as unipolar NRZ data on the RPCMO output pin; the receiver sync output (RSYNCO) transitions low-to-high at the beginning of each frame. Data in each received time slot is also written to the internal buffer memory (RXLBUF, RXHBUF;0x40-0x7F) where it is read by either the slip buffer, the transmitter (for payload or per-channel loopbacks), or the microprocessor. Two complete frames of receive data, including TSO and TS 16, are kept in the buffer memory. The slip buffer reads the appropriate data from buffer memory and assembles the serial output stream at SLPPCMO. Idle code insertion and loopback functions can be performed only on the slip buffer output. (The receive per-channel con- trols actually refer to the slip buffer.) Controlled frame slips are performed when the slip buffer skips or repeats a frame (256 bits) of the receive buffer memory. Signaling freeze is also performed here, again by redirecting buffer read opera- tions (and disabling receive data write operations). The slip buffer sync output (SLPSYNCO) is a multiframe sync, and transitions low-to-high at the beginning of TSO, frame 0 of the 16-frame multiframe. This sync output is compatible with the transmit sync input, which allows the direct connection of the slip buffer out- put to transmit input. The slip buffer time slot indication signal (SLINDY) can be Brooktree* "1 @™® 7811073 0033251 367

in drop-and-insert applications. includes the FAS frame sync pattern, CRC-4 information and various reserved bits. useful in drop-and-insert applications. physical El line via an external transformer and resistors. Compatible with 75 Q. (XPCMO) outputs are also provided for use with an external line interface device. Figure 3. Functional Block Diagram

12 Brooktree*

have a duty cycle between 25% and 75%, and be accurate to within 0.01%. puts for multiple Bt8510 devices on power-up. Figure 4. Clock Signals

16.384 MHz clock input if the internal clock recovery is not used) can also be

large number of Bt8510s faster and more convenient.

Functional Description Bt8510 & Microprocessor Interface Microprocessor Interface The framer is managed by an external microprocessor or microcontroller. An inte- gral interface to an Intel 8051-type controller, a Motorola 68HC11-type control- ler, or equivalent, is provided. A circuit within senses which type of processor (Intel or Motorola) is being used and adjusts itself automatically. The Bt8510 is connected to a microprocessor exactly like static RAM. Two different kinds of registers can be read or written. Direct read and write opera- tions access control and status registers. Indirect read and write operations access the 256 bytes of buffer memory when RAMEN is high. These bytes contain infor- mation associated with each channel or timeslot of the El signal. Control Interface The control interface to the Bt8510 consists of 14 pins: Address Latch Enable (ALE), Read Enable (RD*), Write Enable (WR*), Chip Select (CS), RAM Enable (RAMEN), eight multiplexed address/data bits (AD[7:0]), and Interrupt (INT*). The control interface is designed to allow the direct connection of an Intel 8051-type controller or equivalent, or a Motorola 68HC11-type controller or equivalent. The CS input to the Bt8510 allows the control of multiple devices from a single microprocessor or controller. INT* is used for signaling and moni- toring operations. It is active-low, and stays low until the interrupt condition is cleared. The type of processor used is automatically sensed by looking at the state of the RD* input when ALE is active (high). To use the Bt8510 with an 8051-type controller, connect ALE, WR*, and RD* of the 8051 to the corresponding inputs of the Bt8510. To use the Bt8510 with an HC11-type controller, connect AS of the HC11 to the ALE input of the Bt8510, Enable to RD*, and Read/Write to WR*. In both cases, the CS and RAMEN inputs can be driven by address lines or proper decodes of the address lines. Detailed timing information is contained in the Electrical and Mechanical Specifications chapter. Address Map The register address map for the Bt8510 is given in the Register Summary section of the Registers chapter. There are three types of registers: Control Registers, Sta- tus Registers, and Buffer Memory Registers. Control and Status Registers are located at addresses 0x00-Ox1F when RAM Enable (RAMEN) is low. Buffer Memory Registers are located at addresses 0x00-OxFF, and require RAMEN to be high. CS must be high to address any registers within the Bt8510.

14 Brooktree*

@™@ 7811073 0033254 079 a

Bt8510 Functional Description Microprocessor Interrupts One explicit interrupt signal (INT*) is provided and can be triggered by one or more sources: an LAPD interrupt, an end-of-multiframe signal, an out-of-frame (OOF) event or a saturation of one of the error counters. The Interrupt Status Reg- ister [SR13;0x1F] is provided to aid in determining the source of the interrupt. The Interrupt Control Register [CRO9;0x0F] controls the masking of these inter- Tupt sources. The microprocessor can be interrupted by either the Transmit Multiframe Sync Output signal (XSYNCO) or the Slip Multiframe Syne Output (SLPSYNCO) connected to the interrupt input of the microprocessor. These inter- tupts can be used to synchronize read and write operations to properly inject and extract TS16 signaling data to and from TS16 buffer memory. If the LAPD for- matting operation is enabled, it can interrupt the microprocessor via the INT* pin as well. Depending on the options selected, an interrupt signal may have several dif- ferent sources. In this case, the Interrupt Status Register must first be read to determine the source of the interrupt. The processor should be optioned for level- triggered interrupt operation. To process status interrupts, read the Interrupt Status Register at each inter- rupt. If the counter interrupts are enabled in the Interrupt Control Register, read the Framing Pattern Status Register [SR03;0x 13] for overflow indications for the LCV, CRC, or FAS error counters. The interrupt condition will clear once this register has been read. Line Interface The receive analog interface allows direct connection to the physical E1 line via coupling transformers and two external terminating resistors. Line and local loop- backs are provided for maintenance purposes. A pulse shaping, differential line driver is provided in the transmitter. This driver is always enabled; however, power drain will be negligible if the outputs are left open. Pulse shaping is performed internally so that with the recommended transformers and resistors, a transmitted signal will meet the pulse template requirements of ITU-T G.703 shown in Figure 5 (measured at the secondary side of the transformer with either a 75 Q or 120 Q termination). Refer to Appendices A, Cand D of this document for more details about the transmit analog interface. Brooktree 15 M@ 7611073 0033255 TOS a

Figure 5. G.703 Isolated Pulse Template Operating Data Rate = 2.048 Mb/s. reduces power drain from 20 mA (typical) to 0.5 mA (max). physical line interface devices).

16 Brooktree*

have a duty cycle between 35% and 65%, as shown in Figure 8. Counter (SR10;0x1C) should be ignored. Figure 8. Unclocked Receiver Input multiframe reference for transmitted signals. signals is shown in Figure 9. Figure 9. Transmitter Input Timing and Synchronization Output

18 Brooktree*

Bt8510 Functional Description elf Operation & The system-side data input at XPCMI is synchronized to both the input clock at XCKI and the multiframe synchronization signal at XSYNCI, which can be either externally provided or taken from the multiframe synchronization signal output by the Bt8510 at XSYNCO. The timing of the transmit signals relative to the multiframe is shown in Figure 9. The clock frequency is 2.048 MHz. All transmit system-side inputs are internally sampled on the falling edge of XCKI while the outputs are clocked out on the rising edge. The transmit synchronization input (XSYNCI) should have a low-to-high transition from the last bit of the multiframe’s last frame to the first bit of the mul- tiframe’s first frame. If a 2-frame versus 16-frame multiframe is used, the syn- chronization input can cycle every other frame; however, this will disable the XSYNCO output, and will also continuously reset the CRC-4 multiframe count sequence prematurely. The XSYNCI signal should not transition at a rate faster than every other frame since framing generation errors will result if the Insert Framing bit [InsFrm;CRO00.2] of the Configuration Register is enabled. An alternative method of synchronization is provided when XSYNCL is tied to ground and XSYNCO is used by the system to synchronize the transmit data : supplied to XPCMI. XSYNCO then runs at an internally determined 16-frame multiframe rate (a divide-by-4096 of the XCKI clock). Either of the multiframe synchronization outputs (XSYNCO or SLPSYNCO) can be used as an interrupt to indicate when the receiver status bits are updated. The multiframe synchronization signals transition low-to-high at the beginning of TSO, Frame 0 of the 16-frame multiframe. Frame Alignment Signal and CRC Generation The El framing insertion circuit includes three types of framing as specified in ITU-T G.704: basic frame alignment (FAS), CRC-4 multiframe alignment, and signaling multiframe alignment. While basic FAS framing is a requirement, the other types of multiframe alignment are optional and could be independent of each other. Signaling multiframe alignment is used only with Channel Associated : Signaling (CAS) which employs time slot 16 to carry the signaling information for the 30 channels of PCM data. All automatic framing functions can be disabled in the following sections. The G.704 E1 frame alignment signal (FAS) is automatically generated if the Insert Framing bit (InsertFrm;CRO00.2) is set to a 1. The Sa-bits and the A-bit in TSO of the Not-FAS frame may be programmed as desired in various control reg- isters. If CRC-4 error checking and framing is desired, it must be enabled by set- ting the Insert CRC bit (InsertCRC;CRO0.1) in the Configuration Register [CRO0;0x00]. Automatic CRC-4 performance reporting (FEBE), using the two E- bits in the CRC-4 16-frame multiframe, may be enabled as well. Alternatively, TSO patterns may be sourced directly from the XPCMI pin or read from the Transmit Idle Codes registers. In the latter case, the host processor would supply the desired TSO data. SSeS Brooktree’ 19 M@@ 7411073 0033259 650 a

ister must be cleared to 0 to disable internal framing bit generation. [TxX1;CR02.4], Transmit X3 [TxX3;CR02.6], Transmit X4 [TxX4;CRO2.7] and . Figure 10. Transmitter External Signaling Insertion

20 Brooktree*

Bt8510 Functional Description eee MONAT Meseriplton Receiver Operation Transmit Time Slot Indication ‘The transmitter time slot indicator output (XINDY) is a programmable signal that is high or low for selected channels or timeslots. Programming of each time slot is determined by the Transmit Per-Channel Control Registers [TXCR;0x10-0x1F]. NOTE: For the transmitter, the bit must be set in the register two time slots ahead of the one to be actually indicated, For example, to indicate TS1 the bit for TS31 (Indicate Time Slot [IndTS31;TXCR.7 at address Ox1F]) must be set (see Figure 10). Any number of time slots up to 32 may be indicated. Receiver Operation ‘The receiver features an off-line framer. Internal timing and data recovery is optionally provided. Both the recovered serial data and frame synchronization, and the slip buffer data and slip multiframe synchronization signals are provided to the user via output pins. Timing Recovery The receive El analog signal is converted by an internal adaptive-level compara- tor into a logic-level data stream which is fed to the timing recovery circuit. Tim- ing recovery is accomplished through a Digital Phased Locked Loop (DPLL) using an up-down counter circuit, which operates at the 32.768 MHz (16 x 2.048 MHz) clock rate supplied at CK32I. The timing recovery circuit is designed to center the derived clock edge on each incoming E1 pulse. The phase of the recov- ered clock signal can be adjusted by + 30 ns for each pulse received. The output of the timing circuit is the recovered clock signal at RCKO and the serial data output at RPCMO. The recovered clock signal at RCKO will have jitter of + 30 ns (.062 UI) ata frequency that corresponds to the difference between the receive El signal timing and CK32I. Typically, this amount of jitter is small compared to that introduced by the network El facility. The total of the network and Bt8510 jitter may make RCKO unsuitable for loop-timed applications without some amount of jitter attenuation via an external narrow-bandwidth Phase Lock Loop (PLL). In the event of a loss of incoming signal, the recovered clock will continue to free-run at a rate exactly 1/16 of the clock frequency present at CK32I. Bipolar-to-Unipolar Conversion The bipolar-to-unipolar conversion circuit includes the High-Density Binary 3 (HDB3) decoding circuit. Optionally, Alternate Mark Inversion (AMI) coded sig- nals without HDB3 zero suppression may be received and transmitted by setting the Enable AMI bit (EnAMI;CRO0.5) to a | in the Configuration Register (CROO; 0x00). In AMI mode, no zero code suppression is provided. ee Brooktree’ r4 @® 7811073 0033261 209 mt

RSYNCO, Figure 10 illustrates a timing diagram for the receiver output signals. RPCMO and RSYNCO transition on rising edges of RCKO. Figure 11. Receiver Output Timing timeslot, frame, or multiframe alignment until a new frame alignment is found. frm;CRO1.2) in the Framer/Timing Control Register [CRO1;0x01J. are excessive, or when a false framing pattern is present. .

22 Brookiree*

Bt8510 Functional Description Sun tron! Description Receiver Operation When a new frame alignment is found that is different than the old frame alignment, the Change of Frame Alignment bit [COFADet;SR01.4] will be set. This bit is latched at the end of each successful reframe operation. It can be cleared by forcing a reframe which results in no COFA. The Loss of Frame Alignment indicator [LOFAlign;SRO1.3] is set and held for one transmit multi- frame period if receive FAS frame alignment was lost during the previous trans- mit multiframe period (as measured by the XSYNCO signal), Alarm Detection Alarm and error indicators are provided for El link maintenance. These indica- tors are accessible in various status registers starting at address 0x10, AIS Signal Detection —_ AIS Signal Detect [AISDet;SRO00.2] is updated each frame interval. It is set to a 1 if all bits in three of the last four frames are a one, and there is an OOF condition present as well. This signal can be integrated by the host processor to declare a received AIS to the system, which normally requires a response on the order of three to four seconds. This bit is located in the Maintenance Status Register [SRO00;0x10} Remote Frame — Remote Frame Alarm (RemFrmAlm;SR03.5) is updated every other frame inter- Alarm Detection —_val and is set if bit 3 of the not-FAS word in TSO is set toa 1. This bit is located in the Framing Pattern Status Register [SRO3; 0x13]. Status Data Loss-of-Signal — Loss-of-Signal Detect [LOSDet;SR00.0] is set when 32 consecutive zeros are received before HDB3 decoding. This bit is set to a 1 as soon as the condition is detected. Receiving a single 1 clears the indication. This bit is located in the Maintenance Status Register. Out-Of-Frame Alignment — FAS framing bits are monitored to determine errors and OOF conditions. The In Frame [InFrm;SR00.4] bit in the Maintenance Status Register is cleared when- ever three consecutive FAS words or three consecutive spoiler bits in not-FAS words are in error. This alarm can be integrated by the host processor to deter- mine if a local maintenance alarm should be declared. Once a valid frame align- ment has been established by the reframing process, InFrm will be set to a 1. Checking of the not-FAS spoiler bits can be disabled by setting the Ignore Not- FAS bit [IgnNotFAS;CR03.4] in the Framing Pattern Control Register. Change of Frame = Change of Frame Alignment Detection [COFADet;SRO1.4] is set whenever a Alignment _reframe operation changes the state of the receiver’s bit 1 (first bit) position of the frame. It is held until the next successful reframe operation. This bit is located in the Framer/Timing Status Register (SRO1; 0x11). The Change of} Change of Multiframe Alignment Detection [COMADet;SRO2.1] is set whenever Multiframe Alignment a change in the frame 0 position is detected in Channel Associated Signaling (CAS) mode. It is held until the next successful reframe operation. This signal is located in the TS16 Status Register [SRO2;0x12). meee Brooktree’ 23 M 7811073 00332b3 081 a

Register. The SIGFRZ output pin follows the state of the SigFrzSet bit. by the receiver. The CRCFail bit is located in the Maintenance Status Register. between the receive and slip buffer clocks. per frame of data), which are filled and emptied alternately. chronized to the 2.048 MHz clock supplied at SLPCKI. Figure 12 illustrates a timing diagram for the receive slip buffer output. Figure 12. Receive Slip Buffer Outputs

24 Brooktree’

&9 Functional Description Bt8510 When the slip buffer Short Delay bit [ShrtDly;CRO1.3] is enabled in the Framer/Timing Control Register, the slip buffer will initialize to a 30-bit delay position after a receive reframe with a change of frame alignment. This allows the slip buffer to accommodate + 18 UI of jitter with a minimum of through-put delay. In this mode of operation, if the phase difference between the receive and slip buffer clocks varies by more than + 18 UI, an uncontrolled frame slip will occur, and the short delay characteristic will be lost until the next successful receive reframe has occurred and a new frame alignment established (COFADet = 1). The slip buffer is reset to a one-frame depth during the search for a new frame alignment. An uncontrolled slip is indicated by the Uncontrolled Slip [Unc- trlSlp;SRO1.2] bit transitioning to a 1. . Receive Signaling Buffer The Receive TS16 Buffer Registers [RXTS16;0x80-0x9F] contain the extracted CAS signaling information received in Time Slot 16. The registers are organized as two 16-byte signaling buffers: one located at 0x80-Ox8F and the other at 0x90-0x9F. Each register in the buffer is organized into a Time Slot n and a Time Slot n+16 signaling sample (4 signaling bits or nibbles for each channel). In each CAS multiframe, when a new signaling nibble is received, it is received with another channel's nibble and both then written into one of the two signaling buff- ers. If signaling freeze is set (SigFrzSet =1), this writing is inhibited, and the alternate (old) signaling buffer is used for reading by the slip buffer and by the external microprocessor. The microprocessor can read the signaling bits in the Receive TS16 Buffer Registers directly. In CCS and CAS signaling modes, the microprocessor must first read the Receive Signaling Sector [RxSigHalf;SR13.7] bit in the Interrupt Status Register [SR13;0x1F] to determine the location of the valid signaling buffer half. When RxSigHalf is cleared, it indicates that the lower half of the buffer [(0x80-0x8F] is valid. When set, RxSigHalf indicates that the upper half of the signaling buffer [0x90-0x9F] is valid. If signaling freeze is active (SigFrzSet = 1) in these CCS and CAS signaling modes, the old buffer half will be indicated. The signaling bits are output in TS16 of the slip buffer PCM data stream at SLPPCMO, and in the slip buffer signaling output at SLPSIGO. If signaling freeze is active, the frozen signaling bits from the old signaling buffer will be out- put instead of the received TS16 bits. Receive TS16 Signaling © The Receive TS16 Signaling Insertion Buffer Registers [RXTS16SIG;0xE0- Insertion — OxEF] permit the host processor to write CAS or CCS signaling data for insertion into TS16 of the SLPPCMO data stream. Each register is organized into 2 signal- ing nibbles; one nibble per channel. The TS16 data in each register (2 signaling nibbles at a time) can be selectively inserted in the SLPPCMO output by enabling . the appropriate bit [InsertSig TSn/TSn+16;RXCR.2] in the Receive Per-Channel Control Register [RXCR;0x00-0x0F}. SSS

26 Brooktree*

@@ 7811073 0033266 850 a

Bt8510 Functional Description LAPD Operation 9 LAPD Operation ‘The Bt8510 features an internal LAPD controller for TS16 message processing. This controller manages a 16-byte message buffer for both transmit and receive directions. Idle and abort flag generation, FCS generation and checking, and zero stuffing and removal are also included. These functions are provided according to ITU-T Specification Q.921. Byte synchronization is lost due to zero stuffing, requiring the use of microprocessor interrupts to synchronize the passing of data to and from the TS16 message buffer located at 0x90-Ox9F. In LAPD mode (selected by setting the EnLAPDFmt bit in the Framer/Timing Control Register), TS16 receive data is always written to the Receive TS16 Buffer [RXTS16;0x80-0x9F]. Normal LAPD error detection and Tecovery proce- dures are used, and signaling freeze detection is ignored. ‘There are no restrictions on the total length of the message. Q.921 requires all messages be full 8-bit bytes. The transmitter can only transmit 8-bit bytes. If the receiver is sent a message with a non-integral number of 8-bit bytes, it will indi- cate an FCS error at the end. Since the LAPD receiver removes stuffed zeros before writing received data to buffer memory, a loopback of TS16 does not work in LAPD mode. The TS16 data presented at SLPSIGO is undefined, and the TS16 data embedded in the SLPPCMO data output will also be undefined. For these reasons, it is recom- mended that during LAPD operation, the slip buffer be optioned to output idle code in TS16 of the SLPPCMO data stream. A 16-byte buffer is provided for both the transmit and receive LAPD chan- nels. Filling and emptying of these buffers is accomplished by the processor on an interrupt-driven basis. The buffer is divided into two halves to reduce the real- time requirements on the processor. In the transmitter, half of the data buffer is filled and the control word is then set to send this half. As soon as the control word is loaded into the formatter con- troller, the processor is interrupted to allow loading of the other half of the buffer. In the receiver, each time one half of the receive buffer is filled, the processor is interrupted. This allows that half to be read while the other half is filled from the TS16 data link. Transmitter Upon power up, the LAPD transmitter is in an indeterminate state. It should be initialized to an idle condition by setting the Transmit FCS [TxFCS;CRO2.1] bit to a 1 and the Transmit Idle [TxIdle; CRO2.0] bit to a 1 in the Time Slot 16 Con- trol Register [CRO2;0x02] after LAPD mode is enabled [EnLAPDFmt = 1. Although normally setting both bits is contradictory, this operation serves to ini- tialize the LAPD formatter properly. LAPD idle flags (01111110) will be continu- ously transmitted in TS16 until otherwise programmed by the processor. This operation may be used to reinitialize the formatter at any time. , Brooktree* 27 M@™ 7811073 0033267 727

Functional Description , Bt8510 © LAPD Operation Sending a Message — With the LAPD transmitter in an idle state (as described above), the processor writes the first 16 bytes of message data to the Transmit TS16 Buffer [TXTS16;0xF0-OxFF]. The first byte of data should be in location 0 (address OxF0) of the buffer. The message is read from memory in ascending order, and the least significant bit in each byte is the first to be transmitted. This buffer may be loaded well before the message is sent, if desired. After this initial block of data is loaded in the buffer memory, the processor writes to the Time Slot 16 Con- trol Register (0x02 with RAMEN low) a value of 0x70 to begin transmission (TxPtr[3:0] = 0111, TxAIS = 0, AbortMsg = 0, TxFCS = 0, TxIdle = 0). The 4-bit nibble TxPtr[3:0] is functionally split into two parts. The most significant bit (CRO2.7) indicates to the formatter which half of the buffer to read from next. The three least significant bits indicate the stop location; i.e., where the last mes- sage byte is located. Once new control information in the TS16 Control Register is internally uploaded to the LAPD transmitter, the processor will be interrupted (via LAPDTx [bit 4] in the Interrupt Status Register [SR13;0x1F]) by the INT* output for the next word of control information to be written to this register. The processor will then have several frame periods to write a new control word to the TS16 Control Register and to write the next block of data to the appropriate half of the Transmit TS16 Buffer. When the end of a message is reached, or in the event of a short message, there may not be exactly 8 bytes remaining. In this case, the processor writes the remaining data to the message buffer. The processor must write the highest loca- tion occupied to the nibble TxPtr[3:0] in the upper half of the TS16 Control Reg- ister; also, TxFCS is written to a 1 in this control word, which sends the 2-byte FCS after the last block of data. When this last set of control information is uploaded to the LAPD transmitter circuit, the processor will be interrupted. At this time, a new message may be sent, or idle mode may be selected (TxIdle = 1). If a new message is to be sent immediately, the unused half of the Transmit TS16 Buffer may be loaded, and the TS16 Control Register written accordingly. This will result in only one idle flag being transmitted between messages. If there is no new message ready, the pro- cessor must write TxIdle = | to the control register. If this is not done, undefined data will be transmitted over the TS16 data link. Aborting a Message —To abort a message in progress, the controller writes AbortMsg = 1 to the TS16 Control Register. The LAPD transmitter will finish sending the message byte in progress, then transmit an abort flag (11111110). After writing the AbortMsg bit, a second write operation to the Time Slot 16 Control Register may follow after the ‘ next interrupt to force the formatter into the idle condition or to transmit another message, In the latter case, the abort flag will be followed by one idle flag, and then the new message will begin. If the TS16 Control Register is not written with a new control word, the formatter will continue to transmit abort flags. Transmitter Interrupts © The LAPD transmitter generates an interrupt when it has uploaded the present control word from TS16 Contro] Register and is ready for a new control word to be written by the processor. The Interrupt Status Register [SR13;0x1F] indicates . the source of the interrupt, but not the cause. The software must know from the context what response is required. The interrupt condition is cleared by writing to the TS16 Control Register.

28 Brooktree* ‘

M@ 7811073 0033268 463 =

Bt8510 Functional Description LAPD Operation & If the interrupt is a mid-message interrupt, a new TS16 control word must be written, with TxPtr[3:0] equal to the location of the next message byte. Which half of the Transmit TS16 Buffer should be written to next is indicated by the state of the LAPD Half [LAPDHalf;SR13.6] bit in the Interrupt Status Register. In contrast, the most significant bit of TxPtr[3:0] specifies which half will be transmitted next by the LAPD formatter. Receiver ‘The receiver powers up in an indeterminate state. It is initialized by the receipt of an idle flag, which sets RxIdle = 1 in the TS16 Status Register [SRO2;0x12]. . When a message is received, the receiver removes stuffed zeros and writes the resulting data to the 16-byte upper half of the Receive TS16 Buffer [RXTS16; 0x90-0x9F]. This upper half itself is split into halves, forming two alternate 8- byte buffers which begin at memory locations 0x90 and 0x98. Deformatted data is written to one of the 8-byte buffer halves in ascending order (i.e., 0x90, 0x91, etc.) until all eight memory locations are full. The receiver always begins writing in the 8-byte buffer opposite from where the last message was written. When the first eight buffer locations are full, the processor is interrupted (via LAPDRx [bit 5] in the Interrupt Status Register) by the INT* output to read the data out of that 8-byte buffer half. The processor normally has eight frame peri- ods to read the data, before it is overwritten with new data. The interrupt is cleared when the processor reads the TS16 Status Register [SRO2;0x12]. The TS 16 Status Register will indicate a message in progress at this time (RxIdle = 0, RxPtr[3:0] = 0111). If the upper 8-byte half of the buffer had just been filled, then RxPtr[3:0] = 1111 and locations 0x98 through Ox9F must be read during the next eight frames to retrieve the message. When the last block of data has been received, the processor will again be . interrupted. This time, the TS16 Status Register will indicate the end of message (Rxldle = 1, RxPtr[3:0] = n, BadFCS = 0 or 1). The pointer nibble, RxPtr = n, indicates the highest numbered location that was written. Locations 0x90 to 0x90+n or 0x98 to 0x98+n must be read to retrieve the data. The two highest numbered locations contain the FCS that was received at the end of the message. If the received message is a multiple of 8 bytes, then the processor will be interrupted to read the last block of data before the FCS has yet to be received. In this event, the processor will again be interrupted when the FCS has finally been received and checked, and an idle flag received. The TS16 Status Register will indicate RxPtr[3:0] = 0001, BadFCS = 1 or 0, and RxIdle =1. The FCS that was received will be in locations 0 and 1 of in one of the 8-byte buffers. Again, the data must be read out during the next eight frames, or it may be overwritten by a new message. Alternatively, the FCS data may be ignored, and the state of Bad- FCS used directly by itself. If all ones are received in TS16 for 16 consecutive frames, AIS Detect [TS16 ATSDet;SR02.3] will be set until a zero is received. It is important that software strategies allow for the fact that the LAPD receiver cannot recognize the FCS as such until the closing flag is recognized. It can happen that the processor is interrupted to read 8 message bytes, and the next byte received is the closing flag. In this event, the last two bytes read from mem- ory were not message bytes after all, but were actually the FCS. ee Brooktree* 29 M@ 7411073 0033269 STT

Functional Description Bt8510 © LAPD Operation Interrupts © The LAPD receiver generates an interrupt via the INT* output in response to three events; the current half of the LAPD message buffer is full (indicated by the LAPDRx bit), the end-of-message flag was detected, or an abort flag was detected, After initialization, interrupts should be ignored until an idle flag (end of message) is received. The TS16 Status Register indicates the cause of each receive LAPD interrupt. The interrupt will be cleared upon the reading of this register. The interrupt status is updated upon a new interrupt even if the previous interrupt has not been cleared. If an interrupt is due to the current half of the receive message buffer being full, the RxIdle bit will be cleared, and the RxPtr[3:0] nibble will indicate which half of the buffer must be read. If an interrupt is due to the end-of-message flag being detected, RxIdle = 1, BadFCS will indicate the result of the FCS error check, and RxPtr[3:0] will indi- . cate the last location written. The processor will not be interrupted again until 8 bytes of a new LAPD message have been received. If an interrupt is due to an abort flag being received, the RxAbort bit will be set. The message buffer does not have to be read in this case. The processor will not be interrupted again until 8 bytes of a new message (or a message shorter than 8 bytes) have been received. The LAPD interrupts are maskable in the Interrupt Control Register [CR09;0x0F] via the LAPD Interrupt Enable bit (LAPDIE;CRO9.4). The receiver LAPD interrupt should be masked if the El receiver is out-of-frame (InFrm = 0), because the LAPD receiver considers any byte that is not the idle flag or abort flag to be a message byte. This results in numerous interrupts during out-of-frame events if the interrupt is not masked. When the message received is 1 byte more than a multiple of 8 bytes and a new message starts immediately after a single flag character, the processor will have only two frame periods to read the previous message buffer. Therefore, receive LAPD processing should have a high priority in interrupt processing. .

30 Brooktree* ‘

@™ 7811073 0033270 21)

ee) Registers eI NOTE: For a summary of all registers refer to the Register Summary section at the end of this chapter. Control Registers There are 10 read/write control registers in the Bt8510 (not counting the per-channel control registers which are included as part of the buffer memory). These control registers are located at addresses 0x00-0x08 and OxOF. Register contents are listed in the Register Summary section at the end of this chapter. Control registers are latches set by a write operation by the external processor. Each control register may also be read to confirm its contents. The RAMEN pin must be low during read/write operations to these control registers. 0x00—Configuration Control Register (CRO0) The Configuration Register is located at address 0x00. Table 3 details the operation of the InsertCRC, Insert- Frm, and EnFEBE bits of the Configuration Control Register and the InsertldleTSn (TXCR.1] bit of the Trans- mit Per-Control Register for TSO [0x10]. Por fe Ts Te se ed ; [rio [raven [tow [tons [erent [sett | sno [ene PayLp Payload Loopback—A loopback of the full bit stream to the facility or network side. Setting this bit causes the transmitter to perform a DSO loopback in every time slot. If InsertFrm is also turned off, the FAS framing bits will also be looped. In LAPD mode, the LAPD transmit- ter works as usual. If LAPD mode is not enabled, TS16 is looped back transparently. (In CAS mode, multiframe bit insertion may also be turned on or off.) TxAxClk Transmit/Receive Clock—Enables the loop timing mode when set to a 1. In this mode the receive clock is used for the transmit clock reference instead of the Transmit Clock In (XCKI) signal. If the Enable Clock Recovery (EnCIkRcv) bit is set, then the recovered clock is used, This option should be selected simultaneously with the Payload Loopback (PayLp) bit. If the TxRxClk = 0, the transmitter will default to the XCKI input clock. The transmit clock in use is repeated on Transmit Clock Out (XCKO). EnAMI Enable Alternate Mark Inversion Line Code—Changes the HDB3 line code to AMI on both receive and transmit. This option disables the Loss of Signal Indicator [LOSDet;SR00.0], and changes the function of the line code violation status and the LCV Counter [SR10;0x1C] TxAIS ‘Transmit AIS —Causes the unframed all-ones AIS signal to be transmitted. This option domi- nates over all other transmitter options. ee Brooktree* 31 Mi 7411073 0033271 153

tiframe (FEBE function). Both InsertFrm and InsertCRC bits must be enabled. See Table 3. InsertFrm Insert Framing—Enables the internal insertion of the FAS framing bits in TSO. See Table 3. inserted by the framer into TSO as per ITU-T G.704 and G.706. See Table 3. Table 3. Time Slot 0 Control CRO8 =| the FAS pattern and the .

32 Brooktree*

0x01—Framer/Timing Control Register (CRO1) The Framer/Timing Control Register is located at address 0x01. If none of the EnCAS, EnCCS, or EnLAPDFmt bits are enabled to a 1, the Time Slot 16 (TS16) data is treated as any other data channel (sometimes referred to as channel 31 operation). This mode can also be used to pass through CCS signaling. Poe fos Tos Toe Pe a 7 [_enuaPorm | encas | noes | enarsin [sino | renetm | atorretn | ancas —_| EnLAPDFmt Enable LAPD Formatting—Enables LAPD message processing over TS16 in both transmit and receive directions. LAPD operation requires the use of the LAPD microprocessor inter- rupt, and the use of the Transmit and Receive TS16 Buffers. This is because multiframe syn- chronization is lost due to zero stuffing and FCS transmission. Note that selection of this option changes the meaning of the TS16 Control Register [CRO2;0x02] and TS16 Status Reg- ister [SRO2;0x12]. This signal controls both the transmitter and receiver. EnCAS Enable CAS—Enables the Channel Associated Signaling (CAS) mode. The receiver will look for a multiframe signal (four zeros in the upper nibble of TS16, frame 0). If signaling freeze is enabled, a valid multiframe pattern must be found before any information will be written to the Receive TS16 Buffer. This signal controls both transmitter and receiver. Enccs Enable CCS—Enables the Common Channel Signaling (CCS) mode. The signaling is trans- mitted from the Transmit TS16 Buffer, and received signaling is written to the Receive TS16 Buffer. The InsertIdleTsn bit in the Per-Channel Control Registers must also be set for TS16 to enable this mode (Note that in CCS mode, the Transmit Idle Code Register for TS16 [0xBO] is ignored). Signaling freeze may be asserted by the host processor, but since multiframe infor- mation is assumed to be nonexistent, the Enable Signaling Freeze [EnSigFrz;CR02.1] must be cleared. The half of the Receive TS16 Buffer that is being used is indicated by the RxPtr[3] bit in TS16 Status Register [SRO2;0x12], and in conjunction with the Receive CAS MF Interrupt [RxCASMFItr;SR 13.0] bit or the 2 ms Receive Clock [2msRxClk;SRO1.7] bit, can be used to synchronize data transfers to and from the host processor. EnCCS controls both transmitter and receiver. EnBitStip Enable Bit Slip—Modifies the framer algorithm to allow a single bit slip upstream. If the fram- ing pattern in TSO is detected to have moved plus or minus a single bit position, the receiver is immediately realigned and the occurrence of the bit slip is indicated by the Bit Slip bit (BitSlip;SRO1.0] in the Framer/Timing Status Register [SRO1;0x11]. This occurrence will not be counted as an FAS error. ShrtDly Slip Buffer Short Delay Mode—When ShrtDly = 1, the receive-in-to-slip-buffer-out delay is set to be 30 bits or 14.64 [sec. This option allows the use of the slip buffer for short-term jitter absorption (+18 unit intervals) without incurring unnecessary delay. Each time the receiver reframes and there is a Change of Frame Alignment (COFA), the slip buffer is reset to this position. In CAS signaling mode, if the EnSigFrz bit is set, there will still be a one multiframe delay for signaling to allow the freeze function to operate. If the EnSigFrz bit is cleared, the signaling will have the same delay as the data. If the slip buffer clock (SLPCKI) is allowed to vary by more than +18 clock cycles, the buffer will perform a controlled frame slip, and the short delay characteristic will be lost until the next receive COFA. FreRefrm Force Reframing Operation—Forces a reframe operation on the E1 signal. This control can be used to force reframing on an E1 signal, which has a very high CRC or FAS error count but is not generating an out-of-frame condition. This signal is timed so the new frame search will begin immediately after the present frame bit 1 position, Brooktree’ 33 @ 7611073 0033273 T20

@ Registers Bt8510 Control Registers AbortRefrm Inhibit/Abort Reframing—Stops a framing operation on the receive El signal if in progress and prevents the framer from trying to reframe. This input can be used to discontinue a fram- ing operation and to force the framer to ignore an unassigned or idle E1 line. AItCAS Alternate CAS Multiframe Alignment—If AltCAS = 1, the transmitter will align the CAS mul- tiframe pattern with the not-FAS word in TSO. If AltCAS = 0, the CAS multiframe will be aligned with the FAS word in TSO. 0x02—TS16 Control! Register (CRO2) The TS16 Control Register is located at address 0x02. Time Slot 16 may be used for either CAS, CCS, or D- channel signaling using the LAPD format. CAS is formatted according to ITU-T G.732. In CCS mode, the data from the XPCMI, XSIGI, or the TS16 buffer space is simply transmitted to the other end of the E1 link. LAPD formatting includes FCS generation and checking, zero stuffing and removal, and flag generation and detection. LAPD formatting may only be used with data written to and read from the TS16 Buffers, and requires the use of the microprocessor interrupt for synchronization. Controls labeled as only working in CAS mode are ignored in other modes. CAS/CCS Mode Operation Por foe Ps Pe se [_ tow [ta | tet6nemaim | txt [tensions [resi | entre [seria | TxX4 Transmit X4—Sets the current state of the x4 bit (bit 8) in frame 0 of TS16. This is a CAS mode function only. TxX3 Transmit X3—Sets the current state of the x3 bit (bit 7) in frame 0 of TS16. This is a CAS mode function only. Tx16RemAlm Send Multiframe Remote Alarm Indication—Forces the Y bit (bit 6) of TS16 to 1, indicating a remote multiframe alarm. This is a CAS mode function only. TxX1 Transmit X1—Sets the current state of the x1 bit (bit 5) in frame 0 of TS16. This is a CAS mode function only. TXTS16AIS Transmit TS16 AIS—Causes the AIS all-ones signal to be transmitted in TS16 only. This sig- nal is dominant over the Per-Channel Control Register bits. This function works in any signal- ing mode. - FrzSig Freeze Signaling—Freezes the current state of the Receive TS16 Buffer and redirects the read- ing of TS16 data by the slip buffer. This function works in both CCS and CAS modes. When the processor reads this data, it should read from the TS16 buffer half indicated by the Receive Signaling Sector [RxSigHalf;Sr13.7] bit of the Interrupt Status Register [SR13;0x1F]. Refer to Receive Signaling Buffer description the Receiver Operation section of the Functional Description chapter. EnSigFrz Enable Signaling Freeze—Enables the signaling freeze function. Update of the signaling bits in the Receive TS16 Buffer will be inhibited if the receiver either frame (FAS) or multiframe (CAS) synchronization. In this case, the old signaling bits from the previous multiframe will be output in TS 16 in the slip buffer PCM output (SLPPCMO) and the slip buffer signaling out- put (SLPSIGO). This function only works in CAS mode. If this function is enabled in other signaling modes, writes to the Receive TS16 Buffer will be inhibited unless a valid CAS mul- tiframe pattern is found. - InsCASFrm Insert CAS Framing—When InsCASFrm = 1, the Bt8510 will automatically generate the CAS multiframe pattern and optional bits in TS16, frame 0. This bit must be low for TS16 clear channel mode.

34 Brooktree’

@ =7611073 0033274 967 a

LAPD operations are detailed in the LAPD Operation section in the Functional Description chapter. p27 [os Tos Tos Pos Toe Ty]. TxPtri3] Transmit Pointer[3]—Informs the LAPD formatter of the Transmit TS16 Buffer 8-byte half- buffer from which to start reading the data. TxPtr[3] = 0 selects the lower half (starting at address 0xFO) while TxPrt[3] = 1 selects the upper half (starting at address OxF8). TxPtr[3] must be updated each time the TS16 Control Register is written. TxPtr[2:0) Transmit Pointer[2:0]—Informs the LAPD formatter of where to stop reading message bytes from the Transmit TS16 Buffer. All messages must be an integral number of bytes in length, The first byte to be sent is in address OxFO or OxF8, and the formatter counts up to the value in bytes. When the last byte is read, the processor will be interrupted for more data unless TxFCS is set (indicating the end of this message), in which case the processor will be interrupted after the sending of the last byte of the FCS. ‘TXTS16AIS Transmit AIS—Causes the AIS all-ones signal to be transmitted in TS16 only. This signal is dominant over the Per-Channel Control Register bits. AboriMsg Abort Message—Causes the abort flag (11111110) to be transmitted and the current message is abandoned. The transmitter will then go to idle mode, transmitting idle flags until new instruc- tions are received. TxFCS Transmit FCS—Causes the 16-bit ITU-T Q.921 FCS to be calculated and inserted in the last 2 bytes of a message. The setting of this bit also signals the last block of data in a message. Txldle Transmit Idle Code—Causes the LAPD idle flag sequence (01111110) to be continuously transmitted on TS16 until new instructions are received from the microprocessor. 0x03—Framing Pattern Control Register (CRO3) The Framing Pattern Control Register is located at address 0x03. por fs Ts PT a Ts Te T+ Td [si [so | reremaim | igmotas | entoap | entnip | enti | entra _| bit transmitted during the not-FAS word in CRC MF frame 15. Sid (EO) is the E-bit transmit- ted during the not-FAS word in CRC-4 MF frame 13. Both bits are normally set to one, or may be used for automatic remote CRC error reporting (FEBE) by setting the Enable FEBE bit [EnFEBE;CR00.3] of the Configuration Control Register [CR00;0x00]. In that case, the bit setting in this register is ignored. TxRemAim Transmit Remote Alarm Indication—Forces the A-bit of the not-FAS word in TSO to a one. The Insert Framing bit [InsFrm;CRO00.2] of the Configuration Control Register must be enabled. IgnNotFAS Ignore Not-FAS—Setting IgnNotFAS = 1, forces the receive framer to ignore the checking of the spoiler bit of the not-FAS word (bit 2 in the frame not containing the FAS) in the out-of- frame (OOF) detection circuit once the framer has acquired frame alignment. a Brooktree* 35 M@™ 7511073 0033275 8T3

Figure 15. Line Loopback tionship to the CRC-4 multiframe. Each bit is transmitted in the assigned frame. tionship to the CRC-4 multiframe. Each bit is transmitted in the assigned frame.

te) Registers Bt8510 Control Registers 0x07—Sa7 Bits (CRO7) . Control Register 07 controls the Sa7 bits and is located at address 0x07. The individual bits retain a fixed rela- tionship to the CRC-4 multiframe. Each bit is transmitted in the assigned frame. Por foe Tos Te Ts a 0x08—Sa8 Bits (CRO8) Control Register 08 controls the Sa8 bits and is located at address 0x08. The individual bits retain a fixed rela- tionship to the CRC-4 multiframe. Each bit is transmitted in the assigned frame. Por fT se Ts Te a Ox0F—Interrupt Control Register (CRO9) The Interrupt Control Register is located at address OxOF and serves as a mask for enabling/disabling interrupt sources to trigger the INT* output to transition low. Interrupt sources defined by the bits in this register are log- ically ORed in triggering the INT* output. a ee ee [_vowe [orcs [nase [taro | fooore | ronowe | mrorcwrie | rcaswrie_| LCVIE LCV Interrupt Enable—Enables an interrupt upon overflow of the Line Code Violation Counter [SR10;0x1C]. Reading the Framing Pattern Status Register [SR03;0x13] clears the interrupt without affecting the counter. Reading the counter clears the counter. CRCIE CRC Interrupt Enable—Enables an interrupt upon overflow of the CRC4 Error Counter {SR11;0x1D]. Reading the framing pattern Status Register clears the interrupt without affect- ing the counter. Reading the counter clears the counter. FASIE FAS Interrupt Enable—Enables an interrupt upon overflow of the FAS error counter. Reading : the Framing Pattern Status Register clears the interrupt without affecting the counter. Reading the counter clears the counter. LAPDIE LAPD Interrupt Enable—Enables the LAPD interrupts. Clearing this bit in LAPD mode will prevent spurious interrupts from the LAPD receiver during out-of-frame conditions. RXOOFIE Receive OOF Interrupt Enable—Enables an interrupt signaling the loss-of-frame alignment in the receiver. TxCROMFIE Transmit CRC MF Interrupt Enable—Enables an interrupt at the beginning of each transmit CRC-4 multiframe. The interrupt is cleared when the Interrupt Status Register [SR13;0x1F] is read. This signal will reflect both CAS and CRC-4 multiframe alignment, unless Alternate CAS Multiframe Alignment [AItCAS;CRO1.0] in the Framer/Timing Control Register [CRO1;0x01] has been selected. This signal is used to time the writing of the Sa-bit registers, and signaling insertion registers. These interrupts will occur (if enabled) on a 16-frame bound- ary regardless of the status of the Insert CRC bit [InsCRC;CRO0.1] in the Configuration Con- trol Register [CR00;0x00].

38 Brooktree’

M@@ 7811073 0033278 Soo

Bt8510 Registers & eee EE TCT Status Registers RXCRCMFIE Receive CRC MF Interrupt Enable—Enables an interrupt at the beginning of each receive CRC-4 multiframe. The interrupt is cleared when the Interrupt Status Register is read, This signal will change its timing with a change in frame alignment. This interrupt is used to time the reading of the Sa-bit registers. These interrupts will occur (if enabled) on a 16-frame boundary regardless of the status of the In CRC Frame [InCRCFrm;SR00,7] bit in the Mainte- nance Status Register [SRO0;0x10]. RXCASMFIE Receive CAS MF Interrupt Enable—Enables an interrupt at the beginning of each receive CAS multiframe. The interrupt is cleared when the Interrupt Status Register is read. This sig- nal will change its timing with a change in frame or CAS multiframe alignment. These inter- rupts will occur (if enabled) on a 16-frame boundary regardless of the status of the In Multiframe CAS bit [InMFCAS;SR02] in the TS16 Status Register [SRO2;0x12] Status Registers The Bt8510 has 10 status registers located in addresses 0x10-0x19. The contents of these registers are listed in the Register Overview Summary section at the end of this chapter. The status signals are contained in latches and are applied to the microprocessor data bus on the appropriate read command. Many of the status bits are updated at 2 ms intervals. This interval is timed by the transmit clock circuitry so that it is not affected by reframes. This also synchronizes the status indications when Els from multiple inte- grated circuits are being monitored. Some status bits are updated as they happen. The indication period for each bit is given with each description. Driving an interrupt to the microprocessor with the XSYNCO output provides a convenient way to time the sampling of the status registers every 2 ms. 0x10—Maintenance Status Register (SRO0) The Maintenance Status Register is located at address 0x10 and contains the major E1 maintenance indicators. por fos Tos Tos Tos 7 2 Ta Ts [LLwororm | .cvow [rast [rm | woesoet_| sor [cnorai|vosoet_| InCRCFrm In CRC Frame—Set high when a correct CRC-4 multiframe alignment signal (001011) has been detected during the previous multiframe. This indication is updated every 16 frames according to the receive CRC-4 multiframe alignment signal. A loss of basic frame alignment (FAS) causes an immediate loss of CRC-4 multiframe alignment. If there has been a change in the CRC-4 alignment (not merely an error), InCRCFrm will go high on the second correct alignment signal. LCVvDet Line Code Violation Detection—Set high if there was a Line Code Violation (LCV) during the previous multiframe. In HDB3 mode, this is a bipolar violation that is the same polarity as the previous bipolar violation per ITU-T Recommendation 0.161 §2.2. In AMI mode, any bipolar violation will be counted as an LCV per 0.161 §2.1. This indication is latched every 2 ms by the falling edge of XSYNCO. . FASErr FAS Error—Set high if there was a Frame Alignment Signal (FAS) error during the previous multiframe. This indicator is enabled only when in frame alignment (InFrm = 1). It is latched every other frame and held for two frames following the error. eS Brooktree* 39 MH 7811073 0033279 449 my

© Registers Bt8510 Status Registers InFrm In Frame—Set high if the receive framer is locked onto a valid FAS framing pattern. A mini- mum of three frames is required to validate a new framing pattern (2 FAS words and 1 not- FAS word). Once in frame, a minimum of six frame intervals is required to lose frame (3 con- secutive FAS words in error). This indicator is not latched, but always indicates the current FAS frame alignment status of the receiver. HDB3Det HDB3 Signature Detect—Set high if a legal HDB3 signature per ITU-T Recommendation . 0.162 was present during the previous transmit multiframe. The indicator is active regardless of the setting the Enable AMI Line Code bit [EnAMI;CRO00.5] in the Configuration Control Register. This indication is latched every 2 ms by the falling edge of KXSYNCO. AlsDet AIS Detect—Set high if the receiver is out-of-frame (InFrm =0) and three of the last four frames were all-ones. It is latched each frame. This signal may need to be further integrated by the microprocessor to decide if an AIS signal is actually present, CRCFail CRC Failure—Set high for 1 ms (one CRC-4 block) if the CRC check for the CRC block fails. The CRC Error Counter (SR11; 0x1D) will increment each time a block is in error. If the receiver has not found a valid CRC-4 multiframe pattern, this bit will be set and CRC errors will be reported to the far-end if FEBE is enabled (EnFEBE; CRO00.3). However, the CRC-4 Error Counter will not count errors unless the receiver is in CRC-4 multiframe alignment (InCRCFrm =1). The CRC Error Counter will usually (15 of 16 times) count one error as the CRC-4 multiframe alignment is lost. LOSDet Loss-of-Signal Detect —Indicates that the received signal has been absent for at least 32 clock cycles (prior to HDB3 decoding), meaning that the E1 line signal has been lost. This alarm indicator is valid only when HDB3 line code is selected (EnAMI = 0). This signal is set when 32 consecutive zeros have been detected. It is cleared by the receipt of a 1 of either polarity. 0x11—Framer/Timing Status Register (SRO1) The Framer/Timing Status Register is located at address 0x11 and contains status information about the receive framer. po7 J 6 [os fo « fos Toe foi Too | [_ansrxck | amsticn | cuFrmsio | corane | vofnion | unewsip | rmsonims | sip | 2msRxClk 2 ms Receive Clock—Shows the timing derived by the framer from the receive signal. This signal may change its timing due to reframes on the receive signal. It is high for eight frames, then low for eight frames. In CAS signaling mode, it follows the CAS multiframe alignment. In other signaling modes, it counts modulo-16 frames from the latest new frame event. 2msTxClk 2 ms Transmit Clock—Used to synchronize the scanning of the status indications. This syn- chronization signal can be used as a 2 ms (one multiframe) indicator. It is high for eight frames, then low for eight frames. This signal is independent of the type of signaling present. . CtrlFrmSip Controlled Frame Slip—Set when the slip buffer performs a PCM controlled frame slip due to a long-term variation in the phase relationship of the receive and the slip buffer clocks. This indication will be issued once for every 256 bits or 125 us of phase slip between the received clock (recovered or RCKI) and the slip buffer clock (SLPCKD), and is held until this register is read. “ COFADet Change of Frame Alignment Detection—Set when a reframe changes the receiver bit 1 posi- tion in the frame counter. This indicator changes only upon reframe and thus indicates the result of the last reframe operation. It is cleared by a reframe which results in no COFA. ‘

40 Brooktree*

@@ 7511073 0033280 140

eS gtr: Status Registers LOFAlign Loss of Frame Alignment—Set if basic frame alignment (FAS) was lost at any time during the previous transmit multiframe period. This indication is latched every 2 ms by the falling edge of XSYNCO. UnctriSip Uncontrolled Slip—Indicates that a slip event occurred since the last reading of this register, while the slip buffer was in short delay mode (ShrtDly = 1). . FrmSchtms Frame Search Active Longer than 1 ms—Indicates a frame search operation has taken longer than the indicated interval. It is set during a frame operation at the occurrence of the interval and cleared when the framing operation is finished or aborted. If this appears on several con- secutive 1 ms samples, it is possible that a PCM or data channel is emulating the FAS, or that no valid FAS framing pattern exists. BitSlip Bit Slip—Indicates the framing pattern moved plus or minus one bit position on the receive E] signal, during the previous transmit multiframe period. This indication is held for one transmit multiframe. This indication is latched every 2 ms by the falling edge of XSYNCO. 0x12—TS16 Status Register (SRO2) The TS16 Status Register is located at address 0x12. Time Slot 16 can be used for CAS, CCS, or D-Channel Signaling using the Q.921 LAPD format. CAS is formatted according to G.732. In CCS mode, the only valid status indications are TS16AISDet and SigFrzSet. LAPD formatting includes FCS generation and checking, i zero-bit insertion and deletion, and flag generation and detection. LAPD messages can only be read or written from the Receive and Transmit TS16 Buffers, and require the use of the microprocessor interrupt (INT*) to syn- | chronize the transfer of message data between the framer and the host microprocessor. CAS/CCS Mode i Pa fos Ts Te Ps Te Ts [_ peas [reas [ ream [nxt | roensowt | sates | como | marcas _| RXX4, Receive X4—The received x4 bit (bit 8 of TS16 in frame 0). In CCS mode, this bit is mean- ingless and should be ignored. RxX3 Receive X3—The received x3 bit (bit 7 of TS16 in frame 0). In CCS mode, this bit is mean- ingless and should be ignored. MFRemAlm Multiframe Remote Alarm Indication—Indicates the state of the Multiframe Remote Alarm Indication bit (the Y bit or bit 6 of TS16 in frame 0). In CCS mode, this bit is meaningless and should be ignored. RxX1 Receive X1—Is the received x1 bit (bit 5 of TS16 in frame 0). In CCS mode, this bit is mean- ingless and should be ignored. TS16AISDet TS16 AIS Detect—Set when the all-ones signal is detected in TS16 for a full multiframe after multiframe alignment has been lost. SigFrzSet Signaling Freeze Set—When enabled, this bit is the logical OR of the out-of-frame (InFrm = 0) and out-of-multiframe (InMFCAS = 0) states. It indicates that the received signal- ing buffer is not being updated, and that the slip buffer is being directed to read the old half of the Receive TS16 Buffer. COMADet Change of Multiframe Alignment Detection—Set for one multiframe when the signaling mul- tiframe alignment signal is first lost, then detected in a frame other than frame 0. This event may indicate an upstream frame slip. In CCS mode this bit is meaningless and should be ignored. Se Brooktree’ a @@ 7811073 0033281 OT? om

Ce) Registers Bt8510 Status Registers InMFCAS In Multiframe CAS—Set when the signaling multiframe alignment signal (CAS) is found in TS16. It is latched during frame 0 of each multiframe. This bit is meaningless and should be ignored in CCS mode. LAPD Mode Operation Pov | 6 J os To « Tos foe Toy foo | |_reeiay | rewi | wri) | veri. | rsteatsoet | eabon | sasres | nto _| AxPtr[3] Receive Pointer [3]—Informs the microprocessor of which half of the Receive TS16 Buffer to read each time. The receiver will alternate halves. RxPtr[3] = 0 means that the lower half- buffer starting at 0x90 should be read; RxPtr[3] = 1 means that upper half-buffer starting at 0x98 should be read. RxPtr[2:0] Receive Pointer (2:0}—A pointer indicating the highest numbered location in the Receive TS16 half-buffer that was written by the LAPD receiver. All messages must be an integral number of bytes in length. The receive circuit writes the first data byte received into location 0 (of the half-buffer), and counts upward. TS16AISDet TS16 AIS Detect—Set when the all-ones signal is detected on TS16 for 16 frames. RxAbort Receive Abort Flag—Indicates an abort flag (11111110) was received. The message in progress was aborted by the originator. BadFCs Bad FCS—Indicates an erroneous Frame Check Sequence (FCS) was received at the end of the preceding message. It will remain set until a valid FCS is received. Rxidle Receive Idle Code—Indicates the LAPD idle flag sequence (01111110) was received on TS16. 0x13—Framing Pattern Status Register (SR03) The Framing Pattern Status Register contains the Reserved for International Use (Si bits) and the Remote Alarm Indication (referred to as the A-bit in G.704) bits in the framing pattern that was received during the most recent frame or multiframe. These bits are specified in ITU-T G.704 and G.706. The host processor must read this register to recover the FEBE information received on the two E bits, once per CRC-4 multiframe. The Transmit or Receive CRC-4 Multiframe Interrupts [TxCRCMFItr, RxCRCM- Fitr;SR13.2,1] in the Interrupt Status Register [SR13.0x1F] may be used to time the reading of these bits. The Remote Alarm Indication is contained in the not-FAS word and is received and updated every other frame. Also in this register are the error counter overflow indications. Each counter overflow interrupt status bit is cleared when the Framing Pattern Status Register is read, and does not affect the counter’s operation. Por fs Ps Pe a a [sn [so Tremaine [ova [moor | ovon | cacom | aso _| Sit Sil—The E-bit received during the not-FAS word in CRC MF frame 15. Sid Si0—The E-bit received during the not-FAS word in CRC MF frame 13. RemAlmind Remote Alarm Indication—Set high if the received A-bit is high. The A-bit is bit 3 of time slot 0 in not-FAS frames. Rsvd Reserved—Used to enhance testability. It may change, but is functionally meaningless and should be ignored. . IntO0OMF Integrated OOMF—High if two or more consecutive CAS multiframe alignment signal errors have been detected. This bit is cleared when valid CAS multiframe alignment has been found.

42 Brooktree*

@@ 7811073 0033282 T33

Levovil LCV Error Counter Overflow—High when the Line Code Violation Counter {SR10;0x1C] equals 255, and is cleared when read. The counter will roll over to zero on the next error and resume counting, independent of when (or if) this bit is read. CRCOvi CRC Error Counter Overflow—High when the CRC Error Counter [SR11;0x1D] equals 255, and is cleared when read. The counter will roll over to zero on the next error and resume counting, independent of when (or if) this bit is read. FASOvil FAS Error Counter Overflow—High when the Frame Alignment Signal Error Counter [SR12;0x1E] equals 255, and is cleared when read, The counter will roll over to zero on the next error and resume counting, independent of when (or if) this bit is read. Sa-Bit Registers To aid ISDN and facility data link implementations, five registers are provided to minimize processor overhead for Sa-bit processing. Each register saves the state of each Sa-bit over the last CRC-4 multiframe. The Sa-bits are defined in ITU-T G.704 as additional spare bits reserved for international use. Each bit is updated as it is received. The Receive CRC MF Interrupt signal [RxCRCMFltr;SR13.1] can be used to synchronize the reading of these bits. This ensures that the bits for each multiframe are read together as one word. Note that this process needs to be completed before the start of frame 1 when the new bits start to overwrite the old bits. 0x14-Sa4 Bits (SRO4) Status Register 0x04 records the Sa4 bits and is located at address 0x14. The bits retain a fixed relationship to the CRC-4 multiframe. Each bit is updated in turn when received. a a ee ee 0x15—Sa5 Bits (SRO5) Status Register 05 records the Sa5 bits and is located at address 0x15. The individual bits retain a fixed relation- ship to the CRC-4 multiframe. Each bit is updated in turn when received. [7 fos Tos To « Tos Ts [a]. [_nssstnis | rasastinia | ssstns | asrme [maser | masts | msisime | most | 0x16—Sa6 Bits (SRO6) Status Register 06 records the Sa6 bits and is located at address 0x16. The individual bits retain a fixed relation- ship to the CRC-4 multiframe. Each bit is updated in turn when received. Por foe Tos Tos Tos Te Ts Te] L_rasscrms | esasrinis | masasimis | rosasrme | resserm7 [eesti | aeasrma | mxsasim | 0x17—Sa7 Bits (SRO7) Status Register 07 records the Sa7 bits and is located at address 0x17. The individual bits retain a fixed relation- ship to the CRC-4 multiframe. Each bit is updated in turn when received. po fos Tos To « Tos Tos Ta [Ts | ee Brooktree* 43 M@@ 7811073 0033283 17T

| 0x18—Sa8 Bits (SR08) | Status Register 08 records the Sa8 bits and is located at address 0x18. The individual bits retain a fixed relation- ship to the CRC-4 multiframe. Each bit is updated in turn when received. Po fs Ps a a 0x19—Part Number and Hardware Version Register (SRO9) The Part Number and Hardware Version Register is located at address 0x19. This register allows the processor to verify which Brooktree product is working, and if that product is working with the correct integrated circuit revision. The part number is located in the upper nibble of the register. The revision number in the lower nibble. The revision number will be incremented with any change in circuitry within the integrated circuit. Por fo 6 Tos fa fe Pe a [__pantay | rartay | antyy [rary [vets | vorey very) verton | Part[3:0] Part Number—A unique 4-bit code assigned to the Bt8510. Ver{3:0] Version Number—Gives the version number of the part and is updated with each functional revision of the part starting with 0. Part Number Value Former Base Part Number Bt8510EPJ 0x10 UGA-510 Bt8510EPJB Ox11 UGA-510-2 Bt8S10EPIC 0x12 N/A Error Counters To aid certain implementations, three error counters are provided to minimize processor overhead. Interrupts can be enabled to activate upon overflow of one or more of the counters, Alternatively, the counters can be polled on a regular basis. If a loss of framing alignment is detected, the FAS and CRC error counters are dis- abled (but not cleared) until in frame alignment (InFrm = 1) is declared. The counters are cleared each time they are read by the microprocessor. 0x1C—Line Code Violation Counter (SR10) The Line Code Violation Counter is located ar address 0x1C. In AMI mode (EnAMI = 1), all line code viola- tions including bipolar violations will be counted. If the HDB3 decoder is enabled (EnAMI = 0), each bipolar violation with the same polarity of the previous bipolar violation will increment the counter per ITU-T Recom- mendation 0.162. The counter has 8-bits, and will indicate 0-255 errors. If the counter overflows, the LCV Counter Overflow bit [LCVOvfl;SR03.2] in the Framing Pattern Status Register [SRO3;0x12] will be set, and held until it is read. In this event, the counter will roll over and continue counting. An interrupt may be enabled upon overflow. The counter is cleared each time it is read. ~for foe Tos Toa Ps Pe a

44 Brooktree’

M@@ 7811073 0033284 6806 me

oo CT STS: Error Counters Ox1D—CRC Error Counter (SR11) The CRC Error Counter is located at address 0x1D and is incremented upon each CRC-4 block error (one pos- sible every 8 frames). The counter has 8 bits, and indicates 0-255 errors. If the counter overflows, the CRC Error Counter Overflow bit [CRCOvfl;SR03.1] in the Framing Pattern Status Register will be set and held until it is read. In this event, the counter will roll over and continue counting. An interrupt may be enabled upon over- flow. The counter is cleared each time it is read. If CRC-4 multiframe alignment is lost, the counter is disabled until CRC-4 multiframe alignment is re-established. The counter typically records one error upon loss of CRC- 4 multiframe alignment. pia fos Tos Toe Tos Ta T+]. | [once [crew | cncai) [crow crcatny | cacao Ox1E—Frame Alignment Signal Error Counter (SR12) The Frame Alignment Signal Error Counter is located at address 0x1E and increments upon each FAS word in error. The counter has 8 bits, and indicates 0-255 errors. If the counter overflows, the FAS Error Counter Over- flow bit [FASOvfl;SR03.0] in the Framing Pattern Status Register will be set, and held until it is read, In this event, the counter will roll over and continue counting. An interrupt may be enabled upon overflow. The counter is cleared each time it is read. System requirements will determine how often it must be read. If three consecu- tive FAS words are in error, the hardware will force a reframe operation unless the Inhibit/Abort Reframing bit [AbortRefrm;CRO1.1] is set. Po7 fos Tos Poe Tos Tos T+ To _] Lvs [asia [asin | sin [asi [vases [nasty | mo) | Ox1F—Interrupt Status Register (SR13) The Interrupt Status Register is located at address Ox1F and enables the microprocessor to quickly determine the interrupt source when several interrupts are enabled. LAPD interrupt sources and other indicators are also found in this register. All interrupts reported here are cleared when this register is read with the following exception: LAPD Receiver (bit 5) is cleared when the TS16 Status Register [SR02;0x 12] is read. po fe [os Tos [os Ta Ta [Ts RxSigHalf Receive Signaling Sector (CAS or CCS)—Indicates the location of the valid signaling buffer half. A zero indicates the lower half [0x80-0x8F] and a one indicates the upper half [0x90- Ox9F]. LAPDHalf LAPD Transmit Buffer Sector—Indicates which half of the transmit TS16 buffer should be written to. A one indicates the upper half {0xF8-OxFF] and a zero indicates the lower half {OxFO-OxF7]. LAPDRx LAPD Receiver—Indicates that a LAPD receiver has received a new message. This interrupt is cleared when the TS16 Status Register [SRO2;0x 12] is read. ce Brooktree* 45 M@™ 7611073 00332865 742 mm

@ Registers Bt8510 Buffer Memory Registers LAPDTx LAPD Transmitter—Indicates that the LAPD transmitter is available to accept the next set of controls in the TS16 Control Register. This interrupt is cleared upon writing to the TS16 Con- trol Register [CRO2;0x02]. RxO0Fitr Receive OOF Interrupt—Indicates a out-of-frame alignment state (InFrm = 0) in the receiver. This interrupt is cleared when the Interrupt Status Register is read. TxCRCMFitr Transmitter CRC MF Interrupt—tIndicates the beginning of each transmit multiframe. This interrupt is cleared when the Interrupt Status Register is read. RXCRCMFitr Receive CRC MF Interrupt—Indicates the beginning of each receive CRC multiframe. This interrupt is cleared when the Interrupt Status Register is read. RxCASMFitr Receive CAS MF Interrupt—Indicates the beginning of each receive CAS multiframe. This interrupt is cleared when the Interrupt Status Register is read. Buffer Memory Registers The microprocessor interface allows the indirect reading and direct writing of 256 locations in the RAM buffer memory. For any access to this memory space, RAMEN must be high. When a write operation is performed, the Bt8510 latches the address and data and performs the write opera- tion within the next microsecond. When a read operation is performed, the address is latched, and the read oper- ation takes place within the next microsecond. A second read operation must then be performed to obtain the desired data at the controller. The read operations can be pipelined. If 30 locations are to be read, the first operation should have the address of the first location. On the second read operation, the second address is presented and the data corre- sponding to the first location is returned to the controller. In this way N+1 operations are required to read N buffer locations. A read operation does not affect the contents of the memory. Write operations may be inter- Jeaved with pipelined read operations. The maximum rate at which the buffer memory can be accessed is 1 MHz (976 ns clock period). This limita- tion does not apply to the control and status registers, only to accesses to the buffer memory registers. This rate may be doubled by using a 16.384 MHz system clock. There are nine sets of buffer registers. Each set of registers contains a buffer register for each El channel, except for the TS16 Buffers. The functions of each register are: * Receive Per-Channel Control * Transmit Per-Channel Control + Receive Idle Code * Receive PCM Buffer + Receive TS16 Buffer * Transmit Idle Code * Transmit PCM Buffer * Receive TS16 Signaling Insertion Buffer * Transmit TS16 Buffer These are also described in the RAM address map in Table 6 through Table 14.

46 Brooktree*

M@™§ 7811073 0033286 689 mm

0x00-Ox0F, 0x10-0x1F—Per-Channel Control Registers (RXCR, TXCR) The Per-Channel Control Registers are located at addresses 0x00-0x0F for the receive time slots (RXCR), and addresses 0x10-Ox1F for the transmit time slots (TXCR). Since these addresses are located in RAM buffer memory, the RAM Enable (RAMEN) pin must be high during the configuration accesses. The lower 3 bits of the address correspond to the channel pair number. Signaling control bits are grouped by channel Pairs, as they are in the receive bit stream. For example, in location OxOA the signaling controls operate on both channel 10 and 25 signaling bits, and are always contained in Time Slot 10, These registers must be initialized by the microprocessor upon power-up. Note that telephone channel number 25 is contained in Time Slot 26. Please see ITU-T Recommendation G.704, Table 9 for an explanation of the telephone channel numbering system. Note that because signaling bits are organized in channel pairs, both loopback and insert signaling are effective for the signaling associated with both Time Slot n, and Time Slot n+16, [or fos Tos Toa Ts [2 Pa ed IndTS IndTS Insertldle EnLpDSO LpSig InsertSig Insertidle EnLpDSO TSn+16 TSn TSn+16 TSn+16 TSn/TSN+16 TSn/TSn+16 TSn TSn IndTS TSn+16 Indicate Time Slot (Time Slot n+16)—Enables the marking of the time slot on one of the time slot indication outputs, XINDY or SLINDY. For a transmit time slot, this register actually con- trols the indication for Time Slot n+16+2. That is, to indicate Time Slot 21, bit 7 in Per-Chan- nel Control Register 5 (address 0x15) must be set. For a receive channel, no offset is required. indTS TSn Indicate Time Slot (Time Slot n)—Enables the marking of the time slot on one of the time slot indication outputs XINDY or SLINDY. For a transmit time slot, this register actually controls the indication for Time Slot n +2. That is to indicate transmit Time Slot 7, bit 6 in Per-Channel Control Register 5 (address 0x15) must be set. For a receive channel, no offset is required. Insidle TSn+16 Insert Idle Code (Time Slot n+16)—Same function as for InsertIdleTSn but for the time slot n+16. EnlpDSOTSn+16 Enable DSO Loopback (Time Slot n+16)—Enables the DSO loopback for the selected time slot. For a receive channel, this causes a loopback toward the equipment. For a transmit chan- nel, this causes a loopback toward the line. LpSig TSn/TSn+16 Loopback Signaling (Time Slot n and n+16)—Loopback Signaling enables the signaling loop- back for the signaling associated with the selected time slot. For a receive channel, this causes a loopback toward the equipment. For a transmit channel, this causes a loopback toward the line. InsertSig TSn/ Insert Signaling (Time Slot n and n+16)—Causes the transmitter to read the Transmit TS16 TSn+16 Buffer for transmit data in TS16. Proper signaling information must have been previously written to these locations. On the receive side, the slip buffer will read the Receive TS16 Sig- naling Insertion Buffer for TS16 data inserted into the SLPPCMO output. Insertidle TSn Insert Idle Code (Time Slot n)—Causes the Transmit or Receive Idle Code Buffer for the selected time slot to be read, and that data transmitted, If InsertIdleTSn =0, the data is passed through from the serial input. The InsertIdleTSn bits for the transmit time slots control the idle code insertion into the transmitted E1 signal; the InsertIdleTSn bits for the receive time slots control the idle code insertion into the slip buffer data output (SLPPCMO). Unique idle codes for each of the 32 receive and 32 transmit time slots may be used simultaneously. EnLpDSO TSn Enable DSO Loopback (Time Slot n)—Enables the DSO loopback for the selected time slot. i For a receive channel, this causes a loopback toward the equipment. For a transmit channel, : this causes a loopback toward the line. SS Brooktree’ 47 M@™ 7811073 0033287 515

& Registers Bt8510 Buffer Memory Registers 0x20-0x3F—Receive Idle Code (RXIDLE) The Receive Idle Code Registers are located at addresses 0x20-0x3F. These registers contain the idle codes for insertion in the slip buffer output (SLPPCMO). Idle codes are inserted into the selected time slots as determined by the Receive Per-Channel Control Registers. Receive Idle Code Word Format Por os Ts Te Ts fe a [rater | aaeie) | roetsy | ery | wawtsr | rarer [ery | rnatton_| 0x40-0x5F—Receive PCM Buffer Low (RXLBUF) The Receive PCM Buffer Low is located at addresses 0x40-Ox5F. These registers make up the lower half of the slip buffer. The detailed operation is described in the Receiver Operation section of the Functional Descriptions chapter. Low Slip Buffer PCM Word Format a ee 0x60-0x7F—Receive PCM Buffer High (RXHBUF) The Receive PCM Buffer High is located at addresses 0x60-0x7F. These registers make up the upper half of the slip buffer. The detailed operation is described in the Receiver Operation section of the Functional Description chapter. High Slip Buffer PCM Word Format [oz foe Tos Toe [Tos Toe Tos To Sr 0x80-0x9F—Receive TS16 Buffer (RXTS16) The Receive TS16 Buffer is located at addresses 0x80-0x9F. These registers make up two halves of the Receive TS16 Buffer. In CCS and CAS signaling modes each buffer is alternately written by the framer for each multi- frame. In LAPD mode, only the upper half of the buffer is written to by the LAPD receiver. The detailed opera- tion is described in the Receiver Operation section of the Functional Description chapter. CAS or CCS Signaling Format ’ a ee

48 Brooktree*

@ 7811073 0033288 45)

A eS gists: Buffer Memory Registers LAPD Message Byte Format OxA0-0xBF—Transmit Idle Code (TXIDLE) The Transmit Idle Code registers are located at addresses 0xAO-OxBE. These registers contain the idle codes for insertion in the transmitter output. Idle codes are inserted into the selected time slots as determined by the Transmit Per-Channel Control Registers. Transmit Idle Code Word Format [ov fos [os Tos Tos Te Tf. Tatdeye) | Tales) Tale 0xC0-0xDF—Transmit PCM Buffer (TXBUF) The Transmit PCM Buffer Registers are located at address 0xCO-OxDF and contain the transmit PCM input data. Beginning address 0xCO corresponds to timeslot 0 while ending address 0xDF corresponds to timeslot 31. Transmit PCM Word Format [7 fos [os To « Tos 7 2 [— 1 7T. OxE0-0xEF—Receive TS16 Signaling Insertion Buffer (RXTS16SIG) The Receive TS16 Signaling Insertion Buffer is located at addresses 0xE0-OxEF. These registers contain the signaling bits provided by the host for insertion into the slip buffer output (SLPPCMO). Signaling is inserted into the proper TS16 nibble position for selected time slot as determined by the Receive Per-Channel Control Registers. Receive TS16 Signaling Format eee Brooktree’ 49 M@ 7411073 0033289 398

© Registers Bt8510 Pt athe dal Buffer Memory Registers OxFO-0xFF—Transmit TS16 Buffer (TXTS16) The Transmit TS16 Buffer is located at addresses 0xFO-OxFF. Signaling information is inserted into the proper TS16 nibble position for the selected time slot as determined by the Transmit Per-Charinel Control Registers. In LAPD operation the 16-byte buffer is divided into halves, which are alternately read by the framer. The detailed operation is described in the LAPD Operation section in the Functional Description chapter. CAS or CCS Signaling Format po2 ff os Ts a ee en LAPD Message Byte Format LAPOMSO] ee ee

50 Brooktree*

_oH-T7_Rraistors Register Summary FE alelElelalelelelele toler ies g 2/2 = = pe /S/SiS lel zle| alee |s op pS] SP BIFEZ) 2/8/2818 Pelolel. eglealelele|w Pod -|SlSlEl@/Z ELELELEL EE Pode ISLE) Fl el Els SiS |s/s PL TEIElE/A/2/3/8elale]s te iid FJFlFElelzlé tee alee] e|.|w ast Let E 2\\/S/ElSELEEL ELE je [2/22 2/€/e/s/e/s|s eee f/=|3)2/812/8]/a] als raetc| =| = SIEVE B e/a 2 pees seas 4 l lalalgislalelelelele a fate 2i\\2lels PB) |? /]Ele/E/2/ 2/8/22 si Soa be alalalaloa peara(aated E/E/)/8/S/S|sle2 i cael E -{</-J-/- fee —/E/E/EIESEIE “| Jsl@l/BlelalE/ElEE] e/a sf ad SIZIEISISIS/S/E|S]2 Pop 1S) GS /R e213) alal a] ale Hite gael El" [#22 2/2] 8 Paves ele2leolele fies beas| & al E/ElE/ElE pire] & 4 2|s § Heel eas fee = glel/ele}e | slSls/2|_/ElE/ElE] Ele TE lBIEIEe/e/$/elele|el al & 2/2/2/2/2 fies feb =o g)e= = |. S cl}. = See: © | 8s \\els gls/s/sl/sle S pec: Ey Oo fee: — . Ebeeee S & bsen 5/3/s & a) 2 (8/8 FL . SS Brooktree 51 ME 7811073 003329) Tub mm

© Register Summary perc fecal 2 _ . pees Ss ee z|2 pa Fe : Ss bey ees Pepa ees 2 213/3;/3\\3 Fecestac aa Ef 18/218 /2/8/8la]giala|*|s Pele? le alelelele : ae : lresarpeeae Po e/2/2/2/8]—l5 = fap ot hbica| Ee} 8 fossa] = lease arate s[s/s/3|s fee] © Pl dale lSlals|2/ 2 2lzlzlele aed 23 oyelslzlsis|8\\/e/5|/s/£/5/ 5/5 fee | ae eee as Egg #/2|2/2|2/2 ae feels alalsla : g s| | |3 PEEL Wlele|2 2 Sines = £\\E/2/& 3 Ete 8 a 2/2/2|2|2 ee = poe Of} | 2 2a | 2/2|2/2 2| ee Si) ess 5 B 3 | Ss | s -~ BERIGEE E/]3 Ble : Rees tal o ct

52 Brooktree* ‘

Balii| o “lo lelelels 1 lelelelslclelels pe] B Vole Slels dF -yelelelSle/sleis Bapeal & “f Jeélele FE : ele} e2}e/o|o Berens! SE Bosca te pepe) 2 os eile =n eee bee Set =a Sle | Se oO st al irae spe | ee Thiet, gees Fa ee] Be Hehe he ‘o> } ob] Seabee we fees: @ hrefee Bibel A ee ee eal ed ees —} delelsfs! Bll lelele|/s|slelals jee Phil Sis Tine s slslslslslz £ |. ee Biss) 2| 2 a] Bela 3/8|5|8|3/8)/8)s S pees Soe T ele 2) Ss} | J@/e/e/elelelele 8 lt Heed ~ | e = SP FlEleleyFyeye le =\\#2\\|2\\ 2 pia S| ze & Pe 8 |ge a | => 2 feed © pene S Besee a ligecee is |ESHEE! © fea w= |EESHe = ice O oris S| 3s | @ | sa) wy @ fs. - " wo = |es >| ss. 4 Spas 5 4 2 Pes. Siles| = 3 | Ss g 2 SPs] 6 steal @ ee 2/2 /¢|e/ 2 [glslels) S| & 2/slzlsiglelele ee oe ee ee SS ee ee Brooktree* 53 @@ 7411073 0033293 38195

Rogister Summary ; — pr ze felex as Fe z& 2/32/3e flee be lll zf| 28 Be aie Bt8510 ad a + et 2£ Eads ele om Eve ee reer) B\\s Faas ieee foe ae E/E Head 3 g beac tall ele Ere, eee Pe fess Esa te de ped =| ls] | Ee oe eter lel | ei Ribiaiaeed aa ee | bale Epes peas Baeeee bee | ie ES cs 7 eee a7a aa © teh cee Ee ee ee Bh 2/2 Beaiai Ea] fees ake |32|82 22/2 ie tte be eee zel ze Boe ee pe 2 Ba . | HAE g Hees = [ssi @ leer eee| & 3/3\\8 <4 pa S| ee | _ Eeeeee| E\\El2] ¢ 3-4 S| 2 =, 4 = ce

2 E a s = ee e Zire |

= g\\3| S| ) 3 515 on —. a Een & Z z 7 7811073 00 = : a|s 33294 755 Brookiree

Pt |e lo rele |e | ot }pelge | |gelge oy |S else Be|lSe Pot} ee} ee Po fo Be] Ek geal e |e ase Le besa tbetee ef =e Hae fan | ios Tee Rey leet ae a Eee Eile bole le Vole le 2| je leelse lw | 8282 SP oye = Erets[eiecil = e 2| 3s = Bey a | ss 2) 35 oe} 23. 2\\;e2e) @ 3 lee 2) el] So esl) ye © beeey S$] S$ | © [eekec s eee Brooktree* 55 @® 7811073 0033295 £491 mm

corresponding clock transition. See Table 15 and Table 16. Table 15. Delay Characteristics

1. This refers to internal or external clock recovery
2. Slip buffer short delay mode, initial delay upon reframe

Table 16. Analog Interface Characteristics

58 Brooktree*

Table 17. DC Characteristics

Table 18. 68HC11 MPU Bus Interface Characteristics

60 Brooktree*

Figure 16. 68HC11 Timing Diagram

sions may differ. See Table 19 and Figure 17. Table 19. 80C51 MPU Bus Interface Characteristics

Figure 17. 80051 Timing Diagram

for extended periods may affect device reliability. See Table 20. Table 20. Absolute Maximum Ratings

64 Brooktree*

Figure 18. 68-Pin Plastic Leaded Chip Carrier (J-Bend)

&2 Appendix A S TT Application Circuits Transmitter The circuits in Figure A-1 and Figure A-2 illustrate how to interface the transmit- ter and receiver analog interface to El lines through separately packaged trans- formers. Return loss information is given in Appendix C. Figure A-1. Transmitter Transformer 0 1. XAPOSO Die 75 Qor 1202

350 Transmission Line

• Transformer is Pulse Engineering PE-64934 or equivalent, 1:1 ratio. * For a75 Q line the transformer is Pulse Engineering PE-64934 or equiva- lent, 1:1 ratio (N = 1). * Fora 120 Q line the transformer is Pulse Engineering PE-64938 or equiv- alent, 1:1.26 ratio (N = 1.26) * For a configurable application, dual transformers, such as the Pulse Engi- neering PE-65389 (1:1:1.26 ratio), are available, Receiver —_For receive termination information refer to Appendix C. Figure A-2. Receiver Transformer

7 RAPOSI

75 Qor 1209 °. | Transmission Line 5 V Rterm RANEGI * Transformer is Pulse Engineering PE-64931 or equivalent, 1:1:1 or 1:2CT ! ratio. * Rterm = Ziline X 4 = 301 Q, 1% for 75 Q line = 511 Q, 1% for 120 Q line. Se Brooktree’ 67 M@™§ 7811073 0033306 217

. i PAGE(S) INTENTIONALLY BLANK . | a 7 @® 7811073 0033307 133

(6a) Appendix B Was Bt8510 Analog Drop and Insert in a Local Area Network Introduction This appendix describes an analog drop-and-insert local area network multiplex- ing 31 PCM voice channels onto a 2.048 Mb/s digital line. Each station can be separated by up to 500 feet with no additional components. The digital line uses the ITU-T standard protocols (CEPT or E1) detailed in G.703, G.704, G.706, and G.732. A ring network is described and a possible control protocol is presented. A simple form of line compression is used by assigning time slots to each station on a request basis. This allows any 31 of a possible 255 stations to be active at one time. The time slot indicators can be used to interface an analog codec directly. A multiplexer is required in the transmit direction to insert the transmit data. Performance Voice quality is standard A-law PCM voice coding, as per ITU-T G.711. By using the short delay mode in the framer's slip buffer, the through delay for each active station is about 20 sec. For a fully active network of 31 channels, the total delay is 610 psec. A station not in use is looped from receive to transmit to avoid add- ing additional delay. Network Timing Digital timing recovery from the 2.048 Mb/s line is included in the analog inter- face on-chip. Jitter must be filtered from this clock to provide a clean transmit clock. This is done in a catalog part, a 4046 CMOS phase-locked loop. eee Brooktree* 69 Mi 7811073 0033308 O7T mm

Bt8510 Analog Drop and Insert in a Local Area Network Signaling and Control Protocol A dedicated pin must be provided on the microcontroller to sense on-hook and off-hook states. All other signaling is done in-band using the DTMF functions in the telephone. Control of individual stations is accomplished using the Sa-bits in the stan- dard CEPT framing format. Together, they form a control channel of 20 kb/s bandwidth. Forty Sa bits are updated every 2 ms and are simultaneously known to every station throughout the network. A simple possible protocol follows: The managing entity is called the Head-of-Bus (HOB). The convention for each station is that if the required word is received as zero, it may be used. If it is . anything but zero, it must be repeated to the transmitter. The station will not be able to use the control bandwidth until that word is received as all zeros, indicat- ing that no station upstream is using it. This does give some priority to those sta- tions nearest the head of bus. $a4[7:0] This word conveys a message from a station by sending the HOB its station num- ber in this slot, and the request in another field. The request would usually be for a time slot assignment due to an off-hook condition, or the conveyance of an on- hook (user hung up). $a5[7:0] This word addresses a station by the HOB. The instruction from the HOB is in one of the other fields. ; $a6[7:0] This word conveys atime slot assignment from the HOB to the station. Transmit and receive functions use the same time slot. $a7[7:0]. This word specifies the request from a station, and also reports an error rate or other functional problems for maintenance. $a8[7:0] This word is reserved for future use. Maintenance Each station is assigned a number by setting a dip switch upon installation. The control protocol includes identification of a faulty station by station number, allowing prompt service. While in service, a partially failed station may be instructed to.go into loopback mode to avoid losing the entire ring. A manual switch can switch out a totally failed station. The microprocessor reads the dip- stick setting upon power-up, enabling the use of a common software module for all stations. To avoid the problem of one failed unit killing the entire network due to the serial connection, a bypass relay can be used to bypass a failed station. By wiring the relay to bypass when unenergized, a power failure will automatically take the failed station: out of the circuit. A watchdog timer can be employed to cause a loopback any time a sanity signal from the local processor stops toggling.

70 Brooktree*

@@ 7811073 0033309 Tob mm

Ki . ey Appendix C 2 a 8t8510 Return Loss, Receive Termination, and Receiver Jitter Tolerance Return Loss The general formula for calculating return loss is: Return Loss = 20lo; 2.-2) S\\Z,+Z, where Z, is the terminating impedance and Z, is the source impedance. Receiver — For the receiver, Z, is the line impedance and is nominally either 75 or 120 ohms. A receiver terminating resistor, Ryerm, is chosen such that Z,= Reerm/4 in order to match the terminating impedance to the line through the 1:1:1 transformer. For a 75 ohm line, a 301 Q £1% resistor is chosen for Reerm, While a 511 Q+1% value | is used for the 120 ohm line impedance. Ignoring the framer input impedance and assuming a perfect transformer, the , 1% variation of Rterm combined with the error in choosing the closest 1% value | will cause the return loss to be ~43.6 dB for the 75 ohm line and -31.6 dB for the | 120 ohm line. The actual terminating impedance is a function of the terminating resistor, Rterm in parallel with the input impedance of the receiver inputs. This input impedance is specified to be at least 5 kQ per pin which degrades the return loss to -34.8 dB for the 75 ohm line. The 120 ohm line return loss improves to -38.9 dB. Note that taking the chip input impedance into account reduces the effective Rierm Value. This explains why a 511 Q resistor is a better choice than a 475 Q value. ITU-T Recommendation G.703, paragraph 6.3.3 provides for a minimum return loss value of -18 dB from 102 kHz to 2,048 kHz. A typical transformer will be guaranteed to meet this minimum return loss requirement (see Pulse Engi- neering Application Note AN906-8, 11/90). From the above analysis it should be clear that the transformer will be the dominant factor in determining the return Joss at the line interface. ee Brooktree* 1 M@™ 7811073 0033310 728 a

& Appendix C Bt8510 Bt8510 Return Loss, Receive Termination, and Receiver Jitter Tolerance Transmitter. For the transmitter, we have a driver specified to have an output impedance of 5 +2 Q We also have two 35.7 Q £1% resistors in series for both the 75 and 120 ohm cable interfaces. This gives a total series resistance of between 117.0 Q and 125.6 Q. From transformer theory we know Z, is the turns ratio squared times the series resistance through the transmitter outputs. The 75 ohm line uses a transformer with a turns ratio of 1:1 yielding a worst case return loss of -31.5 dB, ignoring the transformer return loss. Since zeros and ones are driven equally (that is, zeros are not three-stated), this is a steady value. Again, the transformer will dominate the return loss measured at the line inter- face. The 120 ohm line uses a 1:1.26 transformer giving a worst case return loss of ~32.8 dB, ignoring the transformer return loss. Once again, the transformer will dominate the return loss measured at the line interface. Since the transformer is the critical component in the design for this parame- ter, return loss is not directly specified in the Bt8510 interface specification. The board designer must choose a transformer that is good enough to meet the speci- fications, and must also ensure that the layout is clean enough to not further degrade return loss. 72 . Brooktree* @@ 7411073 0033311 bb4 mm | F 1

———WMJ,W TE

818510 Return Loss, Receive Termination, and Receiver Jitter Tolerance

In Figure 1, the line impedance is given as Z,, and the receiver terminating resis- toris Reem: The transformer is a 1:1:1 or a 1:2 with center tap. Figure C-1. 818510 Receive Termination Equivalent Circuit Gg + e = + + h R - G + - Therefore from transformer theory Tn=l th So T= /2 . Also Vi =V2=Vin So V,=V,+V2 or Vi =2Vin and Zin = Vin / Tin | ‘We want Z;, to equal the cable impedance, so choose a value of Rierm where Reem = Ve/ Ty : substituting : Rterm = 2 Vin/ (lin / 2) = 4 Vin / Tin =4Zin | In other words, for a 75 ohm line use a 301 Q, 1% resistor and for a 120 ohm line use a 511 Q, 1% value. ee Brooktree* 3 @@ 7411073 0033312 STO mm

& Appendix C Bt8510 18510 Return Loss, Receive Termination, and Receiver Jitter Tolerance . Receiver Jitter Tolerance : The jitter tolerance of the digital clock recovery circuit on the Bt8510 has been tested with an HP-3785B jitter test set. This test set is limited to a maximum of 10 Unit Intervals (UIs) of jitter. The nature of the clock recovery circuit is such that it will tolerate a product of the frequency and amplitude of jitter at low frequencies, and that is the basis of the extrapolation presented on the chart. The maximum jit- ter tolerated is 118 UI, which is the depth of the slip buffer. Jitter amplitudes greater than 118 UI cause controlled frame slips and, therefore, errors. As is apparent from the chart in Figure C—2, the digital clock recovery circuit on the Bt8510 easily meets the minimum jitter tolerance specified in ITU-T Specifica- tion G.823. Figure C-2. Bt8510 Receiver Jitter Tolerance Graph 1000 | rg oo Eee tr Pt a i] Measured Data PO nt 6.828 Specification voo pop HM ELS Ibo LIB | +: a _ POS Te oe ae S10 ee i i St

3 TTT EN

a oor | LUMI TE TT TE PTT PTT O41 1 10 100 1000 10000 100000 Frequency (Hz) m4 Brooktree* . @®§ 7811073 0033313 437 mm

TK, . a) Appendix D Bt8510 Receiver Sensitivity and Signal Reflection Immunity Introduction input port must be designed to accommodate a signal-to-interference ratio of 18 dB which is attenuated by the characteristic of an interconnecting pair in the range of 0 to 6 dB. Receiver Sensitivity The data pattern generated by the W&G PRA-1 Frame Analyzer is passed through the ME-1002 Short Line Simulator and into the Bt8510 receiver on the Brooktree CEPT Evaluation Board. The signal is then passed through the CEPT transcoder C port via a clear channel and returned to the W&G PRA-1 receiver. A continuous 64 kb/s Bit Error Rate (BER) test is run on the data in order to monitor errors in the transmission path. This setup is shown in Figure D-1. Figure D-1. Receiver Sensitivity Test Set-Up ME-1002 ‘Signal Input Short Line Simulator | Noise Input &) Attenuator A ™ Rx ps | W&G PRA-1 Brooktree CEPT ; Frame Analyzer Transcoder ee Brooktree* 75 MH 7811073 0033314 373 a 1 ee

Bi8510 Receiver Sensitivity and Signal Reflection Immunity _ The maximum programmable attenuation on the ME-1002 is 15.5 dB. At this level the Bt8510 had zero errors. To decrease the signal level further, we fed the signal into the ME-1002 via the noise input port. This provided a fixed 18 dB of attenuation. The signal could then be attenuated further by the programmable attenuator. The Bt8510 receiver was able to recover the data error free with an additional 2 dB of attenuation. This is summarized as follows: Signal to Interference Ratio (S/I) = ©, : Attenuation with 0 BER 2 20 dB Signal Reflection Immunity The signal reflection immunity test setup is similar to the receiver sensitivity test (see Figure D-2), The W&G PRA-1 output is connected to the signal input of the ME-1002, and the El reference stream (noise source) is a Brooktree Bt8510 Eval- uation Board transmitting idle code. The Bt8510 receiver was able to recover the data error free under these condi- tions with the programmable attenuator set to the maximum 15.5 dB. This is sum- marized below. This documents that the ITU-T G.703 requirement of at least 6 GB of attenuation is accommodated by the Bt8510. Signal to Interference Ratio (S/I) = 18 dB, Attenuation with 0 BER 2 15.5dB . Figure D-2. Signal Reflection Immunity Test Set-Up . ME-1002 ‘Signal Input Short Line Simulator . % Programmable Stream ai Tx Rx pe W&G PRA-1 Brooktree CEPT . Frame Analyzer Transcoder Equipment ME-1002 Short Line Simulator Mountain Engineering & Technology 123 Genesee Ct. Boulder, CO 80303 . (303) 494-9120 . W&G PRA-1 Frame Analyzer Wandel and Golterman Inc.

990 North Bowser Road, Suite 780

Richardson, TX 75081 (214) 231-8923

76 Brooktree’

= 7841073 0033315 20T m@

DK . G2 Appendix E A Phase-Locked Loop (PLL) to Meet ITU-T G.823 Jitter Attenuation Requirements In certain loop timing configurations, a system may require a phase-locked looped in order to provide jitter attenuation and clock smoothing. A system might have a bank of framers where one will be selected to provide timing for the unit. Figure E-1 illustrates such a configuration. Figure E~1. System Clock Dejittering Recovered Clock ae LF peeeeen SO —1 Bt8510 Dejittered Clock Bts8s510 oe : Bt8510 oo : Bt8510 mo Brooktree* 77 MB 7811073 0033316 145

A Phase-Locked Loop (PLL) to Meet ITU-T 6.823 Jitter Attenuation Requirements Acommon PLL implementation uses a VCXO. This PLL offers excellent jit- ° ter attenuation as a result of the inherent VCXO characteristics. The Bt8360/8510 EVM Evaluation Module employs such a circuit. This circuit, shown below in Figure E-2, uses a 32.768 MHz VCXO, two counters, a phase comparator and a passive loop filter. The recovered clock, RCKO, is used for one counter. The VCXO output divided by 16 (performed by the Bt8510) is used for the other counter, The counters ensure that the phase detector will not miss an edge in the presence of high amplitude jitter. The two counter outputs are routed to the phase comparator. The output of the phase comparator is filtered and used to drive the VCXO. The output of the VCXO sources the Bt8510 input, CK32I. CK160 can then be used as the Bt8510 system clock, SYSCKI. The VCXO replaces the need for a 16.384 MHz crystal oscillator. BITCKO provides the source for the Trans- mit clock and the Slip Buffer clock. Figure E-2. 32.768 MHz VCXO . RCKO P Pa su | suox| Phase vexo L_cxszi] E1 Framer Comparator 92.768 MHz +—CXS2! ole HCT4046A .

12 Bit

R1 = 10KQ. R2 =1KQ R3 = 4.7KQ C1 = 0.015pF C2 = 0.1pF C3 = 4.7pF Brooktree recommends the following manufacturer for the VCXO: Connor-Winfield Oscillators

2111 Comprehensive Drive

Aurora, IL 60505 . TEL: 1 (708) 851-4722 Part# HV53-200 Freq: 32.768MHz Performance of this circuit was measured and found to meet or exceed CCITT G.823 requirements. Figure E-3 show G.823 specification and circuit performance.

78 Brooktree*

@™ 7611073 0033317 082

A Phase-Locked Loop (PLL) to Meet ITU-T G.823 Jitter Attenuation Requirements Figure E-3. G.823 Specification and Circuit Performance i f ' \\ ' 1 f ' 1 1 1 t Input vitt H t ' 1 15 oer ! d a : 1 1 1 A 1 1 ‘ 1 1 ' \\ 1 1 1 ' t 1 : 1 1 1 \\ i 1 1 i 1 1 1 1 1 1 1 i 1 1 t 1 1 1 1 1 ' 1 1 1 t ~ 1 1 i 1 2 ' ' ; i 5 1 1 1 i = 1 1 1 ' o i ! ‘ i ‘ ( 1 : 1 1 \\ Ce ee Sa, Velasco ' 1 ' t 1 t ' ' 1 1 ' ' 1 , ' 1 1 1 t ' : ielnineey neaeeetnaa aaiaiaaee ioe Output Jitter | ' ' / ' x .05 - : 0.18 UI 10 100 1000 10000 100000 Frequency (Hz) a Brooktree* 79 Mi 7811073 0033318 T15 Ml