BT471 Datasheet | DigiCamel IC Datasheet

Manufacturer	Series	Package	Documents	Available	Select specification
List of Unclassifed Man...	-	-	3	PDF HTML	Viewing

BT481 ETC

Document overview

Manufacturer or author: Provided By www.digicamel.com(free datasheet download site)
PDF pages: 35

Technical content

BROOKTREE CORP SbE D MM 1645595 0004251 a7T MBRK . TS2-33-4R Preliminary Information This document contains information on new product, The parametric information, although not fully characterized, is the result of testing initial devices. B 4 8 1 Distinguishing Features t * 85 and 75 MHz Operation + Sync on all Three Channels * Supports 8:8:8:8, 24-bit True Color + Standard MPU Interface B t48 2 and VGA Overlay + 44-pin PLCC Package * Supports 8:8:8 24-bit True-Color Format : Suppers 568 xn Tine Color Format Applications 256-Word Color Palette uppors 5:5:5 TARGA Tre-Color j ; 15-, 16-, and 24-bit True + High-Resolution Color + 32x 32x 2 User-Definable Graphics Color Power-Down Hardware Cursor + CAB/CAD/CAM RAMDACs™ + Bt471/475/476/477/478 Pin Compatible, mage Processing * Power-On-Reset for Internal Registers. Instrumentation + Power-Down Mode + Desktop Publishing Product Description + Antisparkle Circuitry + Laptop Computers . AE ee cormparanors ‘The Bt481 and Bt482 RAMDACs are de- + Triph vit (8-bit) D/A Converters signed specifically for high-performance + 256 x 18 (24) Color Palette RAM Related Products ¢oi;, ‘sraphics. , eee * 3x 18 (24) Cursor Color Palette Bul7i «Bers Both the Br481 and Bt482 support three = 15x 18 (24) Overlay Registers * Be . true-color modes: 15-bit (5:5:5, 32K colors) © Optional Internal Voltage Reference + BYM76 + Btt77 TARGA format, 16-bit (5:6:5, 65K colors) + Programmable Pedestal + B78 XGA format, and 24-bit (8:8:8, 16.8M col- ors) true-color format. They also support 8- . . bit pseudo-color format (256 colors). Functional Block Diagram ‘The Bt482 has a 256 x 18(24) lookup table RAM, 15x18(24) overlay registers, 32 x 32 x vA op var nee 2 user-definable cursor, 4 x 24 cursor color eS palette and triple 8-bit D/A converters. Both Pe eee ds leetcc al Mee) ony 6-bit and 8-bit color modes are supported. The [i Re ee — cone B1481 is identical to the Br482, but the Br481 0K Ma ca = 3e00 Bebe oo = has no 32 x 32 x 2. cursor RAM. Both devices v0.77 af ovenay | Ea ie ae 4 can support an external cursor. External cur- snc a Est Bas Ac Sa 100 sor data is routed through the 3 x 24 cursorcol- BLANK le Lees | ee | A me | or palette to provide three modes for color se- ae | Sb Be ce lection. Mode 1 is a three-color cursor, Mode ser 4 | ees Ea wae 2 is referred to as PM/Window or XGA cur- MS Gd ee sor, and Mode 3 is referred to as an X- ei _ Windowscursor. unc] = ‘A power-down mode is available on both | es Teor orem ye) quirements when the analog outputs are not cs ate Sta AEB ES aa used. This is useful in laptop computer sys- a | tems that require the option to drive an exter- vo: DY War SO RSL RSE nal RGB monitor. Both the Bt481 and the Bt482 have on- chip analog output comparators to simplify diagnostics and debugging, with the result output onto the SENSE* pin. Also included Brooktree Corporation * 9950 Barnes Canyon Rd. + San Diego, CA 92121 (619) 452-7580 » (800) VIDEO IC + TLX: 383 596 * FAX: (619) 452-1249 ® er al Brooktree

BROOKTREE CORP SbE D MM Lb45595 O004252 706 MBBRK Bt481/482 Brooktree* ption ( ) 1-52-33-43 is an on-chip voltage reference to simplify use of the device. A power-on reset is available on the Bt481/482 devices to On power-up, the Bt481 and Bt482 behave as the initialize internal registers. Bt471 or Bt478, including their antisparkle capabilities, ‘The Bt481 and Bt482 generate RS-343-compatible video on-chip voltage reference, and analog output comparators. _signals into a doubly-terminated 75 Q load. < 3 3 S86 8 8 8 ‘ Ey get pees Masers eenaetecete eeeitee tee: ae ee ee Hegel s As es Pee ceese ye eerie a ee: bY ee ee Seber BEE, oes ee eee 21 -lssle Pus ccses reer rere peeeemeese a pepe ccipeee res | © 3 escstit2.a l- Hee On Pap teeeea lens lejecuie tse st lemme bP pe ep et Paiste] dee Hee de pols lets glo les fd PeoedojS@ Eize a7 Veto lerist le jet |e 2] 88 ed fad 3 3 \\33 Hoe ttttt (| 1318 3 Faia faa Hy eves pel LHS" [ep mes eee EEE pos Ea eee are feos EN MEH Ee oer feral pena ten pees HEHE tars ed] 8 PQ ese ee FSF 8 fc] saa] peters De SE eps rele. Eee 2 xlelp]s/3] sal 8) a/2 fy HBG HEEE lz Detailed Block Diagram. 4-122 SECTION 4

Bt482 support a standard MPU bus interface, allowing the —_read cycles until the entire block has been read. The RSO-RS2 select inputs specify whether the MPU is . . specified by the address register. The address register then zero (see Table 2). block of color values in consecutive locations may be read must be a logical zero (see Table 2). Table 1. Control Input Truth Table.

Table 2. Address Register (ADDR) Operation. (sce Command Register A in the Internal Registers section), quired to load a 16-bit pixel. following format: data can be masked out through the pixel read mask register. He Je, and 24-8 its-per-Pixel clock must be twice as fast as the internal pipeline clock. In the 15- and 16-bit-per-pixel dual-edge clock mode (sce _ alee the pipeline clock from the input clock. Registers section), the least significant byte is latched on the accept 24 bits of pixel data by using three input clock cycles.

BROOKTREE CORP SbE D MM 1645595 0004255 415 MEBRK Brookiree’ Bt481/482 Circuit Description (continued) ption ( ) T-52-33-43 Accessing Command Registers without the RS2 line latched in three input clock cycles, the input clock must be ‘When the cursor or overlay functionality of the Bt481/482 is three times as fast as the internal pipeline clock. The Bt481 _not used and the Register Select Line 2 (RS2) must be tied and Bi482 each have an internal divider to generate the pipe- _Jow at all times, the command registers of the Bt481/482 can line clock from the pixel input clock. Palette data has priori- still be accessed. ty over bypass data, A flag will be set when the pixel read mask register (RS1 = 1 and RSO = 0) is read four times consecutively. The next Additional Information write to the pixel read mask register will be directed to Com- ; . mand Register A and can be used to set the bits in that regis- ‘When the MPU is accessing the color palette RAM, the ad- ter. Any access of the command register thereafter will also dress register resets to $00 following a blue read or write Cy-—euire four consecutive reads to the pixel read mask regis- cle to RAM location SF. While the MPU is accessing the ter. A write to any address or a read to any address other overlay color registers, the 4 most significant bits of the ad- han the pixel read mask register will reset the flag. dross regioter (ADDR4-7) are ignored. - ‘When the extended registers are accessed (Bit AO = 1), ‘The MPU interface operates asynchronously to the pixel his feature is disabled, clock. Data transfers between the color palette RAM/overlay registers and the color registers (R, G, and B in the block di- coon ac syhonit ty eral ge. Das eamion AODGSng the Cursor RAM Array take place in the period between MPU accesses. To reduce noticeable sparkling on the CRT during MPU access to the The 32 x 32 x 2 cursor RAM is accessed in a planar format, color palette RAMs, internal logic maintains the previous —_In the planar format only 7 address bits are used. The eighth ‘output color data on the analog outputs while the transfer be- it determines which plane (0 or 1) data of the cursor RAM tween lookup table RAMs and the RGB registers occurs. array is accessed. A single address presented to the cursor To keep track of the red, green, and blue read/write cycles, RAM accesses cight bit locations in plane 0 or 1, depending the address register has 2 additional bits (ADDRa and ‘on the state of address bit 7. ADDR) that count modulo three, as shown in Table 2, They ‘After each access in the planar format, the address incre- are reset to zero when the MPU writes to the address register ments. The MPU uses ADDR, a binary address counter, to and are not reset to zero when the MPU reads the address access the cursor RAM array (see Table 2). ADDR is the register. The MPU does not have access to these bits. The same binary counter used for RGB autoincrementing. Any other 8 bits of the address register, incremented following a —_write to ADDR after cursor autoincrementing has been ini- blue read or write cycle (ADDRO-7), are accessible to the tiated resets the cursor autoincrementing logic until cursor ‘MPU. These bits arc used to address color palette RAM loca- RAM array has again been accessed. Cursor autoincrement- tions and overlay registers, as specified in Table 2. The MPU ing will then begin from the address written. A read from the may read the address register at any time without modifying ADDR does not reset the cursor autoincrementing logic. To its contents or the existing read/write mode. The pixel clock access the 32 x 32 x 2 cursor RAM, a logical one must be ‘must be active for MPU accesses to the color palette RAM. written to bit CR3 in the cursor register. The cursor register must be indirectly accessed. Accessing Cursor Control Registers and Control Register B Cursor Operation (Bt482 only) A cursor register, CR; four cursor position registers; and a The Bt482 has an on-chip, three-color, 32 x 32 x 2 pixel second control register, B, were defined to control the cur- _user-definable cursor. This cursor works with both interlaced sor, setup select, 6- or 8-bit select, and the sleep modes of and noninterlaced systems. the Bt481/482. Since there are only three register select lines ‘The pattern for the cursor is provided by the cursor RAM, (and all eight combinations have already been used), the cur- which may be accessed by the MPU at any time. The cursor sor register; cursor X,Y registers; and Command Register B is positioned through the cursor position register (Xp,Yp) must be accessed indirectly. (ee Figure 1). A (0,0) written to the cursor position registers For example, the cursor register is accessed with the fol- _will place the cursor completely offscreen. A (1,1) written to lowing sequence of operations: the cursor position registers will place the lower right pixel 1. Set RS2-RSO = 110 in Command Register A. of the cursor on the upper left corner of the screen. Only one 2. Write a logical one to command register bit AO. cursor pattern per frame is displayed at the location specified 3. Set RS2-RSO = 000 in address register write mode. for both interlaced and noninterlaced display formats, regard- 4. Write address register to 0000 0011. less of the number of updates to (Xp,Yp). The cursor’s verti- 5. Set RS2 - RSO = 010 in read mask register. cal or horizontal location is not affected during any frame 6. Read or write cursor register. displayed, There are no restrictions on updating (Xp, Yp) oth- Table 3 contains specifications to indirectly address other _e than both cursor position registers must be written when registers. the cursor location is updated. Internal x and y position regis- PC GRAPHICS 4-125

Table 3. Indirect Register Addressing Truth Table. Figure 1. Cursor Positioning. The cursor pattern can be displayed in an interlaced sys- ter row 1 in the cursor RAM array.

ray relative to the first active cursor line in the even field, _en time, Bit CRS in the cursor register controls cursor type. in a noninterlaced system. Scan lines displayed in a frame ferred to as an X-Windows cursor (see Table 4). Figure 2 is a visual explanation of planar pixel format a .

132 Ato

256 Row 32

Figure 2. Planar Cursor Pixel Format and Mapping.

the CR4 command bit and the FLD®* input, c.g, when displayed and the FLD* pin has been toggled. ‘current field is displayed, displayed, if the FLD* does not change. mode and is considered the first line of the EVEN field. In scan. Noninterlaced display scan is equal to one frame. scan line 1. In the interlaced mode, scan line 2 is even fields. Table 4. Cursor Color Modes. (Planes 1 and 0 refer to the Internal Cursor RAM.) ‘The cursor data has priority over the overlay data. OL3 and OL2 are used for external cursor support. Table 5. External Cursor Color and Overlay Control Truth Table (Pixel/OL Read Mask Register = $FF).

Figure 3. Interlaced / Noninterlaced Display Operation. pin controls 6- or 8-bit operation. While the 6*/8 bit sleep mode. For 6-bit operation, color data is contained on the lower of portions of the internal voltage reference. the data, Also, the RAM may still be read or written to _‘for SENSE* to be stable. running. The RAM automatically powers up during MPU completion of characterization.

The contents of the pixel read mask register, which may rising edge of CLOCK to maintain synchronization with

ANDed with the OLO-OL3 inputs. Bit DO of the overlay _inputs modify the output levels. Register B in the Internal Register section contains Internal Register section).

0 SEF color palette RAM location SFF

Table 6. Pixel and Overlay Control Truth Table (Pixel Read Mask Register = $FF).

Note: 75 Q doubly-terminated load; SETUP = 7.5 IRE. VREF = 1.235 V and RSET = 143 Q. RS-343A levels and tolerances are assumed on all levels. Figure 4. RS-343A Composite Video Output Waveforms Note: 75 Q doubly-terminated load; SETUP = 7.5 IRE. VREF = 1.235 V and RSET = 143 Q. Table 7. RS-343A Video Output Truth Table (SETUP = 7.5 IRE).

Note: 75 Q doubly-terminated load; SETUP = 0 IRE. VREF = 1.235V and RSET = 143 Q. RS-343A levels and tolerances are assumed on all levels. Figure 5. RS-343A Composite Video Output Waveforms Note: 75 Q doubly-terminated load; SETUP = 0 IRE, VREF = 1.235 V and RSET = 143 Q. Table 8. RS-343A Video Output Truth Table (SETUP = 0 IRE).

Figure 6. PS/2 Composite Video Output Waveforms Note: 50 Q load; SETUP = 0 IRE. VREF = 1,235 V and RSET = 176 Q. Table 9, PS/2 Video Output Truth Table (SETUP = 0 IRE).

BROOKTREE CORP SbE D MM 1645595 OOO42b4 428 MBRK Bt481/482 Brooktiree’ ih nerd Internal Registers T-52-33-43 Command Register A This register may be written to or read by the MPU at any time. All bits are initialized to logical zero on power-up. aod cd kennel 32-bit modes when used with Bits A6, AS, and Pseudo Color (256 Colors) A4, If A7 is a logical zero, pseudo-color mode is enabled regardless of the state of A6, AS, or A4. 5:5:5 Dual-Edge Clock (33K Colors) Bit AG determines whether the device is in 15- or 16-bit-per-pixel mode. a Bit AS determines whether the data is input on the. Py fof e| 5:6:5 Dual-Bdge Clock (65K Colors) rising edge of the input clock, or on the rising and falling edges of the input clock. A logical zero 5:5:5 Single-Edge Clock (33K Colors) | Witten to this bit indicates a dual-edge clock, and a logical one indicates a single-edge clock. Eek & Bit A4 indicates a 24- or 32-bit input, ie., a 24- bypass and an 8-bit VGA passthrough. Bit AS Pfofola| E:8:OL Dual-Bdge Clock (168M Cotor)| determines whether the pixels are input 8 bits a a time on every rising edge, or 8 bits at a time on 8:8:8 Single-Edge Clock Only rising and falling edges of the input clock. When (16.8M Colors) bits Ad and A6 are set to logical one, the inputs are 24-bit true-color bypass, operating in single- edge clock mode. A3, A2, Al Reserved (logical zero) A logical zero must be written to these bits to en- sure proper operation. AO Extended Register Select A logical one written to this bit allows the user to indirectly access the extended register set. In- (0) Extended register set cannot be cluded in the extended register set are the cursor accessed. register and the cursor X,Y registers. (1) Extended register set can be accessed. 4-134 SECTION 4

BROOKTREE CORP 5bE D MM 1645595 0004265 364 MBRK Brooktree* Bt481/482 eee RO OL Internal Registers (continued) T-52-33-43 Command Register B This register is operational only while bit AO in Command Register A is a logical one. This register is initialized ‘on power-up. On power-up, bits B7, B6, BS, and BO are set to logical zero; bits B4, B3, B2, and B1 are set to log- ical one to enable the Bt481/482 to emulate the Bt478, While the 6*/8 pin is held low, this register will be func- tionally ignored. B7 Reserved (logical zero) A logical zero must be written to this bit to ensure prop- er operation. B6 Overlay Register Mask Select A logical zero written to this bit inhibits address of the (0) Overlay register mask inhibited overlay registers only during true-color operations. A (1) Overlay register mask enabled logical one written to this bit enables address of the overlay registers only during true-color operations. BS SETUP select This bit specifies the blanking pedestal to be either 0 or (0) OIRE 7.5 IRE. When the interlaced mode is set (bit CR4 = 1), (2) 7.5IRE only this bit will be able to control the SETUP select; the SETUP pin will become the field input (ODD/ EVEN). While the 6*/8 pin is held low, the SETUP pin will act as the pedestal control rather than the field input. Blue sync enable This bit specifies whether the IOB output contains syne (0) nosync on blue information. (1) syne on blue Green sync enable This bit specifies whether the IOG output contains syne (0) no sync on green information. (1) sync on green Red sync enable This bit specifies whether the IOR output contains sync (0) no sync on red information, (1) sync on red BL 6-bit/8-bit select On the Bt481 and Bt482, this bit specifies whether the MPU is reading.and writing 8 bits (logical one) or 6 bits ©) 6-bit (logical zero) of color information each cycle. The 6*/8 (2) 8-bit bit and 6*/8 pin are logically ANDed. BO SLEEP enable While this bit is a logical zero, the Bt482 functions nor- mally. If this bit is a logical one, the DACs and power to (0) normal operation the RAM are turned off. The RAM still retains the data (1) sleep mode and may be read or written to while the pixel clock is running. The RAM automatically powers-up during MPU read/write cycles and shuts down when the MPU access is completed. About 1 second is required for the Bt482 to output valid video data after enabling normal operation (coming out of sleep mode), This time will vary depending on the size of the COMP capacitor. The DACs will be tumed off during sleep mode only if a voltage reference (internal or external) is used. If an extemal current reference is used, external circuitry should turn the current reference off during sleep mode. PC GRAPHICS 4-135

BROOKTREE CORP SbE D MM 1645595 OOO42bb 2TO MEBRK Bt481/482 Brooktree® at Internal Registers (continued) 7252-33-43 Cursor Register This register is operational only when Bit AO in Command Register A is a logical one. All bits are initialized to logical zero on power-up. (CR7, CR6 Reserved (logical zero) A logical zero must be written to these bits to ensure proper operation. CRS Cursor Select This bit determines whether the internal cursor is used or external cursor data is input with the two (0) Internal Cursor Selected MSB overlay pins of the Bt482 (OL3 and OL2). (1) External Cursor When the internal cursor is enabled, all 15 locations Mode/Overlay of the overlay palette can be selected. When an ex- ternal cursor is enabled, only the first four locations of the overlay palette can be selected. CR4 Display Mode Select When this bit is a logical zero, the display format is noninterlaced. When it is a logical one, the display (0) Noninterlaced format is interlaced, and the odd/even fields are in- (1) Interlaced put with the SETUP pin. The mode must be set prop- erly to ensure proper operation of the internal cursor. CR3 Cursor RAM or Cursor Palette Select A logical one written to this bit enables the user to access the 32 x 32 x 2 cursor RAM. A logical zero (0) Cursor Color Palette Selected written to this bit enables the user to access the three (1) Cursor RAM Selected cursor color palette locations. CR2 Reserved (logical zero) A logical zero must be written to this bit to ensure proper operation. CRO, CR1 Cursor Mode Select ‘These bits determine the functionality of the onboard. 32x 32 x 2 cursor. (00) Cursor Disabled (01) 3-Color Cursor (10) 2-Color/Complement Cursor (11) 2-Color/X-Windows Cursor 4-136 SECTION 4

BROOKTREE CORP SbE D MM 2645595 0004267 137 MBRK Brooktree’ Bt481/482 Internal Registers (continued) . T-52- Cursor (x,y) Registers 52-33-43 These registers specify the (x,y) coordinate of the 32 x 32 x 2 hardware cursor. The cursor (x) register is made up of the cursor (x) low register (CXLR) and the cursor (x) high register (CXHR); the cursor (y) register is made up of the cursor (y) low register (CYLR) and the cursor (y) high register (CYHR). The last value written by the MPU to these registers is the value returned on a read. These registers may be written to or read by the MPU at any time. 4 CXLR and CXHR are cascaded to form a 12-bit cursor (x) register. Similarly, CYLR and CYHR are cascaded to form a 12-bit cursor (y) register. Bits D4—D7 of CXHR and CYHR are always logical zeros. Cursor (x) High Cursor (x) Low (CXHR) (CXLR) Data Bit D3 D2 DI DO D7 D6 DS D4 D3 D2 DI DO X Address Xil x10 x9 x8 x7 X6 XS x4 x3 x2 Xi x0 Cursor (y) High Cursor (y) Low (CYHR) (CYLR) Data Bit D3 D2 D1 DO D7 D6 DS D4 D3 D2 DI DO Y Address Yi Y10 Y9 Y8 Y7 Y6 YS Y4 Y3 Y2 Yi YO ‘The cursor (x) value to be written is calculated as follows: Xp = desired display screen (x) position + 32 (or $0020) where the (x) reference point for the display screen, x = 0, is the upper left corner of the screen. The Xp po- sition equation places the upper left comer of the cursor RAM array to the desired screen location. This allows the cursor position to be defined in the same coordinate space as the screen, Values from 0 (or $0000) to 4095 (SOFFF) may be written into the cursor (x) register. If Xp is equal to zero, the cursor will be entirely offscreen (see Cursor Operation in the Circuit Description section). The cursor (y) value to be written is calculated as follows: Yp = desired display screen (y) position + 32 (or $0020) where the (y) reference point for the display screen, y = 0, is the upper left corner of the screen. The Yp po- sition equation places the upper left corner of the cursor RAM array to the desired screen location. This allows the cursor position to be defined in the same coordinate space as the screen. Values from 0 (or $0000) to 4095 (or $OFFF) may be written into the cursor (y) register. If Yp is equal to zero, the cursor will be entirely offscreen (see Cursor Operation in the Circuit Description section). PC GRAPHICS 4-137

REE CORP SbE D MM 1645595 0004268 073 MEBRK Bt481/482 Brooktree® in Descriptions Pin Descript T-52-33-43 Fane & nami Dern BLANK* re) Composite blank control input (TTL compatible). A logic zero drives the analog outputs to the blanking level, as specified in Tables 7-9. BLANK‘ is latched on the rising edge of CLOCK. When BLANK‘ is a logical zero, the pixel and overlay inputs are ignored. SETUP or (23) SETUP is setup control input (TTL compatible). This input is used to specify either a 0 IRE (logical FLD* zero) or 7.5 IRE (logical one) blanking pedestal. FLD* is odd/even field input (TTL Compatible). This signal should be changed only during vertical blanking. This input ensures proper operation of the onboard cursor when interlaced operation (command register bit CR4 = 1) is selected. When it is a logical zero, an even field is specified. When this input is a logical one, an odd field is specified. If CR4 = 1, SETUP can be controlled only through Bit BS in Command Register B. This input becomes the SETUP control if noninterlaced operation is selected (CR4 = 0). This pin should not be left floating. SYNC* (6) Composite syne control input (TTL compatible). A logical zero on this input switches off a 40 IRE current source on the analog outputs (see Figures 4-6). SYNC* does not override any other control or data input, as shown in Tables 7-9; therefore, it should be asserted only during the blanking interval. It is latched on the rising edge of CLOCK. If sync information is not required on the video outputs, SYNC* should be connected to GND. CLOCK (40) Clock input (TTL compatible). The rising edge of CLOCK latches the P0-P7, OLO-OL3, SYNC*, and BLANK‘* inputs. It is typically the pixel clock rate of the video system. It is recommended that CLOCK be driven by a dedicated TTL buffer to avoid reflection-induced jitter. PO-P7 (32-39) | Pixel select inputs (TTL compatible). These inputs specify, on a pixel basis, which one of the 256 entries in the color palette RAM is to be used to provide color information. They are latched on the rising edge of CLOCK. PO is the LSB. Unused inputs should be connected to GND. OLO-OL3 (41-44) | Overlay select inputs (TTL compatible). These inputs specify which palette is to be used to provide color information, as specified in Table 6. When the overlay palette is accessed, the PO-P7 inputs are ignored. They are latched on the rising edge of CLOCK. OLO is the LSB. Unused inputs should be connected to GND. OL2 and OL3 are used for external cursor inputs when external cursor is selected. COMP (29) Compensation pin. If an external or the internal voltage reference is used, this pin should be connected to OPA. If an external current reference is used, this pin should be connected to IREF. A 0.1 pF ceramic capacitor must always be used to bypass this pin to VAA. The COMP capacitor must be as close to the device as possible to keep lead lengths to an absolute minimum. The PC Board Layout Considerations section contains critical layout criteria. VREF Gl) Voltage reference input. If an external voltage reference is used, it must supply this input with a 1.235. V (typical) reference. If an external current reference is used, this pin should be left floating, except for the bypass capacitor. A 0.1 HF ceramic capacitor should decouple this input to GND. The decoupling capacitor must be as close to the device as possible to keep lead lengths to an absolute minimum, When using the internal reference, this pin should not drive any external circuitry other than the decoupling capacitor. The PC Board Layout Considerations section contains further information. OPA (30) Reference amplifier output. If an external or the internal voltage reference is used, this pin must be connected to COMP. When an external current reference is used, this pin should be left floating. The PC Board Layout Considerations section contains further information. TOR, 10G, (25-27) | Red, green, and blue current outputs. These high-impedance current sources can directly drive a IOB doubly-terminated 75 Q coaxial cable. The PC Board Layout Considerations section contains further information. VAA (4, 21, 22)| Analog power. All VAA pins must be connected together on the same PCB plane to prevent latchup. 4-138 SECTION 4

: BROOKTREE CORP SBE D MM 2645595 0004269 TOT MMBRK Brooktree* Bt481/482 ONTOS Pin Descriptions (continued) T-52-33-43 | [Pin Name & Number] eseription id GND G,24)| Analog ground. All GND pins must be connected together on the same PCB plane to prevent latchup. IREF (28) | Full-scale adjust control. ‘The IRE relationships in Figures 4-6 are maintained, regardless of the full-scale output current. When an external or the internal voltage reference is used, a resistor (RSET) connected between this pin and GND controls the magnitude of the full-scale video signal. The relationship between RSET and the full-scale output current on each output is: RSET (Q) = K * 1,000 * VREF (V) / Iout (mA) K is defined in the table below, It is recommended that a 143 Q RSET resistor be used for 50 Q with no sync), a 176 Q RSET resistor is recommended. When an external current reference is used, the relationship between IREF and the full-scale output current on each output is: IREF (mA) = Iout (mA) / K 6-bit 7.5 IRE 3.078 2.211 8-bit 7.5 IRE 3.102 2.230 6-bit OIRE 2.910 2.044 8-bit OIRE 2.934 2.063 ‘See the PC Board Layout Considerations section for further information. WR* (16) ‘Write control input (TTL compatible). D0-D7 data is latched on the tising edge of WR*, and RSO-RS2 are latched on the falling edge of WR* during MPU write operations. RD* and WR* should not be asserted simultancously. RD* 6 Read control input (TTL compatible). To read data from the device, RD* must be a logical zero. RSO-RS2 are latched on the falling edge of RD* during MPU read operations. RD* and WR* should not be asserted simultaneously. RSO,RSi, —(17~19)}_ Register select inputs (TTL compatible). RSO-RS2 specify the type of read or write operation RS2 being performed, as detailed in Tables 1 and 2. DO-D7 (8-15)} Data bus (TTL compatible). Data is transferred into and out of the device over this 8-bit bidirectional data bus. D0 is the least significant bit.

68 Q) 6-bit/8-bit select input (TTL Compatible), This pin specifies whether the MPU is reading and

‘writing 8 bits (logical one) or 6 bits (logical zero) of color information each cycle. For 8-bit ‘operation, MPU Bit D7 is the most significant bit during read/write cycles. For 6-bit ‘operation, MPU Bit DS is the most significant bit during read/write cycles. (D7 and D6 are ignored during write cycles and are logical zero during read cycles.) SENSE* ad) Sense output (CMOS compatible). SENSE* is a logical zero if one or more of the IOR, IOG, and 10B outputs have exceeded the internal voltage reference level. SENSE* may not be stable while SYNC‘ is toggling. TRUECOL* (20) True-color mode select input (TTL compatible). This signal is inverted and logically ORed with Bit A7 in Command Register A. A logical zero will enable the truc-color modes. By programming the proper command register bits, the user can choose either 5:5:5, 5:6:5, 8:8:8, or 8:8:8:OL and determine whether the pixels are input on a single clock edge or a dual clock edge (see the Command Register section for details). The TRUECOL* pin should be tied to VAA to disable the hardware selection of the true-color mode. PC GRAPHICS 4-139

BROOKTREE CORP S5SbE D MM 1645595 0004270 721 MEBRK Bt481/482 tk Pin Descriptions (continued) J-52-33-43 ceeeeeceléé Selelalelalalstatatata cock fe Dr van Bae a0 moucone ao Gigi isrereewecssseteicgee ss 8/6) est ea gt et 9 ng yRaRRSEREESB a 4-140 SECTION4

BROOKTREE CORP SbE D MM 1645595 0004271 &64 MBRK Brooktree’ Bt481/482 eee PC Board Layout Considerations y T-52-33-43 PC Board Considerations Device Decoupling For optimum performance of the Bt481/482, proper For optimum performance, all capacitors should be CMOS RAMDAC layout techniques should be stud- located as close as possible to the device, and the ied in the Bt451/7/8 Evaluation Module Operation _shortest possible leads (consistent with reliable opera- and Measurements, Application Note (AN-16), This tion) should be used to reduce the lead inductance. | application note can be found in Brooktree's Applica- Chip capacitors are recommended for minimum lead tions Handbook. inductance. Radial lead ceramic capacitors may be ; The layout should be optimized for lowest noise on _ substituted for chip capacitors and are better than ax- the Br481/482 power and ground planes by providing _ ial lead capacitors for self-resonance, Values are cho- g00d decoupling. The trace length between groups of sen to have self-resonance above the pixel clock. VAA and GND pins should be as short as possible to i minimize inductive ringing. Power Supply Decoupling A well-designed power distribution network is crit- . . ical to eliminating digital switching noise. The ees power supply Secoupling Performance is ob- ground plane must provide a low-impedance return “ined with a 0.1 UF ceramic capacitor, decoupling amet prov! ‘tha min. ¢ach of the two groups of VAA pins to GND. For path for the digital circuits, A PC board with a mini- tion above 20 Mite at » GN mum of four layers is recommended, with layers 1 yisraton apawe 78 MHZ: a O. UF capacitor in a v1 (top) and 4 (bottom) for signals and layers 2 and3for © With a 0.01 UF chip capacitor is recommended. wer and ground. The capacitors should be placed as close as possible Po to the device VAA and GND pins and connected with short, wide traces. Component Placement The 10 uF capacitor shown in Figures 7-9 is for Components should be placed as close as possible to low-frequency power supply ripple; the 0.1 WF capac- the associated RAMDAC pin. Whenever possible, _itors are for high-frequency power supply noise components should be placed so traces can be con- _rejection. nected point to point. When a linear regulator is used, the power-up se- The optimum layout enables the Bt481/482 to be quence must be verified to prevent latchup, A linear located as close as possible to the power supply con- _ regulator is recommended to filter the analog power nector and the video output connector. supply if the power supply noise is greater than or equal to 200 mV. This is especially important when a Ground Planes switching power supply is used, and the switching n a frequency is close to the raster scan frequency. About rr optimum performance, @ communon digital and an- 10 percent of the power supply hum and ripple noise alog ground plane is recommended. less than | MHz will couple onto the analog outputs. Power Planes COMP Decoupling Separate digital and analog power planes are recom- a . mended. The digital power plane should provide iba 01 ph commie cerca a teat power to all digital logic on the PC board, and the an- ae tan era a ; ply noise will require a larger value. The COMP ca. alog power plane should provide power to all BY481/ itor must be as close as possible to the COMP and 482 power pins, VREF circuitry, and COMP and — Paitor § close a5 possible to & P ane VREF decoupling, There should be at least 1/8-ineh WA Pins. A surface-mount ceramic chip capacitor is between the digital power plane tnd the analo preferred for minimal lead inductance. Lead induc- power vine the digital power plane and the analog tance degrades the noise rejection of the circuit. The analog ower plane should be connected to the Hye tay has a ghosting pacblom. aden digital power plane (VCC) at a single point through a adh ied een snng problem, ad eH a ; capacitance in parallel with the COMP capacitor may ferrite bead, as illustrated in Figures 7-9. This bead fay should be located within 3 inches of the Bt481/482. Pp The bead provides resistance to switching currents, act- ing as a resistance at high frequencies. A low-resistance VREF Decoupling bead should be used, such as Ferroxcube 5659065-38, A 0.1 jWF ceramic capacitor should be used to decou- Fair-Rite 2743001111, or TDK BF45-4001. ple this input to GND. PC GRAPHICS 4-141

BROOKTREE CORP SbE D MM 2645595 0004272 ST4Y MEBRK Bt481/482 Brooktree’ alah a PC Board Layout Considerations (continued, y 7 d T-52-33-43 Digital Signal Interconnect ‘The digital inputs to the B1481/482 should be isolated as _sufficient to absorb reflections. The series or parallel much as possible from the analog outputs and other ana-_resistor values should be adjusted to provide the opti- log circuitry. Also, these input signals should not over- mum clock signal fidelity. lay the analog power plane or analog output signals. ‘Most of the noise on the analog outputs will be © MPU Control Signal Interfacing caused by excessive edge rates (less than 3 ns), over- . Shoot underhoot, and ingng on he digital inputs, TH BUBI/4ED uses the RD*, WR and RS lines ode The digital edge rates should not be faster than nec- amine ae areal ‘nay eae oor essary, as feedthrough noise is proportional to the digi- " S tal edge rates. Lower-speed applications will benefit MPU operation. When a VGA controller with edge rate from using lower-speed logic (3-5 ns edge rates) to re- control is used on these lines, a series termination ‘is not duce data-related noise on the analog outputs. necessary. In non-VGA controller application or in ap- ‘Transmission lines will mismatch if the lines do not _Plications where the MPU control signals are daisy match the source and destination impedance. This will chained, aseries termination, pul down resistors, of ad- degrade signal fidelity ifthe line length reflection time “onal edpacitinee 10 Brot shou access Prevent is greater than one fourth the signal edge time (refer to ‘itches that could canse improper MPU accesses. Brooktree Application Notes AN-11 and AN-12). Line termination or line-length reduction is the solution, Aalog Signal Interconnect For example, logic edge rates of 2 ns require line ‘The Bt481/482 should be located as close as possi- Jengths of less than 4 inches without use of termina- _le to the output connectors to minimize noise pickup tion. Ringing may be reduced by damping the line _and reflections caused by impedance mismatch. with a series resistor (30-300 9). The RS-select inputs The analog outputs are susceptible to crosstalk and RD*/WR¢ lines must be verified for proper levels from digital lines; digital traces must not be routed with no ringing, undershoot, or overshoot. Ringing on under or adjacent to the analog output traces. these lines can cause improper operation. To maximize the high-frequency power supply re- Radiation of digital signals can also be picked up by —_ jection, the video output signals should not overlay the the analog circuitry. This is prevented by reducing the analog power plane. digital edge rates (rise/fall time), minimizing ringing For maximum performance, the analog video output with damping resistors, and minimizing coupling impedance, cable impedance, and load impedance through PC board capacitance by routing the digital should be the same. The load resistor connection be- signals at a 90 degree angle to any analog signals. tween the video outputs and GND should be as close ‘The clock driver and all other digital devices must —_as_possible to the Bt481/482 to minimize reflections. be adequately decoupled to prevent noise generated by Unused analog outputs should be connected to GND. the digital devices from coupling into the analog Analog output video edges exceeding the CRT circuitry. monitor bandwidth can be reflected, producing cable- . length dependent ghosts. Simple pulse filters can re- Clock Interfacing duce high-frequency energy, reducing EMI and noise. ‘The Br481/482 requires a pixel clock with monotonic The filter impedance must match the line impedance. clock edges for proper operation. Impedance mis- , match on the pixel clock Tine will induce reflections | Analog Output Protection on the pixel clock, which may cause erratic operation. The ‘Bt481/482 analog output should be protected The Pixel Clock Pulse Width High Time and Pixel against high-energy discharges, such as those from Clock Pulse Width Low Time minimum specifications monitor arc-over or from hot-switching AC-coupled (see the AC Characteristics section) must not be vio- monitors. lated, or erratic operation can occur. The diode protection circuit shown in Figures 7-9 ‘The pixel clock line must be terminated to prevent _can prevent latchup under severe discharge conditions impedance mismatch. A series termination of 33-68 2 without adversely degrading analog transition times. placed at the pixel clock driver may be used, or a par- © The _1N4148/9 parts are low-capacitance, fast- allel termination may be used at the pixel clock input _ switching diodes, which are also available in multiple- to the RAMDAC. A parallel termination of 220 2 to device packages (FSA2SOX or FSA270X) or surface- VCC and 330 Q to ground will provide a Thevinen mountable pairs (BAV99 or MMBD7001). equivalent of a 110 Q termination, which is normally 4-142 SECTION 4

Note: Each pair of device VAA and GND pins must be separately decoupled. Figure 7. Typical Connection Diagram and Parts List (Internal Voltage Reference).

Note: Each pair of device VAA and GND pins must be separately decoupled. fed 10 pF capacitor Mallory CSR13G106KM. will not affect the performance of the Bt481/482. Figure 8. Typical Connection Diagram and Parts List (External Voltage Reference).

Note: Each pair of device VAA and GND pins must be separately decoupled. will not affect the performance of the Bt481/482. Figure 9. Typical Connection Diagram and Parts List (External Current Reference).

BROOKTREE CORP SLE D MM@ Ub45595 OO0427L LYT M@BRK Bt481/482 Brookiree* aoe a

Application Information

; T-52-33-43 Using Multiple Devices ‘When multiple Bt482s are used, each Bt482 should _Latchup can be prevented by ensuring that all VAA. have its own power plane ferrite bead. If the internal pins are at the same potential and that the VAA sup- Pl Pi po reference is used, each Bt482 should use its own in- _ply voltage is applied before the signal pin voltages. temal reference. ‘The correct power-up sequence ensures that any sig- y Although the multiple Bt482s may be driven by a _nal pin voltage will never exceed the power supply common external voltage/current reference, higher _voltage by more than +0.5 V. performance may be obtained if each RAMDAC uses its own reference. This will reduce the amount of | Reference Selection color channel crosstalk and color palette interaction. F Bach BY482 must still have its own RSET resistor, A €Xtemal voltage reference provides about ten analog output termination resistors, power supply by- times the power supply rejection on the analog out- pass capacitors, COMP capacitor, and reference puts than does an external current reference. capacitors. Sleep Operation ESD and Latchup Considerations When the internal or extemal voltage reference is a . used, the DACs will be turned off during sleep mode. Correct ESD-sensitive handling procedures are re- When an external voltage reference is used, some quired to prevent device damage, which can produce internal circuitry will still be powered during the fymotoms of curstrople failure . erratic device be- tee mode, resulting in 0.5 mA of power supply cur- ‘All ei som ‘ sh mers " Fe held ‘ow until power to ent being drawn (above the rated supply current the de had hae settled to the specified t ence specifications). This unnecessary current drain can be vice ° Specilied tolerance. disabled by tuming off the external voltage reference DAC power decoupling networks with large time during sleep mode. constants should be avoided. They could delay VAA Teen ae eatemal current reference is used, the power f° the device, Fevite beads most be used only DACs are not tured off during the sleep mode. To atime consant delay that dees latch luctors cause disable the DACs during sleep mode, the current ref- ns ay P. erence must be tumed off. As shown in Figure 9, a ‘TTL signal and the 2N2222 transistor are used to dis- able the current reference during sleep mode. 4-146 SECTION 4

BROOKTREE CORP SbE D MM 1645595 0004277 086 MEBRK Brooktree* Bt481/482 oes CC eo ee Recommended Operating Conditions perating T-52-33-43 [ewe Pomme [om [om fm [| Power Supply VAA 85 and 75 MHz Parts 4.75 5.00 5.25 v Ambient Operating Temperature TA 0 +70 °c ‘Output Load RL 37.5 Q Voltage Reference Configuration Reference Voltage VREF 1.14 1.235 1.26 Vv Current Reference Configuration IREF Current IREF Standard RS-343A 3 8.39 -10 mA PS/2 Compatible 3 8.88 -10 mA Absolute Maximum Ratings [ree os me [oe [om VAA (measured to GND) 7.0 v Voltage on any Signal Pin (Note 1) GND-O.5 VAA +05 v Analog Output Short Circuit Duration to any Power Supply or Common Isc indefinite Ambient Operating Temperature TA -55 +125 °C Storage Temperature Ts 65 +150 °c Junction Temperature Tt +150 °C Vapor Phase Soldering TVSOL 220 °C (1 minute) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note 1: This device employs high impedance CMOS devices on all signal pins. It should be handled as an ESD-sensitive device. Voltage on any signal pin that exceeds the power supply voltage by more than +0.5 V can induce destructive latchup. PC GRAPHICS 4-147

BROOKTREE CORP SBE D MM 2645595 0004278 TL2 MMBRK Bt481/482 Brooktree’ eee DC Characteristics T-52-33-43 Resolution (each DAC) Bt482 and Br481 6 6 Bits Bt482 and Bt481 8 8 Bits Accuracy (each DAC) Integral Linearity Error Bt482 and Br481 #1 LSB Differential Linearity Error Bt482 and Br481 #1 LSB Gray-Scale Error 5 % Gray Scale Monotonicity guaranteed Coding Binary Digital Inputs Input High Voltage VI 20 VAA+05 v Input Low Voltage VIL GND-0.S 08 Vv Input High Current (Vin = 2.4 V) nH 1 BA Input Low Current (Vin = 0.4 V) IL -l1 pA Input Capacitance CIN pF (f= 1 MHz, Vin =2.4V) Digital Outputs Output High Voltage VOH 24 Vv (1OH =-400 nA) Output Low Voltage VOL Vv (OL = 3.2 mA) 3-State Current 10z pA ‘Output Capacitance CDOUT pF See test conditions on next page. 4-148 SECTION 4

BROOKTREE CORP SbE D MM 4645595 0004279 959 MEBRK Brooktree’ Bt481/482 aE EON DC Characteristics (continued, ICS (continued) T-52-33-43 a ee ‘Analog Outputs Gray Scale Current Range 20 mA Output Current White Level Relative to Black (Note 1) 16.74 17.62 18.50 mA Black Level Relative to Blank Setup = 7.5 IRE 0.95 1.44 1.90 mA Setup = 0 IRE 0 5 50 HA Blank Level Sync Enabled 6.29 7.62 8.96 mA Sync Disabled i) 5 50 pA Sync Level 0 5 50 BA LSB Size Bt482 and Bi481 69.1 pA DAC-to-DAC Matching 2 5 % Output Compliance voc 0S +15 v Output Impedance RAOUT 10 ka Output Capacitance CAOUT 18 pF (f= 1 MHz, IOUT =0 mA) Power Supply Rejection Ratio 0s %1% AVAA (Note 2) (COMP = 0.1 pF, f= 1 kHz) Test conditions to generate RS-343A standard video signals (unless otherwise specified); “Recommended Operating Conditions” and external voltage reference with RSET = 143 Q, VREF = 1.235 V, SETUP = 7.5 IRE, and 6*/8 pin = logical onc. As the above parameters are guaranteed over the full temperature range, temperature Coefficients are not specified or required. Typical values are based on nominal temperature, i.c., room temperature, and nominal voltage, i.e., 5 V. ‘When the intemal voltage reference is used, RSET may require adjustment to meet these limits. Also, the gray-scale output current (white level relative to black) will have a typical tolerance of +10 percent rather than the +5 Percent specified above. Note I: When the Bt482 or Bt48] is in the 6-bit mode, the output levels are approximately 1.5 percent lower than these values. Note 2: Guaranteed by characterization, not tested. PC GRAPHICS. 4-149

BROOKTREE CORP SE D M™ 2645595 0004280 b70 MMBRK Bt481/482 Brookiree* DUON AOE ae AC Characteristics T-52-33-43

85 MHz Devices 75 MHz Devices

[—Parareter balan] a Input Clk Rate Pseudo Color Fmax 85 75 MHz Input Clk Rate 15-, 16-bit dual-edge clk | Fmax 50 50 MHz Input Clk Rate 15-, 16-bit single-edge clk} Fmax 85 85 MHz Input Clk Rate 32-bit dual-edge clk Fmax 50 50 MHz Input Clk Rate 24-bit single-edge clk Fmax 85 85 Miz RSO-RS2 Setup Time RSO-RS2 Hold Time RD* Asserted to Data Bus Driven 3 2 RD* Asserted to Data Valid 4 RD* Negated to Data Bus 3-Stated 5 Read Data Hold Time 6 2 Write Data Setup Time 1 10 Write Data Hold Time 8 10 RD*, WR* Pulse Width Low 50 RD*, WR* Pulse Width High 6*pl3. Pixel and Control Setup Time i 3 Pixel and Control Hold Time 12 3 (Pseudo Color and 15-, 16-, and 24-bit Single-Edge Clock Mode) Pixel and Control Setup Time 2 | -1 -1 Pixel and Control Hold Time 21 7 7 (15-, 16-, and 32-bit Dual-Edge Clock Mode, LSB and MSB) Clock Cycle Time (p13) 13, 1.77 13,33 ns Pseudo Color Mode ‘Clock Pulse Width High Time (Note 1)) 14 4 4 ms Clock Pulse Width Low Time (Note 1) 1S 4 4 ns Single Edge True Color Modes Clock Pulse Width High Time (Note 1)! 14 5 5 ns ‘Clock Pulse Width Low Time (Note 1) 15 5.5 5.5 ns Clock Cycle Time (Dual-Edge Clock) 13 Clock Pulse Width High Time 14 Clock Pulse Width Low Time 15 ‘Analog Output Delay 16 30 30 ns Analog Output Rise/Fall Time 17 3 3 ns ‘Analog Output Settling Time (Note 2) 18 13 3B 28 ‘Clock and Data Feedthrough (Note 2) 30 -30 dB Glitch Impulse (Note 2) 5 75 pV - sec DAC-to-DAC Crosstalk -23 -23 dB Analog Output Skew 2 2 ns SENSE" Outpt se ae eee ee VAA Supply Current (Note 3) TAA normal operation 270 mA sleep enabled (Note 4) 2 2 mA 4-150 SECTION4

BROOKTREE CORP SbE D MM 1645595 0004281 507 MBBRK Brooktree’ Bt481/482 AC Characteristics (continued) ( 1) T-52-33-43 [remee—[ae [| oP [or [me [om Pipeline Delay Clocks Pseudo Color 7 7 7 7 7 7 5:5:5 Dual-Edge Clock Mode 7 7 7 7 7 7 5:6:5 Dual-Edge Clock Mode 7 7 7 7 7 7 8:8:8:8 Dual-Edge Clock Mode 8 8 8 8 8 8 5:5:5 Single-Edge Clock Mode 8 8 8 8 8 8 5:6:5 Single-Edge Clock Mode 8 8 8 8 8 8 8:8:8 Single-Edge Clock Mode 9 9 9 9 9 9 ‘Test conditions (unless otherwise specified): “Recommended Operating Conditions” and external voltage teference with RSET = 143 Q, VREF = 1.235 V, SETUP = 7.5 IRE, and 6*/8 pin = logical one. TTL input values are 0-3 V with input rise/fall times < 3 ns, measured between the 10-percent and 90-percent points. Timing reference points are at 50 percent for inputs and outputs unless otherwise noted. Analog output load < 10 pF, SENSE*, DO-D7 output load < 75 pF. See the timing notes on the following page. As the above parameters are guaranteed over the full temperature range, temperature coefficients are not specified or required. Typical values are based on nominal temperature, i.e., room temperature, and nominal voltage, i.e., 5 V. Note 1: These pulse widths are specified at VIL = 0.8 V for clock pulse width low and VIH = 2.0 V for clock pulse width high. Note 2: Clock and data feedthrough is a function of the number of edge rates, and the amount of overshoot and undershoot on the digital inputs. For this test, the digital inputs have a 1 kQ resistor to ground and are driven by 74HC logic. Settling time does not include clock and data feedthrough. “Glitch impulse includes clock and data feedthrough, and -3 dB test bandwidth = 2 x clock rate, Note 3: AtFmax. IAA (typ) at VAA = 5.0 V. IAA (max) at VAA (max). Note 4: External current or voltage reference disabled during sleep mode. Test Conditions: +25° to +70° C, pixel and data ports at 0.4 V. toe 0, ws, ns K val) ea ; be-prasab) ———_—Xpataourar-0 [> po. prem =e A MPU Read/Write Timing. PC GRAPHICS 4-151

BROOKTREE CORP SbE D MM 1645595 0004282 443 MMBRK Bt481/482 Brooktree* Timing Waveforms To : 52-334 3 14 15. : woe y 108,100,108 10R, 106, 108, ooo ey, sense Note 1: Output delay is measured from the 50-percent point of the rising edge of CLOCK to the ‘50-percent point of full-scale transition. Note 2: Settling time is measured from the 50-percent point of full-scale transition to the output remaining within +1 LSB. Note 3: Output rise/fall time is measured between the 10-percent and 90-percent points of full-scale transition. Video Input/Output Timing. 4-152 SECTION 4

BROOKTREE CORP SbE D MM 1645595 0004283 38T MBRK Brookiree’ Bt481/482 Traswnlenoa Walocccc Sere Timing Waveforms T-52-33-43 Bitoni Dboe _ a Lane 0,1, mn ao, Of + rere vexays ———_- | | | | true verars ———- 15-, 16-, and 32-bit-per-Pixel Timing, Dual-Edge Clock Mode. PC GRAPHICS 4-153

BROOKTREE CORP SbE D Ml 1645595 0004284 21b MBBRK Beagias2 CC Brocokctrve* Timing Waveforms T-52-33-43 wx \\ f \\_f \\_S*\\ Ss \\_ LAN wae Nf LL VL NS cxocx | _ ; t 15+, 16-, and 24-bit-per-Pixel Timing, ” Single-Edge Clock Mode. 4-154 — SECTION4

BROOKTREE CORP SbE D MM 1645595 004285 152 MEBRK Brooktree’ Bt481/482 IO

Ordering Information

Model Number Palette Speed Package Temperature RAM Range Bt48iKPI85 256 x 24 15x24 85 MHz 44-pin Plastic 0° to +70°C J-Lead Bt481KPI75 256 x24 | 15x24 75 MHz 44-pin Plastic 0° to +70°C J-Lead Bt482KPJ85. 256 x 24 15x24 85 MHz 44-pin Plastic 0° to +70°C J-Lead Bt482KPJ75 256 x 24 15x24 75 MHz 44-pin Plastic 0° to +70°C J-Lead PC GRAPHICS 4-155

Summary

256-Word Color Palette 15-, 16-, and 24-bit True Color Power-Down RAMDACs“ Rev. C

Description

256-Word Color Palette 15-, 16-, and 24-bit True Color Power-Down RAMDACs“ Rev. C

Source title BT471 Datasheet(PDF) - List of Unclassifed Manufacturers

BT471

Compare BT471 variants.

Read the List of Unclassifed Man... document online.