BSC042N03MSG

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Synchronous Buck Controller with Constant On Time and Valley Current Mode Data Sheet ADP1878/ADP1879 Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2011–2012 Analog Devices, Inc. All rights reserved.

FEATURES

Power input voltage range: 2.95 V to 20 V On-board bias regulator Minimum output voltage: 0.6 V 0.6 V reference voltage with ±1.0% accuracy Supports all N-channel MOSFET power stages Available in 300 kHz, 600 kHz, and 1.0 MHz options No current sense resistor required Power saving mode (PSM) for light loads (ADP1879 only) Resistor programmable current limit Power good with internal pull-up resistor Externally programmable soft start Thermal overload protection Short-circuit protection Standalone precision enable input Integrated bootstrap diode for high-side drive Starts into a precharged output Available in a 14-lead LFCSP_WD package

APPLICATIONS

Telecommunications and networking systems Mid-to-high end servers Set-top boxes DSP core power supplies TYPICAL APPLICATIONS CIRCUIT Figure 1. GENERAL DESCRIPTION The ADP1878/ADP1879 are versatile current-mode, synchronous step-down controllers. They provide superior transient response, optimal stability, and current-limit protection by using a constant on time, pseudo fixed frequency with a programmable current-limit, current control scheme. These devices offer optimum performance at low duty cycles by using a valley, current-mode control architec- ture allowing the ADP1878/ADP1879 to drive all N-channel power stages to regulate output voltages to as low as 0.6 V . The ADP1879 is the power saving mode (PSM) version of the device and is capable of pulse skipping to maintain output regulation while achieving improved system efficiency at light loads (see the ADP1879 Power Saving Mode (PSM) section for more information). Available in three frequency options (300 kHz, 600 kHz, and

1.0 MHz) plus the PSM option, the ADP1878/ADP1879 are well

suited for a wide range of applications that require a single input power supply range from 2.95 V to 20 V . Low voltage biasing is supplied via a 5 V internal low dropout regulator (LDO). In addition, soft start programmability is included to limit input inrush current from the input supply during startup and to provide reverse current protection during precharged output conditions. The low-side current sense, current gain scheme and integration of a boost diode, together with the PSM/forced pulse-width modulation (PWM) option, reduce the external device count and improve efficiency. The ADP1878/ADP1879 operate over the −40°C to +125°C junction temperature range and are available in a 14-lead LFCSP_WD package. Figure 2. ADP1878/ADP1879 Efficiency vs. Load Current (VOUT = 1.8 V, 300 kHz)

ADP1878/ADP1879 Data Sheet Rev. A | Page 2 of 40 TABLE OF CONTENTS

REVISION HISTORY

6/12—Rev. 0 to Rev. A 7/11—Revision 0: Initial Version

Data Sheet ADP1878/ADP1879 Rev. A | Page 3 of 40 SPECIFICATIONS All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). VREG = 5 V , BST − SW = VREG − VRECT_DROP (see Figure 40 to Figure 42). VIN = 12 V . The specifications are valid for TJ = −40°C to +125°C, unless otherwise specified. Table 1. Parameter Symbol Test Conditions/Comments Min Typ Max Unit POWER SUPPLY CHARACTERISTICS High Input Voltage Range VIN C VIN = 22 μF(25 V rating) right at Pin 1 to PGND (Pin 11) ADP1878ACPZ-0.3-R7/ADP1879ACPZ-0.3-R7 (300 kHz) 2.95 12 20 V ADP1878ACPZ-0.6-R7/ADP1879ACPZ-0.6-R7 (600 kHz) 2.95 12 20 V ADP1878ACPZ-1.0-R7/ADP1879ACPZ-1.0-R7 (1.0 MHz) 3.25 12 20 V Quiescent Current IQ_REG + IQ_BST FB = 1.5 V, no switching 1.1 mA Shutdown Current IREG,SD + IBST,SD EN < 600 mV 140 225 μA Undervoltage Lockout UVLO Rising VIN (see Figure 35 for temperature variation) 2.65 V UVLO Hysteresis Falling VIN from operational state 178 mV INTERNAL REGULATOR CHARACTERISTICS Do not load VREG externally because it is intended to bias internal circuitry only VREG Operational Output Voltage VREG C VREG = 4.7 μF to PGND, 0.22 μF to GND, VIN = 2.95 V to 20 V ADP1878ACPZ-0.3-R7/ADP1879ACPZ-0.3-R7 (300 kHz) 2.75 5 5.5 V ADP1878ACPZ-0.6-R7/ADP1879ACPZ-0.6-R7 (600 kHz) 2.75 5 5.5 V VREG Output in Regulation V IN = 7 V, 100 mA 4.82 4.981 5.16 V VIN = 12 V, 100 mA 4.83 4.982 5.16 V Load Regulation 0 mA to 100 mA, V IN = 7 V 32 mV 0 mA to 100 mA, V IN = 20 V 34 mV Line Regulation V IN = 7 V to 20 V, 20 mA 1.8 mV VIN = 7 V to 20 V, 100 mA 2.0 mV VIN to VREG Dropout Voltage 100 mA out of VREG, V IN ≤ 5 V 306 415 mV Short VREG to PGND V IN = 20 V 229 320 mA SOFT START Connect external capacitor from SS pin to GND, Soft Start Period Calculation C SS = 10 nF/ms 10 nF/ms ERROR AMPLIFER FB Regulation Voltage VFB T J = 25°C 600 mV TJ = −40°C to +85°C 596 600 604 mV TJ = −40°C to +125°C 594.2 600 605.8 mV Transconductance G m 320 496 670 μS FB Input Leakage Current I FB, LEAK FB = 0.6 V, EN = VREG 1 50 nA CURRENT SENSE AMPLIFIER GAIN Programming Resistor (RES) Value from RES to PGND RES = 47 kΩ ± 1% 2.7 3 3.3 V/V RES = 22 kΩ ± 1% 5.5 6 6.5 V/V RES = none 11 12 13 V/V RES = 100 kΩ ± 1% 22 24 26 V/V SWITCHING FREQUENCY Typical values measured at 50% time points with 0 nF at DRVH and DRVL; maximum values are guaranteed by bench evaluation1 ADP1878ACPZ-0.3-R7/ ADP1879ACPZ-0.3-R7 300 kHz On Time V IN = 5 V, VOUT = 2 V, TJ = 25°C 1120 1200 1345 ns Minimum On Time V IN = 20 V 145 190 ns Minimum Off Time 84% duty cycle (maximum) 340 400 ns

ADP1878/ADP1879 Data Sheet Rev. A | Page 4 of 40 Parameter Symbol Test Conditions/Comments Min Typ Max Unit ADP1878ACPZ-0.6-R7/ ADP1879ACPZ-0.6-R7 600 kHz On Time V IN = 5 V, VOUT = 2 V, TJ = 25°C 500 540 605 ns Minimum On Time V IN = 20 V, VOUT = 0.8 V 82 110 ns Minimum Off Time 65% duty cycle (maximum) 340 400 ns ADP1878ACPZ-1.0-R7/ ADP1879ACPZ-1.0-R7

1.0 MHz

On Time V IN = 5 V, VOUT = 2 V, TJ = 25°C 285 312 360 ns Minimum On Time V IN = 20 V 52 85 ns Minimum Off Time 45% duty cycle (maximum) 340 400 ns OUTPUT DRIVER CHARACTERISTICS High-Side Driver Output Source Resistance I SOURCE = 1.5 A, 100 ns, positive pulse (0 V to 5 V) 2.20 3 Ω Output Sink Resistance I SINK = 1.5 A, 100 ns, negative pulse (5 V to 0 V) 0.72 1 Ω Rise Time2 t r, DRVH BST − SW = 4.4 V, C IN = 4.3 nF (see Figure 59) 25 ns Fall Time2 t f, DRVH BST − SW = 4.4 V, C IN = 4.3 nF (see Figure 60) 11 ns Low-Side Driver Output Source Resistance I SOURCE = 1.5 A, 100 ns, positive pulse (0 V to 5 V) 1.5 2.2 Ω Output Sink Resistance I SINK = 1.5 A, 100 ns, negative pulse (5 V to 0 V) 0.7 1 Ω Rise Time2 t r,DRVL V REG = 5.0 V, CIN = 4.3 nF (see Figure 60) 18 ns Fall Time2 t f,DRVL V REG = 5.0 V, CIN = 4.3 nF (see Figure 59) 16 ns Propagation Delays DRVL Fall to DRVH Rise2 t tpdhDRVH BST − SW = 4.4 V (see Figure 59) 15.7 ns DRVH Fall to DRVL Rise2 t tpdhDRVL BST − SW = 4.4 V (see Figure 60) 16 ns SW Leakage Current ISWLEAK BST = 25 V, SW = 20 V, V REG = 5 V 110 μA Integrated Rectifier Channel Impedance I SINK = 10 mA 22.3 Ω PRECISION ENABLE THRESHOLD Logic High Level V IN = 2.9 V to 20 V, VREG = 2.75 V to 5.5 V 605 634 663 mV Enable Hysteresis V IN = 2.9 V to 20 V, VREG = 2.75 V to 5.5 V 31 mV COMP VOLTAGE COMP Clamp Low Voltage V COMP(LOW) Tie EN pin to VREG to enable device (2.75 V ≤ VREG ≤ 5.5 V) 0.47 V COMP Clamp High Voltage V COMP(HIGH) (2.75 V ≤ V REG ≤ 5.5 V) 2.55 V COMP Zero Current Threshold V COMP_ZCT (2.75 V ≤ V REG ≤ 5.5 V) 1.10 V THERMAL SHUTDOWN TTMSD Thermal Shutdown Threshold Rising temperature 155 °C Thermal Shutdown Hysteresis 15 °C CURRENT LIMIT Hiccup Current-Limit Timing COMP = 2.4 V 6 ms OVERVOLTAGE AND POWER- GOOD THRESHOLDS PGOOD FB Power-Good Threshold FB PGD VFB rising during system power up 542 566 mV FB Power-Good Hysteresis 34 55 mV FB Overvoltage Threshold FB OV V FB rising during overvoltage event, IPGOOD = 1 mA 691 710 mV FB Overvoltage Hysteresis 35 55 mV PGOOD Low Voltage During Sink V PGOOD IPGOOD = 1 mA 143 200 mV PGOOD Leakage Current PGOOD = 5 V 1 100 nA 1 The maximum specified values are with the closed loop measured at 10% to 90% time points (see Figure 59 and Figure 60), CGATE = 4.3 nF, and the high- and low-side MOSFETs being Infineon BSC042N03MS G. 2 Not automatic test equipment (ATE) tested.

soldered in a circuit board for surface-mount packages. convection is used to transfer heat to a 4-layer evaluation board. Table 3. Thermal Resistance

Figure 3. Pin Configuration Table 4. Pin Function Descriptions 1 VIN High-Side Input Voltage. Connect VIN to the drain of the high-side MOSFET. the Compensation Network section). 3 EN IC Enable. Connect EN to VREG to enable the IC. Wh en pulled down to AGND externally, EN disables the IC. 4 FB Noninverting Input of the Internal Error Amplifier. Th is is the node where the feedback resistor is connected. 6 RES Current Sense Gain Resistor (External). Connect a resistor between the RES pin and GND (Pin 5). 7 VREG Internal Regulator Supply Bias Voltage for the ADP1878/ADP1879 Controller (Includes the Output Gate Drivers). of 10 nF for every 1 ms of soft start delay. 9 PGOOD Open-Drain Power-Good Output. PGOOD sinks current when FB is out of regulation or during thermal shutdown. Connect a 3 kΩ resistor between PGOOD and VREG. Leave PGOOD unconnected if it is not used. 11 PGND Power Ground. Ground for the low-side gate driver and low-side N-channel MOSFET. 12 DRVH Drive Output for the External High-Side N-Channel MOSFET. 13 SW Switch Node Connection. between VREG and BST for increased gate drive capability. EP Exposed Pad. Connect the exposed pa d to the analog ground pin (GND).

1. CONNECT THE EXPOSED PAD TO THE

Figure 46. CCM Operation at Heavy Load, 12 A Figure 47. Load Transient Step—PSM Enabled, 12 A Figure 48. Positive Step During Heavy Load Transient Behavior—PSM Enabled, Figure 49. Negative Step During Heavy Load Transient Behavior—PSM Enabled,

12 A (See Figure 95 Application Circuit)

Figure 50. Load Transient Step—Forced PWM at Light Load, 12 A Figure 51. Positive Step During Heavy Load Transient Behavior—Forced PWM

Figure 64. ADP1878/ADP1879 Block Diagram

IN is the high voltage input. VOUT is the desired output voltage. Setting section and Figure 81). Figure 81. Peak Inductor Current vs. Valley Current Limit for 33%, 40%, and Table 8. Recommended Inductors a given positive load current step (ΔILOAD).

used, the available selection is limited to 22 μF maximum. Figure 82. Capacitance vs. DC Voltage Characteristics for Ceramic Capacitors capacitors to reduce the overall series resistance. for the RCOMP and CCOMP component values. series resistance of the output capacitors. Current-Limit Setting sections). ON is the channel impedance of the low-side MOSFET. The zero frequency is set to 1/4th of the crossover frequency.

and the source that starts channel conduction.  QG is the total gate charge.  CN1 is the input capacitance of the high-side switch.  CN2 is the input capacitance of the low-side switch.  Channel conduction loss (both of the MOSFETs).  Body diode conduction loss (low-side MOSFET).  Inductor loss (copper and core loss). to the power dissipated through MOSFET channel conduction. most of the switching period. during operation and the QGATE parameter of the external MOSFETs. upperFET is the input gate capacitance of the high-side MOSFET. ClowerFET is the input gate capacitance of the low-side MOSFET. IBIAS is the dc current flowing into the high- and low-side drivers. minus the rectifier drop (see Figure 83)). Figure 83. Internal Rectifier Voltage Drop vs. Switching Frequency the gate oxide edge overlap and the drain and source terminals. CTOTAL is the CGD + CGS of the external MOSFET. RGATE is the gate input resistance of the external MOSFET. continuing well into idle mode.

SW is the period per switching cycle. VF is the forward drop of the body diode during conduction. Figure 84. Body Diode Conduction Time vs. Low Voltage Input (VREG) core material, the flux swing, the frequency, and the core volume. minimal loss and negligible electromagnetic interference (EMI). stability and transient performance. low-side MOSFET (see the Layout Considerations section). RIPP is usually 1% of the minimum voltage input. ILOAD,MAX is the maximum load current. ESR is the equivalent series resistance rating of the input capacitor. exceed the maximum allowable junction temperature of 125°C. Dropout (LDO) Regulator section).

Data Sheet ADP1878/ADP1879 Rev. A | Page 29 of 40 The rise in package temperature (for a 14-lead LFCSP_WD) is TR = θJA × PDR(LOSS) = 30°C × 132.05 mW = 4.0°C Assuming a maximum ambient temperature environment of 85°C, which is below the maximum junction temperature of 125°C. DESIGN EXAMPLE The ADP1878/ADP1879 are easy to use, requiring only a few design criteria. For example, the example outlined in this section uses only four design criteria: VOUT = 1.8 V , ILOAD = 15 A (pulsing), VIN = 12 V (typical), and fSW = 300 kHz. Input Capacitor The maximum input voltage ripple is usually 1% of the minimum input voltage (11.8 V × 0.01 = 120 mV). VRIPP = 120 mV VMAX,RIPPLE = VRIPP − (ILOAD,MAX × ESR) = 120 mV − (15 A × 0.001) = 45 mV ൌ 15 A 4 ൈ 300 ൈ 10 ଷ ൈ 105 mV = 120 μF Choose five 22 μF ceramic capacitors. The overall ESR of five 22 μF ceramic capacitors is less than 1 mΩ. I RMS = ILOAD/2 = 7.5 A PCIN = (IRMS)2 × ESR = (7.5 A)2 × 1 mΩ = 56.25 mW Inductor Determining inductor ripple current amplitude: ௅ை஺஽ 3 ൌ5 A Then, calculating for the inductor value ை௎்൯ ை௎் ൌ 13.2 V – 1.8 V 5 V ൈ300ൈ10 ଷ ൈ 1.8 V 13.2 V = 1.03 μH The inductor peak current is approximately Therefore, an appropriate inductor selection is 1.0 μH with DCR = 3.3 mΩ (Würth Elektronik 7443552100) with a peak current handling of 20 A. ଶ = 0.003 × (15 A)2 = 675 mW Current-Limit Programming The valley current is approximately Assuming a low-side MOSFET RON of 4.5 mΩ and 13 A, as the valley current limit from Table 7 and Figure 71 indicate, a pro- gramming resistor (RES) of 100 kΩ corresponds to an ACS of 24 V/V . Choose a programmable resistor of RRES = 100 kΩ for a current sense gain of 24 V/V . Output Capacitor Assume that a load step of 15 A occurs at the output and no more than 5% output deviation is allowed from the steady state operating point. In this case, the advantage of the ADP1878 is that because the frequency is pseudo fixed, the converter is able to respond quickly because of the immediate, though temporary, increase in switching frequency. ΔV DROOP = 0.05 × 1.8 V = 90 mV Assuming the overall ESR of the output capacitor ranges from 5 mΩ to 10 mΩ, ௅ை஺஽ ൌ2ൈ 15 A 300ൈ10 ଷ ൈሺ90 mVሻ = 1.11 mF Therefore, an appropriate inductor selection is five 270 μF polymer capacitors with a combined ESR of 3.5 mΩ. Assuming an overshoot of 45 mV , determine if the output capacitor that was calculated previously is adequate ௅ை஺஽ ଶ ሻ ை௎்ሻଶሻ ሺ1.8െ45 mVሻଶ െሺ1.8ሻଶ = 1.4 mF Choose five 270 μF polymer capacitors. The rms current through the output capacitor is ோெௌ ൌ 1 2ൈ 1 ை௎்൯ ை௎் ൌ 1 ൈ 1 ሺ13.2 V – 1.8 Vሻ 1 μFൈ300ൈ103 ൈ 1.8 V 13.2 Vൌ1.49 A The power loss dissipated through the ESR of the output capacitor is PCOUT = (IRMS)2 × ESR = (1.5 A)2 × 1.4 mΩ = 3.15 mW

ADP1878/ADP1879 Data Sheet Rev. A | Page 30 of 40 Feedback Resistor Network Setup Choosing RB = 1 kΩ as an example. Calculate RT as follows: ் ൌ1 kΩൈ ሺ1.8 Vെ0.6 V ሻ

0.6 V ൌ2 k Ω

To calculate RCOMP, CCOMP, and CPAR, the transconductance parameter and the current sense gain variable are required. The transconductance parameter (Gm) is 500 μA/V , and the current sense loop gain is ஼ௌ ൌ 1 ൌ 1 where ACS and RON are taken from setting up the current limit (see the Programming Resistor (RES) Detect Circuit section and the Valley Current-Limit Setting section). The crossover frequency is 1/12th of the switching frequency: 300 kHz/12 = 25 kHz The zero frequency is 1/4th of the crossover frequency: 25 kHz/4 = 6.25 kHz ௓ாோை మ ை௎்ሻଶ ை௎்ሻଶ ை௎் ோாி ൈ 1 √25 kΩଶ ൅6.25 kΩଶ ൈ ඥ1ଶ ൅ሺ2πൈ25 kΩൈሺ ሺ1.8/15ሻ൅0.0035ሻൈ0.0011ሻ ଶ ඥ1ଶ ൅ሺ2πൈ25 kΩൈ0.0035ൈ0.0011ሻ ଶ 1.8 0.6ൈ 1 1.8 = 60.25 kΩ ௓ாோை ൌ 1 = 423 pF Loss Calculations Duty cycle = 1.8/12 V = 0.15 RON(N2) = 5.4 mΩ tBODY(LOSS) = 20 ns (body conduction time) VF = 0.84 V (MOSFET forward voltage) CIN = 3.3 nF (MOSFET gate input capacitance) QN1,N2 = 17 nC (total MOSFET gate charge) RGATE = 1.5 Ω (MOSFET gate input resistance) ଶ = 1.215 W ி ൈ2 = 20 ns × 300 × 103 × 15 A × 0.84 × 2 = 151.2 mW PSW(LOSS) = fSW × RGATE × CTOTAL × ILOAD × VIN × 2 = 300 × 103 × 1.5 Ω × 3.3 × 10−9 × 15 A × 12 × 2 = 534.6 mW P DR(LOSS) = [VDR × (fSWCupperFETVDR + IBIAS)] + [VREG × (fSWClowerFETVREG +IBIAS)] = 57.12 mW P DISS(LDO) = (VIN – VREG) × (fSW × CTOTAL × VREG + IBIAS) = 55.6 mW PCOUT = (IRMS)2 × ESR = (1.5 A)2 × 1.4 mΩ = 3.15 mW ) ( LOADLOSS DCR I DCRP   = 0.003 × (15 A)2 = 675 mW PCIN = (IRMS)2 × ESR = (7.5 A)2 × 1 mΩ = 56.25 mW PLOSS = PN1,N2 + PBODY(LOSS) + PSW + PDCR + PDR + PDISS(LDO) + PCOUT + PCIN = 1.215 W + 151.2 mW + 534.6 mW + 57.12 mW + 55.6 + 3.15 mW + 675 mW + 56.25 mW = 2.655 W

VREG = 5 V (float), and a maximum load current of 14 A. The ADP1879 models listed in Table 10 are the PSM versions of the device. Table 10. External Component Values 1 See the Inductor Selection section and Table 11.

Table 11. Recommended Inductors Table 12. Recommended MOSFETs

PWM jitter and electromagnetic interference. possibly replicated, descending down into the multiple layers. of Q1/Q2, the drain of Q3/Q4, and the inductor. Figure 86. ADP1878 High Current Evaluation Board Schematic (Blue Traces Indicate High Current Paths) Figure 87. Overall Layout of the ADP1878/ADP1879 High Current Evaluation Board

1 VIN 14BST

2 COMP 13SW

3 EN 12DRVH

5 GND 10DRVL

4 FB 11PGND

6 RES 9PGOOD

7 VREG 8SS

Figure 90. Layer 4 (Bottom Layer) of Evaluation Board across the VREG pin (Pin 7) and the GND pin (Pin 5). cause large dV/dt at the SW node. Q1/Q2 and the drain of Q3/Q4. terminal and the positive terminals of the output bulk capacitors. the event switches between D and 1 − D.

12 A, 300 kHz HIGH CURRENT APPLICATION CIRCUIT

Figure 93. Application Circuit for 12 V Input, 1.8 V Output, 12 A, 300 kHz (Q2/Q4 No Connect)

5.5 V INPUT, 600 kHz CURRENT APPLICATION CIRCUIT

Figure 94. Application Circuit for 5.5 V Input, 2.5 V Output, 12 A, 600 kHz (Q2/Q4 No Connect)

Figure 95. Application Circuit for 13 V Input, 1.8 V Output, 12 A, 300 kHz (Q2/Q4 No Connect)

Figure 96. 14-Lead Lead Frame Chip Scale Package [LFCSP_WD]

0.05 MAX

0.02 NOM

0.15 REF

0.50 BSC

0.20 MIN

ADP1878/ADP1879 Data Sheet Rev. A | Page 40 of 40 ORDERING GUIDE Model1 Temperature Range Package Description Package Option ADP1878ACPZ-0.3-R7 −40°C to +125°C 14-Lead Frame Chip Scale Package [LFCSP_WD] CP-14-2 ADP1878ACPZ-0.6-R7 −40°C to +125°C 14-Lead Frame Chip Scale Package [LFCSP_WD] CP-14-2 ADP1878ACPZ-1.0-R7 −40°C to +125°C 14-Lead Frame Chip Scale Package [LFCSP_WD] CP-14-2 ADP1878-0.3-EVALZ Evaluation Board ADP1878-0.6-EVALZ Evaluation Board ADP1878-1.0-EVALZ Evaluation Board ADP1879ACPZ-0.3-R7 −40°C to +125°C 14-Lead Frame Chip Scale Package [LFCSP_WD] CP-14-2 ADP1879ACPZ-0.6-R7 −40°C to +125°C 14-Lead Frame Chip Scale Package [LFCSP_WD] CP-14-2 ADP1879ACPZ-1.0-R7 −40°C to +125°C 14-Lead Frame Chip Scale Package [LFCSP_WD] CP-14-2 ADP1879-0.3-EVALZ Evaluation Board ADP1879-0.6-EVALZ Evaluation Board ADP1879-1.0-EVALZ Evaluation Board 1 Z = RoHS Compliant Part. ©2011–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09441-0-6/12(A) www.analog.com/ADP1878/ADP1879