BF998; BF998R Silicon N-channel dual-gate MOS-FETs
Document overview
- Manufacturer or author: NXP Semiconductors
- PDF pages: 15
Technical content
Supersedes data of April 1991
1996 Aug 01
BF998; BF998R Silicon N-channel dual-gate MOS-FETs
1996 Aug 01 2
NXP Semiconductors Product specification Silicon N-channel dual-gate MOS-FETs BF998; BF998R
FEATURES
Short channel transistor with high forward transfer admittance to input capacitance ratio Low noise gain controlled amplifier up to 1 GHz.
APPLICATIONS
VHF and UHF applications with 12 V supply voltage, such as television tuners and professional communications equipment.
DESCRIPTION
Depletion type field effect transistor in a plastic microminiature SOT143B or SOT143R package with source and substrate interconnected. The transistors are protected against excessive input voltage surges by integrated back-to-back diodes between gates and source. PINNING CAUTION The device is supplied in an antistatic package. The gate-source input must be protected against static discharge during transport or handling. PIN SYMBOL DESCRIPTION 1s , b s o u r c e 2 d drain 2 gate 2 4g 1 gate 1 Fig.1 Simplified outline (SOT143B) and symbol; BF998. Marking code: MOp. handbook, halfpage s,b d 2 1 Top view MAM039 handbook, halfpage s,b d MAM040 1 2 Top view Fig.2 Simplified outline (SOT143R) and symbol; BF998R. Marking code: MOp. QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS TYP. MAX. UNIT VDS drain-source voltage 12 V ID drain current 30 mA Ptot total power dissipation 200 mW yfs forward transfer admittance 24 mS Cig1-s input capacitance at gate 1 2.1 pF Crs reverse transfer capacitance f = 1 MHz 25 fF F noise figure f = 800 MHz 1 dB Tj operating junction temperature 150 C
1996 Aug 01 3
NXP Semiconductors Product specification Silicon N-channel dual-gate MOS-FETs BF998; BF998R LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). Notes 1. Device mounted on a ceramic substrate, 8 mm 10 mm 0.7 mm. 2. Device mounted on a printed-circuit board. SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VDS drain-source voltage 12 V ID drain current 30 mA IG1 gate 1 current 10 mA IG2 gate 2 current 10 mA Ptot total power dissipation; BF998 up to T amb =6 0 C; see Fig.3; note 1 200 mW up to Tamb =5 0 C; see Fig.3; note 2 200 mW Ptot total power dissipation; BF998R up to T amb =5 0 C; see Fig.4; note 1 200 mW Tstg storage temperature 65 +150 C Tj operating junction temperature 150 C Fig.3 Power derating curves; BF998. handbook, halfpage 100 0 200100 200 (mW) Ptot max (1)(2) MLA198 Tamb ( C)o (1) Ceramic substrate. (2) Printed-circuit board. Fig.4 Power derating curve; BF998R. handbook, halfpage 100 0 200100 200 (mW) Ptot max MGA002 Tamb (°C)
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NXP Semiconductors Product specification Silicon N-channel dual-gate MOS-FETs BF998; BF998R THERMAL CHARACTERISTICS Notes 1. Device mounted on a ceramic substrate, 8 mm 10 mm 0.7 mm. 2. Device mounted on a printed-circuit board. STATIC CHARACTERISTICS Tj =2 5 C; unless otherwise specified. Note 1. Measured under pulse condition. DYNAMIC CHARACTERISTICS Common source; Tamb =2 5 C; VDS =8V ; VG2-S =4V ; ID =1 0m A . SYMBOL PARAMETER CONDITIONS VALUE UNIT Rth j-a thermal resistance from junction to ambient in free air; BF998 note 1 460 K/W note 2 500 K/W Rth j-a thermal resistance from junction to ambient in free air; BF998R note 1 500 K/W SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT V(BR)G1-SS gate 1-source breakdown voltage V G2-S =V DS =0 ; IG1-SS = 10 mA 6 20 V V(BR)G2-SS gate 2-source breakdown voltage V G1-S =V DS =0 ; IG2-SS = 10 mA 6 20 V V(P)G1-S gate 1-source cut-off voltage V G2-S =4V ; VDS =8V ; ID =2 0 A 2.0 V V(P)G2-S gate 2-source cut-off voltage V G1-S =0 ; VDS =8V ; ID =2 0 A 1.5 V IDSS drain-source current VG2-S =4V ; VDS =8V ; VG1-S =0 ; n o t e1 2 1 8 m A IG1-SS gate 1 cut-off current VG2-S =V DS =0 ; VG1-S = 5V 50 nA IG2-SS gate 2 cut-off current VG1-S =V DS =0 ; VG2-S = 5V 50 nA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT yfs forward transfer admittance f = 1 kHz 21 24 mS Cig1-s input capacitance at gate 1 f = 1 MHz 2.1 2.5 pF Cig2-s input capacitance at gate 2 f = 1 MHz 1.2 pF Cos output capacitance f = 1 MHz 1.05 pF Crs reverse transfer capacitance f = 1 MHz 25 fF F noise figure f = 200 MHz; G S =2m S ; BS =B Sopt 0.6 dB f=8 0 0M H z ; GS = 3.3 mS; BS =B Sopt 1.0 dB
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NXP Semiconductors Product specification Silicon N-channel dual-gate MOS-FETs BF998; BF998R Fig.5 Output characteristics; typical values. handbook, halfpage 01 0 MGE813 2468 VDS (V) ID (mA) 0.4 V 0.3 V 0.2 V 0.1 V 0 V −0.5 V −0.4 V −0.3 V −0.2 V −0.1 V VG1-S = VG2-S =4V ; Tamb =2 5 C. Fig.6 Transfer characteristics; typical values. handbook, halfpage −11 MGE815 3 V 2 V 1 V 0 V VG2-S = 4 V VG1 (V) ID (mA) VDS =8V ; Tamb =2 5 C. Fig.7 Drain current as a function of gate 1 voltage; typical values. handbook, halfpage −1600 −400−800−1200 400 MGE814 max typ min VG1 (mV) ID (mA) VDS =8V ; VG2-S =4V ; Tamb =2 5 C. Fig.8 Forward transfer admittance as a function of drain current; typical values. handbook, halfpage 02 0 MGE811 161284 ID (mA) 0.5 V 4 V 1 V 2 V 3 V VG2-S = 0 V |yfs| (mS) VDS =8V ; Tamb =2 5 C.
1996 Aug 01 6
NXP Semiconductors Product specification Silicon N-channel dual-gate MOS-FETs BF998; BF998R Fig.9 Forward transfer admittance as a function of gate 1 voltage; typical values. VDS =8V ; Tamb =2 5 C. handbook, halfpage −11 MGE812 VG1 (V) 0 V 1 V 2 V 3 V VG2-S = 4 V|yfs| (mS) Fig.10 Output capacitance as a function of drain-source voltage; typical values. handbook, halfpage 41 4 1.5 1.0 1.1 1.2 1.3 1.4 MGE810 Cos (pF) 6 8 10 12 VDS (V) 12 mA 10 mA 8 mA VG2-S =4V ; f=1M H z ; Tamb =2 5 C. Fig.11 Gate 1 input capacitance as a function of gate 1-source voltage; typical values. handbook, halfpage −2.4 −1.6 −0.8 0.8 MGE809 2.1 1.9 1.7 2.3 1.5 1.3 Cis (pF) VG1-S (V) VDS =8V ; VG2-S = 4 V; f = 1 MHz; Tamb =2 5 C. Fig.12 Gate 1 input capacitance as a function of gate 2-source voltage; typical values. handbook, halfpage 642 Cis (pF) 2.4 2.3 2.1 2.0 2.2 MBH479 VG2−S (V) VDS =8V ; VG1-S = 0 V; f = 1 MHz; Tamb =2 5 C.
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NXP Semiconductors Product specification Silicon N-channel dual-gate MOS-FETs BF998; BF998R Fig.13 Input admittance as a function of the frequency; typical values. VDS =8V ; VG2-S =4V ; ID =1 0m A ; Tamb =2 5 C. 103 MGC466 10210 10 2 10 1 y is (mS) f (MHz) bis gis Fig.14 Reverse transfer admittance and phase as a function of frequency; typical values. VDS =8V ; VG2-S =4V ; ID =1 0m A ; Tamb =2 5 C. 103 MGC467 10210 10 3 10 2 y rs 10 3 (μS) f (MHz) rs yrs (deg) rsϕ ϕ Fig.15 Forward transfer admittance and phase as a function of frequency; typical values. VDS =8V ; VG2-S =4V ; ID =1 0m A ; Tamb =2 5 C. 103 MGC468 10210 10 2 y fs (mS) y fs f (MHz) (deg) fs fsϕ ϕ Fig.16 Output admittance as a function of the frequency; typical values. VDS =8V ; VG2-S =4V ; ID =1 0m A ; Tamb =2 5 C. 103 MGC469 10210 10 1 10 2 yos (mS) f (MHz) bos gos
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NXP Semiconductors Product specification Silicon N-channel dual-gate MOS-FETs BF998; BF998R handbook, full pagewidth MGE802 330 kΩ 1.8 kΩ 360 Ω 100 kΩ 140 kΩ 1 nF 1 nF 47 μF 20 μH 1 nF 10 pF BB405330 kΩ 1 nF 1 nF Vtun output 50 Ω output 5.5 pF 50 Ω input VDD VDD Vagc47 kΩ 1 nF 1 nF 1 nF 1 nF 15 pF BB405 Vtun input VDD =1 2V ; GS =2m S ; GL = 0.5 mS. L1 = 45 nH; 4 turns 0.8 mm copper wire, internal diameter 4 mm. L2 = 160 nH; 3 turns 0.8 mm copper wire, internal diameter 8 mm. Tapped at approximately half a turn from the cold side, to adjust G L = 0.5 mS. C1 adjusted for GS =2m S . Fig.17 Gain control test circuit at f = 200 MHz.
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NXP Semiconductors Product specification Silicon N-channel dual-gate MOS-FETs BF998; BF998R Fig.18 Gain control test circuit at f = 800 MHz. VDD =1 2V ; GS = 3.3 mS; GL =1m S . L1 = L4 = 200 nH; 11 turns 0.5 mm copper wire, without spacing, internal diameter 3 mm. L2 = 2 cm, silvered 0.8 mm copper wire, 4 mm above ground plane. L3 = 2 cm, silvered 0.5 mm copper wire, 4 mm above ground plane. handbook, full pagewidth MGE801 1.8 kΩ 360 Ω 100 kΩ 1 nF 1 nF 1 nF 50 Ω output 1 nF50 Ω input VDD VDD VDD Vagc270 kΩ 140 kΩ 1 nF 1 nF 1 nF 2 to 18 pF 0.5 to 3.5 pF 0.5 to 3.5 pF 4 to 40 pF
1996 Aug 01 10
NXP Semiconductors Product specification Silicon N-channel dual-gate MOS-FETs BF998; BF998R handbook, halfpage 01 0 −50 −40 −30 −20 −10 MGE808 ΔGtr (dB) 2468 Vagc (V) IDSS = max typ min Fig.19 Automatic gain control characteristics measured in circuit of Fig.17. VDD =1 2V ; f=2 0 0M H z ; Tamb =2 5 C. handbook, halfpage 01 0 −50 −40 −30 −20 −10 MGE807 ΔGtr (dB) 2468 Vagc (V) IDSS = max typ min Fig.20 Automatic gain control characteristics measured in circuit of Fig.18. VDD =1 2V ; f=8 0 0M H z ; Tamb =2 5 C.
1996 Aug 01 11
NXP Semiconductors Product specification Silicon N-channel dual-gate MOS-FETs BF998; BF998R PACKAGE OUTLINES UNIT A REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm 1.1 0.9 max 0.1 0.88 0.78 c 0.15 0.09 D 3.0 2.8 E 1.4 1.2 HE y w v Q 2.5 2.1 0.45 0.15 0.55 0.45 e 1.9 1.7 Lp 0.1 0.10.2 bp 0.48 0.38 DIMENSIONS (mm are the original dimensions) SOT143B 04-11-16 06-03-16 0 1 2 mm scale Plastic surface-mounted package; 4 leads SOT143B D HE E AB v M A X A Lp Q detail X c y w M e B bp
1996 Aug 01 12
NXP Semiconductors Product specification Silicon N-channel dual-gate MOS-FETs BF998; BF998R UNIT A REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm 1.1 0.9 max 0.1 0.88 0.78 c 0.15 0.09 D 3.0 2.8 E 1.4 1.2 HE y w v Q 2.5 2.1 0.55 0.25 0.45 0.25 e 1.9 1.7 Lp 0.1 0.10.2 bp 0.48 0.38 DIMENSIONS (mm are the original dimensions) SOT143R SC-61AA 04-11-16 06-03-16 0 1 2 mm scale Plastic surface-mounted package; reverse pinning; 4 leads SOT143R D HE E AB v M A X A Lp Q detail X c y w M e B bp
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NXP Semiconductors Product specification Silicon N-channel dual-gate MOS-FETs BF998; BF998R DATA SHEET STATUS Notes 1. Please consult the most recently issued document before initiating or completing a design. 2. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. DOCUMENT STATUS(1) PRODUCT STATUS(2) DEFINITION Objective data sheet Development This document contains data from the objective specification for product development. Preliminary data sheet Qualification This document contains data from the preliminary specification. Product data sheet Production This document contains the product specification. DEFINITIONS Product specification The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. DISCLAIMERS Limited warranty and liability Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products.
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NXP Semiconductors Product specification Silicon N-channel dual-gate MOS-FETs BF998; BF998R NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. Quick reference data The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Non-automotive qualified products Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications.
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