BF1205 Dual N-channel dual gate MOS-FET
Document overview
- Manufacturer or author: NXP Semiconductors
- PDF pages: 25
Technical content
Product specification 2003 Sep 30 DISCRETE SEMICONDUCTORS BF1205 Dual N-channel dual gate MOS-FET handbook, halfpage MBD128
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NXP Semiconductors Product specification Dual N-channel dual gate MOS-FET BF1205
FEATURES
Two low noise gain controlled amplifiers in a single package. One with a fully integrated bias and one with a partly integrated bias Internal switch reduces the number of external components Superior cross-modulation performance during AGC High forward transfer admittance High forward transfer admittance to input capacitance ratio.
APPLICATIONS
Gain controlled low noise amplifiers for VHF and UHF applications with 5 V supply voltage, such as digital and analog television tuners and professional communications equipment.
DESCRIPTION
The BF1205 is a combination of two equal dual gate MOS-FET amplifiers with shared source and gate 2 leads and an integrated switch. The integrated switch is operated by the gate 1 bias of amplifier b. The source and substrate are interconnected. Internal bias circuits enable DC stabilization and a very good cross-modulation performance during AGC. Integrated diodes between the gates and source protect against excessive input voltage surges. The transistor is encapsulated in SOT363 micro-miniature plastic package. PINNING - SOT363 PIN DESCRIPTION 1g a t e 1 ( a ) 2g a t e 2 3g a t e 1 ( b ) 4 drain (b) 5 source 6 drain (a) handbook, halfpage 123 654 Top view MGX429 AMP a d (a) s d (b) g1 (a) g2 g1 (b) AMP b Fig.1 Simplified outline and symbol. Marking code: L4-.
ORDERING INFORMATION
BF1205 Plastic surface mounted package; 6 leads SOT363
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NXP Semiconductors Product specification Dual N-channel dual gate MOS-FET BF1205 QUICK REFERENCE DATA LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134). Note 1. T s is the temperature at the soldering point of the source lead. THERMAL CHARACTERISTICS SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Per MOS-FET; unless otherwise specified VDS drain-source voltage 10 V ID drain current (DC) 30 mA Ptot total power dissipation Ts 102 C; temperature at the soldering point of the source lead 200 mW yfs forward transfer admittance I D = 1 2 m A 2 63 14 0 m S Cig1-ss input capacitance at gate 1 amp. a: f = 1 MHz 1.8 2.3 pF amp. b: f = 1 MHz 2.0 2.5 pF Crss reverse transfer capacitance f = 1 MHz 20 fF NF noise figure amp. a: f = 800 MHz 1.2 1.9 dB amp. b: f = 800 MHz 1.4 2.1 dB Xmod cross-modulation amp. a: input level for k = 1% at 40 dB AGC 98 102 dBV amp. b: input level for k = 1% at 40 dB AGC 100 105 dBV Tj junction temperature 150 C CAUTION This product is supplied in anti-static packing to prevent damage caused by electrostatic discharge during transport and handling. SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT Per MOS-FET; unless otherwise specified VDS drain-source voltage 10 V ID drain current (DC) 30 mA IG1 gate 1 current 10 mA IG2 gate 2 current 10 mA Ptot total power dissipation Ts 102 C; note 200 mW Tstg storage temperature 65 +150 C Tj junction temperature 150 C SYMBOL PARAMETER VALUE UNIT Rth j-s thermal resistance from junction to soldering point 240 K/W
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NXP Semiconductors Product specification Dual N-channel dual gate MOS-FET BF1205 handbook, halfpage 0 50 100 200 250 200 MGS359 150 150 100 Ts (°C) Ptot (mW) Fig.2 Power derating curve. STATIC CHARACTERISTICS Tj =2 5 C; per MOS-FET; unless otherwise specified. Note 1. R G1 connects gate 1 (b) to VGG = 0 V (see Fig.4). 2. R G1 connects gate 1 (b) to VGG = 5 V (see Fig.4). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT V(BR)DSS drain-source breakdown voltage amp. a: V G1-S =V G2-S =0V ; ID =1 0 A1 0 V amp. b: VG1-S =V G2-S =0V ; ID =1 0 A7 V V(BR)G1-SS gate-source breakdown voltage V GS =V DS =0V ; IG1-S =1 0m A 6 1 0 V V(BR)G2-SS gate-source breakdown voltage V GS =V DS =0V ; IG2-S =1 0m A 6 1 0 V V(F)S-G1 forward source-gate voltage V G2-S =V DS =0V ; IS-G1 =1 0m A 0 . 5 1 . 5 V V(F)S-G2 forward source-gate voltage V G1-S =V DS =0V ; IS-G2 =1 0m A 0 . 5 1 . 5 V VG1-S(th) gate-source threshold voltage V DS =5V ; VG2-S =4V ; ID =1 0 0A0 . 3 1 V VG2-S(th) gate-source threshold voltage V DS =5V ; VG1-S =5V ; ID =1 0 0A0 . 4 1 . 0 V IDSX drain-source current amp. a: VG2-S =4V ; VDS =5V ; RG1 =1 5 0k; note 1 81 6m A amp. b: VG2-S =4V ; VDS =5V ; RG1 =1 5 0k; note 2 81 6m A IG1-S gate cut-off current amp. a: VG1-S =5V ; VG2-S =V DS =0V 50 nA amp. b: VG1-S =5V ; VG2-S =V DS =0V 50 nA IG2-S gate cut-off current VG2-S =4V ; VG1-S =V DS =0V 20 nA
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NXP Semiconductors Product specification Dual N-channel dual gate MOS-FET BF1205 handbook, halfpage VGG (V) 2314 MGX430 ID (mA) (1) (2) (3) (4) (5) (6) Fig.3 Drain currents of MOS-FET a and b as functions of VGG (see Fig.4). handbook, halfpage MGX431VGG RG1 d (a) s d (b) g1 (a) g1 (b) Fig.4 Functional diagram VGG = 5 V: amplifier a is OFF; amplifier b is ON. VGG = 0 V: amplifier a is ON; amplifier b is OFF.
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NXP Semiconductors Product specification Dual N-channel dual gate MOS-FET BF1205 DYNAMIC CHARACTERISTICS AMPLIFIER a Common source; Tamb =2 5 C; VG2-S =4V ; VDS =5V ; ID = 12 mA; note 1 Notes 1. For the MOS-FET not in use: V G1-S (b) = 0 V; VDS (b) = 0 V. 2. Measured in Fig.13 test circuit. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT yfs forward transfer admittance T j =2 5 C2 6 3 1 4 0 m S Cig1-ss input capacitance at gate 1 f = 1 MHz 1.8 2.3 pF Cig2-ss input capacitance at gate 2 f = 1 MHz 3.3 pF Coss output capacitance f = 1 MHz 0.75 pF Crss reverse transfer capacitance f = 1 MHz 20 fF Gtr power gain f = 200 MHz; GS =2m S ; BS =B S(opt); GL =0 . 5m S ; BL =B L(opt) 31 35 39 dB f=4 0 0M H z ; GS =2m S ; BS =B S(opt); GL =1m S ; BL =B L(opt) 27 31 35 dB f=8 0 0M H z ; GS = 3.3 mS; BS =B S(opt); GL =1m S ; BL =B L(opt) 22 26 30 dB NF noise figure f = 10.7 MHz; G S =2 0m S ; BS =0 4 dB f=4 0 0M H z ; YS =Y S(opt) 1.1 1.7 dB f=8 0 0M H z ; YS =Y S(opt) 1.2 1.9 dB Xmod cross-modulation input level for k = 1% at 0 dB AGC; fw =5 0M H z ; funw = 60 MHz; note 2 90 dBV input level for k = 1% at 10 dB AGC; fw =5 0M H z ; funw = 60 MHz; note 2 90 dBV input level for k = 1% at 40 dB AGC; f w =5 0M H z ; funw = 60 MHz; note 2 98 102 dBV
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NXP Semiconductors Product specification Dual N-channel dual gate MOS-FET BF1205 GRAPHS FOR AMPLIFIER a handbook, halfpage 0.4 0.8 1.2 1.6 VG1-S (V) ID (mA) MGX432 (7) (6) (5)(4) (1) (2) (3) Fig.5 Transfer characteristics; typical values; amplifier a. VDS (a) = 5 V; VG1-S (b) = VDS (b) = 0 V; Tj =2 5 C. (1) V G2-S =4V . (3) V G2-S =3V . (5) V G2-S =2V . (7) V G2-S =1V . handbook, halfpage 01 0 VDS (V) ID (mA) 648 MGX433 (7) (6) (5) (4) (3) (2) (1) Fig.6 Output characteristics; typical values; amplifier a. VG2-S =4V ; VG1-S (b) = VDS (b) = 0 V; Tj =2 5 C.
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NXP Semiconductors Product specification Dual N-channel dual gate MOS-FET BF1205 handbook, halfpage ID (mA) 42 0 81 21 6 MGX434 yfs (mS) (5) (4) (3) (2)(1) Fig.7 Forward transfer admittance as a function of drain current; typical values; amplifier a. VDS (a) = 5 V; VG1-S (b) = VDS (b) = 0 V; Tj =2 5 C. (1) V G2-S =4V . (3) V G2-S =3V . (5) V G2-S =2V . handbook, halfpage 01 0 2 0 4 0 ID (b) (μA) ID (a) (mA) MGX435 Fig.8 Drain current as a fu nction of internal G1 current (current in pin drain (b) if MOS-FET (b) is switched off); typical values; amplifier a. VDS (a) = 5 V; VG2-S =4V ; VDS (b) = 5 V; VG1-S (b) = 0 V; Tj =2 5 C.
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NXP Semiconductors Product specification Dual N-channel dual gate MOS-FET BF1205 handbook, halfpage 246 VGG = VDS (V) ID (mA) MGX436 (5) (4) (3) (2)(1) Fig.9 Drain current as a function of gate 2 and drain supply voltage; typical values; amplifier a. VDS (a) = 5 V; VG1-S (b) = 0 V; Gate 1 (a) = open; Tj =2 5 C. (1) V DS (b) = 5 V. (3) V DS (b) = 4 V. (5) V DS (b) = 3 V. handbook, halfpage gain reduction (dB) 120 110 100 20 40 MGX437 Vunw (dBμV) Fig.10 Unwanted voltage for 1% cross-modulation as a function of gain reduction; typical values; amplifier a. VDS (a) = VDS (b) = 5 V; VG1-S (b) = 0 V; f w =5 0M H z ; f unw =6 0M H z ; Tamb =2 5 C; see Fig.13.
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NXP Semiconductors Product specification Dual N-channel dual gate MOS-FET BF1205 handbook, halfpage 012 4 VAGC (V) gain reduction (dB) MGX438 Fig.11 Gain reduction as a function of AGC voltage; typical values; amplifier a. VDS (a) = VDS (b) = 5 V; VG1-S (b) = 0 V; f = 50 MHz; see Fig.13. handbook, halfpage gain reduction (dB) 20 40 MGX439 ID (mA) Fig.12 Drain current as a function of gain reduction; typical values; amplifier a. VDS (a) = VDS (b) = 5 V; VG1-S (b) = 0 V; f = 50 MHz; Tamb =2 5 C; see Fig.13. handbook, full pagewidth 2.2 μHRG1 150 kΩ 10 kΩ RGEN 50 Ω Vi 2.2 μH MGX440 d (a) s d (b) g1 (a) g1 (b) 4.7 nF 4.7 nF 4.7 nF 4.7 nF 4.7 nF BF1205 4.7 nF RL 50 Ω 50 Ω 50 Ω VDS(a) 5 V VDS(b) 5 V VGG 0 V VAGC Fig.13 Cross-modulation test set-up for amplifier a.
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NXP Semiconductors Product specification Dual N-channel dual gate MOS-FET BF1205 handbook, halfpage MGX441 102 10 102 103 f (MHz) 10−2 10−1 yis (mS) gis bis Fig.14 Input admittance as a function of frequency; typical values; amplifier a. VDS (a) = 5 V; VG2-S (a) = 4 V; VDS (b) = VG1-S (b) = 0 V; ID (a) = 12 mA. handbook, halfpage MGX442 102 −102 −10 10 10 2 103 f (MHz) |yfs| (mS) ϕfs (deg) ϕfs |yfs| Fig.15 Forward transfer admittance and phase as a function of frequency; typical values; amplifier a. VDS (a) = 5 V; VG2-S (a) = 4 V; VDS (b) = VG1-S (b) = 0 V; ID (a) = 12 mA. handbook, halfpage MGX443 103 102 10 102 103 f (MHz) −102 −10 ϕrs (deg) −103 |yrs| (μS) ϕrs |yrs| Fig.16 Reverse transfer admittance and phase as a function of frequency; typical values; amplifier a. VDS (a) = 5 V; VG2-S (a) = 4 V; VDS (b) = VG1-S (b) = 0 V; ID (a) = 12 mA. handbook, halfpage MGX444 10 102 103 f (MHz) 10−2 10−1 yos (mS) gos bos Fig.17 Output admittance as a function of frequency; typical values; amplifier a. VDS (a) = 5 V; VG2-S (a) = 4 V; VDS (b) = VG1-S (b) = 0 V; ID (a) = 12 mA.
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NXP Semiconductors Product specification Dual N-channel dual gate MOS-FET BF1205 Scattering parameters: amplifier a VDS (a) = 5 V; VG2-S =4V ; ID (a) = 12 mA; VDS (b) = 0 V; VG-1S (b) = 0 V; Tamb =2 5 C Noise data VDS (a) = 5 V; VG2-S =4V ; ID (a) = 12 mA; VDS (b) = 0 V; VG-1S (b) = 0 V; Tamb =2 5 C DYNAMIC CHARACTERISTICS AMPLIFIER b Common source; T amb =2 5 C; VG2-S =4V ; VDS =5V ; ID =1 2m A f (MHz) s11 s21 s12 s22 MAGNITUDE (ratio) ANGLE (deg) MAGNITUDE (ratio) ANGLE (deg) MAGNITUDE (ratio) ANGLE (deg) MAGNITUDE (ratio) ANGLE (deg) f (MHz) F MIN (dB) GAMMA OPT Rn ()(ratio) (deg) 400 1.1 0.719 16.16 31.18 800 1.2 0.628 32.7 29.74 SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT yfs forward transfer admittance T j =2 5 C2 6 3 1 4 0 m S Cig1-ss input capacitance at gate 1 f = 1 MHz 2.0 2.5 pF Cig2-ss input capacitance at gate 2 f = 1 MHz 3.3 pF Coss output capacitance f = 1 MHz 0.85 pF Crss reverse transfer capacitance f = 1 MHz 20 fF Gtr power gain f = 200 MHz; GS =2m S ; BS =B S(opt); GL =0 . 5m S ; BL =B L(opt); note 1 30 34 38 dB f=4 0 0M H z ; GS =2m S ; BS =B S(opt); GL =1m S ; BL =B L(opt); note 1 27 31 35 dB f=8 0 0M H z ; GS = 3.3 mS; BS =B S(opt); GL =1m S ; BL =B L(opt); note 1 22 26 30 dB NF noise figure f = 10.7 MHz; G S =2 0m S ; BS =0 4 dB f=4 0 0M H z ; YS =Y S(opt) 1.3 1.9 dB f=8 0 0M H z ; YS =Y S(opt) 1.4 2.1 dB
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NXP Semiconductors Product specification Dual N-channel dual gate MOS-FET BF1205 Notes 1. For the MOS-FET not in use: V G1-S (a) = 0; VDS (a) = 0. 2. Measured in test circuit Fig.30. Xmod cross-modulation input level for k = 1% at 0 dB AGC; fw =5 0M H z ; funw = 60 MHz; note 2 90 dBV input level for k = 1% at 10 dB AGC; fw =5 0M H z ; funw = 60 MHz; note 2 92 dBV input level for k = 1% at 40 dB AGC; fw =5 0M H z ; funw = 60 MHz; note 2 100 105 dBV SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT GRAPHS FOR AMPLIFIER b handbook, halfpage 0.4 0.8 1.2 1.6 VG1-S (V) ID (mA) MGX445 (6) (7) (5)(4) (1) (2) (3) Fig.18 Transfer characteristics; typical values; amplifier b. VDS (b) = 5 V; VDS (a) = VG1-S (a) = 0 V; Tj =2 5 C. (1) V G2-S =4V . (3) V G2-S =3V . (5) V G2-S =2V . (7) V G2-S =1V . handbook, halfpage 01 0 VDS (V) ID (mA) 648 MGX446 (6) (7) (5) (4) (3) (2) (1) Fig.19 Output characteristics; typical values; amplifier b. VG2-S =4V ; VDS (a) = VG1-S (a) = 0 V; Tj =2 5 C.
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NXP Semiconductors Product specification Dual N-channel dual gate MOS-FET BF1205 handbook, halfpage 0 0.80.4 1.61.2 2 MGX447 VG1-S (V) IG1 (μA) (7) (5) (4) (6) (3)(2) (1) Fig.20 Gate 1 current as a function of gate 1 voltage; typical values; amplifier b. VDS (b) = 5 V; VDS (a) = VG1-S (a) = 0 V; Tj =2 5 C. (1) V G2-S =4V . (3) V G2-S =3V . (5) V G2-S =2V . (7) V G2-S =1V . handbook, halfpage ID (mA) 42 0 81 21 6 MGX448 yfs (mS) (5) (4) (3) (2)(1) Fig.21 Forward transfer admittance as a function of drain current; typical values; amplifier b. VDS (b) = 5 V; VDS (a) = VG1-S (a) = 0 V; Tj =2 5 C. (1) V G2-S =4V . (3) V G2-S =3V . (5) V G2-S =2V .
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NXP Semiconductors Product specification Dual N-channel dual gate MOS-FET BF1205 handbook, halfpage 05 0 10 20 30 40 IG1 (μA) ID (mA) MGX449 Fig.22 Drain current as a function of gate 1 current; typical values; amplifier b. VDS (b) = 5 V; VG2-S =4V ; VDS (a) = VG1-S (a) = 0 V; Tj =2 5 C. handbook, halfpage VGG (V) 23 4 MGX450 ID (mA) Fig.23 Drain current as a function of gate 1 supply voltage (VGG); typical values; amplifier b. VDS (b) = 5 V; VG2-S =4V ; VDS (a) = VG1-S (a) = 0 V; Tj =2 5 C; RG1 (b) = 150 k (connected to VGG); see Fig.4.
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NXP Semiconductors Product specification Dual N-channel dual gate MOS-FET BF1205 handbook, halfpage 0246 VGG = VDS (V) ID (mA) MGX451 (6) (7) (8) (5) (4) (3) (2) (1) Fig.24 Drain current as a function of gate 1 (V GG) and drain supply voltage; typical values; amplifier b. VG2-S =4V ; VDS (a) = VG1-S (a) = 0 V; Tj =2 5 C; RG1 (b) = 150 k (connected to VGG); see Fig.4. handbook, halfpage 0246 MGX452 VG2-S (V) ID (mA) (5) (4) (3) (2) (1) Fig.25 Drain current as a function of gate 2 voltage; typical values; amplifier b. VDS (b) = 5 V; VDS (a) = VG1-S (a) = 0 V; Tj =2 5 C; RG1 (b) = 150 k (connected to VGG); see Fig.4. (1) V GG =5 . 0V . (2) V GG =4 . 5V . (3) V GG =4 . 0V . (4) V GG =3 . 5V . (5) V GG =3 . 0V .
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NXP Semiconductors Product specification Dual N-channel dual gate MOS-FET BF1205 handbook, halfpage 0246 MGX453 VG2-S (V) IG1 (μA) (5) (4) (3) (2) (1) Fig.26 Gate 1 current as a function of gate 2 voltage; typical values; amplifier b. VDS (b) = 5 V; VDS (a) = VG1-S (a) = 0 V; Tj =2 5 C; RG1 (b) = 150 k (connected to VGG); see Fig.4. (1) V GG =5 . 0V . (2) V GG =4 . 5V . (3) V GG =4 . 0V . (4) V GG =3 . 5V . (5) V GG =3 . 0V . handbook, halfpage gain reduction (dB) 120 110 100 20 40 MGX454 Vunw (dBμV) Fig.27 Unwanted voltage for 1% cross-modulation as a function of gain reduction; typical values; amplifier b. VDS (b) = 5 V; VGG =5V ; VDS (a) = VG1-S (a) = 0 V; RG1 (b) = 150 k (connected to VGG); fw =5 0M H z ; funw =6 0M H z ; Tamb =2 5 C; see Fig.30.
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NXP Semiconductors Product specification Dual N-channel dual gate MOS-FET BF1205 handbook, halfpage 012 4 VAGC (V) gain reduction (dB) MGX455 Fig.28 Typical gain reduction as a function of AGC voltage; amplifier b. VDS (b) = 5 V; VGG =5V ; VDS (a) = VG1-S (a) = 0 V; RG1 (b) = 150 k (connected to VGG); f = 50 MHz; Tamb =2 5 C; see Fig.30. handbook, halfpage gain reduction (dB) 20 40 MGX456 ID (mA) Fig.29 Drain current as a function of gain reduction; typical values; amplifier b. VDS (b) = 5 V; VGG =5V ; VDS (a) = VG1-S (a) = 0 V; RG1 (b) = 150 k (connected to VGG); f = 50 MHz; Tamb =2 5 C; see Fig.30.
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NXP Semiconductors Product specification Dual N-channel dual gate MOS-FET BF1205 handbook, full pagewidth 2.2 μHRG1 150 kΩ 10 kΩ L1 2.2 μH MDB813 d (a) s d (b) g1 (a) g1 (b) 4.7 nF 4.7 nF 4.7 nF 4.7 nF BF1205 4.7 nF RL 50 Ω50 ΩRGEN 50 Ω Vi 50 Ω VDS(a) 5 V VDS(b) 5 V VGG 5 V VAGC Fig.30 Cross-modulation test set-up for amplifier b. handbook, halfpage MGX457 102 10 102 103 f (MHz) 10−1 yis (mS) gis bis Fig.31 Input admittance as a function of frequency; typical values; amplifier b. VDS (b) = 5 V; VG2-S =4V ; VDS (a) = VG1-S (a) = 0 V; ID (b)= 12 mA. handbook, halfpage MGX458 102 −102 −10 10 10 2 103 f (MHz) |yfs| (mS) ϕfs (deg) ϕfs |yfs| Fig.32 Forward transfer admittance and phase as a function of frequency; typical values; amplifier b. VDS (b) = 5 V; VG2-S =4V ; VDS (a) = VG1-S (a) = 0 V; ID (b) = 12 mA.
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NXP Semiconductors Product specification Dual N-channel dual gate MOS-FET BF1205 handbook, halfpage MGX459 103 102 10 102 103 f (MHz) −102 −10 ϕrs (deg) −103 |yrs| (μS) |yrs| ϕrs Fig.33 Reverse transfer admittance and phase as a function of frequency; typical values; amplifier b. VDS (b) = 5 V; VG2-S =4V ; VDS (a) = VG1-S (a) = 0 V; ID (b) = 12 mA. handbook, halfpage MGX460 10 102 103 f (MHz) 10−2 10−1 yos (mS) gos bos Fig.34 Output admittance as a function of frequency; typical values; amplifier b. VDS (b) = 5 V; VG2-S =4V ; VDS (a) = VG1-S (a) = 0 V; ID (b) = 12 mA.
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NXP Semiconductors Product specification Dual N-channel dual gate MOS-FET BF1205 Scattering parameters: amplifier b VDS (b) = 5 V; VG2-S =4V ; ID (b) = 12 mA; VDS (a) = 0 V; VG1-S (a) = 0 V; Tamb =2 5 C Noise data VDS (b) = 5 V; VG2-S =4V ; ID (b) = 12 mA; VDS (a) = 0 V; VG1-S (a) = 0 V; Tamb =2 5 C f (MHz) s11 s21 s12 s22 MAGNITUDE (ratio) ANGLE (deg) MAGNITUDE (ratio) ANGLE (deg) MAGNITUDE (ratio) ANGLE (deg) MAGNITUDE (ratio) ANGLE (deg) f (MHz) F MIN (dB) F MIN (dB) Rn () (ratio) (deg) 400 1.3 0.662 16.76 31.55 800 1.4 0.578 33.97 30.53
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NXP Semiconductors Product specification Dual N-channel dual gate MOS-FET BF1205 PACKAGE OUTLINE REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA SOT363 SC-88 wBMbp D e pin 1 index A Lp Q detail X HE E v M A AB y 0 1 2 mm scale c X 13 2 4 56 Plastic surface-mounted package; 6 leads SOT363 UNIT A1 max bp cD E e1 HE Lp Qy w v mm 0.1 0.30 0.20 2.2 1.8 0.25 0.10 1.35 1.15 0.65 e 1.3 2.2 2.0 0.2 0.10.2 DIMENSIONS (mm are the original dimensions) 0.45 0.15 0.25 0.15 A 1.1 0.8 04-11-08 06-03-16
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NXP Semiconductors Product specification Dual N-channel dual gate MOS-FET BF1205 DATA SHEET STATUS Notes 1. Please consult the most recently issued document before initiating or completing a design. 2. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. DOCUMENT STATUS(1) PRODUCT STATUS(2) DEFINITION Objective data sheet Development This document contains data from the objective specification for product development. Preliminary data sheet Qualification This document contains data from the preliminary specification. Product data sheet Production This document contains the product specification. DEFINITIONS Product specification The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. DISCLAIMERS Limited warranty and liability Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products.
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NXP Semiconductors Product specification Dual N-channel dual gate MOS-FET BF1205 NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. Quick reference data The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Non-automotive qualified products Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications.
provides High Performance Mixed Signal and Standard Product solutions that leverage its leading RF, Analog, Power Management, Interface, Security and Digital Processing expertise Contact information For additional information please visit: http://www.nxp.com For sales offices addresses send e-mail to: salesaddresses@nxp.com © NXP B.V. 2010 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Customer notification This data sheet was changed to reflect the new company name NXP Semiconductors, including new legal definitions and disclaimers. No changes were made to the technical content, except for package outline drawings which were updated to the latest version. Printed in The Netherlands R77/01/pp 25 Date of release: 2003 Sep 30