BD00GA3WEFJ-E2 ROHM
Document overview
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Technical content
○Product structure:Silicon monolithic integrated circuit ○ This product is not designed to have protection against radioactive rays. 1/20 TSZ02201-0R6R0A600180-1-2© 2012 ROHM Co., Ltd. All rights reserved. www.rohm.com TSZ22111・14・001 03.Dec.2012 Rev.002 300mA Variable / Fixed Output LDO Regulators BDxxGA3WEFJ / BDxxGA3WNUX
- General Description BDxxGA3WEFJ / BDxxGA3WNUX series devices are LDO regulators with output current capability of 0.3A. It has an output voltage accuracy of ±1%. Both fixed and variable output voltage devices are available. The variable output voltage can be varied from 1.5V to 13.0V using external resistors. Various fixed output voltage devices that do not use external resistors are also available. These LDO regulators are available in HTSOP-J8 / VSON008X2030 package and can be used in wide variety of digital appliances. It has bu ilt-in over current protection to protect the device when output is shorted, 0 μA shutdown mode, and thermal shutdown circuit to protect the device during thermal over-load conditions. These LDO regulators are usable with ceramic capacitors that enable a smaller layout and longer life.
- Package ( T y p . ) ( T y p . ) ( M a x . ) ●Features High accuracy reference voltage circuit Built-in Over Current Protection (OCP) Built-in Thermal Shut Down circuit (TSD) Zero µA shutdown mode
- Key Specifications Input power supply voltage range: 4.5V to 14.0V Output voltage range(Variable type): 1.5V to 13.0V Output current: 0.3A (Max.) Shutdown current: 0μA(Typ.) Operating temperature range: -25 ℃ to +85 ℃
- Typical Application Circuit HTSOP-J8 (EFJ) 4.90mm x 6.00mm x 1.00mm VSON008X2030 (NUX) 2.00mm x 3.00mm x 0.60mm HTSOP-J8 (EFJ) VSON008X2030 (NUX) VCC EN GND FIN VO VO VCC EN GND FIN R VO_S COUT CIN CIN, COUT : Ceramic Capacitor FB COUT CIN CIN, COUT : Ceramic Capacitor Variable type output voltage Fixed type output voltage Datasheet
BDxxGA3WEFJ / BDxxGA3WNUX Datasheet
- Ordering Information B D x x G A 3 W y y y - z z Part Number Output voltage 00:Variable 15:1.5V 18:1.8V 25:2.5V 30:3.0V 33:3.3V 50:5.0V 60:6.0V 70:7.0V 80:8.0V 90:9.0V J0:10.0V J2:12.0V Input Voltage G:15V Output Current A3:0.3A Shutdown Mode “W”:Included Package EFJ :HTSOP-J8 NUX:VSON008X2030 Packaging and forming specification E2:Emboss tape reel (HTSOP-J8) TR:Emboss tape reel (VSON008X2030)
- Line up *1 under development xx Output Voltage(V) Product Name 00 variable BD00GA3WEFJ-E2 BD00GA3WNUX-TR 15 1.5 BD15GA3WEFJ-E2 BD15GA3WNUX-TR*1 18 1.8 BD18GA3WEFJ-E2 BD18GA3WNUX-TR*1 25 2.5 BD25GA3WEFJ-E2 BD25GA3WNUX-TR*1 30 3.0 BD30GA3WEFJ-E2 BD30GA3WNUX-TR*1 33 3.3 BD33GA3WEFJ-E2 BD33GA3WNUX-TR*1 50 5.0 BD50GA3WEFJ-E2 BD50GA3WNUX-TR*1 60 6.0 BD60GA3WEFJ-E2 BD60GA3WNUX-TR*1 70 7.0 BD70GA3WEFJ-E2 BD70GA3WNUX-TR*1 80 8.0 BD80GA3WEFJ-E2 BD80GA3WNUX-TR*1 90 9.0 BD90GA3WEFJ-E2 BD90GA3WNUX-TR*1 J0 10.0 BDJ0GA3WEFJ-E2 BDJ0GA3WNUX-TR*1 J2 12.0 BDJ2GA3WEFJ-E2 BDJ2GA3WNUX-TR*1 2/20 TSZ02201-0R6R0A600180-1-2© 2012 ROHM Co., Ltd. All rights reserved. www.rohm.com TSZ22111・15・001 03.Dec.2012.Rev.002
- Block Diagram BD00GA3WEFJ (Variable type output voltage)
- Pin Configuration (TOP VIEW)
- Pin Description Pin No. Pin name Pin Function
1 V O Output pin
2 FB Feedback pin
3 GND GND pin
5 EN Enable pin
8 V CC Input pin
Figure 1. Block Diagram
- Block Diagram BDxxGA3WEFJ (Fixed type output voltage)
- Pin Configuration (TOP VIEW)
- Pin Description Pin No. Pin name Pin Function
2 V O_S Output voltage monitor pin
Figure 2. Block Diagram
BDxxGA3WEFJ / BDxxGA3WNUX Datasheet
- Absolute Maximum Ratings (Ta=25℃) Parameter Symbol Limits Unit Power supply voltage VCC 15.0 *2 V EN voltage VEN 15.0 V HTSOP-J8 Pd *3 2110 *3 Power dissipation VSON008X2030 Pd *4 1700 *4 mW Operating Temperature Range Topr -25 to +85 ℃ Storage Temperature Range Tstg -55 to +150 ℃ Junction Temperature Tjmax +150 ℃ *2 Not to exceed Pd *3 Reduced by 16.9mW/℃ for temperature above 25 ℃. (When mounted on a two-layer glass epoxy board with 70mm×70mm×1.6mm dimension)
- Recommended Operating Range (Ta=25℃) Parameter Symbol Min. Max. Unit Input power supply voltage VCC 4.5 14.0 V EN voltage VEN 0.0 14.0 V Output voltage setting range VO 1.5 13.0 V Output current IO 0.0 0.3 A
- Electrical Characteristics (Unless otherwise specified, Ta=25℃, EN=3V, VCC=6V, R1=43kΩ, R2=8.2kΩ) Parameter Symbol Min. Typ. Max. Unit Conditions Circuit current at shutdown mode ISD - 0 5 μA V EN=0V, OFF mode Bias current ICC - 600 900 μA Line regulation Reg.I -1 0.5 1 % VCC=( VO+0.9V )→14.0V Load regulation Reg IO -1.5 0.5 1.5 % IO=0→0.3A Minimum dropout Voltage VCO - 0.6 0.9 V VCC=5V, IO=0.3A Output reference voltage(Variable type) VFB 0.792 0.800 0.808 V IO=0A Output voltage(Fixed type) VO V O×0.99 VO V O×1.01 V I O=0A EN Low voltage VEN (Low) 0 - 0.8 V EN High voltage VEN (High) 2.4 - 14.0 V EN Bias current IEN 1 3 9 µA 5/20 TSZ02201-0R6R0A600180-1-2© 2012 ROHM Co., Ltd. All rights reserved. www.rohm.com TSZ22111・15・001 03.Dec.2012.Rev.002
12/20 TSZ02201-0R6R0A600180-1-2© 2012 ROHM Co., Ltd. All rights reserved. www.rohm.com TSZ22111・15・001 03.Dec.2012.Rev.002 BDxxGA3WEFJ / BDxxGA3WNUX Datasheet
- Power Dissipation ◎HTSOP-J8 ◎VSON008X2030 周囲温度:Ta [℃] Measurement condition: mounted on a ROHM board PCB size: 70mm × 70mm × 1.6mm ( P C B w i t h t h e r m a l v i a ) ・Solder the thermal pad to Ground ① IC only θj-a=249.5 ℃/W ② 1-layer (copper foil : 0mm×0mm) θj-a=153.2 ℃/W ③ 2-layer (copper foil : 15mm×15mm) θj-a=113.6 ℃/W ④ 2-layer (copper foil : 70mm×70mm) θj-a=59.2℃ /W ⑤ 4-layer (copper foil : 70mm×70mm) θj-a=33.3℃ /W Power Dissipation :Pd [W] 0 25 50 75 100 125 150 2.0 3.0 4.0 ①0.50W 1.0 ①0.50W ②0.82W ③1.10W ④2.11W ⑤3.76W Ambient Temperature : Ta [℃] Power Dissipation :Pd [W] 0 25 50 75 100 125 150 2.0 3.0 4.0 周囲温度:Ta [℃] 1.0 ①0.26W ②0.56W ③1.70W ④1.80W Ambient Temperature : Ta [℃] Measurement condition: mounted on a ROHM board PCB size: 114.3mm × 76.2mm × 1.6 mm ・Solder the thermal pad to Ground ① IC only θj-a=480.8 ℃/W ② 1-layer (copper foil : 0mm θj-a=223.2 ℃/W ③ 4-layer (copper foil : 5655mm2, 4th layer copper foil : thermal land) θj-a=73.5℃ /W ④ 4-layer (copper foil at 2nd, 3rd, 4th layers : 5655mm2) θj-a=69.4℃ /W
BDxxGA3WEFJ / BDxxGA3WNUX Datasheet As the power consumption increases above the maximum allowa ble power dissipation of the chip, the temperature across the chip also increases. When considering thermal design for the regulator, operation should be maintained within the following conditions: 1. Ambient temperature Ta can be not higher than 85℃. 2. Chip junction temperature (Tj) can be not higher than 150℃. Chip junction temperature can be determined as follows: Calculation based on ambient temperature (Ta) Tj=Ta+θj-a×W <Reference values> θj-a: HTSOP-J8 153.2℃/W 1-layer PCB(copper foil 0mm ×0mm) 113.6℃/W 2-layer PCB(copper foil 15mm ×15mm) 59.2℃/W 2-layer PCB(copper foil 70mm ×70mm) 33.3℃/W 4-layer PCB (copper foil 70mm ×70mm) PCB size: 70mm×70mm×1.6mm (PCB with thermal via) θj-a: VSON008X2030 223.2℃/W 1-layer PCB(copper foil 0mm 73.5℃/W 4-layer PCB (2 nd, 3rd copper foil 5655mm2, 4th layer copper foil : thermal land) 69.4℃/W 4-layer PCB (copper foil 5655mm 2) PCB size: 114.3mm×76.2mm ×1.6mm Most of the heat loss that occurs in the BDxxGA3WEFJ / BD xxGA3WNUX series is generated from the output Pch FET. Power loss is determined by the voltage drop across V CC-VO and the output current. Be sure to confirm the system’s input and output voltages, as well as the output cu rrent conditions in relation to the powe r dissipation characteristics of the V CC and VO in the design. Bearing in mind that the power dissipation may vary substantially depending on the PCB employed, it is important to consider PCB size based on thermal design and power dissipation characteristics of the chip with the PCB. Power consumption [W] = Input voltage (V CC) - Output voltage (VO) × IO(Ave) Example: Where VCC=5.0V, VO=3.3V, IO (Ave) = 0.1A, Power consumption [W] = 5.0V - 3.3V ×0.1A = 0 . 1 7 W 13/20 TSZ02201-0R6R0A600180-1-2© 2012 ROHM Co., Ltd. All rights reserved. www.rohm.com TSZ22111・15・001 03.Dec.2012.Rev.002
BDxxGA3WEFJ / BDxxGA3WNUX Datasheet
- Input and Output Capacitor It is recommended that a capacitor is placed near pins betwe en input pin and GND as well as output pin and GND. The input capacitor becomes more necessary when the power supply impedance is high or when the PCB trace has significant length. Also, as for a capacitor between output pin and GND, t he greater the capacitance, t he more stable the output will be depending on the load and line voltage variations. However, please check the actual functionality of this part by mounting on a board for the actual applicat ion. Ceramic capacitors usually have different thermal and equivalent series resistance characteristics and may degrade gradually over continued use. For additional details, please check with the manufacturer and select the best ceramic capacitor for your application. DC Bias Voltage [V] Ceramic capacitor capacity – DC bias characteristics (Characteristics example) -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 1 2 3 4 Rated Voltage:10V B1 characteristics Rated Voltage:4V X6S characteristics Capacitance Change [%] Rated Voltage:10V F characteristics Rated Voltage:6.3V B characteristics B characteristics Rated Voltage:10V
- Equivalent Series Resistance ESR (ceramic capacitor etc.) To prevent oscillation, please attach a capacitor between V O and GND. Capacitors usually have ESR (Equivalent Series Resistance). Operation will be stable in ESR-IO range shown in the right. Ceramic, tantalum and electronic capacitors have different ESR values, so please be sure to use a capacitor that operates in the stable operating region shown in the right. Finally, please evaluate in the actual application. CO=1μF ESR – IO characteristics 14/20 TSZ02201-0R6R0A600180-1-2© 2012 ROHM Co., Ltd. All rights reserved. www.rohm.com TSZ22111・15・001 03.Dec.2012.Rev.002
15/20 TSZ02201-0R6R0A600180-1-2© 2012 ROHM Co., Ltd. All rights reserved. www.rohm.com TSZ22111・15・001 03.Dec.2012.Rev.002 BDxxGA3WEFJ / BDxxGA3WNUX Datasheet
- Evaluation Board Circuit
- Evaluation Board Parts List
- Board Layout ・Input capacitor C IN connected to VCC (VIN) should be placed as close as possible to VCC(VIN) pin and use wide layout. Output capacitor COUT should also be placed as close as possible to IC pin. In case connected to inner layer GND plane, please use several through hole. ・FB pin has comparatively high impedance and can be affected by noise, so floating capacitance should be small as possible. Please be careful of this during layout. ・Please make GND pattern wide enough to handle the power dissipation of the chip. ・For output voltage setting (BD00GA3WEFJ / BD00GA3WNUX) Output voltage can be set by FB pin voltage(0.800V typ.)and external resistance R1, R2. (The use of resistors with R1+R2=1k to 90kΩ is recommended ) Designation Value Part No. Company Designation Value Part No. Company R1 43k Ω MCR01PZPZF4302 ROHM C4 ‐ ‐ ‐ R2 8.2k Ω MCR01PZPZF8201 ROHM C5 1µF CM105B105K16A KYOCERA C1 1µF CM105B105K16A KYOCERA C10 ‐ ‐ ‐ C2 ‐ ‐ ‐ U1 ‐ BDxxGA3WEFJ / BDxxGA3WNUX ROHM VO = VFB× R1+R2 N.C.GND FB N.C. N.C. VO VO
1 VCC
( VCC VIN ) CIN R1 R2 COUT
16/20 TSZ02201-0R6R0A600180-1-2© 2012 ROHM Co., Ltd. All rights reserved. www.rohm.com TSZ22111・15・001 03.Dec.2012.Rev.002 BDxxGA3WEFJ / BDxxGA3WNUX Datasheet
- I/O Equivalent Circuits (Variable type : BD00GA3WEFJ)
- I/O Equivalent Circuits (Fixed type : BDxxGA3WEFJ) 8pin (VCC) / 1pin (VO) 2pin (FB) 5pin (EN) 2pin (FB) 8pin (VCC) 1pin (VO) 5pin (EN) 1MΩ 2MΩ 8pin (VCC) / 1pin (VO) 2pin (VO_S) 5pin (EN) 2pin (VO_S) 8pin (VCC) 1pin (VO) 5pin (EN) 1MΩ 2MΩ
BDxxGA3WEFJ / BDxxGA3WNUX Datasheet
- Operational Notes (1). Absolute maximum ratings Operating the IC over the absolute maximum ratings may damage the IC. The damage can either be a short circuit between pins or an open circuit between pins. Therefore, it is important to consider circuit protection measures, such as adding a fuse, in case the IC is operated over the absolute maximum ratings. (2). Reverse connection of power supply Connecting the power supply in reverse polarity can damage the IC. Take precautions against reverse polarity when connecting the power supply, such as mounting an exter nal diode between the power supply and the IC’s power supply terminals. (3). Power supply lines Design the PCB layout pattern to provide low impedance ground and supply lines. Separate the ground and supply lines of the digital and analog blocks to prevent noise in the ground and supply lines of the digital block from affecting the analog block. Furthermore, connect a capacitor to groun d at all power supply pins. Consider the effect of temperature and aging on the capacitance value when using electrolytic capacitors. (4). Ground voltage The voltage of the ground pin must be the lo west voltage of all pins of the IC at all operating conditions. Ensure that no pins are at a voltage below the ground pin at any time, even during transient condition. (5). Thermal consideration Use a thermal design that allows for a sufficient margin by taking into account the permissible power dissipation (Pd) in actual operating conditions. Consider Pc that does not exceed Pd in actual operating conditions (Pc≥Pd) Package Power dissipation : Pd (W)=(Tjmax- Ta)/θja Power dissipation : Pc (W)=(Vcc -Vo)×Io+Vcc×Ib Tjmax : Maximum junction temperature=150℃, Ta : Peripheral temperature[℃] , θja : Thermal resistance of package-ambience[℃/W], Pd : Package Power dissipation [W], Pc : Power dissipation [W], Vcc : Input Voltage, Vo : Output Voltage, Io : Load, Ib : Bias Current (6). Short between pins and mounting errors Be careful when mounting the IC on printed circuit boards. The IC may be damaged if it is mounted in a wrong orientation or if pins are shorted together. Short circuit may be caused by conductive particles caught between the pins. (7). Operation under strong electromagnetic field Operating the IC in the presence of a strong electromagnetic field may cause the IC to malfunction. (8). Area of Safe Operation (ASO) Operate the IC such that th e output voltage, output current, and power dissipation are all within the Area of Safe Operation (ASO). (9). Thermal shutdown circuit The IC incorporates a built-in thermal shutdown circuit, which is designed to turn off the IC when the internal temperature of the IC reaches a specif ied value. It is not designed to protec t the IC from damage or guarantee its operation. Do not continue to operate the IC after this function is activated. Do not use the IC in conditions where this function will always be activated. TSD ON Temperature[℃] (typ.) Hysteresis Temperature [℃] (typ.) BDxxGA3WEFJ / BDxxGA3WNUX 175 15 (10). Testing on application boards When testing the IC on an application board, connecting a capacitor directly to a low-impedance output pin may subject the IC to stress. Always dischar ge capacitors completely after each process or step. The IC’s power supply should always be turned off completely before connecting or removing it from the test setup during the inspection 17/20 TSZ02201-0R6R0A600180-1-2© 2012 ROHM Co., Ltd. All rights reserved. www.rohm.com TSZ22111・15・001 03.Dec.2012.Rev.002
BDxxGA3WEFJ / BDxxGA3WNUX Datasheet process. To prevent damage from static discharge, ground the IC during assemb ly and use similar precautions during transport and storage. (11). Regarding input pins of the IC This monolithic IC contains P+ isolat ion and P substrate layers between adjac ent elements in order to keep them isolated. P-N junctions are formed at the intersection of t he P layers with the N layers of other elements, creating a parasitic diode or transistor. For example (refer to figure below): When GND > Pin A and GND > Pin B, the P-N j unction operates as a parasitic diode. When GND > Pin B, the P-N junction operates as a parasitic transistor. Parasitic diodes inevitably occur in the structure of the IC. The operation of parasitic diodes can result in mutual interference among circuits, operational faults, or physical damage. Therefore, conditions that cause these diodes to operate, such as applying a voltage lower than the GND voltage to an input pin (and thus to the P substrate) should be avoided. Resi stor Transistor (NPN) N N N P+ P + P P substrate GND Parasitic element Pin A N N P+ P+ P P substrate GND Parasitic element Pin B C B E N GND Pin A Pin B Other adjacent elements E B C GND Parasitic element Parasitic element Example of monolithic IC structure (12). Ground Wiring Pattern. When using both small-signal and large-cu rrent ground traces, the two ground traces should be routed separately but connected to a single ground at the reference point of the application board to avoid fluctuations in the small-signal ground caused by large currents. Also ensure that the ground traces of external components do not cause variations on the ground voltage. The power supply and ground lines must be as short and thick as possible to reduce line impedance. Status of this document The Japanese version of this document is t he official specification. If there are any differences in the translated version of this document then official version takes priority. 18/20 TSZ02201-0R6R0A600180-1-2© 2012 ROHM Co., Ltd. All rights reserved. www.rohm.com TSZ22111・15・001 03.Dec.2012.Rev.002
19/20 TSZ02201-0R6R0A600180-1-2© 2012 ROHM Co., Ltd. All rights reserved. www.rohm.com TSZ22111・15・001 03.Dec.2012.Rev.002 BDxxGA3WEFJ / BDxxGA3WNUX Datasheet
- Physical Dimension Tape and Reel Information
- Marking Diagram (Unit : mm) HTSOP-J8 0.08 S 0.08 M S 1.0MAX 0.85±0.05 1.27 0.08±0.08 0.42 +0.05 -0.04 1.05±0.2 0.65±0.15 4°+6° −4° 0.17 +0.05 -0.03 234 5 6 8 (MAX 5.25 include BURR) 0.545 (3.2) 4.9±0.1 6.0±0.2 (2.4) 3.9±0.1 1PIN MARK ∗ Order quantity needs to be multiple of the minimum quantity. <Tape and Reel information> Embossed carrier tapeTape Quantity Direction of feed The direction is the 1pin of product is at the upper left when you hold reel on the left hand and you pull out the tape on the right hand 2500pcs Direction of feed Reel 1pin HTSOP-J8 (TOP VIEW) xxGA3W Part Number Marking LOT Number 1PIN MARK VSON008X2030 (TOP VIEW) GA3 x x Part Number Marking LOT Number 1PIN MARK ∗ Order quantity needs to be multiple of the minimum quantity. <Tape and Reel information> Embossed carrier tapeTape Quantity Direction of feed The direction is the 1pin of product is at the upper right when you hold reel on the left hand and you pull out the tape on the right hand 4000pcs TR Direction of feed Reel 1pin (Unit : mm) VSON008X2030 1.4±0.1 0.25 1.5±0.1 0.5 0.3±0.1 0.25 +0.05 −0.04 C0.25 0.6MAX (0.12) 0.02 +0.03 −0.02 3.0±0.1 2.0±0.1 1PIN MARK 0.08 S S
BDxxGA3WEFJ / BDxxGA3WNUX Datasheet
- Revision History Date Revision Changes 20.July.2012 001 New Release 03.Dec.2012 002 Improved the English translation and added Package Lineup 20/20 TSZ02201-0R6R0A600180-1-2© 2012 ROHM Co., Ltd. All rights reserved. www.rohm.com TSZ22111・15・001 03.Dec.2012.Rev.002
Notice - Rev.004 © 2013 ROHM Co., Ltd. All rights reserved. Notice
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Notice - Rev.004 © 2013 ROHM Co., Ltd. All rights reserved.
- Precaution for Mounting / Circuit board design 1) When a highly active halogenous (chlori ne, bromine, etc.) flux is used, the residue of flux may negatively affect product performance and reliability. 2) In principle, the reflow soldering method must be used; if flow soldering method is preferred, please consult with the ROHM representative in advance. For details, please refer to ROHM Mounting specification
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