AV9110

AV9110 RENESAS

Document overview

• Manufacturer or author: Provided By www.digicamel.com(free datasheet download site)
• PDF pages: 12

Technical content

General Description Features AV9110 Block Diagram Serially Programmable Frequency Generator

• Complete user programmability of output frequency through serial input data port  On-chip Phase-Locked Loop for clock generation  Generates accurate frequencies up to 130 MHz  Tristate CMOS outputs  5 volt power supply  Low power CMOS technology  14-pin DIP or 150-mil SOIC  Very low jitter  Wide operating range VCO The A V9110 generates user specified clock frequencies using an externally generated input reference, such as 14.318 MHz or 10.00 MHz crystal connected between pins 1 and 14. Alternately, a TTL input reference clock signal can be used. The output frequency is determined by a 24-bit digital word entered through the serial port. The serial port enables the user to change the output frequency on-the-fly. The clock outputs utilize CMOS level output buffers that operate up to 130 MHz.

Applications

Graphics: The A V9110 generates low jitter, high speed pixel (or dot) clocks. It can be used to replace multiple expensive high speed crystal oscillators. The flexibility of this device allows it to generate nonstandard graphics clocks, allowing the user to program frequencies on-the-fly.

14 Pin Dip, SOIC

The A V9110 requires a stable reference clock (5 to 32 MHz) to generate a stable, low jitter output clock. The A V9 11 0 -01 is optimized to use an external quartz crystal as a frequency reference, without the need of additional external components. The A V9110-02 is optimized to accept an TTL clock reference. Either device can be used with an external crystal or accept a TTL clock reference, although extra components may be required. The various combinations implied are summarized in Figure 2 (see page 7). Clock Reference Implementations: AV9110-01 vs. AV9110-02 R E B M U N N I PE M A N N I PN I P E P Y T N O I T P I R C S E D 11 Xt u p nI. k c o l c e c n e r e f e r L T T r o t u p n i l a t s y r C 2D D VAr e w oP. V 5 + o t t c e n n o C . y l p p u s r e w o p G O L A N A 3D N GAr e w oP. D N U O R G G O L A N A 4D DVr e w oP. V 5 + o t t c e n n o C . y l p p u s r e w o p l a t i g i D 5D NGr e w oP. D N U O R G l a t i g i D 6A T ADt u p nI. n i p A T A D l a i r e S 7K L CSt u p nI. r e t s i g e r t f i h s s k c o l C . K C O L C L A I R E S 8# ECt u p nI. r e f s n a r t a t a d s l o r t n o c , w o l e v i t c A . E L B A N E P I H C 9X / K LCt u p t uO. t u p t u o X y b d e d i v i d K C O L C S O M C 01D NGr e w oP. D N U O R G l a t i g i D 11D DVr e w oP. V 5 + o t t c e n n o C . y l p p u s r e w o p l a t i g i D 21K LCt u p t uO. t u p t u o K C O L C S O M C 31E Ot u p nI. w o l n e h w s t u p t u o h t o b s e t a t s i r T . E L B A N E T U P T U O 412 Xt u p t uO. k c o l c e c n e r e f e r L T T r o t u p n i l a t s y r C

Electrical Characteristics

VDD = +5V±10%, TA = 0 – 70°C unless otherwise stated Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production. Absolute Maximum Ratings Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. C I T A T S / C D R E T E M A R APL O B M YSS N O I T I D N O C T S ETN IMP YTX AMS T I N U e g a t l o V w o L t u p n I V L I V D D V 5=- - 8.0V e g a t l o V h g i H t u p n IV H I V D D V 5=0 .2- - V t n e r r u C w o L t u p n I I L I V N I V O=- - 5 -A µ t n e r r u C h g i H t u p n II H I V N I D D V=- - 5 A µ e g a t l o V w o L t u p t u O1 V L O I L O a M 8=- - 4 .0V e g a t l o V h g i H t u p t u O1 V H OI H O a M 8 = 4 .2- - V e m i T e s i R k c o l C t u p n I1 I r K L C --0 2s n e m i T l l a F k c o l C t u p n I1 I f K L C --0 2s n t n e r r u C y l p p u S I D D d a o l oN- 5 2- A m C I M A N Y D / C A e g n a r y c n e u q e r f t u p t u Ofo 8 7 .0- 0 31z H M % 0 8 - 0 2 , e m i t e s i R1 tr d a o l F p 52- - 3 s n % 0 2 - 0 8 , e m i t l l a F1 tf d a o l F p 52- - 3 s n e l c y c y t u D1 % 0 5 @ dt d a o l F p 520 4- 0 6% a m g i s 1 , r e t t i J1 -0 4±- s p e t u l o s b a , r e t t i J1 -5 2 1±- s p 1 0 - 0 1 1 9 V A ; . q e r f e c n e r e f e r t u p n I1 f F E R t u p n i l a t s y rC5 8 1 3 . 412 3z H M 2 0 - 0 1 1 9 V A ; . q e r f e c n e r e f e r t u p n I1 f F E R t u p n i L TT6 .08 1 3 . 412 3z H M y c n e u q e r f K L C S r o A T A D t u p n I1 f A T A D --2 3z H M

1 X / t u p t u O o t t u p t u O , w e k St w e k s -0 04- s p

The A V9110 is programmed to generate clock frequencies by entering data through the shift register. Figure 1 displays the proper timing sequence. On the negative going edge of CE#, the shift register is enabled and the data at the DATA pin is loaded into the shift register on the rising edge of the SCLK. Bit D0 is loaded first, followed by D1, D2, etc. This data consists of the 24 bits shown in the Shift Register Bit Assignment in Table 1, and therefore takes 24 clock cycles to load. An internal counter then disables the input and transfers the data to internal latches on the rising edge of the 24th cycle of the SCLK. Any data entered after the 24th cycle is ignored until CE# must remain low for a minimum of 24 SLCK clock cycles. If CE# is taken high before 24 clock cycles have elapsed, the data is ignored (no frequency change occurs) and the counter is reset. Tables 1 and 2 display the bit location for generating the output clock frequency and the output divider circuitry, respectively. T IBT N E M N G I S S A N O I T A U Q E E L B A I R A V T L U A F E D T I B 1 0-2 0 - 0) B S L ( r e d i v i d y c n e u q e r f O C V N r e g e t n I M r e g e t n I 110 1r e d i v i d y c n e u q e r f O C V 111 2r e d i v i d y c n e u q e r f O C V 112 3r e d i v i d y c n e u q e r f O C V 113 4r e d i v i d y c n e u q e r f O C V 114 5r e d i v i d y c n e u q e r f O C V 115 6) B S M ( r e d i v i d y c n e u q e r f O C V 116 7) B S L ( r e d i v i d y c n e u q e r f e c n e r e f e R 007 8r e d i v i d y c n e u q e r f e c n e r e f e R 118 9r e d i v i d y c n e u q e r f e c n e r e f e R 009 01r e d i v i d y c n e u q e r f e c n e r e f e R 00 0 1 11r e d i v i d y c n e u q e r f e c n e r e f e R 11 1 1 21r e d i v i d y c n e u q e r f e c n e r e f e R 00 2 1 31) B S M ( r e d i v i d y c n e u q e r f e c n e r e f e R 00 3 1 4 1 V8 y b e d i v i d = 1 , 1 y b e d i v i d = 0 ( e d i v i d e l a c s - e r p O C V00 4 1 5 1 ) 2 e l b a T e e s ( 0 D O C e d i v i d t u p t u o X / K L C X 01 5 1 6 1 ) 2 e l b a T e e s ( 1 D O C e d i v i d t u p t u o X / K L C 10 6 1 7 1 ) 3 e l b a T e e s ( 0 D O V e d i v i d t u p t u o O C V R 00 7 1 8 1 ) 3 e l b a T e e s ( 1 D O V e d i v i d t u p t u o O C V 11 8 1 9 1 ) e t a t s i r t = 0 ( K L C e l b a n e t u l p t u O 11 9 1 0 2 ) e t a t s i r t = 0 ( X / K L C e l b a n e t u p t u O 11 0 2 12) 1 ( h g i h d e m m m a r g o r p e b d l u o h S . d e v r e s e R11 1 2 22) y c n e u q e r f e c n e r e f e r = 1 ( K L C n o t c e l e s k c o l c e c n e r e f e R00 2 2 32) 1 ( h g i h d e m m a r g o r p e b d l u o h S . d e v r e s e R 11 3 2

Output Divider Turth Tables

1 D OC0 D O C

) X ( 001 01 2 104 118 Table 2 ) R ( 001 01 2 104 118 Table 3 Programming the PLL The A V9110 has a wide operating range but it is recommended that it is operated within the following limits: The A V9110 is a classical PLL circuit and the VCO output frequency is given by: fVCO = NV fREF M Where N = VCO divided, 3 to 127 M =m Reference divide, 3 to 127 V = Perscale, 1 or 8 The 2 output drivers then give the following frequencies: fCLK = fVCO R = NV fREF M•R or fREF (output mixable by bit 17) fCLK/X = = fVCLK X Where R, X = output dividers 1, 2, 4 or 8 fVCO RX Notes: 1. Output frequency accuracy will depend solely on input reference frequency accuracy. 2. For output frequencies below 125 MHz, it is recommended that the VCO output divide, R, should be 2 or greater. This will give improved duty cycle. 3. The minimum output frequency step size is approximately 0.2% due to the divider range provided. f < z H M 2F E R z H M 2 3<f F E R y c n e u q e r f e c n e r e f e r t u p n I = z H M 5 < < z H k 0 027 2 1 o t 3 , e d i v i d e c n e r e f e R = M f < z H M 0 5O C V z H M 0 5 2<f O C V y c n e u q e r f t u p t u o O C V = f O C V z H M 0 5 2<f K L C y c n e u q e r f t u p t u o X / K L C r o K L C = fREF M

Figure 1 - Serial Programming AC Timing Frequency Acquisition Time Frequency acquisition (or “lock”) time is the time that it takes to change from one frequency to another, and is a function of the difference between the old and new frequencies. The A V9 11 0 can typically lock to within 1% of a new frequency in less than 200 microseconds. This is also true with power-on. Power-On Reset Upon power-up the internal latches are preset to provide the following output clock frequencies (14.318 MHz reference assumed): Device CLK output CLK/X output A V9110-01 25.175 MHz 6.29 MHz A V9110-02 25.175 MHz 12.59 MHz These preset default frequencies can be changed with a custom metal mask, as can other attributes. The actual numbers of these output clock frequencies (14.318MHz reference assumed) are: Device CLK output CLK/X output A V9110-01 25.255 MHz 6.31 MHz A V9110-02 25.255 MHz 12.63 MHz and these are within 0.32%. Jitter For high performance applications, the A V9110 offers ex- tremely low jitter and excellent power supply rejection. The one sigma jitter distribution is typically less than ±125ps. For optimum performance, the device should be decoupled with both a 2.2mF and a 0.1mF capacitor. Refer to Recommended Board Layout diagram on page 8. Output Enable The A V9110 outputs can be disabled with either the OE pin or through serial programming. Setting the OE pin low tristates CLK and CLK/X. Alternatively, setting bits D19 and D20 low in the serial word will tristate the two outputs. Both the OE pin and D19 or D20 must be high to enable an output. Frequency Transition Glitches The A V9110 starts changing frequency on the rising edge of the 24th serial clock. If the programming of any output divider is changed, the output clock may glitch before locking to the new frequency in less than 200µs with no output glitches (no partial clock cycles). r e t e m a r aP) s n ( e m i t m u m i n i M t 1 u s 0 1 t 2 u s 0 1 t 1 h 0 1 t 2 h 0 1

AV9110 Quartz Crystal Selection When an external quartz crystal will be used as a frequency reference for the A V9110, attention needs to be given to crystal selection if accurate reference frequency and output frequency is desired. The A V9110 uses a Pierce oscillator design which operates the quartz crystal in parallel-resonant mode. It requires a quartz crystal cut for parallel-resonant operation to ensure an accurate frequency of oscillation (a less expensive series-reso-nant crystal can be used with the device but it will oscillate approximately 0.1% too fast). The A V9110-01 has internal crystal load capacitors which result in a total crystal load capacitance of approximately 12pF±10%.The A V9110-02 does not have internal load capacitors, but contributes about 3pFload capacitance to the crystal. Following is a list of recommended crystal devices for the A V9110. They have been tested by the crystal manufacturer to operate suitably with the A V91xx-series crystal oscillator de-sign, having load capacitance characteristics that are compatible with the A V9110-01. Toyocom Part Number Epson Part Number MA-506 Using A V9110-01 with a crystal Using A V9110-01 with an external clock Using A V9110-02 with a crystal Using A V9110-02 with an external clock Figure 2 - Clock Reference Combinations

AV9110 Recommended Board Layout This is the recommended layout for the A V9110 to maximize clock performance. Shown are the power and ground connections, the ground plane, and the input/output traces. Use of the isolated ground plane and power connection, as shown, will prevent stray high frequency ground and system noise from coupling to the A V9110. As when compared to using the system ground and power planes, this technique will lessen output clock jitter. The isolated ground plane should be connected to the system ground plane at one point near the 2.2mF decoupling cap. For lowest jitter performance, the isolated ground plane should be kept away from clock output pins and traces. Keeping the isolated ground plane area as small as possible will minimize EMI radiation. Use a sufficient gap between the isolated ground plane and system ground plane to prevent AC coupling. The ferrite bead in the VDD line is optional, but will help reduce EMI. The traces to distribute the output clocks should be over an unbroken system ground or power supply plane. The trace width should be about two times the thickness of the PC board between the trace and the underlying plane. These guidelines help minimize clock jitter and EMI radiation. The traces to distribute power should be as wide as possible.

mA % AV9110 Typical Duty Cycle VCO Output Divide, R = 1 Duty Cycle will improve if R > 1 AV9110 Idd CL = pF, R = 1

ICS XXXX S-PPP X#W LF Example: Package Type S=SOIC N=DIP (plastic) Device Type (consists of 3 or 4 digit numbers) ICS=Standard Device Prefix

Ordering Information

AV9110-01CN14LF, AV9110-02CN14LF AV9110-01CS14LF, AV9110-02CS14LF Pattern Number(2 or 3 digit number for parts with ROM code patterns) Lead Count Lead Count=1,2 or 3 digits 14-Pin DIP Package 14-Pin 150 mil SOIC Package Lead Free, RoHS Compliant (Optional)

Revision History

Rev. Issue Date Description Page # G 3/19/2008 added LF ordering Information. 10

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