ATMEGA128L-8MU

ATMEGA128_08 ATMEL

Document overview

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Technical content

Datasheet sections

Features

• High-performance, Low-power AVR® 8-bit Microcontroller  Advanced RISC Architecture – 133 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers + Peripheral Control Registers – Fully Static Operation – Up to 16 MIPS Throughput at 16 MHz – On-chip 2-cycle Multiplier  High Endurance Non-volatile Memory segments – 128K Bytes of In-System Self-programmable Flash program memory – 4K Bytes EEPROM – 4K Bytes Internal SRAM – Write/Erase cycles: 10,000 Flash/100,000 EEPROM – Data retention: 20 years at 85°C/100 years at 25°C (1) – Optional Boot Code Section with Independent Lock Bits In-System Programming by On-chip Boot Program True Read-While-Write Operation – Up to 64K Bytes Optional External Memory Space – Programming Lock for Software Security – SPI Interface for In-System Programming  JTAG (IEEE std. 1149.1 Compliant) Interface – Boundary-scan Capabilities According to the JTAG Standard – Extensive On-chip Debug Support – Programming of Flash, EEPROM, Fuses and Lock Bits through the JTAG Interface  Peripheral Features – Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes – Two Expanded 16-bit Timer/Counters with Separate Prescaler, Compare Mode and Capture Mode – Real Time Counter with Separate Oscillator – Two 8-bit PWM Channels – 6 PWM Channels with Programmable Resolution from 2 to 16 Bits – Output Compare Modulator – 8-channel, 10-bit ADC

8 Single-ended Channels

7 Differential Channels

2 Differential Channels with Programmable Gain at 1x, 10x, or 200x

– Byte-oriented Two-wire Serial Interface – Dual Programmable Serial USARTs – Master/Slave SPI Serial Interface – Programmable Watchdog Timer with On-chip Oscillator – On-chip Analog Comparator  Special Microcontroller Features – Power-on Reset and Programmable Brown-out Detection – Internal Calibrated RC Oscillator – External and Internal Interrupt Sources – Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby, and Extended Standby – Software Selectable Clock Frequency – ATmega103 Compatibility Mode Selected by a Fuse – Global Pull-up Disable  I/O and Packages – 53 Programmable I/O Lines – 64-lead TQFP and 64-pad QFN/MLF  Operating Voltages – 2.7 - 5.5V ATmega128L – 4.5 - 5.5V ATmega128  Speed Grades – 0 - 8 MHz ATmega128L – 0 - 16 MHz ATmega128 8-bit Microcontroller with 128K Bytes In-System Programmable Flash ATmega128 ATmega128L Rev. 2467R–AVR–06/08

Figure 1. Pinout ATmega128 package should be soldered to ground. power consumption versus processing speed.

Figure 2. Block Diagram

2467R–AVR–06/08 ATmega128 The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achiev ing throughputs up to ten times faster than con- ventional CISC microcontrollers. The ATmega128 provides the following features: 128K bytes of In-System Programmable Flash with Read-While-Write capabilities, 4K bytes EEPROM, 4K bytes SRAM, 53 general purpose I/O lines, 32 general purpose working registers, Real Time Counter (RTC), four flexible Timer/Counters with compare modes and PWM, 2 USARTs, a byte oriented Two-wire Serial Interface, an 8-channel, 10-bit ADC with optional differential input stage with programmable gain, programmable Watchdog Timer with Internal Oscillator, an SPI serial port, IEEE std. 1149.1 compliant JTAG test interface, also used for accessing the On-chip Debug system and programming and six software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI por t, and interrupt system to continue function- ing. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or Hardware Reset. In Power-save mode, the asyn- chronous timer continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules except Asynchronous Timer and ADC, to minimize switching noise during ADC conversions. In Standby mode, the Crystal/Resonator Oscillator is runn ing while the rest of the device is sleeping. This allows very fast start-up combined with low power consumption. In Extended Standby mode, both the main Oscillator and the Asynchronous Timer continue to run. The device is manufactured using Atmel’s high-density nonvolatile memory technology. The On- chip ISP Flash allows the program memory to be reprogrammed in-system through an SPI serial interface, by a conventional nonvolatile memory programmer, or by an On-chip Boot program running on the AVR core. The boot program can use any interface to download the application program in the application Flash memory. Software in the Boot Flash section will continue to run while the Application Flash section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega128 is a powerful microcontroller that provides a highly flexible and cost effec- tive solution to many embedded control applications. The ATmega128 AVR is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits. ATmega103 and ATmega128 Compatibility The ATmega128 is a highly complex microcontroller where the number of I/O locations super- sedes the 64 I/O locations reserved in the AVR instruction set. To ensure backward compatibility with the ATmega103, all I/O locations present in ATmega103 have the same location in ATmega128. Most additional I/O locations are added in an Extended I/O space starting from $60 to $FF, (i.e., in the ATmega103 internal RAM space). These locations can be reached by using LD/LDS/LDD and ST/STS/STD instructions only, not by using IN and OUT instructions. The relo- cation of the internal RAM space may still be a problem for ATmega103 users. Also, the increased number of interrupt vectors might be a problem if the code uses absolute addresses. To solve these problems, an ATmega103 compatibility mode can be selected by programming the fuse M103C. In this mode, none of the functions in the Extended I/O space are in use, so the internal RAM is located as in ATmega103. Also, the Extended Interrupt vectors are removed. The ATmega128 is 100% pin compatible with ATmega103, and can replace the ATmega103 on current Printed Circuit Boards. The applic ation note “Replacing ATmega103 by ATmega128” describes what the user should be aware of replacing the ATmega103 by an ATmega128.

2467R–AVR–06/08 ATmega128 ATmega103 Compatibility Mode By programming the M 103C fuse, the ATmega12 8 will be compatible with the ATmega103 regards to RAM, I/O pins and interrupt vectors as described above. However, some new fea- tures in ATmega128 are not available in this compatibility mode, these features are listed below:  One USART instead of two, Asynchronous mode only. Only the eight least significant bits of the Baud Rate Register is available.  One 16 bits Timer/Counter with two compare registers instead of two 16-bit Timer/Counters with three compare registers.  Two-wire serial interface is not supported.  Port C is output only.  Port G serves alternate functions only (not a general I/O port).  Port F serves as digital input only in addition to analog input to the ADC.  Boot Loader capabilities is not supported.  It is not possible to adjust the frequency of the internal calibrated RC Oscillator.  The External Memory Interface can not release any Address pins for general I/O, neither configure different wait-states to different External Memory Address sections. In addition, there are some other minor differences to make it more compatible to ATmega103:  Only EXTRF and PORF exists in MCUCSR.  Timed sequence not required for Watchdog Time-out change.  External Interrupt pins 3 - 0 serve as level interrupt only.  USART has no FIFO buffer, so data overrun comes earlier. Unused I/O bits in ATmega103 should be written to 0 to ensure same operation in ATmega128. Pin Descriptions VCC Digital supply voltage. GND Ground. Port A (PA7..PA0) Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port A output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port A pi ns that are externally pulled low will source current if the pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port A also serves the functions of various special features of the ATmega128 as listed on page 73. Port B (PB7..PB0) Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pi ns that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B also serves the functions of various special features of the ATmega128 as listed on page 74. Port C (PC7..PC0) Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C output buffers have symmetrical drive c haracteristics with bot h high sink and source capability. As inputs, Port C pi ns that are externally pulled lo w will source current if the pull-up

2467R–AVR–06/08 ATmega128 resistors are activated. The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port C also serves the functions of s pecial features of the ATmega128 as listed on page 77. In ATmega103 compatibility mode , Port C is output only, and the port C pins are not tri-stated when a reset condition becomes active. Note: The ATmega128 is by default shipped in ATmega103 compatibility mode. Thus, if the parts are not programmed before they are put on the PCB, PORTC will be output during first power up, and until the ATmega103 compatibility mode is disabled. Port D (PD7..PD0) Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive c haracteristics with bot h high sink and source capability. As inputs, Port D pi ns that are externally pulled lo w will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port D also serves the functions of various special features of the ATmega128 as listed on page 78. Port E (PE7..PE0) Port E is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port E output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port E pi ns that are externally pulled low will source current if the pull-up resistors are activated. The Port E pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port E also serves the functions of various special features of the ATmega128 as listed on page 81. Port F (PF7..PF0) Port F serves as the analog inputs to the A/D Converter. Port F also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used. Port pins can provide internal pull-up resistors (selected for each bit). The Port F output buffers have sym- metrical drive characteristics with both high sink and source capa bility. As inputs, Port F pins that are externally pulled low will source current if the pull-up resistors are activated. The Port F pins are tri-stated when a reset condition becomes active, even if the clock is not running. If the JTAG interface is enabled, the pull-up resistors on pins PF7(TDI), PF5(TMS), and PF4(TCK) will be activated even if a Reset occurs. The TDO pin is tri-stated unless TAP states that shift out data are entered. Port F also serves the functions of the JTAG interface. In ATmega103 compatibility mode, Port F is an input Port only. Port G (PG4..PG0) Port G is a 5-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port G output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port G pins that are extern ally pulled low will sour ce current if the pull-up resistors are activated. The Port G pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port G also serves the functions of various special features. The port G pins are tri-stated when a reset condi tion becomes active, even if the clock is not running. In ATmega103 compatibility mode, these pins only serves as strobes signals to the external memory as well as input to the 32 kHz Oscillator, and the pins ar e initialized to PG0 = 1, PG1 = 1, and PG2 = 0 asynchronously when a reset condition becomes active, even if the clock is not running. PG3 and PG4 are oscillator pins.

2467R–AVR–06/08 ATmega128 RESET Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in Table 19 on page 51. Shorter pulses are not guaranteed to generate a reset. XTAL1 Input to the inverting Oscillator amplifier and input to the internal clock operating circuit. XTAL2 Output from the inverting Oscillator amplifier. AVCC AVCC is the supply voltage pin for Port F and the A/D Converter. It should be externally con- nected to V CC, even if the ADC is not used. If the ADC is used, it should be connected to V CC through a low-pass filter. AREF AREF is the analog reference pin for the A/D Converter. PEN PEN is a programming enable pin for the SPI Serial Programming mode, and is internally pulled high . By holding this pin low during a Power-on Reset, the device will enter the SPI Serial Pro- gramming mode. PEN has no function during normal operation.

2467R–AVR–06/08 ATmega128 Resources A comprehensive set of development tools, application notes, and datasheets are available for download on http://www.atmel.com/avr. ATmega128/L rev. A - M characterization is found in the ATmega128 Appendix A. Note: 1. Data Retention Reliability Qualification results show that the pr ojected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C.

2467R–AVR–06/08 ATmega128 About Code Examples This datasheet contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compi- lation. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Please confirm with the C compiler documentation for more details. For I/O registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructio ns that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”.

perform calculations, control peripherals and handle interrupts. Figure 3. Block Diagram of the AVR Architecture in every clock cycle. The program memory is In-System Reprogrammable Flash memory. and the result is stored back in the Register file – in one clock cycle. tion, the Status Register is updated to reflect information about the result of the operation.

2467R–AVR–06/08 ATmega128 Program flow is provided by conditional and uncon ditional jump and call instructions, able to directly address the whole address space. Most AVR instructions have a single 16-bit word for- mat. Every program memory address contains a 16- or 32-bit instruction. Program Flash memory space is divided in two sections, the Boot Program section and the Application Program section. Both sections have dedicated Lock bits for write and read/write protection. The SPM instruction that writes into the Application Flash Memory section must reside in the Boot Program section. During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack. The Stack is effectively allocated in the general data SRAM, and consequently the stack size is only limited by the to tal SRAM size and the usage of the SRAM. All user programs must initialize the SP in the reset routine (before subroutines or interrupts are executed). The Stack Pointer – SP – is read/write accessible in the I/O space. The data SRAM can easily be accessed through the five different addressing modes supported in the AVR architecture. The memory spaces in the AVR architecture are all linear and regular memory maps. A flexible interrupt module has its control registers in the I/O space with an additional global interrupt enable bit in the Status Register. All interrupts have a separate interrupt vector in the interrupt vector table. The interrupts have priority in accordance with their interrupt vector posi- tion. The lower the interrupt vector address, the higher the priority. The I/O memory space contains 64 addresses wh ich can be accessed directly, or as the Data Space locations following those of the Register file, $20 - $5F. In addition, the ATmega128 has Extended I/O space from $60 - $FF in SRAM where only the ST/STS/STD and LD/LDS/LDD instructions can be used. ALU – Arithmetic Logic Unit The high-performance AVR ALU operates in dire ct connection with all the 32 general purpose working registers. Within a single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are executed. The ALU operations are divided into three main categories – arithmetic, logical, and bit-functions. Some implementations of the architecture also provide a powerful multiplier supporting both signed/unsigned multiplication and fractional format. See the “Instruction Set” section for a detailed description. Status Register The Status Register contains information about the result of the most recently executed arith- metic instruction. This information can be used fo r altering program flow in order to perform conditional operations. Note that the Status Register is updated after all ALU operations, as specified in the Instruction Set Reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code. The status register is not automatically st ored when entering an interrupt routine and restored when returning from an interrupt. This must be handled by software. The AVR status Register – SREG – is defined as: B i t 76543210 I T H S V N Z C SREG Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0

2467R–AVR–06/08 ATmega128  Bit 7 – I: Global Interrupt Enable The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual inter- rupt enable control is then performed in separate control registers. If the Global Interrupt Enable Register is cleared, none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared in software with the SEI and CLI instructions, as described in the instruction set reference.  Bit 6 – T: Bit Copy Storage The Bit Copy instructions BLD (Bit LoaD) and BST (B it STore) use the T-bit as source or desti- nation for the operated bit. A bit from a register in the Register file can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the Register file by the BLD instruction.  Bit 5 – H: Half Carry Flag The Half Carry Flag H indicates a half carry in some arithmetic operations. Half carry is useful in BCD arithmetic. See the “Instruction Set Description” for detailed information.  Bit 4 – S: Sign Bit, S = N ⊕ V The S-bit is always an exclusive or between the negative flag N and the two’s complement over- flow flag V. See the “Instruction Set Description” for detailed information.  Bit 3 – V: Two’s Complement Overflow Flag The Two’s Complement Overflow Flag V suppor ts two’s complement arithmetics. See the “Instruction Set Description” for detailed information.  Bit 2 – N: Negative Flag The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information.  Bit 1 – Z: Zero Flag The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information.  Bit 0 – C: Carry Flag The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. General Purpose Register File The Register file is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required performance and flexib ility, the followin g input/output schemes are supported by the Register file:  One 8-bit output operand and one 8-bit result input  Two 8-bit output operands and one 8-bit result input  Two 8-bit output operands and one 16-bit result input  One 16-bit output operand and one 16-bit result input Figure 4 on page 13 shows the structure of the 32 general purpose working registers in the CPU.

Figure 4. AVR CPU General Purpose Working Registers most of them are single cycle instructions. registers, as the X-, Y-, and Z-pointer Registers can be set to index any register in the file. address registers X, Y, and Z are described in Figure 5. Figure 5. The X-, Y -, and Z-registers automatic increment, and automatic decrement (see the Instruction Set Reference for details).

15 XH XL 0

15 YH YL 0

15 ZH ZL 0

2467R–AVR–06/08 ATmega128 Stack Pointer The Stack is mainly used for storing temporary data, for storing local variables and for storing return addresses after interrupts and subroutine calls. The Stack Pointer Register always points to the top of the Stack. Note that the Stack is implemented as growing from higher memory loca- tions to lower memory locations. This implies that a Stack PUSH command decreases the Stack Pointer. The Stack Pointer points to the data SRAM stack area where the Subroutine and Interrupt Stacks are located. This Stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. The Stack Pointer must be set to point above $60. The Stack Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction, and it is decremented by two when the return address is pushed onto the Stack with subroutine call or interrupt. The Stack Pointer is incremented by one when data is popped from the Stack with the POP instruction, and it is incremented by two when data is popped from the Stack with return from subroutine RET or return from interrupt RETI. The AVR Stack Pointer is implemented as two 8- bit registers in the I/O space. The number of bits actually used is implementation dependent. Note that the data space in some implementa- tions of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register will not be present. RAM Page Z Select Register – RAMPZ  Bits 7..1 – Res: Reserved Bits These are reserved bits and will always read as zero. When writing to this address location, write these bits to zero for compatibility with future devices.  Bit 0 – RAMPZ0: Extended RAM Page Z-pointer The RAMPZ Register is normally used to sele ct which 64K RAM Page is accessed by the Z- pointer. As the ATmega128 does not support more than 64K of SRAM memory, this register is used only to select which page in the program memory is accessed when the ELPM/SPM instruction is used. The different settings of the RAMPZ0 bit have the following effects: Note that LPM is not affected by the RAMPZ setting. Instruction Execution Timing This section describes the general access timi ng concepts for instruction execution. The AVR CPU is driven by the CPU clock clkCPU, directly generated from the selected clock source for the chip. No internal clock division is used. B i t 1 51 41 31 21 11 0 9 8 SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SPH SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL 76543210 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 00000000 B i t 765432 1 0 Read/Write R R R R R R R R/W Initial Value 0 0 0 0 0 0 0 0 RAMPZ0 = 0: Program memory address $0000 - $7FFF (lower 64K bytes) is accessed by ELPM/SPM RAMPZ0 = 1: Program memory address $8000 - $FFFF (higher 64K bytes) is accessed by ELPM/SPM

2467R–AVR–06/08 ATmega128 There are basically two types of interrupts. The fi rst type is triggered by an event that sets the interrupt flag. For these interrupts, the Program Counter is vectored to the actual interrupt vector in order to execute the interrupt handling rout ine, and hardware clears the corresponding inter- rupt flag. Interrupt flags can also be cleared by writing a logic one to the flag bit position(s) to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is cleared, the interrupt flag will be set and re membered until the interrupt is enabled, or the flag is cleared by software. Similarly, if one or more interrup t conditions occur while the global interrupt enable bit is cleared, the corresponding interrupt flag(s) will be set and remembered until the global interrupt enable bit is set, and will then be executed by order of priority. The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do not necessarily have interrupt flags. If the interrupt condition disappears before the interrupt is enabled, the interrupt will not be triggered. When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served. Note that the Status Register is not automatica lly stored when entering an interrupt routine, nor restored when returning from an interrupt routine. This must be handled by software. When using the CLI instruction to disable interrupts, the interrup ts will be immediately disabled. No interrupt will be executed af ter the CLI instruction, even if it occurs simultaneously with the CLI instruction. The following example shows how this can be used to avoid interrupts during the timed EEPROM write sequence. Assembly Code Example in r16, SREG ; store SREG value cli ; disable interrupts during timed sequence sbiEECR, EEMWE ; start EEPROM write sbiEECR, EEWE outSREG, r16 ; restore SREG value (I-bit) C Code Example char cSREG; cSREG = SREG;/* store SREG value */ /* disable interrupts during timed sequence */ __disable_interrupt(); EECR |= (1<<EEMWE); /* start EEPROM write */ EECR |= (1<<EEWE); SREG = cSREG; /* restore SREG value (I-bit) */

2467R–AVR–06/08 ATmega128 When using the SEI instruction to enable interr upts, the instruction following SEI will be exe- cuted before any pending interrupts, as shown in this example. Interrupt Response Time The interrupt execution response for all the enabl ed AVR interrupts is four clock cycles mini- mum. After four clock cycles, the program vector address for the actual interrupt handling routine is executed. During this 4-clock cycle period, the Program Counter is pushed onto the Stack. The vector is normally a jump to the interrupt routine, and this jump takes three clock cycles. If an interrupt occurs during execution of a multi- cycle instruction, this in struction is completed before the interrupt is served. If an interrupt occurs when the MCU is in Sleep mode, the inter- rupt execution response time is increased by four clock cycles. This increase comes in addition to the start-up time from the selected sleep mode. A return from an interrupt handling routine takes four clock cycles. During these 4-clock cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is incre- mented by two, and the I-bit in SREG is set. Assembly Code Example sei ; set global interrupt enable sleep; enter sleep, waiting for interrupt ; note: will enter sleep before any pending ; interrupt(s) C Code Example __enable_interrupt(); /* set global interrupt enable */ __sleep(); /* enter sleep, waiting for interrupt */ /* note: will enter sleep before any pending interrupt(s) */

Boot Program section and Application Program section.

1. “Memory Programming” on page 286 contains a detailed description on Flash programming

in SPI, JTAG, or Parallel Programming mode. – Load Program Memory and ELPM – Extended Load Program Memory instruction description). Figure 8. Program Memory Map

Figure 9 shows how the ATmega128 SRAM Memory is organized. memory, and the next 4096 locations address the internal data SRAM. to take advantage of the external memory map. enabled by setting the SRE bit in the MCUCR Register. more than specified in the instruction set manual for one, two, and three wait-states. registers R26 to R31 feature the indirect addressing pointer registers. The direct addressing reaches the entire data space. Table 1. Memory Configurations

ment, the address registers X, Y, and Z are decremented or incremented. file is described in “General Purpose Register File” on page 12. Figure 9. Data Memory Map

32 Registers

64 I/O Registers

internal data SRAM access is performed in two clkCPU cycles as described in Figure 10. Figure 10. On-chip Data SRAM Access Cycles the EEPROM Control Register. The EEPROM access registers are accessible in the I/O space. ing EEPROM Corruption” on page 25. for details on how to avoid problems in these situations. In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to the description of the EEPROM Control Register for details on this. write these bits to zero for compatibility with future devices.

2467R–AVR–06/08 ATmega128  Bits 11..0 – EEAR11..0: EEPROM Address The EEPROM Address Registers – EEARH and EEAR L – specify the EEPR OM address in the 4K bytes EEPROM space. The EEPROM data by tes are addressed li nearly between 0 and 4096. The initial value of EEAR is undefined. A proper valu e must be written before the EEPROM may be accessed. EEPROM Data Register – EEDR  Bits 7..0 – EEDR7.0: EEPROM Data For the EEPROM write operation, the EEDR Register contains the data to be written to the EEPROM in the address given by the EEAR Regi ster. For the EEPROM read operation, the EEDR contains the data read out from the EEPROM at the address given by EEAR. EEPROM Control Register – EECR  Bits 7..4 – Res: Reserved Bits These bits are reserved bits in the ATmega128 and will always read as zero.  Bit 3 – EERIE: EEPROM Ready Interrupt Enable Writing EERIE to one enab les the EEPROM Ready Interrupt if th e I-bit in SREG is set. Writing EERIE to zero disables the interrupt. The EEPROM Ready interrupt generates a constant inter- rupt when EEWE is cleared.  Bit 2 – EEMWE: EEPROM Master Write Enable The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written. When EEMWE is written to one, writing EEWE to one within four clock cycles will write data to the EEPROM at the selected address. If EEMWE is zero, writing EEWE to one will have no effect. When EEMWE has been written to one by software, hardware clears the bit to zero after four clock cycles. See the description of the EEWE bit for an EEPROM write procedure.  Bit 1 – EEWE: EEPROM Write Enable The EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When address and data are correctly set up, the EEWE bit must be set to write the value into the EEPROM. The EEMWE bit must be set when the logical o ne is written to EEWE, otherwise no EEPROM write takes place. The following procedure shoul d be followed when writing the EEPROM (the order of steps 3 and 4 is not essential): 1. Wait until EEWE becomes zero. 2. Wait until SPMEN in SPMCSR becomes zero. 3. Write new EEPROM address to EEAR (optional). 4. Write new EEPROM data to EEDR (optional). 5. Write a logical one to the EEMWE bit while writing a zero to EEWE in EECR. 6. Within four clock cycles after setting EEMWE, write a logical one to EEWE. B i t 76543210 MSB LSB EEDR Read/Write R/W R/W R/W R/W R/W R/W R/W R/W I n i t i a l V a l u e 00000000 B i t 76543210 – – – – EERIE EEMWE EEWE EERE EECR Read/Write R R R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 X 0

must check that the Flash programming is co mpleted before initiating a new EEPROM write. during the four last steps to avoid these problems. the CPU is halted for two cycles before the next instruction is executed. next instruction is executed. progress, it is neither possible to read the EEPROM, nor to change the EEAR Register. gramming time for EEPROM access from the CPU. Note: 1. Uses 1 MHz clock, independent of CKSEL-fuse settings. Table 2. EEPROM Programming Time

2467R–AVR–06/08 ATmega128 The following code examples show one assembly and one C function for writing to the EEPROM. The examples assume that interrupts are controlled (e.g., by disabling interrupts glo- bally) so that no interrupts will occur during ex ecution of these functions. The examples also assume that no flash boot loader is present in the software. If such code is present, the EEPROM write function must also wait for any ongoing SPM command to finish. Assembly Code Example EEPROM_write: ; Wait for completion of previous write sbic EECR,EEWE rjmp EEPROM_write ; Set up address (r18:r17) in address register out EEARH, r18 out EEARL, r17 ; Write data (r16) to data register out EEDR,r16 ; Write logical one to EEMWE sbi EECR,EEMWE ; Start eeprom write by setting EEWE sbi EECR,EEWE ret C Code Example void EEPROM_write(unsigned int uiAddress, unsigned char ucData) /* Wait for completion of previous write */ while(EECR & (1<<EEWE)) /* Set up address and data registers */ EEAR = uiAddress; EEDR = ucData; /* Write logical one to EEMWE */ EECR |= (1<<EEMWE); /* Start eeprom write by setting EEWE */ EECR |= (1<<EEWE);

2467R–AVR–06/08 ATmega128 The next code examples show assembly and C functions for reading the EEPROM. The exam- ples assume that interrupts are controlled so that no interrupts will occur during execution of these functions. EEPROM Write During Power-down Sleep Mode When entering Power-down sleep mode whil e an EEPROM write operation is active, the EEPROM write operation will c ontinue, and will complete before the write access time has passed. However, when the writ e operation is completed, the Oscillator continues running, and as a consequence, the device does not enter Power-down entirely. It is therefore recommended to verify that the EEPROM write operation is completed before entering Power-down. Preventing EEPROM Corruption During periods of low V CC, the EEPROM data can be corrupted because the supply voltage is too low for the CPU and the EEPROM to operate properly. These issues are the same as for board level systems using EEPROM, and the same design solutions should be applied. An EEPROM data corruption can be caused by two situations when the voltage is too low. First, a regular write sequence to the EEPROM requires a minimum voltage to operate correctly. Sec- ondly, the CPU itself can execute instructions incorrectly, if the supply voltage is too low. EEPROM data corruption can easily be avoided by following this design recommendation: Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can be done by enabling the internal Brown-out Detector (BOD). If a reset occurs while a write oper- Assembly Code Example EEPROM_read: ; Wait for completion of previous write sbic EECR,EEWE rjmp EEPROM_read ; Set up address (r18:r17) in address register out EEARH, r18 out EEARL, r17 ; Start eeprom read by writing EERE sbi EECR,EERE ; Read data from data register in r16,EEDR ret C Code Example unsigned char EEPROM_read(unsigned int uiAddress) /* Wait for completion of previous write */ while(EECR & (1<<EEWE)) /* Set up address register */ EEAR = uiAddress; /* Start eeprom read by writing EERE */ EECR |= (1<<EERE); /* Return data from data register */ return EEDR;

2467R–AVR–06/08 ATmega128 ation is in progress, the write operation will be completed provided that the power supply voltage is sufficient. I/O Memory The I/O space definition of the ATmega128 is shown in “Register Summary” on page 362. All ATmega128 I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose working registers and the I/O space. I/O registers within the address range $00 - $1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. Refer to the instruction set section for more details. When using the I/O specific commands IN and OUT, the I/O addresses $00 - $3F must be used. When addressing I/O registers as data space using LD and ST instructions, $20 must be added to these addresses. The ATmega128 is a complex micro- controller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions. For t he Extended I/O space from $60 - $FF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used. The Extended I/O space is replaced with SRAM locations when the ATmega128 is in the ATmega103 compatibility mode. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. Some of the status flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on all bits in the I/O register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions work with registers $00 to $1F only. The I/O and peripherals control registers are explained in later sections. External Memory Interface With all the features the External Memory Interf ace provides, it is well suited to operate as an interface to memory devices such as External SRAM and Flash, and peripherals such as LCD- display, A/D, and D/A. The main features are:  Four different wait-state settings (including no wait-state).  Independent wait-state setting for different extErnal Memory sectors (configurable sector size).  The number of bits dedicated to address high byte is selectable.  Bus-keepers on data lines to minimize current consumption (optional). Overview When the eXternal MEMory (XMEM) is enabl ed, address space outside the internal SRAM becomes available using the dedicated External Memory pins (see Figure 1 on page 2, Table 27 on page 73 , Table 33 on page 77 , and Table 45 on page 85 ). The memory configuration is shown in Figure 11.

Figure 11. External Memory with Sector Select  Only two wait-states settings are available (SRW1n = 0b00 and SRW1n = 0b01).  The number of bits that are assigned to address high byte are fixed.  Bus-keeper is not available. , WR and ALE pins are output only (Port G in ATmega128).  AD7:0: Multiplexed low-order address bus and data bus.  A15:8: High-order address bus (configurable number of bits).  ALE: Address latch enable.

Memory Control Register B – XMCRB. latch (typically “74 x 573” or equivalent) which is transparent when G is high.  Data setup time before G low (t SU).  Data (address) hold time after G low ( TH). wiring delay (dependent on the capacitive load). Figure 12. External SRAM Connected to the AVR

writing the Port register to zero before entering sleep. AD7:0 bus when these lines would otherwise be tri-stated by the XMEM interface. quently, the XMEM interface is not suited for synchronous operation. Figure 13. External Data Memory Cycles without Wait-state (SRWn1=0 and SRWn0=0) accesses the RAM (internal or external).

external memory address space can be divided in two sectors that have separate wait-state bits. tor, the wait-states are configured by the SRW11 and SRW10 bits. nal memory address space, see Table 4. nal memory address space, see Table 4. Note: 1. n = 0 or 1 (lower/upper sector). 13 through Figures 16 for how the setting of the SRW bits affects the timing. this bit to zero for compatibility with future devices. Table 3. Sector limits with different settings of SRL2..0 Table 4. Wait States(1)

write these bits to zero for compatibility with future devices. When the External Memory is enabled, all Port C pins are default used for the high address byte. access all 64KB locations of the External Memory. ATmega103 compatibility mode, configuration A to the non-compatible mode. Table 5. Port C Pins Released as Normal Port Pins when the External Memory is Enabled

appear as one linear 32 KB address space from 0x1000 to 0x8FFF. Figure 17. Address Map with 32 KB External Memory

2467R–AVR–06/08 ATmega128 Using all 64KB Locations of External Memory Since the External Memory is mapped af ter the Internal Memory as shown in Figure 11 , only 60KB of External Memory is av ailable by default (address spac e 0x0000 to 0x10FF is reserved for internal memory). However, it is possible to take advantage of the entire External Memory by masking the higher address bits to zero. This can be done by using the XMMn bits and control by software the most significant bits of the address. By setting Port C to output 0x00, and releas- ing the most significant bits for normal Port Pin operation, the Memory Interface will address 0x0000 - 0x1FFF. See the following code examples. Note: 1. See “About Code Examples” on page 9. Care must be exercised using this option as most of the memory is masked away. Assembly Code Example(1) ; OFFSET is defined to 0x2000 to ensure ; external memory access ; Configure Port C (address high byte) to ; output 0x00 when the pins are released ; for normal Port Pin operation ldi r16, 0xFF out DDRC, r16 ldi r16, 0x00 out PORTC, r16 ; release PC7:5 ldi r16, (1<<XMM1)|(1<<XMM0) sts XMCRB, r16 ; write 0xAA to address 0x0001 of external ; memory ldi r16, 0xaa sts 0x0001+OFFSET, r16 ; re-enable PC7:5 for external memory ldi r16, (0<<XMM1)|(0<<XMM0) sts XMCRB, r16 ; store 0x55 to address (OFFSET + 1) of ; external memory ldi r16, 0x55 sts 0x0001+OFFSET, r16 C Code Example(1) #define OFFSET 0x2000 void XRAM_example(void) unsigned char *p = (unsigned char *) (OFFSET + 1); DDRC = 0xFF; PORTC = 0x00; XMCRB = (1<<XMM1) | (1<<XMM0); *p = 0xaa; XMCRB = 0x00; *p = 0x55;

Timer/Counter as a real-time counter even when the device is in sleep mode. ment for processing power is low. can be written run-time to vary the clock frequency as suitable to the application. when a division factor is used. clock. Otherwise, interrupts may be lost, and accessing the Timer/Counter0 registers may fail. Table 6. Device Clocking Options Select

Note: 1. For all fuses “1” means unprogrammed while “0” means programmed. start-up time. The number of WDT Oscillator cycles used for each time-out is shown in Table 7. users can make their desired clock source setting using an In-System or Parallel Programmer. Table 7. Number of Watchdog Oscillator Cycles

used to drive other clock buffers. capacitor values given by the manufacturer should be used. Figure 19. Crystal Oscillator Connections range. The operating mode is selected by the fuses CKSEL3..1 as shown in Table 8. Note: 1. This option should not be used with crystals, only with ceramic resonators. The CKSEL0 fuse together with the SUT1..0 fuses select the start-up times as shown in Table 9. Table 8. Crystal Oscillator Operating Modes

options are not suitable for crystals.

1. These options are intended for use with ceramic resonators and will ensure frequency stability

quency of the device, and if frequency stability at start-up is not important for the application. nal capacitors have a nominal value of 36 pF. Table 9. Start-up Times for the Crystal Oscillator Clock Selection Table 10. Start-up Times for the Low-frequency Crystal Oscillator Clock Selection

11 Reserved

Figure 20. External RC Configuration range. The operating mode is selected by the fuses CKSEL3..0 as shown in Table 11. Note: 1. This option should not be used when operating close to the maximum frequency of the device. Table 11. External RC Oscillator Operating Modes Table 12. Start-Up Times for the External RC Oscillator Clock Selection

components. The CKOPT fuse should always be unprogrammed when using this clock option. frequency selected, this calibration gives a frequency within ± 3% of the nominal frequency. tion “Calibration Byte” on page 289. Note: 1. The device is shipped with this option selected. Table 14. XTAL1 and XTAL2 should be left unconnected (NC). Notes: 1. The device is shipped with this option selected. Note: OSCCAL Register is not available in ATmega103 compatibility mode. in the signature row high byte (address 0x00) is automatically loaded into the OSCCAL Register. If the internal RC is used at other frequencies, the calibration values must be loaded manually. Table 13. Internal Calibrated RC Oscillator Operating Modes Table 14. Start-up Times for the Internal Calibrated RC Oscillator Clock Selection

guaranteed, as indicated in Table 15.

1. To run the device on an external clock, the CKSEL fuses must be programmed to “0000”. By

Figure 21. External Clock Drive Configuration MCU is kept in Reset during such changes in the clock frequency. Table 15. Internal RC Oscillator Frequency Range. Table 16. Start-up Times for the External Clock Selection

2467R–AVR–06/08 ATmega128 Timer/Counter Oscillator For AVR microcontrollers with Timer/Counter Oscillator pins (TOSC1 and TOSC2), the crystal is connected directly between the pins. No external capacitors are needed. The Oscillator is opti- mized for use with a 32.768 kHz watch crystal. Ap plying an external cl ock source to TOSC1 is not recommended. Note: The Timer/Counter Oscillator uses the same ty pe of crystal oscillator as Low-Frequency Oscillator and the internal capacitors have the same nominal value of 36 pF .

tion to the application’s requirements. the MCU wakes up and executes from the Reset Vector. tion. The figure is helpful in selecting an appropriate sleep mode. The MCU Control Register contains control bits for power management. execution of the SLEEP instruction and to clear it immediately after waking up. These bits select between the six available sleep modes as shown in Table 17. Table 17. Sleep Mode Select

000 I d l e

010 P o w e r - d o w n

011 P o w e r - s a v e

100 R e s e r v e d

101 R e s e r v e d

110 S t a n d b y

2467R–AVR–06/08 ATmega128 Idle Mode When the SM2..0 bits are written to 000, the SLEEP instruction makes the MCU enter Idle mode, stopping the CPU but allowing SPI, USART, Analog Comparator, ADC, Two-wire Serial Interface, Timer/Counters, Watchdog, and the interrupt system to continue operating. This sleep mode basically halts clk CPU and clkFLASH, while allowing the other clocks to run. Idle mode enables the MCU to wake up from external triggered interrupts as well as internal ones like the Timer Overflow and USART Transmit Complete interrupts. If wake-up from the Analog Comparator interrupt is not required, the Analog Comparator can be powered down by setting the ACD bit in the Analog Comparator Control and Status Register – ACSR. This will reduce power consumption in Idle mode. If t he ADC is enabled, a conversion starts automati- cally when this mode is entered. ADC Noise Reduction Mode When the SM2..0 bits are written to 001, the SLEEP instruction makes the MCU enter ADC Noise Reduction mode, stopping the CPU but allowing the ADC, the External Interrupts, the Two-wire Serial Interface address watch, Timer/Counter0 and the Watchdog to continue operating (if enabled). This sleep mode basically halts clk I/O, clkCPU, and clkFLASH, while allowing the other clocks to run. This improves the noise environment for the AD C, enabling higher resolution measurements. If the ADC is enabled, a conversion starts automatically when this mode is entered. Apart form the ADC Conversion Complete interrupt, only an External Reset, a Watchdog Reset, a Brown-out Reset, a Two-wire Serial Interface address match interrupt, a Timer/Counter0 interrupt, an SPM/EEPROM ready interrupt, an External Level Interrupt on INT7:4, or an External Interrupt on INT3:0 can wake up the MCU from ADC Noise Reduction mode. Power-down Mode When the SM2..0 bits are written to 010, the SLEEP instruction makes the MCU enter Power- down mode. In this mode, the External Oscillator is stopped, while the External Interrupts, the Two-wire Serial Interface address watch, and the Watchdog continue operating (if enabled). Only an External Reset, a Watchdog Reset, a Brown-out Reset, a Two-wire Serial Interface address match interrupt, an External Level Interr upt on INT7:4, or an External Interrupt on INT3:0 can wake up the MCU. This sleep mode basically halts all gener ated clocks, allowing operation of asynchronous modules only. Note that if a level triggered interrupt is used for wake-up from Power-down mode, the changed level must be held for some time to wake up the MCU. Refer to “External Interrupts” on page 90 for details. When waking up from Power-down mode, there is a delay from the wake-up condition occurs until the wake-up becomes effective. This allows the clock to restart and become stable after having been stopped. The wake-up period is defined by the same CKSEL fuses that define the Reset Time-out period, as described in “Clock Sources” on page 37. Power-save Mode When the SM2..0 bits are written to 011, the SLEEP instruction makes the MCU enter Power- save mode. This mode is identical to Power-down, with one exception: If Timer/Counter0 is clocked as ynchronously, i.e., the AS0 bit in ASSR is set, Timer/Counter0 will run during sleep. The device can wake up from either Timer Overflow or Output Compare event from Timer/Counter0 if the corresponding Timer/Counter0 interrupt enable bits are set in TIMSK, and the global interrupt enable bit in SREG is set. If the Asynchronous Timer is NOT clocked asynchronously, Power-down mode is recommended instead of Power-save mode because the contents of the registers in the asynchronous timer should be considered undefined after wake-up in Power-save mode if AS0 is 0. This sleep mode basically halts all clocks except clk ASY, allowing operation only of asynchronous modules, including Timer/Counter0 if clocked asynchronously.

mode, the device wakes up in six clock cycles.

1. If AS 0 bit in ASSR is set
2. Only INT3:0 or level interrupt INT7:4

Table 18. Active Clock Domains and Wake Up Sources in the Different Sleep Modes

2467R–AVR–06/08 ATmega128 Minimizing Power Consumption There are several issues to consider when trying to minimize the power consumption in an AVR controlled system. In general, sleep modes should be used as much as possible, and the sleep mode should be selected so that as few as possi ble of the device’s functions are operating. All functions not needed should be disabled. In particular, the following modules may need special consideration when trying to achieve the lowest possible power consumption. Analog to Digital Converter If enabled, the ADC will be enabled in all sleep modes. To save power, the ADC should be dis- abled before entering any sleep mode. When the ADC is turned off and on again, the next conversion will be an extended conversion. Refer to “Analog to Digital Converter” on page 230 for details on ADC operation. Analog Comparator When entering Idle mode, the Analog Comparator should be disabled if not used. When entering ADC Noise Reduction mode, the Analog Comparat or should be disabled. In the other sleep modes, the Analog Comparator is automatically di sabled. However, if the Analog Comparator is set up to use the Internal Voltage Reference as input, the Analog Comparator should be dis- abled in all sleep modes. Ot herwise, the Internal Volt age Reference will be enabled, independent of sleep mode. Refer to “Analog Comparator” on page 227 for details on how to configure the Analog Comparator. Brown-out Detector If the Brown-out Detector is not needed in the application, this module should be turned off. If the Brown-out Detector is enabled by the BODEN fuse, it will be enabled in all sleep modes, and hence, always consume power. In the deeper slee p modes, this will contribute significantly to the total current consumption. Refer to “Brown-out Detector” on page 48 for details on how to configure the Brown-out Detector. Internal Voltage Reference The Internal Voltage Referenc e will be enabled when needed by the Brown-out Detector, the Analog Comparator or the ADC. If these modules are disabled as described in the sections above, the internal voltage reference will be disabled and it w ill not be consuming power. When turned on again, the user must allow the reference to start up before the output is used. If the reference is kept on in sleep mode, the output can be used immediately. Refer to “Internal Volt- age Reference” on page 54 for details on the start-up time. Watchdog Timer If the Watchdog Timer is not needed in the application, this module should be turned off. If the Watchdog Timer is enabled, it will be enabled in all sleep modes, and hence, always consume power. In the deeper sleep modes, this will contribute signific antly to the total current consump- tion. Refer to “Watchdog Timer” on page 55 for details on how to configure the Watchdog Timer. Port Pins When entering a sleep mode, all port pins should be configured to use minimum power. The most important thing is then to ensure that no pins drive resistive loads. In sleep modes where the both the I/O clock (clk I/O) and the ADC clock (clk ADC) are stopped, the input buffers of the device will be disabled. This ensures that no power is consumed by the input logic when not needed. In some cases, the input logic is needed for detecting wake-up conditions, and it will then be enabled. Refer to the section “Digital Input Enable and Sleep Modes” on page 70 for details on which pins are enabled. If the input buffer is enabled and the input signal is left floating or have an analog signal level close to V CC/2, the input buffer will use excessive power.

2467R–AVR–06/08 ATmega128 JTAG Interface and On-chip Debug System If the On-chip debug system is enabled by the OCDEN Fuse and the chip enter Power down or Power save sleep mode, the main clock source remains enabled. In these sleep modes, this will contribute significantly to the total current c onsumption. There are three alternative ways to avoid this:  Disable OCDEN Fuse.  Disable JTAGEN Fuse.  Write one to the JTD bit in MCUCSR. The TDO pin is left floating when the JTAG interface is enabled while the JTAG TAP controller is not shifting data. If the hardware connected to t he TDO pin does not pull up the logic level, power consumption will increase. Note that the TDI pin for the next device in the scan chain con- tains a pull-up that avoids this problem. Writi ng the JTD bit in the MCUCSR register to one or leaving the JTAG fuse unprogrammed disables the JTAG interface.

2467R–AVR–06/08 ATmega128 System Control and Reset Resetting the AVR During Reset, all I/O registers are set to their initial values, and the program starts execution from the Reset Vector. The instruction placed at the Reset Vector must be a JMP – absolute jump – instruction to the reset handling routine. If the program never enables an interrupt source, the interrupt vectors are not used, and regular program code can be placed at these locations. This is also the case if the Reset Vector is in the Application section while the interrupt vectors are in the Boot section or vice versa. The circuit diagram in Figure 22 shows the reset logic. Table 19 defines the electrical parameters of the reset circuitry. The I/O ports of the AVR are immediately reset to their initial state when a reset source goes active. This does not require any clock source to be running. After all reset sources have gone inactive, a delay counter is invoked, stretching the internal reset. This allows the power to reach a stable level before normal operation starts. The time-out period of the delay counter is defined by the user through the CKSEL fuses. The different selec- tions for the delay period are presented in “Clock Sources” on page 37. Reset Sources The ATmega128 has five sources of reset:  Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (V POT).  External Reset. The MCU is reset wh en a low level is present on the RESET pin for longer than the minimum pulse length.  Watchdog Reset. The MCU is reset when the Watchdog Timer period expires and the Watchdog is enabled.  Brown-out Reset. The MCU is reset when the supply voltage V CC is below the Brown-out Reset threshold (VBOT) and the Brown-out Detector is enabled.  JTAG AVR Reset. The MCU is reset as long as there is a logic one in the Reset Register, one of the scan chains of the JTAG system. Refer to the section “IEEE 1149.1 (JTAG) Boundary-scan” on page 252 for details.

Figure 22. Reset Logic Table 19. Reset Characteristics

55 for details on operation of the Watchdog Timer. Figure 27. Watchdog Reset During Operation Note that only EXTRF and PORF are available in ATmega103 compatibility mode. This bit is set if a Power-on Reset occurs. The bit is reset only by writing a logic zero to the flag. occurs, the source of the reset can be found by examining the reset flags. erence to the ADC is generated from the internal bandgap reference.

1. When the BOD is enabled (by programming the BODEN fuse).
2. When the bandgap reference is connected to the Analog Comparator (by setting the

conditions above to ensure that the reference is turned off before entering Power-down mode. Timer. The Watchdog Timer is also reset when it is disabled and when a Chip Reset occurs. Reset Vector. For timing details on the Watchdog Reset, refer to page 54. different safety levels are selected by the Fuses M103C and WDTON as shown in Table 21. the Watchdog Timer” on page 58 for details. Table 20. Internal Voltage Reference Characteristics

Figure 28. Watchdog Timer These bits are reserved bits in the ATmega128 and will always read as zero. Configuration of the Watchdog Timer” on page 58. Table 21. WDT Configuration as a Function of the Fuse Settings of M103C and WDTON.

1. In the same operation, write a logic one to WDCE and WDE. A logic one must be written

to WDE even though it is set to one before the disable operation starts.

1. Within the next four clock cycles, write a logic 0 to WDE. This disables the Watchdog.

Table 22. Watchdog Timer Prescale Select

2467R–AVR–06/08 ATmega128 The following code example shows one assembly and one C function for turning off the WDT. The example assumes that interrupts are controlled (e.g. by disabling interrupts globally) so that no interrupts will occur during execution of these functions. Timed Sequences for Changing the Configuration of the Watchdog Timer The sequence for changing configuration differs s lightly between the three safety levels. Sepa- rate procedures are described for each level. Safety Level 0 This mode is compatible with the Watchdog operation found in ATmega103. The Watchdog Timer is initially disabled, but can be enabled by writing the WDE bit to 1 without any restriction. The time-out period can be changed at any time without restriction. To disable an enabled Watchdog Timer, the procedure described on page 56 (WDE bit description) must be followed. Safety Level 1 In this mode, the Watchdog Timer is initially disabled, but can be enabled by writing the WDE bit to 1 without any restriction. A timed sequence is needed when changing the Watchdog Time-out period or disabling an enabled Watchdog Timer. To disable an enabled Watchdog Timer, and/or changing the Watchdog Time-out, the following procedure must be followed: 1. In the same operation, write a logic one to WDCE and WDE. A logic one must be written to WDE regardless of the previous value of the WDE bit. 2. Within the next four clock cycles, in the same operation, write the WDE and WDP bits as desired, but with the WDCE bit cleared. Safety Level 2 In this mode, the Watchdog Timer is always enabled, and the WDE bit will always read as one. A timed sequence is needed when changing the Watchdog Time-out period. To change the Watchdog Time-out, the following procedure must be followed: Assembly Code Example WDT_off: ; Reset WDT wdr in r16, WDTCR ; Write logical one to WDCE and WDE ori r16, (1<<WDCE)|(1<<WDE) out WDTCR, r16 ; Turn off WDT ldi r16, (0<<WDE) out WDTCR, r16 ret C Code Example void WDT_off(void) /* Reset WDT*/ __watchdog_reset(); /* Write logical one to WDCE and WDE */ WDTCR |= (1<<WDCE) | (1<<WDE); /* Turn off WDT */ WDTCR = 0x00;

2467R–AVR–06/08 ATmega128 1. In the same operation, write a logical one to WDCE and WDE. Even though the WDE always is set, the WDE must be written to one to start the timed sequence. 2. Within the next four clock cycles, in the same operation, write the WDP bits as desired, but with the WDCE bit cleared. The value written to the WDE bit is irrelevant.

2467R–AVR–06/08 ATmega128 Interrupts This section describes the specifics of the interrupt handling as performed in ATmega128. For a general explanation of the AVR interrupt handling, refer to “Reset and Interrupt Handling” on page 15. Interrupt Vectors in ATmega128 Table 23. Reset and Interrupt Vectors Vector No. Program Address(2) Source Interrupt Definition 1 $0000 (1) RESET External Pin, Power-on Reset, Brown-out Reset, Watchdog Reset, and JTAG AVR Reset 2 $0002 INT0 External Interrupt Request 0 3 $0004 INT1 External Interrupt Request 1 4 $0006 INT2 External Interrupt Request 2 5 $0008 INT3 External Interrupt Request 3 6 $000A INT4 External Interrupt Request 4 7 $000C INT5 External Interrupt Request 5 8 $000E INT6 External Interrupt Request 6 9 $0010 INT7 External Interrupt Request 7 10 $0012 TIMER2 COMP Timer/ Counter2 Compare Match 11 $0014 TIMER2 OVF Timer/Counter2 Overflow 12 $0016 TIMER1 CAPT Timer/Counter1 Capture Event 13 $0018 TIMER1 COMPA Timer/Counter1 Compare Match A 14 $001A TIMER1 COMPB Timer/Counter1 Compare Match B 15 $001C TIMER1 OVF Timer/Counter1 Overflow 16 $001E TIMER0 COMP Timer/ Counter0 Compare Match 17 $0020 TIMER0 OVF Timer/Counter0 Overflow 18 $0022 SPI, STC SPI Serial Transfer Complete 19 $0024 USART0, RX USART0, Rx Complete 20 $0026 USART0, UDRE USART0 Data Register Empty 21 $0028 USART0, TX USART0, Tx Complete 22 $002A ADC ADC Conversion Complete 23 $002C EE READY EEPROM Ready 24 $002E ANALOG COMP Analog Comparator 25 $0030 (3) TIMER1 COMPC Timer/Countre1 Compare Match C 26 $0032 (3) TIMER3 CAPT Timer/Counter3 Capture Event 27 $0034 (3) TIMER3 COMPA Timer/Counter3 Compare Match A 28 $0036 (3) TIMER3 COMPB Timer/Counter3 Compare Match B 29 $0038 (3) TIMER3 COMPC Timer/Counter3 Compare Match C 30 $003A (3) TIMER3 OVF Timer/Counter3 Overflow

reset, see “Boot Loader Support – Read-While-Write Self-Programming” on page 273.

1. When the IVSEL bit in MCUCR is set, interrupt vectors will be moved to the start of the Boot

the start address of the boot Flash section.

1. The Interrupts on address $0030 - $0044 do not exist in ATmega103 compatibility mode.

unprogrammed while “0” means programmed. Table 24. Reset and Interrupt Vectors Placement Table 23. Reset and Interrupt Vectors (Continued)

2467R–AVR–06/08 ATmega128 The most typical and general program setup for the Reset and Interrupt Vector Addresses in ATmega128 is: Address LabelsCode Comments $0000 jmp RESET ; Reset Handler $0002 jmp EXT_INT0 ; IRQ0 Handler $0004 jmp EXT_INT1 ; IRQ1 Handler $0006 jmp EXT_INT2 ; IRQ2 Handler $0008 jmp EXT_INT3 ; IRQ3 Handler $000A jmp EXT_INT4 ; IRQ4 Handler $000C jmp EXT_INT5 ; IRQ5 Handler $000E jmp EXT_INT6 ; IRQ6 Handler $0010 jmp EXT_INT7 ; IRQ7 Handler $0012 jmp TIM2_COMP ; Timer2 Compare Handler $0014 jmp TIM2_OVF ; Timer2 Overflow Handler $0016 jmp TIM1_CAPT ; Timer1 Capture Handler $0018 jmp TIM1_COMPA; Timer1 CompareA Handler $001A jmp TIM1_COMPB; Timer1 CompareB Handler $001C jmp TIM1_OVF ; Timer1 Overflow Handler $001E jmp TIM0_COMP ; Timer0 Compare Handler $0020 jmp TIM0_OVF ; Timer0 Overflow Handler $0022 jmp SPI_STC ; SPI Transfer Complete Handler $0024 jmp USART0_RXC; USART0 RX Complete Handler $0026 jmp USART0_DRE; USART0,UDR Empty Handler $0028 jmp USART0_TXC; USART0 TX Complete Handler $002A jmp ADC ; ADC Conversion Complete Handler $002C jmp EE_RDY ; EEPROM Ready Handler $002E jmp ANA_COMP ; Analog Comparator Handler $0030 jmp TIM1_COMPC; Timer1 CompareC Handler $0032 jmp TIM3_CAPT ; Timer3 Capture Handler $0034 jmp TIM3_COMPA; Timer3 CompareA Handler $0036 jmp TIM3_COMPB; Timer3 CompareB Handler $0038 jmp TIM3_COMPC; Timer3 CompareC Handler $003A jmp TIM3_OVF ; Timer3 Overflow Handler $003C jmp USART1_RXC; USART1 RX Complete Handler $003E jmp USART1_DRE; USART1,UDR Empty Handler $0040 jmp USART1_TXC; USART1 TX Complete Handler $0042 jmp TWI ; Two-wire Serial Interface Interrupt Handler $0044 jmp SPM_RDY ; SPM Ready Handler $0046 RESET:ldir16, high(RAMEND); Main program start $0047 out SPH,r16 ; Set stack pointer to top of RAM $0048 ldi r16, low(RAMEND) $0049 out SPL,r16 $004A sei ; Enable interrupts $004B <instr> xxx

2467R–AVR–06/08 ATmega128 When the BOOTRST fuse is unprogrammed, the Boot section size set to 8K bytes and the IVSEL bit in the MCUCR Register is set before an y interrupts are enabled, the most typical and general program setup for the Reset and Interrupt Vector Addresses is: Address LabelsCode Comments $0000 RESET:ldi r16,high(RAMEND); Main program start $0001 out SPH,r16 ; Set stack pointer to top of RAM $0002 ldi r16,low(RAMEND) $0003 out SPL,r16 $0004 sei ; Enable interrupts $0005 <instr> xxx .org $F002 $F002 jmp EXT_INT0 ; IRQ0 Handler $F004 jmp EXT_INT1 ; IRQ1 Handler $F044 jmp SPM_RDY ; Store Program Memory Ready Handler When the BOOTRST fuse is programmed and the Boot section size set to 8K bytes, the most typical and general program setup for the Reset and Interrupt Vector Addresses is: Address LabelsCode Comments .org $0002 $0002 jmp EXT_INT0 ; IRQ0 Handler $0004 jmp EXT_INT1 ; IRQ1 Handler $0044 jmp SPM_RDY ; Store Program Memory Ready Handler .org $F000 $F000 RESET: ldi r16,high(RAMEND); Main program start $F001 out SPH,r16 ; Set stack pointer to top of RAM $F002 ldi r16,low(RAMEND) $F003 out SPL,r16 $F004 sei ; Enable interrupts $F005 <instr> xxx When the BOOTRST fuse is programmed, the Boot section size set to 8K bytes and the IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and Interrupt Vector Addresses is: Address Labels Code Comments .org $F000 $F000 jmp RESET ; Reset handler $F002 jmp EXT_INT0 ; IRQ0 Handler $F004 jmp EXT_INT1 ; IRQ1 Handler $F044 jmp SPM_RDY ; Store Program Memory Ready Handler $F046 RESET: ldi r16,high(RAMEND); Main program start $F047 out SPH,r16 ; Set stack pointer to top of RAM $F048 ldi r16,low(RAMEND)

2467R–AVR–06/08 ATmega128 $F049 out SPL,r16 $F04A sei ; Enable interrupts $F04B <instr> xxx Moving Interrupts Between Application and Boot Space The General Interrupt Control Register controls the placement of the interrupt vector table. MCU Control Register – MCUCR  Bit 1 – IVSEL: Interrupt Vector Select When the IVSEL bit is cleared (zero), the interrupt vectors are placed at the start of the Flash memory. When this bit is set (one), the interrupt vectors are moved to the beginning of the Boot Loader section of the flash. The actual address of the start of the Boot Flash section is deter- mined by the BOOTSZ fuses. Refer to the section “Boot Loader Support – Read-While-Write Self-Programming” on page 273 for details. To avoid unintentional changes of interrupt vector tables, a special write procedure must be followed to change the IVSEL bit: 1. Write the Interrupt Vector Change Enable (IVCE) bit to one. 2. Within four cycles, write the desired valu e to IVSEL while writing a zero to IVCE. Interrupts will automatically be disabled while this sequence is executed. Interrupts are disabled in the cycle IVCE is set, and they remain disabl ed until after the instruction following the write to IVSEL. If IVSEL is not written, interrupts remain disabled for four cycles. The I-bit in the Status Register is unaffected by the automatic disabling. Note: If interrupt vectors are placed in the Boot L oader section and Boot Lock bit BLB02 is programmed, interrupts are disabled while executing from the Application section. If interrupt vectors are placed in the Application section and Boot Lock bit BLB12 is programed, interrupts are disabled while executing from the Boot Loader section. Refer to the section “Boot Loader Support – Read-While- Write Self-Programming” on page 273 for details on Boot Lock bits. B i t 76543210 SRE SRW10 SE SM1 SM0 SM2 IVSEL IVCE MCUCR Read/Write R/W R/W R/W R/W R/W R/W R/W R/W I n i t i a l V a l u e 00000000

2467R–AVR–06/08 ATmega128  Bit 0 – IVCE: Interrupt Vector Change Enable The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is cleared by hardware four cycles after it is written or when IVSEL is written. Setting the IVCE bit will disable interrupts, as explained in the IVSEL description above. See Code Example below. Assembly Code Example Move_interrupts: ; Enable change of interrupt vectors ldi r16, (1<<IVCE) out MCUCR, r16 ; Move interrupts to boot flash section ldi r16, (1<<IVSEL) out MCUCR, r16 ret C Code Example void Move_interrupts(void) /* Enable change of interrupt vectors */ MCUCR = (1<<IVCE); /* Move interrupts to boot flash section */ MCUCR = (1<<IVSEL);

Introduction All AVR ports have true Read-Modi fy-Write functionality when used as general digital I/O ports. teristics” on page 318 for a complete list of parameters. Figure 29. I/O Pin Equivalent Schematic ters and bit locations are listed in “Register Description for I/O Ports” on page 87. I/O location is read only, while the Data Register and the Data Direction Register are read/write.

1. Most port pins are multiplexed with alternate functions for the peripheral features on the

other pins in the port as General Digital I/O.

description of one I/O port pin, here generically called Pxn. Figure 30. General Digital I/O(1) and PUD are common to all ports. PORTxn bits at the PORTx I/O address, and the PINxn bits at the PINx I/O address. active, even if no clocks are running.

disable all pull-ups in all ports. = 0b11) as an intermediate step. Table 25 summarizes the control signals for the pin value. pd,max and tpd,min respectively. Figure 31. Synchronization when Reading an Externally Applied Pin Value Table 25. Port Pin Configurations

between ½ and 1½ system clock period depending upon the time of assertion. clock. In this case, the delay tpd through the synchronizer is one system clock period. Figure 32. Synchronization when Reading a Software Assigned Pin Value

2467R–AVR–06/08 ATmega128 The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, and define the port pins from 4 to 7 as input with pull-ups assigned to port pins 6 and 7. The resulting pin values are read back again, but as previously discussed, a nop instruction is included to be able to read back the value recently assigned to some of the pins. Note: 1. For the assembly program, two temporary re gisters are used to minimize the time from pull- ups are set on pins 0, 1, 6, and 7, until the di rection bits are correctly set, defining bit 2 and 3 as low and redefining bits 0 and 1 as strong high drivers. Digital Input Enable and Sleep Modes As shown in Figure 30 , the digital input signal can be clamped to ground at the input of the schmitt-trigger. The signal denot ed SLEEP in the figure, is set by the MCU Sleep Controller in Power-down mode, Power-save mode, Standby mode, and Extended Standby mode to avoid high power consumption if some input signals are left floating, or have an analog signal level close to V CC/2. SLEEP is overridden for port pins enabled as Exte rnal Interrupt pins. If the External Interrupt Request is not enabled, SLEEP is active also fo r these pins. SLEEP is also overridden by vari- ous other alternate functions as described in “Alternate Port Functions” on page 71. If a logic high level (“one”) is present on an Asynchronous External Interrupt pin configured as “Interrupt on Rising Edge, Falling Edge, or Any Logic Change on Pin” while the external interrupt is not enabled, the corresponding External Interrupt Flag will be set when resuming from the above mentioned sleep modes, as the clamping in these sleep modes produces the requested logic change. Assembly Code Example (1) ... ; Define pull-ups and set outputs high ; Define directions for port pins out PORTB,r16 out DDRB,r17 ; Insert nop for synchronization nop ; Read port pins in r16,PINB ... C Code Example(1) unsigned char i; ... /* Define pull-ups and set outputs high */ /* Define directions for port pins */ /* Insert nop for synchronization*/ __no_operation(); /* Read port pins */ i = PINB; ...

inputs are enabled (Reset, Active mode and Idle mode). The simplest method to ensure a defined level of an unused pin, is to enable the internal pull-up. accidentally configured as an output. generic description applicable to all port pins in the AVR microcontroller family. Figure 33. Alternate Port Functions and PUD are common to all ports. All other signals are unique for each pin.

the modules having the alternate function. Table 26. Generic Description of Overriding Signals for Alternate Functions. enabled when {DDxn, PORTxn, PUD} = 0b010. DDxn, PORTxn, and PUD Register bits. driver is enabled by the DDxn Register bit. is controlled by the PORTxn Register bit. the setting of the PORTxn Register bit. alternate function will use its own synchronizer. This is the Analog Input/output to/from alternate functions.

figuring the Pin” on page 67 for more details about this feature. nal Memory Interface” on page 26 for details. Table 27. Port A Pins Alternate Functions Table 28. Overriding Signals for Alternate Functions in PA7..PA4

The Port B pins with alternate functions are shown in Table 30. Note: 1. OC1C not applicable in ATmega103 compatibility mode. serve this function. The OC2 pin is also the output pin for the PWM mode timer function. to serve this function. The OC1C pin is also the output pin for the PWM mode timer function. Table 29. Overriding Signals for Alternate Functions in PA3..PA0 Table 30. Port B Pins Alternate Functions

2467R–AVR–06/08 ATmega128  OC1B, Bit 6 OC1B, Output Compare Match B output: The PB6 pin can serve as an external output for the Timer/Counter1 Output Compare B. The pin has to be configured as an output (DDB6 set (one)) to serve this function. The OC1B pin is also the output pin for the PWM mode timer function.  OC1A, Bit 5 OC1A, Output Compare Match A output: The PB5 pin can serve as an external output for the Timer/Counter1 Output Compare A. The pin has to be configured as an output (DDB5 set (one)) to serve this function. The OC1A pin is also the output pin for the PWM mode timer function.  OC0, Bit 4 OC0, Output Compare Match output: The PB4 pin can serve as an external output for the Timer/Counter0 Output Compare. The pin has to be configured as an output (DDB4 set (one)) to serve this function. The OC0 pin is also the output pin for the PWM mode timer function.  MISO – Port B, Bit 3 MISO: Master Data input, Slave Data output pin for SPI channel. When the SPI is enabled as a master, this pin is configured as an input r egardless of the setting of DDB3. When the SPI is enabled as a slave, the data direction of this pin is controlled by DDB3. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB3 bit.  MOSI – Port B, Bit 2 MOSI: SPI Master Data output, Slave Data input for SPI channel. When the SPI is enabled as a slave, this pin is configured as an input regar dless of the setting of DDB2. When the SPI is enabled as a master, the data direction of this pin is controlled by DDB2. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB2 bit.  SCK – Port B, Bit 1 SCK: Master Clock output, Slave Clock input pin for SPI channel. When the SPI is enabled as a slave, this pin is configured as an input regar dless of the setting of DDB1. When the SPI is enabled as a master, the data direction of this pin is controlled by DDB1. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB1 bit. S S – Port B, Bit 0 SS: Slave Port Select input. When the SPI is enab led as a slave, this pin is configured as an input regardless of the setting of DDB0. As a slav e, the SPI is activated when this pin is driven low. When the SPI is enabled as a master, the data di rection of this pin is controlled by DDB0. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB0 bit. Table 31 and Table 32 relate the alternate functions of Port B to the overriding signals shown in Figure 33 on page 71. SPI MSTR INPUT and SPI SLAVE OUTP UT constitute the MISO signal, while MOSI is divided into SPI MSTR OUTPUT and SPI SLAVE INPUT.

ATmega103 compatibility mode. Table 31. Overriding Signals for Alternate Functions in PB7..PB4 Table 32. Overriding Signals for Alternate Functions in PB3..PB0

Note: 1. XMM = 0 in ATmega103 compatibility mode. Table 33. Port C Pins Alternate Functions Table 34. Overriding Signals for Alternate Functions in PC7..PC4

Note: 1. XMM = 0 in ATmega103 compatibility mode. The Port D pins with alternate functions are shown in Table 36. Note: 1. XCK1, TXD1, RXD1, SDA, and SCL not applicable in ATmega103 compatibility mode. T2, Timer/Counter2 counter source. T1, Timer/Counter1 counter source. operates in Synchronous mode. Table 35. Overriding Signals for Alternate Functions in PC3..PC0(1) Table 36. Port D Pins Alternate Functions

2467R–AVR–06/08 ATmega128  ICP1 – Port D, Bit 4 ICP1 – Input Capture Pin1: The PD4 pin can act as an Input Capture Pin for Timer/Counter1.  INT3/TXD1 – Port D, Bit 3 INT3, External Interrupt source 3: The PD3 pin c an serve as an external interrupt source to the MCU. TXD1, Transmit Data (Data output pin for t he USART1). When the USART1 Transmitter is enabled, this pin is configured as an output regardless of the value of DDD3.  INT2/RXD1 – Port D, Bit 2 INT2, External Interrupt source 2. The PD2 pin can serve as an External Interrupt source to the MCU. RXD1, Receive Data (Data input pin for the U SART1). When the USART1 receiver is enabled this pin is configured as an input regardless of the value of DDD2. When the USART forces this pin to be an input, the pull-up can still be controlled by the PORTD2 bit.  INT1/SDA – Port D, Bit 1 INT1, External Interrupt source 1. The PD1 pin c an serve as an external interrupt source to the MCU. SDA, Two-wire Serial Interface Data: When the TWEN bit in TWCR is set (one) to enable the Two-wire Serial Interface, pin PD1 is disconnected from the port and becomes the Serial Data I/O pin for the Two-wire Serial Interface. In this mode, there is a spike filter on the pin to sup- press spikes shorter than 50 ns on the input signal, and the pin is driven by an open drain driver with slew-rate limitation. I N T 0 / S C L – P o r t D , B i t 0 INT0, External Interrupt source 0. The PD0 pin c an serve as an external interrupt source to the MCU. SCL, Two-wire Serial Interface Clock: When the TWEN bit in TWCR is set (one) to enable the Two-wire Serial Interface, pin PD0 is disconnec ted from the port and bec omes the Serial Clock I/O pin for the Two-wire Serial Interface. In this mode, there is a spike filter on the pin to sup- press spikes shorter than 50 ns on the input signal, and the pin is driven by an open drain driver with slew-rate limitation. Table 37 and Table 38 relates the alternate functions of Port D to the overriding signals shown in Figure 33 on page 71.

the AIO outputs shown in the port figure and the digital logic of the TWI module. Table 37. Overriding Signals for Alternate Functions PD7..PD4 Table 38. Overriding Signals for Alternate Functions in PD3..PD0(1)

The Port E pins with alternate functions are shown in Table 39. INT7, External Interrupt source 7: The PE7 pin can serve as an external interrupt source. ICP3 – Input Capture Pin3: The PE7 pin can act as an Input Capture Pin for Timer/Counter3. INT6, External Interrupt source 6: The PE6 pin can serve as an external interrupt source. T3, Timer/Counter3 counter source. INT5, External Interrupt source 5: The PE5 pin can serve as an External Interrupt source. to serve this function. The OC3C pin is also the output pin for the PWM mode timer function. INT4, External Interrupt source 4: The PE4 pin can serve as an External Interrupt source. to serve this function. The OC3B pin is also the output pin for the PWM mode timer function. to serve this function. The OC3A pin is also the output pin for the PWM mode timer function. Table 39. Port E Pins Alternate Functions

operates in Synchronous mode. used as data output line for the ATmega128. as data input line for the ATmega128. USART0 receiver is enabled this pin is configured as an input regardless of the value of DDRE0. Table 40. Overriding Signals for Alternate Functions PE7..PE4

PF5(TMS), and PF4(TCK) will be activated even if a Reset occurs. ister (scan chains). When the JTAG interface is enabled, this pin can not be used as an I/O pin. ADC6, Analog to Digital Converter, Channel 6. the JTAG interface is enabled, this pin can not be used as an I/O pin. The TDO pin is tri-stated unless TAP states that shift out data are entered. ADC5, Analog to Digital Converter, Channel 5. Table 41. Overriding Signals for Alternate Functions in PE3..PE0 Table 42. Port F Pins Alternate Functions

machine. When the JTAG interface is enabled, this pin can not be used as an I/O pin. ADC4, Analog to Digital Converter, Channel 4. enabled, this pin can not be used as an I/O pin. Analog to Digital Converter, Channel 3..0. Table 43. Overriding Signals for Alternate Functions in PF7..PF4 Table 44. Overriding Signals for Alternate Functions in PF3..PF0

pin can not be used as an I/O pin. the pin can not be used as an I/O pin. ALE is the external data memory Address Latch Enable signal. RD is the external data memory read control strobe. WR is the external data memory write control strobe. Table 45. Port G Pins Alternate Functions Table 46. Overriding Signals for Alternate Functions in PG4..PG1

Table 47. Overriding Signals for Alternate Functions in PG0

2467R–AVR–06/08 ATmega128 Register Description for I/O Ports Port A Data Register – PORTA Port A Data Direction Register – DDRA Port A Input Pins Address – PINA Port B Data Register – PORTB Port B Data Direction Register – DDRB Port B Input Pins Address – PINB Port C Data Register – PORTC Port C Data Direction Register – DDRC B i t 76543210 PORTA7 PORTA6 PORTA5 PORTA4 PORTA3 PORTA2 PORTA1 PORTA0 PORTA Read/Write R/W R/W R/W R/W R/W R/W R/W R/W I n i t i a l V a l u e 00000000 B i t 76543210 DDA7 DDA6 DDA5 DDA4 DDA3 DDA2 DDA1 DDA0 DDRA Read/Write R/W R/W R/W R/W R/W R/W R/W R/W I n i t i a l V a l u e 00000000 B i t 7 6543210 PINA7 PINA6 PINA5 PINA4 PI NA3 PINA2 PINA1 PINA0 PINA R e a d / W r i t e R RRRRRRR Initial Value N/A N/A N/A N/A N/A N/A N/A N/A B i t 76543210 PORTB7 PORTB6 PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 PORTB Read/Write R/W R/W R/W R/W R/W R/W R/W R/W I n i t i a l V a l u e 00000000 B i t 76543210 DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 DDRB Read/Write R/W R/W R/W R/W R/W R/W R/W R/W I n i t i a l V a l u e 00000000 B i t 76543210 PINB7 PINB6 PINB5 PINB4 PI NB3 PINB2 PINB1 PINB0 PINB R e a d / W r i t e RRRRRRRR Initial Value N/A N/A N/A N/A N/A N/A N/A N/A B i t 76543210 PORTC7 PORTC6 PORTC5 PORTC4 PORTC3 PORTC2 PORTC1 PORTC0 PORTC Read/Write R/W R/W R/W R/W R/W R/W R/W R/W I n i t i a l V a l u e 00000000 B i t 76543210 DDC7 DDC6 DDC5 DDC4 DDC3 DDC2 DDC1 DDC0 DDRC Read/Write R/W R/W R/W R/W R/W R/W R/W R/W I n i t i a l V a l u e 00000000

2467R–AVR–06/08 ATmega128 Port C Input Pins Address – PINC In ATmega103 compatibility mode, DDRC and PINC Registers are initialized to being Push-Pull Zero Output. The port pins assumes their initial value, even if the clock is not running. Note that the DDRC and PINC Registers are available in ATmega103 compatibility mode, and should not be used for 100% back-ward compatibility. Port D Data Register – PORTD Port D Data Direction Register – DDRD Port D Input Pins Address – PIND Port E Data Register – PORTE Port E Data Direction Register – DDRE Port E Input Pins Address – PINE Port F Data Register – PORTF B i t 76543210 PINC7 PINC6 PINC5 PINC4 PI NC3 PINC2 PINC1 PINC0 PINC R e a d / W r i t e RRRRRRRR Initial Value N/A N/A N/A N/A N/A N/A N/A N/A B i t 76543210 PORTD7 PORTD6 PORTD5 PORTD4 PORTD3 PORTD2 PORTD1 PORTD0 PORTD Read/Write R/W R/W R/W R/W R/W R/W R/W R/W I n i t i a l V a l u e 00000000 B i t 76543210 DDD7 DDD6 DDD5 DDD4 DDD3 DDD2 DDD1 DDD0 DDRD Read/Write R/W R/W R/W R/W R/W R/W R/W R/W I n i t i a l V a l u e 00000000 B i t 76543210 PIND7 PIND6 PIND5 PIND4 PI ND3 PIND2 PIND1 PIND0 PIND R e a d / W r i t e RRRRRRRR Initial Value N/A N/A N/A N/A N/A N/A N/A N/A B i t 76543210 PORTE7 PORTE6 PORTE5 PORTE4 PORTE3 PORTE2 PORTE1 PORTE0 PORTE Read/Write R/W R/W R/W R/W R/W R/W R/W R/W I n i t i a l V a l u e 00000000 B i t 76543210 DDE7 DDE6 DDE5 DDE4 DDE3 DDE2 DDE1 DDE0 DDRE Read/Write R/W R/W R/W R/W R/W R/W R/W R/W I n i t i a l V a l u e 00000000 B i t 76543210 PINE7 PINE6 PINE5 PINE4 PINE3 PINE2 PINE1 PINE0 PINF R e a d / W r i t e RRRRRRRR Initial Value N/A N/A N/A N/A N/A N/A N/A N/A B i t 76543210 PORTF7 PORTF6 PORTF5 PORTF4 PORTF3 PORTF2 PORTF1 PORTF0 PORTF Read/Write R/W R/W R/W R/W R/W R/W R/W R/W I n i t i a l V a l u e 00000000

2467R–AVR–06/08 ATmega128 Port F Data Direction Register – DDRF Port F Input Pins Address – PINF Note that PORTF and DDRF Registers are no t available in ATmega103 compatibility mode where Port F serves as digital input only. Port G Data Register – PORTG Port G Data Direction Register – DDRG Port G Input Pins Address – PING Note that PORTG, DDRG, and PING are not available in ATmega103 compatibility mode. In the ATmega103 compatibility mode Port G serves its alternate functions only (TOSC1, TOSC2, WR, RD and ALE). B i t 76543210 DDF7 DDF6 DDF5 DDF4 DDF3 DDF2 DDF1 DDF0 DDRF Read/Write R/W R/W R/W R/W R/W R/W R/W R/W I n i t i a l V a l u e 00000000 B i t 76543210 PINF7 PINF6 PINF5 PINF4 PINF3 PINF2 PINF1 PINF0 PINF R e a d / W r i t e RRRRRRRR Initial Value N/A N/A N/A N/A N/A N/A N/A N/A B i t 7 6 543210 ––– PORTG4 PORTG3 PORTG2 PORTG1 PORTG0 PORTG Read/Write R R R R/W R/W R/W R/W R/W I n i t i a l V a l u e 0 0 000000 B i t 76543210 – – – DDG4 DDG3 DDG2 DDG1 DDG0 DDRG Read/Write R R R R/W R/W R/W R/W R/W I n i t i a l V a l u e 00000000 B i t 76543210 – – – PING4 PING3 PING2 PING1 PING0 PING R e a d / W r i t e RRRRRRRR Initial Value 0 0 0 N/A N/A N/A N/A N/A

2467R–AVR–06/08 ATmega128 External Interrupts The External Interrupts are triggered by the INT7:0 pins. Observe that, if enabled, the interrupts will trigger even if the INT7:0 pins are configured as outputs. This feature provides a way of gen- erating a software interrupt. The External Interrupts can be triggered by a falling or rising edge or a low level. This is set up as indicated in the specification for the External Interrupt Control Reg- isters – EICRA (INT3:0) and EICRB (INT7:4) . When the external interrupt is enabled and is configured as level triggered, the interrupt will trigger as long as the pin is held low. Note that recognition of falling or rising edge interrupts on INT7:4 requires the presence of an I/O clock, described in “Clock Systems and their Distribution” on page 36 . Low level interrupts and the edge interrupt on INT3:0 are detected asynchronously. This implies that these interrupts can be used for waking the part also from sleep modes other than Idle mode. The I/O clock is halted in all sleep modes except Idle mode. Note that if a level triggered interrupt is used for wake-up from Power-down mode, the changed level must be held for some time to wake up the MCU. This makes the MCU less sensitive to noise. The changed level is sampled twice by the Watchdog Oscillator clock. The period of the Watchdog Oscillator is 1 µs (nominal) at 5.0V and 25°C. The frequency of the Watchdog Oscilla- tor is voltage dependent as shown in the “Electrical Characteristics” on page 318. The MCU will wake up if the input has the required level during this sampling or if it is held until the end of the start-up time. The start-up time is defined by the SUT fuses as described in “Clock Systems and their Distribution” on page 36. If the level is sampled twice by the Watchdog Oscillator clock but disappears before the end of the start-up time, the MCU will still wake up, but no interrupt will be generated. The required level must be held long enough for the MCU to complete the wake up to trigger the level interrupt. External Interrupt Control Register A – EICRA This Register can not be reached in ATmega103 compatibility mode, but the initial value defines INT3:0 as low level interrupts, as in ATmega103.  Bits 7..0 – ISC31, ISC30 – ISC00, ISC00: External Interrupt 3 - 0 Sense Control Bits The External Interrupts 3 - 0 are activated by the external pins INT3:0 if the SREG I-flag and the corresponding interrupt mask in the EIMSK is set. The level and edges on the external pins that activate the interrupts are defined in Table 48. Edges on INT3..INT0 are registered asynchro- nously. Pulses on INT3:0 pins wider than the minimum pulse width given in Table 49 will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level interrupt is selected, the low level must be held until the completion of the currently executing instruction to generate an interrupt. If enabled, a level triggered interrupt will generate an inter- rupt request as long as the pin is held low. When changing the ISCn bit, an interrupt can occur. Therefore, it is recommended to first disable INTn by clearing its Interrupt Enable bit in the EIMSK Register. Then, the ISCn bit can be changed. Finally, the INTn interrupt flag should be cleared by writing a logical one to its Interrupt Flag bit (INTFn) in the EIFR Register before the interrupt is re-enabled. B i t 76543210 ISC31 ISC30 ISC21 ISC20 ISC11 ISC10 ISC01 ISC00 EICRA Read/Write R/W R/W R/W R/W R/W R/W R/W R/W I n i t i a l V a l u e 00000000

Enable bit in the EIMSK Register. Otherwise an interrupt can occur when the bits are changed. period will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. generate an interrupt request as long as the pin is held low. Enable bit in the EIMSK Register. Otherwise an interrupt can occur when the bits are changed. Table 48. Interrupt Sense Control(1) 0 0 The low level of INTn generates an interrupt request.

01 R e s e r v e d

1 0 The falling edge of INTn generates asynchronously an interrupt request. 1 1 The rising edge of INTn generates asynchronously an interrupt request. Table 49. Asynchronous External Interrupt Characteristics Table 50. Interrupt Sense Control(1) 0 0 The low level of INTn generates an interrupt request.

10 The falling edge between two samples of INTn generates an interrupt

11 The rising edge between two samples of INTn generates an interrupt

2467R–AVR–06/08 ATmega128 External Interrupt Mask Register – EIMSK  Bits 7..0 – INT7 – INT0: External Interrupt Request 7 - 0 Enable When an INT7 – INT0 bit is written to one and the I-bit in the Status Register (SREG) is set (one), the corresponding external pin interrupt is enabled. The Interrupt Sense Control bits in the External Interrupt Control Registers – EICRA an d EICRB – defines whether the external inter- rupt is activated on rising or falling edge or level sensed. Activity on any of these pins will trigger an interrupt request even if the pin is enabled as an output. This provides a way of generating a software interrupt. External Interrupt Flag Register – EIFR  Bits 7..0 – INTF7 - INTF0: External Interrupt Flags 7 - 0 When an edge or logic change on the INT7:0 pin triggers an interrupt request, INTF7:0 becomes set (one). If the I-bit in SREG and the corresponding interrupt enable bit, INT7:0 in EIMSK, are set (one), the MCU will jump to the interrupt vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. These flags are always cleared when INT7:0 are configured as level interrupt. Note that when entering sleep mode with the INT3:0 inte rrupts disabled, the input buffers on these pins will be disabled. This may cause a logic change in internal si gnals which will set the INTF3:0 flags. See “Digital Input Enable and Sleep Modes” on page 70 for more information. B i t 76543210 INT7 INT6 INT5 INT4 INT3 INT2 INT1 IINT0 EIMSK Read/Write R/W R/W R/W R/W R/W R/W R/W R/W I n i t i a l V a l u e 00000000 B i t 76543210 INTF7 INTF6 INTF5 INTF4 INTF3 INTF2 INTF1 IINTF0 EIFR Read/Write R/W R/W R/W R/W R/W R/W R/W R/W I n i t i a l V a l u e 00000000

listed in the “8-bit Timer/Counter Register Description” on page 104. Figure 34. 8-bit Timer/Counter Block Diagram request (shorten as Int.Req.) signals are all visible in the Timer Interrupt Flag Register (TIFR). TIMSK are not shown in the figure since these registers are shared by other timer units.

which can be used to generate an output compare interrupt request. The definitions in Table 51 are also used extensively throughout the document. “Timer/Counter Prescaler” on page 110. 35 shows a block diagram of the counter and its surrounding environment. Figure 35. Counter Unit Block Diagram Table 51. Definitions BOTTOM The counter reaches the BOTTOM when it becomes zero (0x00). MAX The counter reaches its MAXimum when it becomes 0xFF (decimal 255). assignment is dependent on the mode of operation.

2467R–AVR–06/08 ATmega128 Signal description (internal signals): count Increment or decrement TCNT0 by 1. direction Selects between increment and decrement. clear Clear TCNT0 (set all bits to zero). clkT0 Timer/Counter clock. top Signalizes that TCNT0 has reached maximum value. bottom Signalizes that TCNT0 has reached minimum value (zero). Depending on the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clk T0). clkT0 can be generated from an external or internal clock source, selected by the clock select bits (CS02:0). When no clock source is selected (CS02:0 = 0) the timer is stopped. However, the TCNT0 value can be accessed by the CPU, regardless of whether clk T0 is present or not. A CPU write overrides (has priority over) all counter clear or count operations. The counting sequence is determined by the setting of the WGM01 and WGM00 bits located in the Timer/Counter Control Register (TCCR0). There are close connections between how the counter behaves (counts) and how waveforms are generated on the output compare output OC0. For more details about advanced counting sequences and waveform generation, see “Modes of Operation” on page 98. The Timer/Counter overflow (TOV0) flag is set according to the mode of operation selected by the WGM01:0 bits. TOV0 can be used for generating a CPU interrupt. Output Compare Unit The 8-bit comparator continuously compares TCNT0 with the Output Compare Register (OCR0). Whenever TCNT0 equals OCR0, the comparator signals a match. A match will set the output compare flag (OCF0) at the next timer clock cycle. If enabled (OCIE0 = 1), the output compare flag generates an output compare interrupt. The OCF0 flag is automatically cleared when the interrupt is executed. Alternatively, t he OCF0 flag can be cleared by software by writ- ing a logical one to its I/O bit location. The waveform generator uses the match signal to generate an output according to operating mode set by the WGM01:0 bits and compare output mode (COM01:0) bits. The max and bottom signals are used by the waveform generator for han- dling the special cases of the extreme values in some modes of operation (“Modes of Operation” on page 98). Figure 36 shows a block diagram of the output compare unit.

Figure 36. Output Compare Unit, Block Diagram of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free. the CPU will access the OCR0 directly. had occurred (the COM01:0 bits settings define whether the OC0 pin is set, cleared or toggled).

between waveform generation modes. Be aware that the COM01:0 bits are not double buffered together with the compare value. Changing the COM01:0 bits will take effect immediately. is for the internal OC0 Register, not the OC0 pin. Figure 37. Compare Match Output Unit, Schematic pin. The port override function is independent of the waveform generation mode. operation. See “8-bit Timer/Counter Register Description” on page 104. The waveform generator uses the COM01:0 bits differently in normal, CTC, and PWM modes. and for phase correct PWM refer to Table 55 on page 106.

match (See “Compare Match Output Unit” on page 97.). For detailed timing information refer to “Timer/Counter Timing Diagrams” on page 102. plifies the operation of counting external events. Figure 38. CTC Mode, Timing Diagram

2467R–AVR–06/08 ATmega128 value of TCNT0, the counter will miss the compare match. The counter will then have to count to its maximum value (0xFF) and wrap around starting at 0x00 before the compare match can occur. For generating a waveform output in CTC mode, the OC0 output can be set to toggle its logical level on each compare match by setting the Compare Output mode bits to Toggle mode (COM01:0 = 1). The OC0 value will not be visible on the port pin unless the data direction for the pin is set to output. The waveform generated will have a maximum frequency of f OC0 = fclk_I/O/2 when OCR0 is set to zero (0x00). The waveform frequency is defined by the following equation: The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024). As for the normal mode of operation, the TOV0 flag is set in the same timer clock cycle that the counter counts from MAX to 0x00. Fast PWM Mode The fast Pulse Width Modulation or fast PWM mode (WGM01:0 = 3) provides a high frequency PWM waveform generation option. The fast PWM di ffers from the other PWM option by its sin- gle-slope operation. The counter counts from BOTTOM to MAX then restarts from BOTTOM. In non-inverting Compare Output mode, the output compare (OC0) is cleared on the compare match between TCNT0 and OCR0, and set at BOTTOM. In inverting Compare Output mode, the output is set on compare match and cleared at BOTTOM. Due to the single-slope operation, the operating frequency of the fast PWM mode can be twice as high as the phase correct PWM mode that uses dual-slope operation. This high frequency makes the fast PWM mode well suited for power regulation, rectification, and DAC app lications. High frequency allows physically small sized external components (coils, capacitors), and therefore reduces total system cost. In fast PWM mode, the counter is incremented until the counter value matches the MAX value. The counter is then cleared at the following timer clock cycle. The timing diagram for the fast PWM mode is shown in Figure 39. The TCNT0 value is in the timing diagram shown as a histo- gram for illustrating the single-s lope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line ma rks on the TCNT0 slopes represent compare matches between OCR0 and TCNT0. f OCn fclk_I/O

Figure 39. Fast PWM Mode, Timing Diagram is enabled, the interrupt handler routine can be used for updating the compare value. counter is cleared (changes from MAX to BOTTOM). The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024). compare unit is enabled in the fast PWM mode.

waveform generation option. The phase correct PWM mode is based on a dual-slope operation. timer clock cycle. The timing diagram fo r the phase correct PWM mode is shown on Figure 40. line marks on the TCNT0 slopes represent compare matches between OCR0 and TCNT0. Figure 40. Phase Correct PWM Mode, Timing Diagram

2467R–AVR–06/08 ATmega128 Figure 44. Timer/Counter Timing Diagram, Clear Ti mer on Compare Match Mode, with Pres-

Description

Register – TCCR0  Bit 7 – FOC0: Force Output Compare The FOC0 bit is only active when the WGM bits specify a non-PWM mode. However, for ensur- ing compatibility with future devices, this bit must be set to zero when TCCR0 is written when operating in PWM mode. When writing a logica l one to the FOC0 bit, an immediate compare match is forced on the waveform generation unit. The OC0 output is changed according to its COM01:0 bits setting. Note that the FOC0 bit is implemented as a strobe. Therefore it is the value present in the COM01:0 bits that determines the effect of the forced compare. A FOC0 strobe will not generate any interrupt, nor will it clear the timer in CTC mode using OCR0 as TOP. The FOC0 bit is always read as zero.  Bit 6, 3 – WGM01:0: Waveform Generation Mode These bits control the counting sequence of the counter, the source for the maximum (TOP) counter value, and what type of waveform generation to be used. Modes of operation supported by the Timer/Counter unit are: Normal mode, Clear Timer on Compare match (CTC) mode, and two types of Pulse Width Modulation (PWM) modes. See Table 52 and “Modes of Operation” on page 98. OCFn OCRn TCNTn (CTC) TOP TOP - 1 TOP BOTTOM BOTTOM + 1 clkI/O clkTn (clkI/O/8) B i t 76543210 FOC0 WGM00 COM01 COM00 WGM01 CS02 CS01 CS00 TCCR0 Read/Write W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0

Note: 1. The CTC0 and PWM0 bit definition names are now obsolete. Use the WGM01:0 definitions. are set, the OC0 output overrides the normal port functionality of the I/O pin it is connected to. in order to enable the output driver. normal or CTC mode (non-PWM). Table 52. Waveform Generation Mode Bit Description Table 53. Compare Output Mode, non-PWM Mode 0 0 Normal port operation, OC0 disconnected. Table 54. Compare Output Mode, Fast PWM Mode(1) 0 0 Normal port operation, OC0 disconnected.

introduces a risk of missing a compare match between TCNT0 and the OCR0 Register. generate a waveform output on the OC0 pin. Table 55. Compare Output Mode, Phase Correct PWM Mode 0 0 Normal port operation, OC0 disconnected. Table 56. Clock Select Bit Description

2467R–AVR–06/08 ATmega128 Asynchronous Operation of the Timer/Counter Asynchronous Status Register – ASSR  Bit 3 – AS0: Asynchronous Timer/Counter0 When AS0 is written to zero, Timer/Counter0 is clocked from the I/O clock, clk I/O. When AS0 is written to one, Timer/Counter is clocked from a crystal Oscillator connected to the Timer Oscilla- tor 1 (TOSC1) pin. When the value of AS0 is changed, the contents of TCNT0, OCR0, and TCCR0 might be corrupted.  Bit 2 – TCN0UB: Timer/Counter0 Update Busy When Timer/Counter0 operates asynchronously and TCNT0 is written, this bit becomes set. When TCNT0 has been updated from the temporary storage register, this bit is cleared by hard- ware. A logical zero in this bit indicates that TCNT0 is ready to be updated with a new value.  Bit 1 – OCR0UB: Output Co mpare Register0 Update Busy When Timer/Counter0 operates asynchronously and OCR0 is written, this bit becomes set. When OCR0 has been updated from the temporary storage register, this bit is cleared by hard- ware. A logical zero in this bit indicates that OCR0 is ready to be updated with a new value.  Bit 0 – TCR0UB: Timer/Counter Control Register0 Update Busy When Timer/Counter0 operates asynchronously and TCCR0 is written, this bit becomes set. When TCCR0 has been updated from the temporary storage register, this bit is cleared by hard- ware. A logical zero in this bit indicates that TCCR0 is ready to be updated with a new value. If a write is performed to any of the three Timer/Counter0 Registers while its update busy flag is set, the updated value might get corrupted and cause an unintentional interrupt to occur. The mechanisms for reading TCNT0, OCR0, and TCCR0 are different. When reading TCNT0, the actual timer value is read. When reading OC R0 or TCCR0, the value in the temporary stor- age register is read. Asynchronous Operation of Timer/Counter0 When Timer/Counter0 operates asynchronously, some considerations must be taken.  Warning: When switching between asynchronous and synchronous clocking of Timer/Counter0, the Timer Registers TCNT0, OCR0, and TCCR0 might be corrupted. A safe procedure for switching clock source is: 1. Disable the Timer/Counter0 interrupts by clearing OCIE0 and TOIE0. 2. Select clock source by setting AS0 as appropriate. 3. Write new values to TCNT0, OCR0, and TCCR0. 4. To switch to asynchronous operation: Wait for TCN0UB, OCR0UB, and TCR0UB. 5. Clear the Timer/Counter0 interrupt flags. 6. Enable interrupts, if needed.  The Oscillator is optimized for use with a 32.768 kHz watch crystal. Applying an external clock to the TOSC1 pin may result in incorrect Timer/Counter0 operation. The CPU main clock frequency must be more than four times the Oscillator frequency. B i t 76543 2 1 0 – – – – AS0 TCN0UB OCR0UB TCR0UB ASSR R e a d / W r i t e RRRR R / W R R R Initial Value 0 0 0 0 0 0 0 0

2467R–AVR–06/08 ATmega128  When writing to one of the r egisters TCNT0, OCR0, or TCCR0, the value is transferred to a temporary register, and latched after two positive edges on TOSC1. The user should not write a new value before the contents of the Temporary Register have been transferred to its destination. Each of the three mentioned registers have their individual temporary register, which means that e.g., writing to TCNT0 does not disturb an OCR0 write in progress. To detect that a transfer to the destination register has taken place, the Asynchronous Status Register – ASSR has been implemented.  When entering Power-save or Extended Standby mode after having written to TCNT0, OCR0, or TCCR0, the user must wait until the written register has been updated if Timer/Counter0 is used to wake up the device. Otherwise, the MCU will enter sleep mode before the changes are effective. This is particularly important if the Output Compare0 interrupt is used to wake up the device, since the output compare function is disabled during writing to OCR0 or TCNT0. If the write cycle is not finished, and the MCU enters sleep mode before the OCR0UB bit returns to zero, the device will never receive a compare match interrupt, and the MCU will not wake up.  If Timer/Counter0 is used to wake the device up from Power-save or Extended Standby mode, precautions must be taken if the user wants to re-enter one of these modes: The interrupt logic needs one TOSC1 cycle to be reset. If the time between wake-up and re- entering sleep mode is less than one TOSC1 cycle, the interrupt will not occur, and the device will fail to wake up. If the user is in doubt whether the time before re-entering Power- save or Extended Standby mode is sufficient, the following algorithm can be used to ensure that one TOSC1 cycle has elapsed: 1. Write a value to TCCR0, TCNT0, or OCR0. 2. Wait until the correspo nding Update Busy flag in ASSR returns to zero. 3. Enter Power-save or Extended Standby mode.  When the asynchronous operation is selected, the 32.768 kHZ Oscillator for Timer/Counter0 is always running, except in Power-down and Standby modes. After a Power-up Reset or wake-up from Power-down or Standby mode, the user should be aware of the fact that this Oscillator might take as long as one second to stabilize. The user is advised to wait for at least one second before using Timer/Counter0 after power-up or wake-up from Power-down or Standby mode. The contents of all Timer/Counter0 Registers must be considered lost after a wake-up from Power-down or Standby mode due to unstable clock signal upon start- up, no matter whether the Oscillator is in use or a clock signal is applied to the TOSC1 pin.  Description of wake up from Power-save or Extended Standby mode when the timer is clocked asynchronously: When the interrupt condition is met, the wake up process is started on the following cycle of the timer clock, that is, the timer is always advanced by at least one before the processor can read the counter value. After wake-up, the MCU is halted for four cycles, it executes the interrupt routine, and resumes execution from the instruction following SLEEP.  Reading of the TCNT0 Register shortly after wake-up from Power-save may give an incorrect result. Since TCNT0 is clocked on the asynchronous TOSC clock, reading TCNT0 must be done through a register synchronized to the internal I/O clock domain. Synchronization takes place for every rising TOSC1 edge. When waking up from Power- save mode, and the I/O clock (clk I/O) again becomes active, TCNT0 will read as the previous value (before entering sleep) until the next rising TOSC1 edge. The phase of the TOSC clock after waking up from Power-save mode is essentially unpredictable, as it depends on the wake-up time. The recommended procedure for reading TCNT0 is thus as follows: 1. Write any value to either of the registers OCR0 or TCCR0. 2. Wait for the corresponding Update Busy Flag to be cleared. 3. Read TCNT0.

2467R–AVR–06/08 ATmega128  During asynchronous operation, the synchronization of the interrupt flags for the asynchronous timer takes three processor cycles plus one timer cycle. The timer is therefore advanced by at least one before the processor can read the timer value causing the setting of the interrupt flag. The output compare pin is changed on the timer clock and is not synchronized to the processor clock. Timer/Counter Interrupt Mask Register – TIMSK  Bit 1 – OCIE0: Timer/Counter0 Output Compare Match Interrupt Enable When the OCIE0 bit is written to one, and the I-bit in the Status Register is set (one), the Timer/Counter0 Compare Match interrupt is enabled. The corresponding interrupt is executed if a compare match in Timer/Counter0 occurs, i.e., when the OCF0 bit is set in the Timer/Counter Interrupt Flag Register – TIFR.  Bit 0 – TOIE0: Timer/Counter0 Overflow Interrupt Enable When the TOIE0 bit is written to one, and the I-bit in the Status Register is set (one), the Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt is executed if an overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is set in the Timer/Counter Interrupt Flag Register – TIFR. Timer/Counter Interrupt Flag Register – TIFR  Bit 1 – OCF0: Output Compare Flag 0 The OCF0 bit is set (one) when a compare match occurs between the Timer/Counter0 and the data in OCR0 – Output Compare Register0. OCF0 is cleared by hardware when executing the corresponding interrupt handling vector. Alternativel y, OCF0 is cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE0 (Timer/Counter0 Compare Match Interrupt Enable), and OCF0 are set (one), the Timer/Counter0 Compare Match Interrupt is executed.  Bit 0 – TOV0: Timer/Counter0 Overflow Flag The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared by hard- ware when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logic one to the flag. When the SR EG I-bit, TOIE0 (Timer/Counter0 Overflow Inter- rupt Enable), and TOV0 are set (one), the Time r/Counter0 Overflow Interrupt is executed. In PWM mode, this bit is set when Timer/Counter0 changes counting direction at $00. B i t 76543210 OCIE2 TOIE2 TICIE1 OCIE1A OCIE1B TOIE1 OCIE0 TOIE0 TIMSK Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 B i t 76543210 OCF2 TOV2 ICF1 OCF1A OCF1B TOV1 OCF0 TOV0 TIFR Read/Write R/W R/W R/W R/W R/W R/W R/W R/W I n i t i a l V a l u e 00000000

2467R–AVR–06/08 ATmega128 Timer/Counter Prescaler Figure 45. Prescaler for Timer/Counter0 The clock source for Timer/Counter0 is named clkT0. clkT0 is by default connected to the main system clock clk I/O. By setting the AS0 bit in ASSR , Timer/Counter0 is asynchro- nously clocked from the TOSC1 pin. This enables use of Timer/Counter0 as a Real Time Counter (RTC). When AS0 is set, pins TOSC1 and TOSC2 are disconnected from Port C. A crystal can then be connected between the TOSC1 and TOSC2 pins to serve as an independent clock source for Timer/Counter0. The O scillator is optimized for use with a 32.768 kHz crystal. Applying an ex ternal clock source to TOSC1 is not recommended. For Timer/Counter0, the possible prescaled selections are: clk T0S/8, clkT0S/32, clkT0S/64, clkT0S/128, clkT0S/256, and clk T0S/1024. Additionally, clk T0S as well as 0 (stop) may be selected. Setting the PSR0 bit in SFIOR rese ts the prescaler. This allows the user to operate with a predictable prescaler. Special Function IO Register – SFIOR  Bit 7 – TSM: Timer/Counter Synchronization Mode Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the value that is written to the PSR0 and PSR321 bits is kept, hence keeping the corresponding prescaler reset signals asserted. This ensures that the corresponding Timer/Counters are halted and can be configured to the same value without the risk of one of them advancing during configuration. When the TSM bit is written to zero, the PSR0 and PSR321 bits are cleared by hardware, and the Timer/Counters start counting simultaneously. 10-BIT T/C PRESCALER TIMER/COUNTER0 CLOCK SOURCE clkI/O clkT0S TOSC1 AS0 CS00 CS01 CS02 clk T0S clk T0S /64 clk T0S /128 clk T0S /1024 clk T0S /256 clk T0S /32 0PSR0 Clear clkT0 Bit 7 6 5 4 3 2 1 0 TSM – – – ACME PUD PSR0 PSR321 SFIOR Read/Write R/W R R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0

2467R–AVR–06/08 ATmega128  Bit 1 – PSR0: Prescaler Reset Timer/Counter0 When this bit is one, the Time r/Counter0 prescaler will be rese t. This bit is normally cleared immediately by hardware. If this bit is written when Timer/Counter0 is operating in asynchronous mode, the bit will remain one until the presca ler has been reset. The bit will not be cleared by hardware if the TSM bit is set.

2467R–AVR–06/08 ATmega128 16-bit Timer/Counter (Timer/Counter 1 and Timer/Counter3 The 16-bit Timer/Counter unit allows accurate program execution timing (event management), wave generation, and signal timing measurement. The main features are:  True 16-bit Design (i.e.,Allows 16-bit PWM)  Three Independent Output Compare Units  Double Buffered Output Compare Registers  One Input Capture Unit  Input Capture Noise Canceler  Clear Timer on Compare Match (Auto Reload)  Glitch-free, Phase Correct Pulse width Modulator (PWM)  Variable PWM Period  Frequency Generator  External Event Counter  Ten Independent Interrupt Sources (TOV1, OCF1A, OCF1B, OCF1C, ICF1, TOV3, OCF3A, OCF3B, OCF3C, and ICF3) Restrictions in ATmega103 Compatibility Mode Note that in ATmega103 compatibility mode, only one 16-bit Timer/Counter is available (Timer/Counter1). Also note that in ATmega103 compatibility mode, the Timer/Counter1 has two Compare Registers (Compare A and Compare B) only. Overview Most register and bit references in this sect ion are written in general form. A lower case “n” replaces the Timer/Counter number, and a lower case “x” replaces the Output Compare unit channel. However, when using the register or bit defines in a program, the precise form must be used i.e., TCNT1 for accessing Timer/Counter1 counter value and so on. A simplified block diagram of the 16-bit Timer/Counter is shown in Figure 46 . For the actual placement of I/O pins, refer to “Pin Configurations” on page 2. CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit loca- tions are listed in the “16-bit Timer/Counter Register Description” on page 133.

Figure 46. 16-bit Timer/Counter Block Diagram and 3 pin placement and description. since these registers are shared by other timer units. ator to generate a PWM or variable frequency output on the Output Compare Pin (OCnA/B/C).

match flag (OCFnA/B/C) which can be used to generate an output compare interrupt request. Canceler) for reducing the chance of capturing noise spikes. as an alternative, freeing the OCRnA to be used as PWM output.  Bit locations inside all 16-bit Timer/Counter Registers, including Timer Interrupt Registers.  PWMn0 is changed to WGMn0.  PWMn1 is changed to WGMn1.  Timer/Counter Control Register C (TCCRnC).  Output Compare Register C, OCRn CH and OCRnCL, combined OCRnC.  COM1C1:0 are added to TCCR1A.  FOCnA, FOCnB, and FOCnC are added in the new TCCRnC Register. Interrupt flag and mask bits for output compare unit C are added. Table 57. Definitions BOTTOM The counter reaches the BOTTOM when it becomes 0x0000. MAX The counter reaches its MAXimum when it becomes 0xFFFF (decimal 65535). Register. The assignment is dependent of the mode of operation.

2467R–AVR–06/08 ATmega128 Accessing 16-bit Registers The TCNTn, OCRnA/B/C, and ICRn are 16-bit registers that can be accessed by the AVR CPU via the 8-bit data bus. The 16-bit register must be byte accessed using two read or write opera- tions. Each 16-bit timer has a single 8-bit register for temporary storing of the high byte of the 16- bit access. The same Temporary Register is shared between all 16-bit registers within each 16- bit timer. Accessing the low byte triggers the 16-bit read or write operation. When the low byte of a 16-bit register is written by the CPU, the high byte stored in the Temporary Register, and the low byte written are both copied into the 16-bit register in the same clock cycle. When the low byte of a 16-bit register is read by the CPU, the high byte of the 16-bit register is copied into the Temporary Register in the same clock cycle as the low byte is read. Not all 16-bit accesses uses the Temporary Register for the high byte. Reading the OCRnA/B/C 16-bit registers does not involve using the Temporary Register. To do a 16-bit write, the high byte must be written before the low byte. For a 16-bit read, the low byte must be read before the high byte. The following code examples show how to access the 16-bit timer registers assuming that no interrupts updates the temporary register. The same principle can be used directly for accessing the OCRnA/B/C and ICRn Registers. Note that when using “C”, the compiler handles the 16-bit access. Note: 1. See “About Code Examples” on page 9. The assembly code example returns the TCNTn value in the r17:r16 register pair. It is important to notice that accessing 16-bit registers are atomic operations. If an interrupt occurs between the two instructions accessing the 16-bit register, and the interrupt code updates the temporary register by accessing the same or any other of the 16-bit Timer Regis- ters, then the result of the a ccess outside the interrupt will be corrupted. Therefore, when both the main code and the interrupt code update the temporary register, the main code must disable the interrupts during the 16-bit access. Assembly Code Examples (1) ... ; Set TCNTn to 0x01FF ldir17,0x01 ldir16,0xFF outTCNTnH,r17 outTCNTnL,r16 ; Read TCNTn into r17:r16 in r16,TCNTnL in r17,TCNTnH ... C Code Examples(1) unsigned int i; ... /* Set TCNTn to 0x01FF */ TCNTn = 0x1FF; /* Read TCNTn into i */ i = TCNTn; ...

2467R–AVR–06/08 ATmega128 The following code examples show how to do an atomic read of the TCNTn Register contents. Reading any of the OCRnA/B/C or ICRn Registers can be done by using the same principle. Note: 1. See “About Code Examples” on page 9. The assembly code example returns the TCNTn value in the r17:r16 register pair. Assembly Code Example(1) TIM16_ReadTCNTn: ; Save global interrupt flag in r18,SREG ; Disable interrupts cli ; Read TCNTn into r17:r16 in r16,TCNTnL in r17,TCNTnH ; Restore global interrupt flag outSREG,r18 ret C Code Example(1) unsigned int TIM16_ReadTCNTn( void ) unsigned char sreg; unsigned int i; /* Save global interrupt flag */ sreg = SREG; /* Disable interrupts */ __disable_interrupt(); /* Read TCNTn into i */ i = TCNTn; /* Restore global interrupt flag */ SREG = sreg; return i;

2467R–AVR–06/08 ATmega128 The following code examples show how to do an atomic write of the TCNTn Register contents. Writing any of the OCRnA/B/C or ICRn Registers can be done by using the same principle. Note: 1. See “About Code Examples” on page 9. The assembly code example requires that the r1 7:r16 register pair contains the value to be written to TCNTn. Reusing the Temporary High Byte Register If writing to more than one 16-bit register where the high byte is the same for all registers written, then the high byte only needs to be written once. However, note that the same rule of atomic operation described previously also applies in this case. Assembly Code Example (1) TIM16_WriteTCNTn: ; Save global interrupt flag in r18,SREG ; Disable interrupts cli ; Set TCNTn to r17:r16 outTCNTnH,r17 outTCNTnL,r16 ; Restore global interrupt flag outSREG,r18 ret C Code Example(1) void TIM16_WriteTCNTn( unsigned int i ) unsigned char sreg; unsigned int i; /* Save global interrupt flag */ sreg = SREG; /* Disable interrupts */ __disable_interrupt(); /* Set TCNTn to i */ TCNTn = i; /* Restore global interrupt flag */ SREG = sreg;

sequences and waveform generation, see “Modes of Operation” on page 124. the WGMn3:0 bits. TOVn can be used for generating a CPU interrupt. small “n” in register and bit names indicates the Timer/Counter number. Figure 48. Input Capture Unit Block Diagram writing a logical one to its I/O bit location.

2467R–AVR–06/08 ATmega128 into the high byte Temporary Register (TEMP). When the CPU reads the ICRnH I/O location it will access the TEMP Register. The ICRn Register can only be written when us ing a Waveform Generation mode that utilizes the ICRn Register for defining the counter’s TOP value. In these cases the Waveform Genera- tion mode (WGMn3:0) bits must be set before the TOP value can be written to the ICRn Register. When writing the ICRn Register the high byte must be written to the ICRnH I/O location before the low byte is written to ICRnL. For more information on how to access the 16-bit registers refer to “Accessing 16-bit Registers” on page 115. Input Capture Pin Source The main trigger source for the Input Capture unit is the Input Capture Pin (ICPn). Timer/Counter1 can alternatively use the analog comparator output as trigger source for the Input Capture unit. The Analog Comparator is selected as trigger source by setting the analog Comparator Input Capture (ACIC) bit in the Analog Comparator Control and Status Register (ACSR). Be aware that changing trigger source can trigger a capture. The Input Capture flag must therefore be cleared after the change. Both the Input Capture Pin (ICPn) and the Analog Comparator output (ACO) inputs are sampled using the same technique as for the Tn pin ( Figure 59 on page 144 ). The edge detector is also identical. However, when the noise canceler is enabled, additional logic is inserted before the edge detector, which increases the delay by four system clock cycles. Note that the input of the noise canceler and edge detector is always enabl ed unless the Timer/Counter is set in a Wave- form Generation mode that uses ICRn to define TOP. An Input Capture can be triggered by software by controlling the port of the ICPn pin. Noise Canceler The noise canceler improves noise immunity by using a simple digital filtering scheme. The noise canceler input is monitored over four samples, and all four must be equal for changing the output that in turn is used by the edge detector. The noise canceler is enabled by setting the Input Capture Noise Canceler (ICNCn) bit in Timer/Counter Control Register B (TCCRnB). When enabled the noise canceler introduces addi- tional four system clock cycles of delay from a change applied to the input, to the update of the ICRn Register. The noise canceler uses the sy stem clock and is therefore not affected by the prescaler. Using the Input Capture Unit The main challenge when using the Input Capture unit is to assign enough processor capacity for handling the incoming events. The time between two events is critical. If the processor has not read the captured value in th e ICRn Register before the nex t event occurs, the ICRn will be overwritten with a new value. In this case the result of the capture will be incorrect. When using the Input Capture interrupt, the ICRn Register should be read as early in the inter- rupt handler routine as possible. Even though the Input Capture interrupt has relatively high priority, the maximum interrupt response time is dependent on the maximum number of clock cycles it takes to handle any of the other interrupt requests. Using the Input Capture unit in any mode of operation when the TOP value (resolution) is actively changed during operation, is not recommended. Measurement of an external signal’s duty cycle requires that the trigger edge is changed after each capture. Changing the edge sensing must be done as early as possible after the ICRn Register has been read. After a change of the edge, the Input Capture flag (ICFn) must be cleared by software (writing a logical one to the I/O bit location). For measuring frequency only, the clearing of the ICFn flag is not required (if an interrupt handler is used).

2467R–AVR–06/08 ATmega128 The OCRnx Register access may seem complex, but this is not case. When the double buffering is enabled, the CPU has access to the OCRnx buffer register, and if double buffering is disabled the CPU will access the OCRnx directly. The conten t of the OCR1x (buffer or compare) register is only changed by a write operation (the Timer/Counter does not update this register automati- cally as the TCNTn- and ICRn Register). Therefore OCRnx is not read via the high byte Temporary Register (TEMP). However, it is a good practice to read the low byte first as when accessing other 16-bit registers. Writing the OCRnx registers must be done via the TEMP Regis- ter since the compare of all 16 bits is done c ontinuously. The high byte (OCRnxH) has to be written first. When the high byte I/O location is written by the CPU, the TEMP Register will be updated by the value written. Then when the low byte (OCRnxL) is written to the lower 8 bits, the high byte will be copied into the upper 8 bits of either the OCRnx buffer or OCRnx Compare Register in the same system clock cycle. For more information of how to access the 16-bit registers refer to “Accessing 16-bit Registers” on page 115. Force Output Compare In non-PWM Waveform Generation modes, the match output of the comparator can be forced by writing a one to the Force Output Compare (FOCnx) bit. Forcing compare match will not set the OCFnx flag or reload/clear the timer, but the OCnx pin will be updated as if a real compare match had occurred (the COMnx1:0 bits settings de fine whether the OCnx pin is set, cleared or toggled). Compare Match Blocking by TCNTn Write All CPU writes to the TCNTn Register will block any compare match that occurs in the next timer clock cycle, even when the timer is stopped. This feature allows OCRnx to be initialized to the same value as TCNTn without triggering an interrupt when the Timer/Counter clock is enabled. Using the Output Compare Unit Since writing TCNTn in any mode of operation will block all compare matches for one timer clock cycle, there are risks involved when changing TCNTn when using any of the output compare channels, independent of whether the Timer/Counter is running or not. If the value written to TCNTn equals the OCRnx value, the compare match will be missed, resulting in incorrect wave- form generation. Do not write the TCNTn equal to TOP in PWM modes with variable TOP values. The compare match for the TOP will be ignored and the counter will continue to 0xFFFF. Similarly, do not write the TCNTn value equal to BOTTOM when the counter is downcounting. The setup of the OCnx should be performed before setting the Data Direction Register for the port pin to output. The easiest way of setting the OCnx value is to use the force output compare (FOCnx) strobe bits in normal mode. The OCnx Register keeps its value even when changing between waveform generation modes. Be aware that the COMnx1:0 bits are not doubl e buffered together with the compare value. Changing the COMnx1:0 bits will take effect immediately.

the COMnx1:0 bits for defining the output compare (OCnx) state at the next compare match. the OCnx Register is reset to “0”. Figure 50. Compare Match Output Unit, Schematic mode, but there are some exceptions. Refer to Table 58, Table 59 and Table 60 for details. operation. See “16-bit Timer/Counter Register Description” on page 133. The COMnx1:0 bits have no effect on the Input Capture unit. The waveform generator uses the COMnx1:0 bits differently in normal, CTC, and PWM modes.

For detailed timing information refer to “Timer/Counter Timing Diagrams” on page 131. extend the resolution for the capture unit. tion of counting external events. Figure 51. CTC Mode, Timing Diagram

2467R–AVR–06/08 ATmega128 An interrupt can be generated at each time the counter value reaches the TOP value by either using the OCFnA or ICFn flag according to the register used to define the TOP value. If the inter- rupt is enabled, the interrupt handler routine can be used for updating the TOP value. However, changing the TOP to a value close to BOTTOM w hen the counter is running with none or a low prescaler value must be done with care since the CTC mode does not have the double buffering feature. If the new value written to OCRnA or ICRn is lower than the current value of TCNTn, the counter will miss the compare matc h. The counter will then have to count to its maximum value (0xFFFF) and wrap around starting at 0x0000 before the compare match can occur. In many cases this feature is not desirable. An alternative will then be to use the fast PWM mode using OCRnA for defining TOP (WGMn3:0 = 15) since the OCRnA then will be double buffered. For generating a waveform output in CTC mode, the OCnA output can be set to toggle its logical level on each compare match by setting the compare output mode bits to toggle mode (COMnA1:0 = 1). The OCnA value will not be visible on the port pin unless the data direction for the pin is set to output (DDR_OCnA = 1). Th e waveform generated will have a maximum fre- quency of f OCnA = fclk_I/O /2 when OCRnA is set to zero (0x0000). The waveform frequency is defined by the following equation: The N variable represents the prescaler factor (1, 8, 64, 256, or 1024). As for the normal mode of operation, the TOVn flag is set in the same timer clock cycle that the counter counts from MAX to 0x0000. Fast PWM Mode The fast Pulse Width Modulation or fast PWM mode (WGMn3:0 = 5,6,7,14, or 15) provides a high frequency PWM waveform generation option. The fast PWM differs from the other PWM options by its single-slope operation. The counter counts from BOTTOM to TOP then restarts from BOTTOM. In non-inverting Compare Output mode, the output compare (OCnx) is cleared on the compare match between TCNTn and OCRnx, and setat BOTTOM. In inverting compare output mode output is set on compare match and cleared at BOTTOM. Due to the single-slope operation, the operating frequency of the fast PWM mode can be twice as high as the phase cor- rect and phase and frequency correct PWM modes that use dual-slope operation. This high frequency makes the fast PWM mode well suited for power regula tion, rectification, and DAC applications. High frequency allows physically sm all sized external com ponents (coils, capaci- tors), hence reduces total system cost. The PWM resolution for fast PWM can be fixed to 8-, 9-, or 10-bit, or defined by either ICRn or OCRnA. The minimum resolution allowed is 2-bit (ICRn or OCRnA set to 0x0003), and the max- imum resolution is 16-bit (ICRn or OCRnA set to MAX). The PWM resolution in bits can be calculated by using the following equation: In fast PWM mode the counter is incremented until the counter value matches either one of the fixed values 0x00FF, 0x01FF, or 0x03FF (WGMn3:0 = 5, 6, or 7), the value in ICRn (WGMn3:0 = 14), or the value in OCRnA (WGMn3:0 = 15). The counter is then cleared at the following timer clock cycle. The timing diagram for the fast PWM mode is shown in Figure 52. The figure shows fast PWM mode when OCRnA or ICRn is used to define TOP. The TCNTn value is in the timing diagram shown as a histogram for illustrating t he single-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNTn slopes represent compare matches between OCRnx and TCNTn. The OCnx interrupt flag will be set when a compare match occurs. fOCnA fclk_I/O RFPWM TOP 1+()log

Figure 52. Fast PWM Mode, Timing Diagram dler routine can be used for updating the TOP and compare values. MAX value (0xFFFF) and wrap around starting at 0x0000 before the compare match can occur. at the same timer clock cycle as the TCNTn is cleared and the TOVn flag is set. as TOP is clearly a better choice due to its double buffer feature. In fast PWM mode, the compare units allow generation of PWM waveforms on the OCnx pins. the timer clock cycle the counter is cleared (changes from TOP to BOTTOM).

2467R–AVR–06/08 ATmega128 The PWM frequency for the output can be calculated by the following equation: The N variable represents the prescaler divider (1, 8, 64, 256, or 1024). The extreme values for the OCRnx Register represents special cases when generating a PWM waveform output in the fast PWM mode. If the OCRnx is set equal to BOTTOM (0x0000) the out- put will be a narrow spike for eac h TOP+1 timer clock cycle. Se tting the OCRnx equal to TOP will result in a const ant high or low output (depending on the polarity of the output set by the COMnx1:0 bits.) A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by set- ting OCnA to toggle its logical level on each compare match (COMnA1:0 = 1). This applies only if OCRnA is used to define the TOP value (WGM n3:0 = 15). The waveform generated will have a maximum frequency of f OCnA = fclk_I/O/2 when OCRnA is set to zero (0x0000). This feature is similar to the OCnA toggle in CTC mode, except the double buffer feature of the output compare unit is enabled in the fast PWM mode. Phase Correct PWM Mode The phase correct Pulse Width Modulation or phase correct PWM mode (WGMn3:0 = 1, 2, 3, 10, or 11) provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is, like the phase and frequency correct PWM mode, based on a dual- slope operation. The counter counts repeatedly from BOTTOM (0x0000) to TOP and then from TOP to BOTTOM. In non-inverting compare output mode, the output compare (OCnx) is cleared on the compare match between TCNTn and OCRnx while counting up, and set on the compare match while downcounting. In inverting Output Compare mode, the operation is inverted. The dual-slope operation has lower maximum operation frequency than single slope operation. How- ever, due to the symmetric feature of the dual-slope PWM modes, these modes are preferred for motor control applications. The PWM resolution for the phase correct PWM mode can be fixed to 8-, 9-, or 10-bit, or defined by either ICRn or OCRnA. The minimum resolution allowed is 2 bit (ICRn or OCRnA set to 0x0003), and the maximum resolution is 16 bit (ICRn or OCRnA set to MAX). The PWM resolu- tion in bits can be calculated by using the following equation: In phase correct PWM mode the counter is incremented until the counter value matches either one of the fixed values 0x00FF, 0x01FF, or 0x03FF (WGMn3:0 = 1, 2, or 3), the value in ICRn (WGMn3:0 = 10), or the value in OCRnA (WGMn3:0 = 11). The counter has then reached the TOP and changes the count direction. The TCNTn value will be equal to TOP for one timer clock cycle. The timing diagram for the ph ase correct PWM mode is shown on Figure 53. The figure shows phase correct PWM mode when OCRnA or ICRn is used to define TOP. The TCNTn value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNTn slopes represent compare matches between OCRnx and TCNTn. The OCnx inter- rupt flag will be set when a compare match occurs. fOCnxPWM fclk_I/O RPCPWM TOP 1+()log

Figure 53. Phase Correct PWM Mode, Timing Diagram reaches the TOP or BOTTOM value. period will differ in length. The difference in length gives the unsymmetrical result on the output. TOP value there are practically no differences between the two modes of operation.

2467R–AVR–06/08 ATmega128 the counter decrements. The PWM frequency for the output when using phase correct PWM can be calculated by the following equation: The N variable represents the prescaler divider (1, 8, 64, 256, or 1024). The extreme values for the OCRnx Register represents special cases when generating a PWM waveform output in the phase correct PWM mode. If the OCRnx is set equal to BOTTOM the output will be continuously low and if set equal to TOP the output will be continuously high for non-inverted PWM mode. For inverted PWM the output will have the opposite logic values. If OCnA is used to define the TOP value (WGMn3:0 = 11) and COMnA1:0 = 1, the OCnA Output will toggle with a 50% duty cycle. Phase and Frequency Correct PWM Mode The phase and frequency correct Pulse Width Modulation, or phase and frequency correct PWM mode (WGMn3:0 = 8 or 9) provides a high reso lution phase and frequency correct PWM wave- form generation option. The phase and frequency correct PWM mode is, like the phase correct PWM mode, based on a dual-slope operation. The counter counts repeatedly from BOTTOM (0x0000) to TOP and then from TOP to BOTTOM. In non-inverting Compare Output mode, the output compare (OCnx) is cleared on the compare match between TCNTn and OCRnx while counting up, and set on the compare match while downcounting. In inverting Compare Output mode, the operation is inverted. The dual-slope operation gives a lower maximum operation fre- quency compared to the single-slope operation. Howe ver, due to the symmetric feature of the dual-slope PWM modes, these modes are preferred for motor control applications. The main difference between the phase correct, and the phase and frequency correct PWM mode is the time the OCRnx Register is updated by the OCRnx buffer Register, (see Figure 53 and Figure 54). The PWM resolution for the phase and frequency correct PWM mode can be defined by either ICRn or OCRnA. The minimum resolution allowed is 2-bit (ICRn or OCRnA set to 0x0003), and the maximum resolution is 16-bit (ICRn or OCRn A set to MAX). The PWM resolution in bits can be calculated using the following equation: In phase and frequency correct PWM mode the counter is incremented until the counter value matches either the value in ICRn (WGMn3:0 = 8), or the value in OCRnA (WGMn3:0 = 9). The counter has then reac hed the TOP and ch anges the count di rection. The TCNTn value will be equal to TOP for one timer clock cycle. The timing diagram for the phase correct and frequency correct PWM mode is shown on Figure 54. The figure shows phase and frequency correct PWM mode when OCRnA or ICRn is used to define TOP. The TCNTn value is in the timing diagram shown as a histogram for illustrating the dual- slope operation. The diagram incl udes non- inverted and inverted PWM outputs. The small horizontal line marks on the TCNTn slopes repre- sent compare matches between OCRnx and TCNTn. The OCnx interrupt flag will be set when a compare match occurs. f OCnxPCPWM fclk_I/O RPFCPWM TOP 1+()log

Figure 54. Phase and Frequency Correct PWM Mode, Timing Diagram is used for defining the TOP value, the OCnA or ICFn flag set when TCNTn has reached TOP. pare registers, a compare match will never occur between the TCNTn and the OCRnx. TOP is clearly a better choice due to its double buffer feature. The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).

2467R–AVR–06/08 ATmega128 16-bit Timer/Counter Register Control Register A – TCCR1A Timer/Counter3 Control Register A – TCCR3A Bit 7:6 – COMnA1:0: Compare Output Mode for Channel A  Bit 5:4 – COMnB1:0: Compare Output Mode for Channel B  Bit 3:2 – COMnC1:0: Compare Output Mode for Channel C The COMnA1:0, COMnB1:0, and COMnC1:0 control the output compare pins (OCnA, OCnB, and OCnC respectively) behavior. If one or both of the COMnA1:0 bits are written to one, the OCnA output overrides the normal port functionality of the I/O pin it is connected to. If one or both of the COMnB1:0 bits are written to one, the OCnB output overrides the normal port func- tionality of the I/O pin it is connected to. If one or both of the COMnC1:0 bits are written to one, the OCnC output overrides the normal port functionality of the I/O pin it is connected to. How- ever, note that the Data Direction Register (DDR) bit corresponding to the OCnA, OCnB or OCnC pin must be set in order to enable the output driver. When the OCnA, OCnB or OCnC is connected to the pin, the function of the COMnx1:0 bits is dependent of the WGMn3:0 bits setting. Table 58 shows the COMnx1:0 bit functionality when the WGMn3:0 bits are set to a normal or a CTC mode (non-PWM). B i t 765432 1 0 COM1A1 COM1A0 COM1B1 COM1B0 COM1C1 COM1C0 WGM11 WGM10 TCCR1A Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 B i t 765432 1 0 COM3A1 COM3A0 COM3B1 COM3B0 COM3C1 COM3C0 WGM31 WGM30 TCCR3A Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Table 58. Compare Output Mode, non-PWM match (set output to low level).

is done at BOTTOM. See “Fast PWM Mode” on page 125. for more details. rect and frequency correct PWM mode. Table 59. Compare Output Mode, Fast PWM Table 60. Compare Output Mode, Phase Correct and Phase and Frequency Correct PWM

location of these bits are compatible with previous versions of the timer. Table 61. Waveform Generation Mode Bit Description

2467R–AVR–06/08 ATmega128 Timer/Counter1 Control Register B – TCCR1B Timer/Counter3 Control Register B – TCCR3B  Bit 7 – ICNCn: Input Capture Noise Canceler Setting this bit (to one) activates the Input Capture Noise Canceler. When the Noise Canceler is activated, the input from the Input Capture Pin (ICPn) is filtered. The filter function requires four successive equal valued samples of the ICPn pin for changing its output. The Input Capture is therefore delayed by four Oscillator cycles when the noise canceler is enabled.  Bit 6 – ICESn: Input Capture Edge Select This bit selects which edge on the Input Capture Pin (ICPn) that is used to trigger a capture event. When the ICESn bit is written to zero, a falling (negative) edge is used as trigger, and when the ICESn bit is written to one, a rising (positive) edge will trigger the capture. When a capture is triggered according to the ICESn setting, the counter value is copied into the Input Capture Register (ICRn). The event will also set the Input Capture Flag (ICFn), and this can be used to cause an Input Capture Interrupt, if this interrupt is enabled. When the ICRn is used as TOP value (see description of the WGMn3:0 bits located in the TCCRnA and the TCCRnB Register), the ICPn is disconnected and consequently the Input Cap- ture function is disabled.  Bit 5 – Reserved Bit This bit is reserved for future use. For ensuring compatibility with future devices, this bit must be written to zero when TCCRnB is written.  Bit 4:3 – WGMn3:2: Waveform Generation Mode See TCCRnA Register description.  Bit 2:0 – CSn2:0: Clock Select The three clock select bits select the clock source to be used by the Timer/Counter, see Figure 55 and Figure 56. B i t 76543210 ICNC1 ICES1 – WGM13 WGM12 CS12 CS11 CS10 TCCR1B Read/Write R/W R/W R R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 B i t 76543210 ICNC3 ICES3 – WGM33 WGM32 CS32 CS31 CS30 TCCR3B Read/Write R/W R/W R R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0

effect of the forced compare. Timer on Compare Match (CTC) mode using OCRnA as TOP. The FOCnA/FOCnB/FOCnB bits are always read as zero. must be written to zero when TCCRnC is written. Table 62. Clock Select Bit Description

2467R–AVR–06/08 ATmega128 Timer/Counter1 – TCNT1H and TCNT1L Timer/Counter3 – TCNT3H and TCNT3L The two Timer/Counter I/O locations (TCNTnH and TCNTnL , combined TCNTn) give direct access, both for read and for write operations, to the Timer/Counter unit 16-bit counter. To ensure that both the high and low bytes are read and written simultaneously when the CPU accesses these registers, the access is perfo rmed using an 8-bit temporary High Byte Register (TEMP). This Temporary Register is shared by all the other 16-bit registers. See “Accessing 16- bit Registers” on page 115. Modifying the counter (TCNTn) while the counte r is running introduces a risk of missing a com- pare match between TCNTn and one of the OCRnx Registers. Writing to the TCNTn Register blocks (removes) the compare match on the following timer clock for all compare units. Output Compare Register 1 A – OCR1AH and OCR1AL Output Compare Register 1 B – OCR1BH and OCR1BL Output Compare Register 1 C – OCR1CH and OCR1CL Output Compare Register 3 A – OCR3AH and OCR3AL B i t 76543210 TCNT1[15:8] TCNT1H TCNT1[7:0] TCNT1L Read/Write R/W R/W R/W R/W R/W R/W R/W R/W I n i t i a l V a l u e 00000000 B i t 76543210 TCNT3[15:8] TCNT3H TCNT3[7:0] TCNT3L Read/Write R/W R/W R/W R/W R/W R/W R/W R/W I n i t i a l V a l u e 00000000 B i t 76543210 OCR1A[15:8] OCR1AH OCR1A[7:0] OCR1AL Read/Write R/W R/W R/W R/W R/W R/W R/W R/W I n i t i a l V a l u e 00000000 B i t 76543210 OCR1B[15:8] OCR1BH OCR1B[7:0] OCR1BL Read/Write R/W R/W R/W R/W R/W R/W R/W R/W I n i t i a l V a l u e 00000000 B i t 76543210 OCR1C[15:8] OCR1CH OCR1C[7:0] OCR1CL Read/Write R/W R/W R/W R/W R/W R/W R/W R/W I n i t i a l V a l u e 00000000 B i t 76543210 OCR3A[15:8] OCR3AH OCR3A[7:0] OCR3AL Read/Write R/W R/W R/W R/W R/W R/W R/W R/W I n i t i a l V a l u e 00000000

2467R–AVR–06/08 ATmega128 Output Compare Register 3 B – OCR3BH and OCR3BL Output Compare Register 3 C – OCR3CH and OCR3CL The Output Compare Registers contain a 16-bit value that is continuously compared with the counter value (TCNTn). A match can be used to generate an output compare interrupt, or to generate a waveform output on the OCnx pin. The Output Compare Registers are 16-bit in size. To ensure that both the high and low bytes are written simultaneously when the CPU writes to these registers, the access is performed using an 8-bit temporary High Byte Register (TEMP). This Temporary Register is shared by all the other 16-bit registers. See “Accessing 16-bit Registers” on page 115. Input Capture Register 1 – ICR1H and ICR1L Input Capture Register 3 – ICR3H and ICR3L The Input Capture is updated with the counter (TCNTn) value each time an event occurs on the ICPn pin (or optionally on the Analog Comparat or Output for Timer/Counter1). The Input Cap- ture can be used for defining the counter TOP value. The Input Capture Register is 16-bit in size. To ensure that both the high and low bytes are read simultaneously when the CPU accesses these regi sters, the access is performed using an 8-bit temporary High Byte Register (TEMP). This Temporary Register is shared by all the other 16-bit registers. See “Accessing 16-bit Registers” on page 115. Timer/Counter Interrupt Mask Register – TIMSK Note: This register contains interrupt control bits fo r several Timer/Counters, but only Timer1 bits are described in this section. The remaining bits are described in their respective timer sections. B i t 76543210 OCR3B[15:8] OCR3BH OCR3B[7:0] OCR3BL Read/Write R/W R/W R/W R/W R/W R/W R/W R/W I n i t i a l V a l u e 00000000 B i t 76543210 OCR3C[15:8] OCR3CH OCR3C[7:0] OCR3CL Read/Write R/W R/W R/W R/W R/W R/W R/W R/W I n i t i a l V a l u e 00000000 B i t 76543210 ICR1[15:8] ICR1H ICR1[7:0] ICR1L Read/Write R/W R/W R/W R/W R/W R/W R/W R/W I n i t i a l V a l u e 00000000 B i t 76543210 ICR3[15:8] ICR3H ICR3[7:0] ICR3L Read/Write R/W R/W R/W R/W R/W R/W R/W R/W I n i t i a l V a l u e 00000000 B i t 76543210 OCIE2 TOIE2 TICIE1 OCIE1A OCIE1B TOIE1 OCIE0 TOIE0 TIMSK Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0

2467R–AVR–06/08 ATmega128  Bit 5 – TICIE1: Timer/Counter1, Input Capture Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Input Capture interrupt is enabled. The corresponding interrupt vector (See “Interrupts” on page 60.) is executed when the ICF1 flag, located in TIFR, is set.  Bit 4 – OCIE1A: Timer/Counter1, Output Compare A Match Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Output Compare A Match Interrupt is enabled. The corresponding interrupt vector (see “Interrupts” on page 60) is executed when the OCF1A flag, located in TIFR, is set.  Bit 3 – OCIE1B: Timer/Counter1, Output Compare B Match Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Output Compare B Match Interrupt is enabled. The corresponding interrupt vector (see “Interrupts” on page 60) is executed when the OCF1B flag, located in TIFR, is set.  Bit 2 – TOIE1: Timer/Counter1, Overflow Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 overflow interrupt is enabled. The corresponding interrupt vector (see “Interrupts” on page 60) is executed when the TOV1 flag, located in TIFR, is set. Extended Timer/Counter Interrupt Mask Register – ETIMSK Note: This register is not available in ATmega103 compatibility mode.  Bit 7:6 – Reserved Bits These bits are reserved for future use. For ensuring compatibility with future devices, these bits must be set to zero when ETIMSK is written.  Bit 5 – TICIE3: Timer/Counter3, Input Capture Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter3 Input Capture Interrupt is enabled. The corresponding interrupt vector (see “Interrupts” on page 60) is executed when the ICF3 flag, located in ETIFR, is set.  Bit 4 – OCIE3A: Timer/Counter3, Output Compare A Match Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter3 Output Compare A Match Interrupt is enabled. The corresponding interrupt vector (see “Interrupts” on page 60) is executed when the OCF3A flag, located in ETIFR, is set.  Bit 3 – OCIE3B: Timer/Counter3, Output Compare B Match Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter3 Output Compare B Match Interrupt is enabled. The corresponding interrupt vector (see “Interrupts” on page 60) is executed when the OCF3B flag, located in ETIFR, is set. B i t 76543210 – – TICIE3 OCIE3A OCIE3B TOIE3 OCIE3C OCIE1C ETIMSK Read/Write R R R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0

2467R–AVR–06/08 ATmega128  Bit 2 – TOIE3: Timer/Counter3, Overflow Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter3 Overflow Interrupt is enabled. The corresponding interrupt vector (see “Interrupts” on page 60) is executed when the TOV3 flag, located in ETIFR, is set.  Bit 1 – OCIE3C: Timer/Counter3, Output Compare C Match Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter3 Output Compare C Match Interrupt is enabled. The corresponding interrupt vector (see “Interrupts” on page 60) is executed when the OCF3C flag, located in ETIFR, is set.  Bit 0 – OCIE1C: Timer/Counter1, Output Compare C Match Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Output Compare C Match Interrupt is enabled. The corresponding interrupt vector (see “Interrupts” on page 60) is executed when the OCF1C flag, located in ETIFR, is set. Timer/Counter Interrupt Flag Register – TIFR Note: This register contains flag bits for several Timer/Counters, but only timer 1 bits are described in this section. The remaining bits are described in their respective timer sections.  Bit 5 – ICF1: Timer/Count er1, Input Capture Flag This flag is set when a capture event occurs on the ICP1 pin. When the Input Capture Register (ICR1) is set by the WGMn3:0 to be used as the TOP value, the ICF1 flag is set when the counter reaches the TOP value. ICF1 is automatically cleared when the Input Capt ure Interrupt vector is executed. Alternatively, ICF1 can be cleared by writing a logic one to its bit location.  Bit 4 – OCF1A: Timer/Counter1, Output Compare A Match Flag This flag is set in the timer clock cycle afte r the counter (TCNT1) value matches the Output Compare Register A (OCR1A). Note that a forced output compare (FOC1A) strobe will not set the OCF1A flag. OCF1A is automatically cleared when the Output Compare Match A interrupt vector is executed. Alternatively, OCF1A can be cleared by writing a logic one to its bit location.  Bit 3 – OCF1B: Timer/Counter1, Output Compare B Match Flag This flag is set in the timer clock cycle afte r the counter (TCNT1) value matches the Output Compare Register B (OCR1B). Note that a forced output compare (FOC1B) strobe will not set the OCF1B flag. OCF1B is automatically cleared when the Output Compare Match B interrupt vector is executed. Alternatively, OCF1B can be cleared by writing a logic one to its bit location.  Bit 2 – TOV1: Timer/Counter1, Overflow Flag The setting of this flag is dependent of the WGMn3:0 bits setting. In normal and CTC modes, the TOV1 flag is set when the timer overflows. Refer to Table 61 on page 135 for the TOV1 flag behavior when using another WGMn3:0 bit setting. B i t 76543210 OCF2 TOV2 ICF1 OCF1A OCF1B TOV1 OCF0 TOV0 TIFR Read/Write R/W R/W R/W R/W R/W R/W R/W R/W I n i t i a l V a l u e 00000000

2467R–AVR–06/08 ATmega128 TOV1 is automatically cleared when the Timer/Counter1 Overflow interrupt vector is executed. Alternatively, TOV1 can be cleared by writing a logic one to its bit location. Extended Timer/Counter Interrupt Flag Register – ETIFR  Bit 7:6 – Reserved Bits These bits are reserved for future use. For ensuring compatibility with future devices, these bits must be set to zero when ETIFR is written.  Bit 5 – ICF3: Timer/Count er3, Input Capture Flag This flag is set when a capture event occurs on the ICP3 pin. When the Input Capture Register (ICR3) is set by the WGM3:0 to be used as the TOP value, the ICF3 flag is set when the counter reaches the TOP value. ICF3 is automatically cleared when the Input Capt ure 3 interrupt vector is executed. Alterna- tively, ICF3 can be cleared by writing a logic one to its bit location.  Bit 4 – OCF3A: Timer/Counter3, Output Compare A Match Flag This flag is set in the timer clock cycle afte r the counter (TCNT3) value matches the Output Compare Register A (OCR3A). Note that a forced output compare (FOC3A) strobe will not set the OCF3A flag. OCF3A is automatically cleared when the Output Compare Match 3 A interrupt vector is exe- cuted. Alternatively, OCF3A can be cleared by writing a logic one to its bit location.  Bit 3 – OCF3B: Timer/Counter3, Output Compare B Match Flag This flag is set in the timer clock cycle afte r the counter (TCNT3) value matches the Output Compare Register B (OCR3B). Note that a forced output compare (FOC3B) strobe will not set the OCF3B flag. OCF3B is automatically cleared when the Output Compare Match 3 B interrupt vector is exe- cuted. Alternatively, OCF3B can be cleared by writing a logic one to its bit location.  Bit 2 – TOV3: Timer/Counter3, Overflow Flag The setting of this flag is dependent of the WGM3:0 bits setting. In normal and CTC modes, the TOV3 flag is set when the timer overflows. Refer to Table 52 on page 105 for the TOV3 flag behavior when using another WGM3:0 bit setting. TOV3 is automatically cleared when the Timer/Counter3 Overflow interrupt vector is executed. Alternatively, TOV3 can be cleared by writing a logic one to its bit location.  Bit 1 – OCF3C: Timer/Counter3, Output Compare C Match Flag This flag is set in the timer clock cycle afte r the counter (TCNT3) value matches the Output Compare Register C (OCR3C). Note that a forced output compare (FOC3C) strobe will not set the OCF3C flag. OCF3C is automatically cleared when the Output Compare Match 3 C interrupt vector is exe- cuted. Alternatively, OCF3C can be cleared by writing a logic one to its bit location.  Bit 0 – OCF1C: Timer/Counter1, Output Compare C Match Flag This flag is set in the timer clock cycle afte r the counter (TCNT1) value matches the Output Compare Register C (OCR1C). B i t 76543210 – – ICF3 OCF3A OCF3B TOV3 OCF3C OCF1C ETIFR Read/Write R/W R/W R/W R/W R/W R/W R/W R/W I n i t i a l V a l u e 00000000

2467R–AVR–06/08 ATmega128 Note that a forced output compare (FOC1C) strobe will not set the OCF1C flag. OCF1C is automatically cleared when the Output Compare Match 1 C interrupt vector is exe- cuted. Alternatively, OCF1C can be cleared by writing a logic one to its bit location.

the mentioned Timer/Counters. Internal Clock Source The Timer/Counter can be clocked directly by the System Clock (by setting the CSn2:0 = 1). fCLK_I/O/256, or fCLK_I/O/1024. from 1 to N+1 system clock cycles, where N equals the prescaler divisor (8, 64, 256, or 1024). is transparent in the high period of the internal system clock. tive (CSn2:0 = 6) edge it detects. Figure 59. Tn Pin Sampling from an edge has been applied to the Tn pin to the counter is updated. system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse is generated.

An external clock source can not be prescaled. Figure 60. Prescaler for Timer/Counter1, Timer/Counter2, and Timer/Counter3 Note: The synchronization logic on the input pins ( T3/T2/T1) is shown in Figure 59. hardware, and the Timer/Counters start counting simultaneously. reset of this prescaler will affect all three timers.

listed in the “8-bit Timer/Counter Register Description” on page 157. Figure 61. 8-Bit Timer/Counter Block Diagram

which can be used to generate an output compare interrupt request. The definitions in Table 63 are also used extensively throughout the document. “Timer/Counter3, Timer/Counter2, and Timer/Counter1 Prescalers” on page 144. 62 shows a block diagram of the counter and its surroundings. Figure 62. Counter Unit Block Diagram count Increment or decrement TCNT2 by 1. direction Select between increment and decrement. clear Clear TCNT2 (set all bits to zero). clkTn Timer/Counter clock, referred to as clkT0 in the following. top Signalize that TCNT2 has reached maximum value. Table 63. Definitions BOTTOM The counter reaches the BOTTOM when it becomes 0x00. MAX The counter reaches its MAXimum when it becomes 0xFF (decimal 255). assignment is dependent on the mode of operation.

bottom Signalize that TCNT2 has reached minimum value (zero). “Modes of Operation” on page 150. the WGM21:0 bits. TOV2 can be used for generating a CPU interrupt. Figure 63. Output Compare Unit, Block Diagram

2467R–AVR–06/08 ATmega128 ering is disabled. The double buffering synchronizes the update of the OCR2 Compare Register to either top or bottom of the counting sequenc e. The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free. The OCR2 Register access may seem complex, but this is not case. When the double buffering is enabled, the CPU has access to the OCR2 buffer Register, and if double buffering is disabled the CPU will access the OCR2 directly. Force Output Compare In non-PWM Waveform Generation modes, the match output of the comparator can be forced by writing a one to the force outp ut compare (FOC2) bit. Forcin g compare match will not set the OCF2 flag or reload/clear the timer, but the OC2 pin will be updated as if a real compare match had occurred (the COM21:0 bits settings define whether the OC2 pin is set, cleared or toggled). Compare Match Blocking by TCNT2 Write All CPU write operations to th e TCNT2 Register will block any co mpare match that occur in the next timer clock cycle, even when the timer is stopped. This feature allows OCR2 to be initialized to the same value as TCNT2 without triggering an interrupt when the Timer/Counter clock is enabled. Using the Output Compare Unit Since writing TCNT2 in any mode of operation will block all compare matches for one timer clock cycle, there are risks involved when changi ng TCNT2 when using the output compare channel, independently of whether the Timer/Counter is running or not. If the value written to TCNT2 equals the OCR2 value, the compare match will be missed, resulting in incorrect waveform gen- eration. Similarly, do not write the TCNT2 value equal to BOTTOM when the counter is downcounting. The setup of the OC2 should be performed before setting the Data Direction Register for the port pin to output. The easiest way of setting the OC2 value is to use the Force Output Compare (FOC2) strobe bits in normal mode. The OC2 Register keeps its value even when changing between waveform generation modes. Be aware that the COM21:0 bits are not double buffered together with the compare value. Changing the COM21:0 bits will take effect immediately. Compare Match Output Unit The Compare Output mode (COM21:0) bits have two functions. The waveform generator uses the COM21:0 bits for defining the output compare (OC2) state at the next compare match. Also, the COM21:0 bits control the OC2 pin output source. Figure 64 shows a simplified schematic of the logic affected by the COM21:0 bit setting. The I/O registers, I/O bits, and I/O pins in the fig- ure are shown in bold. Only the parts of the general I/O Port Control Registers (DDR and PORT) that are affected by the COM21:0 bits are shown. When referring to the OC2 state, the reference is for the internal OC2 Register, not the OC2 pin. If a System Reset occur, the OC2 Register is reset to “0”.

Figure 64. Compare Match Output Unit, Schematic pin. The port override function is independent of the Waveform Generation mode. operation. See “8-bit Timer/Counter Register Description” on page 157. The waveform generator uses the COM21:0 bits differently in normal, CTC, and PWM modes. and for phase correct PWM refer to Table 67 on page 158. match (see “Compare Match Output Unit” on page 149). “Timer/Counter Timing Diagrams” on page 155.

plifies the operation of counting external events. Figure 65. CTC Mode, Timing Diagram

The N variable represents the prescale factor (1, 8, 64, 256, or 1024). counter counts from MAX to 0x00. sized external components (coils, capacitors), and therefore reduces total system cost. In fast PWM mode, the counter is incremented until the counter value matches the MAX value. matches between OCR2 and TCNT2. Figure 66. Fast PWM Mode, Timing Diagram rupt is enabled, the interrupt handler routine can be used for updating the compare value. counter is cleared (changes from MAX to BOTTOM).

2467R–AVR–06/08 ATmega128 The PWM frequency for the output can be calculated by the following equation: The N variable represents the prescale factor (1, 8, 64, 256, or 1024). The extreme values for the OCR2 Register represents special cases when generating a PWM waveform output in the fast PWM mode. If the OCR2 is set equal to BOTTOM, the output will be a narrow spike for each MAX+1 timer clock cycle. Setting the OCR2 equal to MAX will result in a constantly high or low output (depending on the polarity of the output set by the COM21:0 bits.) A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by set- ting OC2 to toggle its logical level on each compare match (COM21:0 = 1). The waveform generated will have a maximum frequency of f OC2 = fclk_I/O/2 when OCR2 is set to zero. This fea- ture is similar to the OC2 toggle in CTC mode, except the double buffer feature of the output compare unit is enabled in the fast PWM mode. Phase Correct PWM Mode The phase correct PWM mode (WGM21:0 = 1) pr ovides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is based on a dual-slope operation. The counter counts repeatedly from BOTTOM to MAX and then from MAX to BOTTOM. In non- inverting Compare Output mode, the output compare (OC2) is cleared on the compare match between TCNT2 and OCR2 while counting up, and set on the compare match while downcount- ing. In inverting Output Compare mode, the operation is inverted. The dual-slope operation has lower maximum operation frequency than single slope operation. However, due to the symmet- ric feature of the dual-slope PWM modes, these modes are preferred for motor control applications. The PWM resolution for the phase correct PWM mode is fixed to 8 bits. In phase correct PWM mode the counter is incremented until the counter value matches Max When the counter reaches MAX, it changes the count direction. The TCNT2 value will be equal to MAX for one timer clock cycle. The timing diagram fo r the phase correct PWM mode is shown on Figure 67. The TCNT2 value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT2 slopes represent compare matches between OCR2 and TCNT2. f OCnPWM fclk_I/O

Figure 67. Phase Correct PWM Mode, Timing Diagram The N variable represents the prescale factor (1, 8, 64, 256, or 1024). inverted PWM mode. For inverted PWM the output will have the opposite logic values. is no Compare Match. The point of this transition is to guarantee symmetry around BOTTOM.

2467R–AVR–06/08 ATmega128 8-bit Timer/Counter Register Register – TCCR2  Bit 7 – FOC2: Force Output Compare The FOC2 bit is only active when the WGM20 bit specifies a non-PWM mode. However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR2 is written when operating in PWM mode. When writing a logical one to the FOC2 bit, an immediate com- pare match is forced on the waveform generati on unit. The OC2 output is changed according to its COM21:0 bits setting. Note that the FOC2 bi t is implemented as a strobe. Therefore it is the value present in the COM21:0 bits that determines the effect of the forced compare. A FOC2 strobe will not gene rate any interrupt, nor will it cl ear the Timer in CTC mode using OCR2 as TOP. The FOC2 bit is always read as zero.  Bit 6, 3 – WGM21:0: Waveform Generation Mode These bits control the counting sequence of the counter, the source for the maximum (TOP) counter value, and what type of waveform generation to be used. Modes of operation supported by the Timer/Counter unit are: Normal mode, Clear Timer on Compare match (CTC) mode, and two types of Pulse Width Modulation (PWM) modes. See Table 64 and “Modes of Operation” on page 150. Note: The CTC2 and PWM2 bit definition names are now obsolete. Use the WGM21:0 definitions. How- ever, the functionality and location of these bits are compatible with previous versions of the timer.  Bit 5:4 – COM21:0: Compare Match Output Mode These bits control the Output Compare Pin (OC2) behavior. If one or both of the COM21:0 bits are set, the OC2 output overrides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corresponding to the OC2 pin must be set in order to enable the output driver. When OC2 is connected to the pin, the function of the COM21:0 bits depends on the WGM21:0 bit setting. Table 65 shows the COM21:0 bit functionality when the WGM21:0 bits are set to a normal or CTC mode (non-PWM). B i t 76543210 FOC2 WGM20 COM21 COM20 WGM21 CS22 CS21 CS20 TCCR2 Read/Write W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Table 64. Waveform Generation Mode Bit Description

The three clock select bits select the clock source to be used by the Timer/Counter. Table 65. Compare Output Mode, Non-PWM Mode 0 0 Normal port operation, OC2 disconnected. Table 66. Compare Output Mode, Fast PWM Mode(1) 0 0 Normal port operation, OC2 disconnected. Table 67. Compare Output Mode, Phase Correct PWM Mode(1) 0 0 Normal port operation, OC2 disconnected. Table 68. Clock Select Bit Description

introduces a risk of missing a compare match between TCNT2 and the OCR2 Register. generate a waveform output on the OC2 pin. Interrupt Flag Register – TIFR.

2467R–AVR–06/08 ATmega128 Timer/Counter Interrupt Flag Register – TIFR  Bit 7 – OCF2: Output Compare Flag 2 The OCF2 bit is set (one) when a compare match occurs between the Timer/Counter2 and the data in OCR2 – Output Compare Register2. OCF2 is cleared by hardware when executing the corresponding interrupt handling vector. Alternativel y, OCF2 is cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE2 (Timer/Counter2 Compare Match Interrupt Enable), and OCF2 are set (one), the Timer/Counter2 Compare Match Interrupt is executed.  Bit 6 – TOV2: Timer/Counter2 Overflow Flag The bit TOV2 is set (one) when an overflow occurs in Timer/Counter2. TOV2 is cleared by hard- ware when executing the corresponding interrupt handling vector. Alternatively, TOV2 is cleared by writing a logic one to the flag. When the SR EG I-bit, TOIE2 (Timer/Counter2 Overflow Inter- rupt Enable), and TOV2 are set (one), the Timer/Counter2 Overflow interrupt is executed. In PWM mode, this bit is set when Timer/Counter2 changes counting direction at $00. B i t 76543210 OCF2 TOV2 ICF1 OCF1A OCF1B TOV1 OCF0 TOV0 TIFR Read/Write R/W R/W R/W R/W R/W R/W R/W R/W I n i t i a l V a l u e 00000000

Compare Output mode (COMnx1:0 = 1). Figure 74. Output Compare Modulator, Timing Diagram by the Output Compare unit C of the Timer/Counter1.

Figure 75. SPI Block Diagram Note: Refer to Figure 1 on page 2 and Table 30 on page 74 for SPI pin placement.

buffer register for later use. incoming data. The last incoming byte will be kept in the buffer register for later use. Figure 76. SPI Master-Slave Interconnection erwise, the first byte is lost. Low period: Longer than 2 CPU clock cycles. High period: Longer than 2 CPU clock cycles. Table 69. SPI Pin Overrides(1)

2467R–AVR–06/08 ATmega128 Note: 1. See “Alternate Functions of Port B” on page 74 for a detailed description of how to define the direction of the user defined SPI pins. The following code examples show how to initialize the SPI as a Master and how to perform a simple transmission. DDR_SPI in the examples must be replaced by the actual data direction register controlling the SPI pins. DD_MOSI, DD_MISO and DD_SCK must be replaced by the actual data direction bits for these pins. For example, if MOSI is placed on pin PB5, replace DD_MOSI with DDB5 and DDR_SPI with DDRB. Note: 1. See “About Code Examples” on page 9. Assembly Code Example(1) SPI_MasterInit: ; Set MOSI and SCK output, all others input out DDR_SPI,r17 ; Enable SPI, Master, set clock rate fck/16 out SPCR,r17 ret SPI_MasterTransmit: ; Start transmission of data (r16) out SPDR,r16 Wait_Transmit: ; Wait for transmission complete sbis SPSR,SPIF rjmp Wait_Transmit ret C Code Example(1) void SPI_MasterInit(void) /* Set MOSI and SCK output, all others input */ /* Enable SPI, Master, set clock rate fck/16 */ void SPI_MasterTransmit(char cData) /* Start transmission */ SPDR = cData; /* Wait for transmission complete */ while(!(SPSR & (1<<SPIF)))

2467R–AVR–06/08 ATmega128 The following code examples show how to initialize the SPI as a slave and how to perform a sim- ple reception. Note: 1. See “About Code Examples” on page 9. Assembly Code Example(1) SPI_SlaveInit: ; Set MISO output, all others input ldi r17,(1<<DD_MISO) out DDR_SPI,r17 ; Enable SPI ldi r17,(1<<SPE) out SPCR,r17 ret SPI_SlaveReceive: ; Wait for reception complete sbis SPSR,SPIF rjmp SPI_SlaveReceive ; Read received data and return in r16,SPDR ret C Code Example(1) void SPI_SlaveInit(void) /* Set MISO output, all others input */ DDR_SPI = (1<<DD_MISO); /* Enable SPI */ SPCR = (1<<SPE); char SPI_SlaveReceive(void) /* Wait for reception complete */ while(!(SPSR & (1<<SPIF))) /* Return data register */ return SPDR;

2467R–AVR–06/08 ATmega128 SS Pin Functionality Slave Mode When the SPI is configured as a slave, the Slave Select (SS) pin is always input. When SS is held low, the SPI is activated, and MISO becomes an output if configured so by the user. All other pins are inputs. When SS is driven high, all pins are inputs except MISO which can be user configured as an output, and the SPI is passive, which means that it will not receive incoming data. Note that the SPI logic will be reset once the SS pin is driven high. The SS pin is useful for packet/byte synchroniza tion to keep the slave bit counter synchronous with the master clock generator. When the SS pin is driven high, the SPI slave will immediately reset the send and receive logic, and drop any partially received data in the Shift Register. Master Mode When the SPI is configured as a master (MSTR in SPCR is set), the user can determine the direction of the SS pin. If SS is configured as an output, the pin is a general output pin which does not affect the SPI system. Typically, the pin will be driving the SS pin of the SPI slave. If SS is configured as an input, it must be held high to ensure Master SPI operation. If the SS pin is driven low by peripheral circuitry when the SPI is configured as a master with the SS pin defined as an input, the SPI syst em interprets this as another master selecting the SPI as a slave and starting to send data to it. To avoid bus contention, the SPI system takes the following actions: 1. The MSTR bit in SPCR is cleared and the SPI system becomes a slave. As a result of the SPI becoming a slave, the MOSI and SCK pins become inputs. 2. The SPIF flag in SPSR is set, and if the SPI interrupt is enabled, and the I-bit in SREG is set, the interrupt routine will be executed. Thus, when interrupt-driven SPI transmission is used in master mode, and there exists a possi- bility that SS is driven low, the interrup t should always check that the MSTR bit is still set. If the MSTR bit has been cleared by a slave select, it must be set by the user to re-enable SPI master mode. SPI Control Register – SPCR  Bit 7 – SPIE: SPI Interrupt Enable This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and the if the global interrupt enable bit in SREG is set.  Bit 6 – SPE: SPI Enable When the SPE bit is written to one, the SPI is enabled. This bit must be set to enable any SPI operations.  Bit 5 – DORD: Data Order When the DORD bit is written to one, the LSB of the data word is transmitted first. When the DORD bit is written to zero, the MSB of the data word is transmitted first.  Bit 4 – MSTR: Master/Slave Select This bit selects Master SPI mode when written to one, and Slave SPI mode when written logic zero. If SS is configured as an input and is driven low while MSTR is set, MSTR will be cleared, B i t 76543210 SPIE SPE DORD MSTR CPOL CPHA SPR1 SPR0 SPCR Read/Write R/W R/W R/W R/W R/W R/W R/W R/W I n i t i a l V a l u e 00000000

Table 70. CPOL functionality

0 Rising Falling

1 Falling Rising

Table 71. CPHA functionality

0 Sample Setup

Table 72. Relationship Between SCK and the Oscillator Frequency

2467R–AVR–06/08 ATmega128 SPI Status Register – SPSR  Bit 7 – SPIF: SPI Interrupt Flag When a serial transfer is complete, the SPIF flag is set. An interrupt is generated if SPIE in SPCR is set and global interrupts are enabled. If SS is an input and is driven low when the SPI is in Master mode, this will also set the SPIF flag. SPIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, the SPIF bit is cleared by first reading the SPI Status Register with SPIF set, then accessing the SPI Data Register (SPDR).  Bit 6 – WCOL: Write COLlision flag The WCOL bit is set if the SPI Data Register (SPDR) is written during a data transfer. The WCOL bit (and the SPIF bit) are cleared by first reading the SPI Status Register with WCOL set, and then accessing the SPI Data Register.  Bit 5..1 – Res: Reserved Bits These bits are reserved bits in the ATmega128 and will always read as zero.  Bit 0 – SPI2X: Double SPI Speed Bit When this bit is written logi c one the SPI speed (SCK Freque ncy) will be doubled when the SPI is in Master mode (see Table 72). This means that the minimum SCK period will be 2 CPU clock periods. When the SPI is configured as Slave, the SPI is only guaranteed to work at f osc /4 or lower. The SPI interface on the ATmega128 is also used for program memory and EEPROM down- loading or uploading. See page 300 for SPI Serial Programming and verification. SPI Data Register – SPDR The SPI Data Register is a Read/Write Register used for data transfer between the register file and the SPI Shift Register. Writing to the register initiates data transmission. Reading the regis- ter causes the Shift Register Receive buffer to be read. B i t 76543210 S P I F W C O L ––––– S P I 2 X S P S R R e a d / W r i t e RRRRRRR R / W I n i t i a l V a l u e 00000000 B i t 76543210 MSB LSB SPDR Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value X X X X X X X X Undefined

2467R–AVR–06/08 ATmega128 USART The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a highly flexible serial communication device. The main features are:  Full Duplex Operation (Independent Serial Receive and Transmit Registers)  Asynchronous or Synchronous Operation  Master or Slave Clocked Synchronous Operation  High Resolution Baud Rate Generator  Supports Serial Frames with 5, 6, 7, 8, or 9 Data Bits and 1 or 2 Stop Bits  Odd or Even Parity Generation and Parity Check Supported by Hardware  Data OverRun Detection  Framing Error Detection  Noise Filtering Includes False Start Bit Detection and Digital Low Pass Filter  Three Separate Interrupts on TX Complete, TX Data Register Empty, and RX Complete  Multi-processor Communication Mode  Double Speed Asynchronous Communication Mode Dual USART The ATmega128 has two USART’s, USART0 and USART1. The functionality for both USART’s is described below. USART0 and USART1 ha ve different I/O registers as shown in “Register Summary” on page 362. Note that in ATmega103 compatibility mode, USART1 is not available, neither is the UBRR0H or UCRS0C Registers. This means that in ATmega103 compatibility mode, the ATmega128 supports asynchronous operation of USART0 only. Overview A simplified block diagram of the USART transmitter is shown in Figure 79. CPU accessible I/O registers and I/O pins are shown in bold.

Figure 79. USART Block Diagram the top): Clock Generator, Transmitter, and Receiver. Control registers are shared by all units. detect frame error, data overrun and parity errors.

xcki Input from XCK pin (internal Signal). Used for synchronous slave operation. fosc XTAL pin frequency (System Clock). operation. The description in this section refers to Figure 80. UMSEL, U2X and DDR_XCK bits. the UBRR value for each mode of operation using an internally generated clock source. Note: 1. The baud rate is defined to be the transfer rate in bit per second (bps). for the asynchronous operation. Set this bit to zero when using synchronous operation. this mode is used. For the Transmitter, there are no downsides. Table 74. Equations for Calculating Baud Rate Register Setting

section refers to Figure 80 for details. add some margin to avoid possible loss of data due to frequency variations. site XCK clock edge of the edge the data output (TxD) is changed. Figure 81. Synchronous Mode XCK Timing. falling XCK edge and sampled at rising XCK edge.

2467R–AVR–06/08 ATmega128 USART Initialization The USART has to be initialized before any communication can take place. The initialization pro- cess normally consists of setting the baud rate, setting frame format and enabling the Transmitter or the Receiver depending on the usage. For interrupt driven USART operation, the global interrupt flag should be cleared (and interrupts globally disabled) when doing the initialization. Before doing a re-initialization with changed baud rate or frame format, be sure that there are no ongoing transmissions during the period the registers are changed. The TXC flag can be used to check that the Transmitter has completed all transfers, and the RXC flag can be used to check that there are no unread data in the receive buffer. Note that the TXC flag must be cleared before each transmission (before UDR is written) if it is used for this purpose. The following simple USART initialization code examples show one assembly and one C func- tion that are equal in functionality. The exampl es assume asynchronous operation using polling (no interrupts enabled) and a fixed frame format. The baud rate is given as a function parameter. For the assembly code, the baud rate parameter is assumed to be stored in the r17:r16 registers. Note: 1. See “About Code Examples” on page 9. More advanced initialization routines can be made that include frame format as parameters, disable interrupts and so on. However, many applications use a fixed setting of the baud and control registers, and for these types of app lications the initialization code can be placed directly in the main routine, or be combined with initialization code for other I/O modules. Assembly Code Example(1) USART_Init: ; Set baud rate out UBRRH, r17 out UBRRL, r16 ; Enable receiver and transmitter ldi r16, (1<<RXEN)|(1<<TXEN) out UCSRB,r16 ; Set frame format: 8data, 2stop bit ldi r16, (1<<USBS)|(3<<UCSZ0) out UCSRC,r16 ret C Code Example(1) #define FOSC 1843200// Clock Speed #define BAUD 9600 #define MYUBRR FOSC/16/BAUD-1 void main( void ) ... USART_Init ( MYUBRR ); ... void USART_Init( unsigned int ubrr ) /* Set baud rate */ UBRRH = (unsigned char)(ubrr>>8); UBRRL = (unsigned char)ubrr; /* Enable receiver and transmitter */ UCSRB = (1<<RXEN)|(1<<TXEN); /* Set frame format: 8data, 2stop bit */ UCSRC = (1<<USBS)|(3<<UCSZ0);

2467R–AVR–06/08 ATmega128 Data Transmission – The USART Transmitter The USART Transmitter is enabled by setting the Transmit Enable (TXEN) bit in the UCSRB Register. When the Transmitter is enabled, the no rmal port operation of the TxD pin is overrid- den by the USART and given the function as the transmitter’s serial output. The baud rate, mode of operation and frame format must be set up once before doing any trans missions. If synchro- nous operation is used, the clock on the XCK pin will be ov erridden and used as transmission clock. Sending Frames with 5 to 8 Data Bit A data transmission is initiated by loading the transmit buffer with the data to be transmitted. The CPU can load the transmit buffer by writing to the UDR I/O location. The buffered data in the transmit buffer will be moved to the Shift Register when the Shift Register is ready to send a new frame. The Shift Register is loaded with new data if it is in idle state (no ongoing transmission) or immediately after the last stop bit of the previous frame is transmitted. When the Shift Register is loaded with new data, it will transfer one complete frame at the rate given by the baud register, U2X bit or by XCK depending on mode of operation. The following code examples show a simple USART transmit function based on polling of the Data Register Empty (UDRE) flag. When using frames with less than eight bits, the most signifi- cant bits written to the UDR are ignored. The USART has to be initialized before the function can be used. For the assembly code, the data to be sent is assumed to be stored in Register R16 Note: 1. See “About Code Examples” on page 9.. The function simply waits for the transmit buffer to be empty by checking the UDRE flag, before loading it with new data to be transmitted. If the data register empty interrupt is utilized, the inter- rupt routine writes the data into the buffer. Assembly Code Example (1) USART_Transmit: ; Wait for empty transmit buffer sbis UCSRA,UDRE rjmp USART_Transmit ; Put data (r16) into buffer, sends the data out UDR,r16 ret C Code Example(1) void USART_Transmit( unsigned char data ) /* Wait for empty transmit buffer */ while ( !( UCSRA & (1<<UDRE)) ) /* Put data into buffer, sends the data */ UDR = data;

2467R–AVR–06/08 ATmega128 Sending Frames with

9 Data Bit

If 9-bit characters are used (UCSZ = 7), the nint h bit must be written to the TXB8 bit in UCSRB before the low byte of the character is written to UDR. The following code examples show a transmit function that handles 9 bit characters. For the assembly code, the data to be sent is assumed to be stored in Registers R17:R16. Note: 1. These transmit functions are written to be general functions. They can be optimized if the con- tents of the UCSRB is static. I.e., only the TXB8 bit of the UCSRB Register is used after initialization. For I/O registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”. The ninth bit can be used for indicating an address frame when using multi processor communi- cation mode or for other protocol handling as for example synchronization. Transmitter Flags and Interrupts The USART Transmitter has two flags that indi cate its state: USART Data Register Empty (UDRE) and Transmit Complete (TXC). Both flags can be used for generating interrupts. The Data Register Empty (UDRE) flag indicates whether the transmit buffer is ready to receive new data. This bit is set when the transmit buffer is empty, and cleared when the transmit buffer contains data to be transmitted that has not yet been moved into the Shift Register. For compat- ibility with future devices, always write this bit to zero when writing the UCSRA Register. When the Data Register empty Interrupt Enable (UDRIE) bit in UCSRB is writte n to one, the USART Data Register Empty Interrupt will be ex ecuted as long as UDRE is set (provided that global interrupts are enabled). UDRE is cleared by writing UDR. When interrupt-driven data Assembly Code Example (1) USART_Transmit: ; Wait for empty transmit buffer sbis UCSRA,UDRE rjmp USART_Transmit ; Copy 9th bit from r17 to TXB8 cbi UCSRB,TXB8 sbrc r17,0 sbi UCSRB,TXB8 ; Put LSB data (r16) into buffer, sends the data out UDR,r16 ret C Code Example void USART_Transmit( unsigned int data ) /* Wait for empty transmit buffer */ while ( !( UCSRA & (1<<UDRE)) ) /* Copy 9th bit to TXB8 */ UCSRB &= ~(1<<TXB8); if ( data & 0x0100 ) UCSRB |= (1<<TXB8); /* Put data into buffer, sends the data */ UDR = data;

2467R–AVR–06/08 ATmega128 transmission is used, the data register empty Interrupt routine must either write new data to UDR in order to clear UDRE or disable the data register empty interrupt, other- wise a new interrupt will occur once the interrupt routine terminates. The Transmit Complete (TXC) flag bit is set one when the entire frame in the Transmit Shift Register has been shifted out and there are no new data currently present in the transmit buffer. The TXC flag bit is automatically cleared when a transmit complete inter- rupt is executed, or it can be cleared by wr iting a one to its bit location. The TXC flag is useful in half-duplex communication interf aces (like the RS485 standard), where a transmitting application must enter receive mode and free the communication bus immediately after completing the transmission. When the Transmit Compete Interrupt Enable (TXCIE) bit in UCSRB is set, the USART Transmit Complete Interrupt will be executed when the TXC flag becomes set (provided that global interrupts are enabled). When the transmit complete interrupt is used, the interrupt handling routine does not have to clear the TXC flag, this is done automatically when the interrupt is executed. Parity Generator The parity generator calculates the parity bit for the serial frame data. When parity bit is enabled (UPM1 = 1), the transmitter control logic inserts the parity bit between the last data bit and the first stop bit of the frame that is sent. Disabling the Transmitter The disabling of the Transmitter (setting the TXEN to zero) will not become effective until ongoing and pending transmissions are completed, i.e., when the Transmit Shift Register and Transmit Buffer register do not contain data to be transmitted. When dis- abled, the Transmitter will no longer override the TxD pin. Data Reception – The USART Receiver The USART Receiver is enabled by writing the Receive Enable (RXEN) bit in the UCSRB Register to one. When the receiver is enabled, the normal pin operation of the RxD pin is overridden by the USART and given the function as the receiver’s serial input. The baud rate, mode of operation and frame format must be set up once before any serial reception can be done. If synchronous operation is used, the clock on the XCK pin will be used as transfer clock. Receiving Frames with 5 to 8 Data Bits The Receiver starts data reception when it detects a valid start bit. Each bit that follows the start bit will be sampled at the baud rate or XCK clock, and shifted into the Receive Shift Register until the first stop bit of a frame is received. A second stop bit will be ignored by the receiver. When the first stop bit is received, i.e., a complete serial frame is present in the Receive Shift Register, the contents of the Shift Register will be moved into the receive buffer. The receive buffer can then be read by reading the UDR I/O location.

2467R–AVR–06/08 ATmega128 The following code example shows a simple US ART receive function based on polling of the Receive Complete (RXC) flag. When using frames with less than eight bits the most significant bits of the data read from t he UDR will be masked to zero. T he USART has to be initialized before the function can be used. Note: 1. See “About Code Examples” on page 9. The function simply waits for data to be present in the receive buffer by checking the RXC flag, before reading the buffer and returning the value. Assembly Code Example(1) USART_Receive: ; Wait for data to be received sbis UCSRA, RXC rjmp USART_Receive ; Get and return received data from buffer in r16, UDR ret C Code Example(1) unsigned char USART_Receive( void ) /* Wait for data to be received */ while ( !(UCSRA & (1<<RXC)) ) /* Get and return received data from buffer */ return UDR;

2467R–AVR–06/08 ATmega128 Receiving Frames with

9 Data Bits

If 9-bit characters are used (UCSZ=7) the ninth bit must be read from the RXB8 bit in UCSRB before reading the low bits from the UDR. This rule applies to the FE, DOR and UPE status flags as well. Read status from UCSRA, then data from UDR. Reading the UDR I/O location will change the state of the receive buffer FIFO and consequently the TXB8, FE, DOR, and UPE bits, which all are stored in the FIFO, will change. The following code example shows a simple USART receive function that handles both nine bit characters and the status bits. Assembly Code Example (1) USART_Receive: ; Wait for data to be received sbis UCSRA, RXC rjmp USART_Receive ; Get status and 9th bit, then data from buffer in r18, UCSRA in r17, UCSRB in r16, UDR ; If error, return -1 breq USART_ReceiveNoError ldi r17, HIGH(-1) ldi r16, LOW(-1) USART_ReceiveNoError: ; Filter the 9th bit, then return lsr r17 andi r17, 0x01 ret C Code Example(1) unsigned int USART_Receive( void ) unsigned char status, resh, resl; /* Wait for data to be received */ while ( !(UCSRA & (1<<RXC)) ) /* Get status and 9th bit, then data */ /* from buffer */ status = UCSRA; resh = UCSRB; resl = UDR; /* If error, return -1 */ return -1; /* Filter the 9th bit, then return */ resh = (resh >> 1) & 0x01; return ((resh << 8) | resl);

2467R–AVR–06/08 ATmega128 Note: 1. See “About Code Examples” on page 9.. The receive function example reads all the I/O registers into the register file before any compu- tation is done. This gives an optimal receive buffer utilization since the buffer location read will be free to accept new data as early as possible. Receive Compete Flag and Interrupt The USART Receiver has one flag that indicates the receiver state. The Receive Complete (RXC) flag indicates if there are unread data present in the receive buffer. This flag is one when unread data exist in the receive buffer, and zero when the receive buffer is empty (i.e., does not contain any unread data). If the Receiver is disabled (RXEN = 0), the receive buffer will be flushed and consequently the RXC bit will become zero. When the Receive Complete Interrupt Enable (RXCIE) in UCSRB is set, the USART Receive Complete Interrupt will be executed as long as the RXC flag is set (provided that global inter- rupts are enabled). When interrupt-driven data reception is used, the receive complete routine must read the received data from UDR in order to clear the RX C flag, otherwise a new interrupt will occur once the interrupt routine terminates. Receiver Error Flags The USART receiver has three error flags: Frame Error (FE), Data OverRun (DOR) and Parity Error (UPE). All can be accessed by reading UCSRA. Common for the error flags is that they are located in the receive buffer together with the frame for which they indicate the error status. Due to the buffering of the error flags, the UCSRA must be read before the receive buffer (UDR), since reading the UDR I/O location changes the buffer read location. Another equality for the error flags is that they can not be altered by software doing a write to the flag location. However, all flags must be set to zero when the UCSRA is written for upward compatibility of future USART implementations. None of the error flags can generate interrupts. The Frame Error (FE) flag indicates the state of the first stop bit of the next readable frame stored in the receive buffer. The FE flag is zero when the stop bit was correctly read (as one), and the FE flag will be one when the stop bit wa s incorrect (zero). This flag can be used for detecting out-of-sync conditions, detecting break conditions and protocol handling. The FE flag is not affected by the setting of the USBS bit in UCSRC since the receiver ignores all, except for the first, stop bits. For compatibility with future devices, always set this bit to zero when writing to UCSRA. The Data OverRun (DOR) flag indicates data loss due to a receiver buffer full condition. A data overrun occurs when the receive buffer is full (two characters), it is a new character waiting in the Receive Shift Register, and a new start bit is detected. If the DOR flag is set there was one or more serial frame lost between the frame last read from UDR, and the next frame read from UDR. For compatibility with future devices, always write this bit to zero when writing to UCSRA. The DOR flag is cleared when the frame received was successfully moved from the Shift Regis- ter to the receive buffer. The Parity Error (UPE) flag indicates that the next frame in the receive buffer had a parity error when received. If parity check is not enabled the UPE bit will alwa ys be read zero. For compati- bility with future devices, always set this bit to zero when writing to UCSRA. For more details see “Parity Bit Calculation” on page 176 and “Parity Checker” on page 184.

2467R–AVR–06/08 ATmega128 Parity Checker The parity checker is active when the high USART Parity mode (UPM1) bit is set. Type of parity check to be performed (odd or even) is select ed by the UPM0 bit. When enabled, the parity checker calculates the parity of the data bits in incoming frames and compares the result with the parity bit from the serial frame. The result of the check is stored in the receive buffer together with the received data and stop bits. The Parity Error (UPE) flag can then be read by software to check if the frame had a Parity Error. The UPE bit is set if the next character that can be read from the receive buffer had a parIty Error when received and the parity checking was enabl ed at that point (UPM1 = 1). This bit is valid until the Receive buffer (UDR) is read. Disabling the Receiver In contrast to the Transmitter, disabling of the Receiver will be immediate. Data from ongoing receptions will therefore be lost. When disabled (i.e., the RXEN is set to zero) the receiver will no longer override the normal function of the RxD po rt pin. The receiver buffer FIFO will be flushed when the receiver is disabled. Remaining data in the buffer will be lost Flushing the Receive Buffer The receiver buffer FIFO will be flushed when the receiver is disabled, i.e. the buffer will be emp- tied of its contents. Unread data will be lost. If the buffer has to be flushed during normal operation, due to for instance an error condition, read the UDR I/O location until the RXC flag is cleared. The following code example shows how to flush the receive buffer. Note: 1. See “About Code Examples” on page 9.. The USART includes a clock recovery and a data recovery unit for handling asynchronous data reception. The clock recovery logic is used for synchronizing the internally generated baud rate clock to the incoming asynchronous serial frames at the RxD pin. The data recovery logic samples and low pass filters each incoming bit, thereby improving the noise immunity of the receiver. The asynchronous reception operational range depends on the accuracy of the internal baud rate clock, the rate of the incoming frames, and the frame size in number of bits. Assembly Code Example(1) USART_Flush: sbis UCSRA, RXC ret in r16, UDR rjmp USART_Flush C Code Example(1) void USART_Flush( void ) unsigned char dummy; while ( UCSRA & (1<<RXC) ) dummy = UDR;

Figure 85. Stop Bit Sampling and Next Start Bit Sampling bit is registered to have a logic 0 value, the Frame Error (FE) flag will be set. point marked (A) in Figure 85. For Double Speed mode the first low level must be delayed to (B). Table 75) base frequency, the Receiver will not be able to synchronize the frames to the start bit. SM = 5 for Double Speed mode. normal speed mode has higher toleration of baud rate variations.

tion that the receiver and transmitter equally divides the maximum total error. that gives an acceptable low error can be used if possible. frame type bit is zero the frame is a data frame. Table 75. Recommended Maximum Receiver Baud Rate Error for Normal Speed Mode (U2X = Table 76. Recommended Maximum Receiver Baud Rate Error for Double Speed Mode (U2X =

2467R–AVR–06/08 ATmega128 The Multi-processor Communication mode enables several slave MCUs to receive data from a master MCU. This is done by first decoding an address frame to find out which MCU has been addressed. If a particular slave MCU has been addressed, it will rece ive the following data frames as normal, while the other slave MCUs will ignore the received frames until another address frame is received. Using MPCM For an MCU to act as a master MCU, it can use a 9-bit character frame format (UCSZ = 7). The ninth bit (TXB8) must be set when an address frame (TXB8 = 1) or cleared when a data frame (TXB = 0) is being transmitted. The slave MCUs must in this case be set to use a 9-bit character frame format. The following procedure should be used to exchange data in Multi-processor Communication mode: 1. All slave MCUs are in Mult i-processor Communication mode (MPCM in UCSRA is set). 2. The master MCU sends an address frame, and all slaves receive and read this frame. In the slave MCUs, the RXC flag in UCSRA will be set as normal. 3. Each slave MCU reads the UDR Register and determines if it has been selected. If so, it clears the MPCM bit in UCSRA, otherwise it waits for the next address byte and keeps the MPCM setting. 4. The addressed MCU will receive all data fram es until a new address frame is received. The other slave MCUs, which still have the MPCM bit set, will ignore the data frames. 5. When the last data frame is received by the addressed MCU, the addressed MCU sets the MPCM bit and waits for a new address frame from master. The process then repeats from 2. Using any of the 5- to 8-bit character frame formats is possible, but impractical since the receiver must change between using n and n+1 character frame formats. This makes full-duplex opera- tion difficult since the transmitter and receiver uses the same character size setting. If 5- to 8-bit character frames are used, the transmitter must be set to use tw o stop bit (USBS = 1) since the first stop bit is used for indicating the frame type. Do not use read-modify-write instructions (SBI and CBI) to set or clear the MPCM bit. The MPCM bit shares the same I/O location as the TXC flag and this might accidentally be cleared when using SBI or CBI instructions.

2467R–AVR–06/08 ATmega128 USART Register Register – UDRn The USARTn Transmit Data Buffer Register and USARTn Receive Data Buffer Registers share the same I/O address referred to as USARTn Data Register or UDRn. The Transmit Data Buffer Register (TXBn) will be the destination for data written to the UDRn Register location. Reading the UDRn Register location will return the contents of the receive data buffer register (RXBn). For 5-, 6-, or 7-bit characters the upper unused bits will be ignored by the Transmitter and set to zero by the Receiver. The transmit buffer can only be written when the UDREn flag in the UCSRAn Register is set. Data written to UDRn when the UDREn flag is not set, will be ignored by the USARTn Transmit- ter. When data is written to the transmit buffer, and the Transmitter is enabled, the Transmitter will load the data into the Transmit Shift Regist er when the Shift Register is empty. Then the data will be serially transmitted on the TxDn pin. The receive buffer consists of a two level FIFO . The FIFO will change its state whenever the receive buffer is accessed. Due to this behavior of the receive buffer, do not use read modify write instructions (SBI and CBI) on this location. Be careful when using bit test instructions (SBIC and SBIS), since these also will change the state of the FIFO. USART Control and Status Register A – UCSRnA  Bit 7 – RXCn: USART Receive Complete This flag bit is set when there are unread data in the receive buffer and cleared when the receive buffer is empty (i.e., does not contain any unread data). If the receiver is disabled, the receive buffer will be flus hed and consequently the RXCn bit will become zero. The RXCn flag can be used to generate a Receive Complete interrupt (see description of the RXCIEn bit).  Bit 6 – TXCn: USART Transmit Complete This flag bit is set when the entire frame in the Transmit Shift Register has been shifted out and there are no new data currently present in the transmit buffer (UDRn). The TXCn flag bit is auto- matically cleared when a transmit complete interrupt is executed, or it can be cleared by writing a one to its bit location. The TXCn flag can generate a Transmit Complete interrupt (see descrip- tion of the TXCIEn bit).  Bit 5 – UDREn: USART Data Register Empty The UDREn flag indicates if the transmit buffer (UDRn) is ready to receive new data. If UDREn is one, the buffer is empty, and therefore ready to be written. The UDREn flag can generate a Data Register Empty interrupt (see description of the UDRIEn bit). UDREn is set after a reset to indicate that the Transmitter is ready.  Bit 4 – FEn: Frame Error B i t 76543210 RXBn[7:0] UDRn (Read) TXBn[7:0] UDRn (Write) Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 B i t 76543210 RXCn TXCn UDREn FEn DORn UPEn U2Xn MPCMn UCSRnA Read/Write R R/W R R R R R/W R/W I n i t i a l V a l u e 00100000

2467R–AVR–06/08 ATmega128 This bit is set if the next character in the receive buffer had a Frame Error when received. I.e. when the first stop bit of the next character in the receive buffer is zero. This bit is valid until the receive buffer (UDRn) is read. The FEn bit is zero when the stop bit of received data is one. Always set this bit to zero when writing to UCSRnA.  Bit 3 – DORn: Data OverRun This bit is set if a Data OverRun condition is detected. A data overrun occurs when the receive buffer is full (two characters), it is a new char acter waiting in the Receive Shift Register, and a new start bit is detected. This bi t is valid until the receive buffer (UDRn) is read. Always set this bit to zero when writing to UCSRnA.  Bit 2 – UPEn: Parity Error This bit is set if the next character in the receive buffer had a Parity Error when received and the parity checking was enabled at that point (UPMn1 = 1). This bit is valid until the receive buffer (UDRn) is read. Always set this bit to zero when writing to UCSRnA.  Bit 1 – U2Xn: Double the USART Transmission Speed This bit only has effect for the asynchronous operation. Write this bit to zero when using syn- chronous operation. Writing this bit to one will reduce the divisor of the baud rate divider from 16 to 8 effectively dou- bling the transfer rate for asynchronous communication.  Bit 0 – MPCMn: Multi-Processor Communication Mode This bit enables the Multi-processor Communica tion mode. When the MPCMn bit is written to one, all the incoming frames received by the USART Receiver that do not contain address infor- mation will be ignored. Th e transmitter is unaffected by the MPCMn setting. For more detailed information see “Multi-processor Communication Mode” on page 187. USARTn Control and Status Register B – UCSRnB  Bit 7 – RXCIEn: RX Co mplete Interrupt Enable Writing this bit to one enables interrupt on the RXC flag. A USART Receive Complete interrupt will be generated only if the RXCIE bit is written to one, the global interrupt flag in SREG is writ- ten to one and the RXC bit in UCSRnA is set.  Bit 6 – TXCIE: TX Complete Interrupt Enable Writing this bit to one enables interrupt on the TXCn flag. A USARTn Transmit Complete inter- rupt will be generated only if the TXCIEn bit is written to one, the global interrupt flag in SREG is written to one and the TXCn bit in UCSRnA is set.  Bit 5 – UDRIEn: USART Data Register Empty Interrupt Enable Writing this bit to one enables interrupt on the UDREn flag. A Da ta Register Empty interrupt will be generated only if the UDRIEn bit is written to one, the global interrupt flag in SREG is written to one and the UDREn bit in UCSRnA is set.  Bit 4 – RXENn: Receiver Enable Writing this bit to one enables the USARTn Rece iver. The Receiver will override normal port operation for the RxDn pin when enabled. Disabl ing the Receiver will fl ush the receive buffer invalidating the FEn, DORn and UPEn flags.  Bit 3 – TXENn: Transmitter Enable B i t 76543210 RXCIEn TXCIEn UDRIEn RXENn TXENn UCSZn2 RXB8n TXB8n UCSRnB Read/Write R/W R/W R/W R/W R/W R/W R R/W I n i t i a l V a l u e 00000000

ted. When disabled, the transmitter will no longer override the TxDn port. (character size) in a frame the Receiver and Transmitter use. data bits. Must be read before reading the low bits from UDRn. with 9 data bits. Must be written before writing the low bits to UDRn. Note that this register is not available in ATmega103 compatibility mode. to zero when UCSRnC is written. This bit selects between Asynchronous and Synchronous mode of operation. Receiver will generate a parity value for the incoming data and compare it to the UPMn0 setting. If a mismatch is detected, the UPEn flag in UCSRnA will be set. Table 77. UMSELn Bit Settings

0 Asynchronous Operation

1 Synchronous Operation

Table 78. UPMn Bits Settings

(character size) in a frame the Receiver and Transmitter use. and the synchronous clock (XCKn). Table 79. USBSn Bit Settings Table 80. UCSZn Bits Settings

110 R e s e r v e d

Table 81. UCPOLn Bit Settings

0 Rising XCKn Edge Falling XCKn Edge

1 Falling XCKn Edge Rising XCKn Edge

2467R–AVR–06/08 ATmega128  Bit 15:12 – Reserved Bits These bits are reserved for future use. For compatibility with future devices, these bit must be written to zero when UBRRnH is written.  Bit 11:0 – UBRRn11:0: USARTn Baud Rate Register This is a 12-bit register which contains t he USARTn baud rate. The UBRRnH contains the four most significant bits, and the UBRRnL contains the eight least significant bits of the USARTn baud rate. Ongoing transmissions by the transmit ter and receiver will be corrupted if the baud rate is changed. Writing UBRRnL will trigger an immediate update of the baud rate prescaler.

Table 82. Examples of UBRR Settings for Commonly Used Oscillator Frequencies

Table 83. Examples of UBRR Settings for Commonly Used Oscillator Frequencies

Table 84. Examples of UBRR Settings for Commonly Used Oscillator Frequencies

Table 85. Examples of UBRR Settings for Commonly Used Oscillator Frequencies

contention are inherent in the TWI protocol. Figure 86. TWI Bus Interconnection TWI Terminology The following definitions are frequently encountered in this section. pull-up resistors. The bus drivers of all TWI-compliant devices are open-drain or open-collector. Table 86. TWI Terminology

designer, but the address 0000 000 is reserved for a general call. bus, all slaves set up to acknowledge the general call will pull the SDA line low in the ack cycle. this would cause contention if several slaves started transmitting different data. All addresses of the format 1111 xxx should be reserved for future purposes. Figure 89. Address Packet Format transmitter by sending a NACK after the final byte. The MSB of the data byte is transmitted first.

2467R–AVR–06/08 ATmega128 Note that arbitration is not allowed between:  A REPEATED START cond ition and a data bit  A STOP condition and a data bit  A REPEATED START and a STOP condition It is the user software’s responsibility to ensur e that these illegal arbitration conditions never occur. This implies that in multi-master systems, all data transfers must use the same composi- tion of SLA+R/W and data packets. In other words: All transmissions must contain the same number of data packets, otherwise the result of the arbitration is undefined.

in a thick line are accessible through the AVR data bus. Figure 94. Overview of the TWI Module line load. See Table 133 on page 322 for value of pull-up resistor.

2467R–AVR–06/08 ATmega128 or cleared by manipulating the TWI Control R egister (TWCR). When in Transmitter mode, the value of the received (N)ACK bit can be determined by the value in the TWSR. The START/STOP Controller is responsible for generation and detection of START, REPEATED START, and STOP conditions. The START/STOP controller is able to detect START and STOP conditions even when the AVR MCU is in one of the sleep modes, enabling the MCU to wake up if addressed by a master. If the TWI has initiated a transmission as master, the Arbitration Detection hardware continu- ously monitors the transmission trying to determine if arbitration is in process. If the TWI has lost an arbitration, the Control Unit is informed. Correct action can then be taken and appropriate status codes generated. Address Match Unit The Address Match unit checks if received address bytes match the 7-bit address in the TWI Address Register (TWAR). If the TWI General Call Recognition Enable (TWGCE) bit in the TWAR is written to one, all incoming address bits will also be compared against the General Call address. Upon an address match, the Control Unit is informed, allowing correct action to be taken. The TWI may or may not acknowledge it s address, depending on settings in the TWCR. The Address Match unit is able to compare addresses even when the AVR MCU is in sleep mode, enabling the MCU to wake up if addressed by a master. If another interrupt (e.g., INT0) occurs during TWI Power-down address match and wakes up the CPU, the TWI aborts opera- tion and return to it’s idle state. If this cause any problems, ensure that TWI Address Match is the only enabled interrupt when entering Power-down. Control Unit The Control unit monitors the TWI bus and generates responses corresponding to settings in the TWI Control Register (TWCR). When an event requiring the attention of the application occurs on the TWI bus, the TWI Interrupt Flag (TWINT) is asserted. In the next clock cycle, the TWI Sta- tus Register (TWSR) is updated with a stat us code identifying the event. The TWSR only contains relevant status information when the TW I Interrupt Flag is asserted. At all other times, the TWSR contains a special stat us code indicating that no relevant status information is avail- able. As long as the TWINT flag is set, the SCL line is held low. This allows the application software to complete its tasks before allowing the TWI transmission to continue. The TWINT flag is set in the following situations:  After the TWI has transmitted a START/REPEATED START condition  After the TWI has transmitted SLA+R/W  After the TWI has transmitted an address byte  After the TWI has lost arbitration  After the TWI has been addressed by own slave address or general call  After the TWI has received a data byte  After a STOP or REPEATED START has been received while still addressed as a slave  When a bus error has occurred due to an illegal START or STOP condition

2467R–AVR–06/08 ATmega128 TWI Register – TWBR  Bits 7..0 – TWI Bit Rate Register TWBR selects the division factor for the bit rate generator. The bit rate generator is a frequency divider which generates the SCL clock frequency in the Master modes. See “Bit Rate Generator Unit” on page 204 for calculating bit rates. TWI Control Register – TWCR The TWCR is used to control the operation of the TWI. It is used to enable the TWI, to initiate a master access by applying a START condition to the bus, to generate a receiver acknowledge, to generate a stop condition, and to control halting of the bus while the data to be written to the bus are written to the TWDR. It also indicates a write collision if data is attempted written to TWDR while the register is inaccessible.  Bit 7 – TWINT: TWI Interrupt Flag This bit is set by hardware when the TWI has finished its current job and expects application software response. If the I-bit in SREG and TWIE in TWCR are set, the MCU will jump to the TWI interrupt vector. While the TWINT flag is set, the SCL low period is stretched. The TWINT flag must be cleared by software by writing a logic one to it. Note that this flag is not automatically cleared by hardware when executing the interrupt routine. Also note that clearing this flag starts the operation of the TWI, so all accesses to the TWI Address Register (TWAR), TWI Status Register (TWSR), and TWI Data Register (TWDR) must be complete before clearing this flag.  Bit 6 – TWEA: TWI Enable Acknowledge Bit The TWEA bit controls the generation of the acknowledge pulse. If the TWEA bit is written to one, the ACK pulse is generated on the TWI bus if the following conditions are met: 1. The device’s own slave address has been received. 2. A general call has been received, while the TWGCE bit in the TWAR is set. 3. A data byte has been received in Master Receiver or Slave Receiver mode. By writing the TWEA bit to zero, the device can be virtually disconnected from the Two-wire Serial Bus temporarily. Address recognition can then be resumed by writing the TWEA bit to one again.  Bit 5 – TWSTA: TWI START Condition Bit The application writes the TWSTA bit to one when it desires to become a master on the Two- wire Serial Bus. The TWI hardware checks if the bus is available, and generates a START con- dition on the bus if it is free. However, if the bus is not free, the TWI waits until a STOP condition is detected, and then generates a new START condition to claim the bus Master status. TWSTA must be cleared by software when the START condition has been transmitted. B i t 76543210 TWBR7 TWBR6 TWBR5 TWBR4 TWBR3 TWBR2 TWBR1 TWBR0 TWBR Read/Write R/W R/W R/W R/W R/W R/W R/W R/W I n i t i a l V a l u e 00000000 B i t 76543210 TWINT TWEA TWSTA TWSTO TWWC TWEN – TWIE TWCR Read/Write R/W R/W R/W R/W R R/W R R/W I n i t i a l V a l u e 00000000

matically. In slave mode, setting the TWSTO bit can be used to recover from an error condition. Slave mode and releases the SCL and SDA lines to a high impedance state. low. This flag is cleared by writing the TWDR Register when TWINT is high. transmissions are terminated, regardless of any ongoing operation. This bit is a reserved bit and will always read as zero. vated for as long as the TWINT flag is high. prescaler setting. This approach is used in this datasheet, unless otherwise noted. This bit is reserved and will always read as zero. These bits can be read and written, and control the bit rate prescaler. Table 87. TWI Bit Rate Prescaler

2467R–AVR–06/08 ATmega128 TWI Data Register – TWDR In Transmit mode, TWDR contains the next byte to be transmitted. In receive mode, the TWDR contains the last byte received. It is writable while the TWI is not in the process of shifting a byte. This occurs when the TWI interrupt flag (TWINT) is set by hardware. Note that the Data Register cannot be initialized by the user before the first interrupt occurs. The data in TWDR remains sta- ble as long as TWINT is set. While data is shifted out, data on the bus is simultaneously shifted in. TWDR always contains the last byte present on the bus, except after a wake up from a sleep mode by the TWI interrupt. In this case, the contents of TWDR is undefined. In the case of a lost bus arbitration, no data is lost in the transition from Master to Slave. Handling of the ACK bit is controlled automatically by the TWI logic, the CPU cannot access the ACK bit directly.  Bits 7..0 – TWD: TWI Data Register These eight bits constitute the next data byte to be transmitted, or the latest data byte received on the Two-wire Serial Bus. TWI (Slave) Address Register – TWAR The TWAR should be loaded with the 7-bit slave address (in the seven most significant bits of TWAR) to which the TWI will respond when progra mmed as a slave transmitter or receiver, and not needed in the master modes. In multimaster systems, TWAR must be set in masters which can be addressed as slaves by other masters. The LSB of TWAR is used to enable recognition of the general call address ($00). There is an associated address comparator that looks for the slave address (or general call address if enabled) in the received serial address. If a match is found, an interrupt request is generated.  Bits 7..1 – TWA: TWI (Slave) Address Register These seven bits constitute the slave address of the TWI unit.  Bit 0 – TWGCE: TWI General Call Recognition Enable Bit If set, this bit enables the recognition of a General Call given over the Two-wire Serial Bus. Using the TWI The AVR TWI is byte-oriented and interrupt based. Interrupts are issued after all bus events, like reception of a byte or transmission of a START condition. Because the TWI is interrupt-based, the application software is free to carry on other operations during a TWI byte transfer. Note that the TWI Interrupt Enable (TWIE) bit in TWCR to gether with the Global Interrupt Enable bit in SREG allow the application to decide whether or not assertion of the TWINT flag should gener- ate an interrupt request. If the TWIE bit is cl eared, the application must poll the TWINT flag in order to detect actions on the TWI bus. When the TWINT flag is asserted, the TWI has finished an operation and awaits application response. In this case, the TWI Status Register (TWSR) contains a value indicating the current state of the TWI bus. The application software can then decide how the TWI should behave in the next TWI bus cycle by manipulating the TWCR and TWDR Registers. Figure 95 is a simple example of how the application can interface to the TWI hardware. In this example, a master wishes to transmit a single dat a byte to a slave. This description is quite B i t 76543210 TWD7 TWD6 TWD5 TWD4 TWD3 TWD2 TWD1 TWD0 TWDR Read/Write R/W R/W R/W R/W R/W R/W R/W R/W I n i t i a l V a l u e 11111111 B i t 76543210 TWA6 TWA5 TWA4 TWA3 TWA2 TWA1 TWA0 TWGCE TWAR Read/Write R/W R/W R/W R/W R/W R/W R/W R/W I n i t i a l V a l u e 11111110

menting the desired behavior is also presented. Figure 95. Interfacing the Application to the TWI in a Typical Transmission

1. The first step in a TWI transmission is to transmit a START condition. This is done by

application has cleared TWINT, the TWI will initiate transmission of the START condition.

1. When the START condition has been transmitted, the TWINT flag in TWCR is set, and
2. The application software should now examine the value of TWSR, to make sure that the

to transmit the SLA+W present in TWDR. Whic h value to write is described later on. transmission of the address packet.

1. When the address packet has been transmitted, the TWINT flag in TWCR is set, and
2. The application software should now examine the value of TWSR, to make sure that the
3. Check TWSR to see if START
4. Check TWSR to see if SLA+W
5. Check TWSR to see if data

2467R–AVR–06/08 ATmega128 application must load a data packet into TWDR. Subsequently, a specific value must be written to TWCR, instructing the TWI hardwa re to transmit the data packet present in TWDR. Which value to write is described late r on. However, it is important that the TWINT bit is set in the value written. Writing a one to TWINT clears the flag. The TWI will not start any operation as long as the TWINT bit in TWCR is set. Immediately after the application has cleared TWINT, the TWI will initiate transmission of the data packet. 6. When the data packet has been transmitted, the TWINT flag in TWCR is set, and TWSR is updated with a status code indicating that the data packet has successfully been sent. The status code will also reflect whether a slave acknowledged the packet or not. 7. The application software should now examine the value of TWSR, to make sure that the data packet was successfully transmitted, and that the value of the ACK bit was as expected. If TWSR indicates otherwise, the application software might take some special action, like calling an erro r routine. Assuming that the st atus code is as expected, the application must write a specific value to TWCR, instructing the TWI hardware to transmit a STOP condition. Which value to write is described later on. However, it is important that the TWINT bit is set in the value written. Writing a one to TWINT clears the flag. The TWI will not start any operation as long as the TW INT bit in TWCR is set. Immediately after the application has cleared TWINT, the TWI will initiate transmission of the STOP condi- tion. Note that TWINT is NOT set after a STOP condition has been sent.

2467R–AVR–06/08 ATmega128 Even though this example is simple, it shows t he principles involved in all TWI transmissions. These can be summarized as follows:  When the TWI has finished an operation and expects application response, the TWINT flag is set. The SCL line is pulled low until TWINT is cleared.  When the TWINT flag is set, the user must update all TWI Registers with the value relevant for the next TWI bus cycle. As an example, TWDR must be loaded with the value to be transmitted in the next bus cycle.  After all TWI Register updates and other pending application software tasks have been completed, TWCR is written. When writing TWCR, the TWINT bit should be set. Writing a one to TWINT clears the flag. The TWI will then commence executing whatever operation was specified by the TWCR setting. In the following an assembly and C implementation of the example is given. Note that the code below assumes that several definitions have been made for example by using include-files.

2467R–AVR–06/08 ATmega128 Note: For I/O registers located in extended I /O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”. Assembly Code Example C Example Comments 1 ldi r16, (1<<TWEN) out TWCR, r16 (1<<TWEN) Send START condition 2 wait1: in r16,TWCR sbrs r16,TWINT rjmp wait1 while (!(TWCR & (1<<TWINT))) ; Wait for TWINT flag set. This indicates that the START condition has been transmitted 3 in r16,TWSR andi r16, 0xF8 cpi r16, START brne ERROR if ((TWSR & 0xF8) != START) ERROR(); Check value of TWI Status Register. Mask prescaler bits. If status different from START go to ERROR ldi r16, SLA_W out TWDR, r16 ldi r16, (1<<TWINT) | (1<<TWEN) out TWCR, r16 TWDR = SLA_W; TWCR = (1<<TWINT) | (1<<TWEN); Load SLA_W into TWDR Register. Clear TWINT bit in TWCR to start transmission of address 4 wait2: in r16,TWCR sbrs r16,TWINT rjmp wait2 while (!(TWCR & (1<<TWINT))) ; Wait for TWINT flag set. This indicates that the SLA+W has been transmitted, and ACK/NACK has been received. 5 in r16,TWSR andi r16, 0xF8 cpi r16, MT_SLA_ACK brne ERROR if ((TWSR & 0xF8) != MT_SLA_ACK) ERROR(); Check value of TWI Status Register. Mask prescaler bits. If status different from MT_SLA_ACK go to ERROR ldi r16, DATA out TWDR, r16 ldi r16, (1<<TWINT) | (1<<TWEN) out TWCR, r16 TWDR = DATA; TWCR = (1<<TWINT) | (1<<TWEN); Load DATA into TWDR Register. Clear TWINT bit in TWCR to start transmission of data 6 wait3: in r16,TWCR sbrs r16,TWINT rjmp wait3 while (!(TWCR & (1<<TWINT))) ; Wait for TWINT flag set. This indicates that the DATA has been transmitted, and ACK/NACK has been received. 7 in r16,TWSR andi r16, 0xF8 cpi r16, MT_DATA_ACK brne ERROR if ((TWSR & 0xF8) != MT_DATA_ACK) ERROR(); Check value of TWI Status Register. Mask prescaler bits. If status different from MT_DATA_ACK go to ERROR ldi r16, (1<<TWSTO) out TWCR, r16 (1<<TWSTO); Transmit STOP condition

2467R–AVR–06/08 ATmega128 Transmission Modes The TWI can operate in one of four major modes. These are named Master Transmitter (MT), Master Receiver (MR), Slave Transmitter (ST) and Slave Receiver (SR). Several of these modes can be used in the same application. As an example, the TWI can use MT mode to write data into a TWI EEPROM, MR mode to read the data back from the EEPROM. If other masters are present in the system, some of these might transmit data to the TWI, and then SR mode would be used. It is the application software that decides which modes are legal. The following sections describe each of these modes. Possible status codes are described along with figures detailing data transmission in each of the modes. These figures contain the following abbreviations: S: START condition Rs: REPEATED START condition R: Read bit (high level at SDA) W: Write bit (low level at SDA) A: Acknowledge bit (low level at SDA) A : Not acknowledge bit (high level at SDA) Data: 8-bit data byte P: STOP condition SLA: Slave Address In Figure 97 to Figure 103, circles are used to indicate that the TWINT flag is set. The numbers in the circles show the status code held in TWSR, with the prescaler bits masked to zero. At these points, actions must be taken by the application to continue or complete the TWI transfer. The TWI transfer is suspended until the TWINT flag is cleared by software. When the TWINT flag is set, the status code in TWSR is used to determine the appropriate soft- ware action. For each status code, the required software action and details of the following serial transfer are given in Table 88 to Table 91. Note that the prescaler bits are masked to zero in these tables. Master Transmitter Mode In the Master Transmitter mode, a number of data bytes are transmitted to a slave receiver (see Figure 96). In order to enter a Master mode, a START condition must be transmitted. The format of the following address packet determines whether Master Transmitter or Master Receiver mode is to be entered. If SLA+W is transmitte d, MT mode is entered, if SLA+R is transmitted, MR mode is entered. All the status codes mentioned in this section assume that the prescaler bits are zero or are masked to zero.

Figure 96. Data Transfer in Master Transmitter Mode

mode without losing control of the bus. Table 88. Status Codes for Master Transmitter Mode

Figure 97. Formats and States in the Master Transmitter Mode

mode without losing control over the bus. Figure 99. Formats and States in the Master Receiver Mode

2467R–AVR–06/08 ATmega128 The upper seven bits are the address to which t he Two-wire Serial Interface will respond when addressed by a master. If the LSB is set, the TWI will respond to the general call address ($00), otherwise it will ignore the general call address. TWEN must be written to one to enable the TWI. The TWEA bit must be written to one to enable the acknowledgment of the device’s own slave address or the general call address. TWSTA and TWSTO must be written to zero. When TWAR and TWCR have been initialized, the TWI waits until it is addressed by its own slave address (or the general call address if enabled) followed by the data direction bit. If the direction bit is “0” (write), the TWI will operate in SR mode, otherwise ST mode is entered. After its own slave address and the write bit have been received, the TWINT flag is set and a valid status code can be read from TWSR. The status code is used to determine the appropriate soft- ware action. The appropriate action to be taken for each status code is detailed in Table 90. The slave receiver mode may also be entered if arbitration is lost while the TWI is in the master mode (see states $68 and $78). If the TWEA bit is reset during a transfer, the TW I will return a “Not Acknowledge” (“1”) to SDA after the next received data byte. This can be us ed to indicate that the slave is not able to receive any more bytes. While TWEA is zero, the TWI does not acknowledge its own slave address. However, the Two-wire Serial Bus is still monitored and address recognition may resume at any time by setting TWEA. This implies that the TWEA bit may be used to temporarily isolate the TWI from the Two-wire Serial Bus. In all sleep modes other than Idle mode, the clock system to the TWI is turned off. If the TWEA bit is set, the interface can still acknowledge its own slave address or the general call address by using the Two-wire Serial Bus clock as a clock source. The part will then wake up from sleep and the TWI will hold the SCL clock low during the wake up and until the TWINT flag is cleared (by writing it to one). Further data reception will be carri ed out as normal, with the AVR clocks running as normal. Observe that if the AVR is set up with a long start-up time, the SCL line may be held low for a long time, blocking other data transmissions. Note that the Two-wire Serial Interface Data Register – TWDR does not reflect the last byte present on the bus when waking up from these sleep modes. TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN – TWIE value 0 100 01 0 X

Table 90. Status Codes for Slave Receiver Mode

otherwise it will ignore the general call address. TWSTO must be written to zero. Serial Bus is still monitored an d address recognition may resume at any time by setting TWEA. SCL line may be held low for a long time, blocking other data transmissions. present on the bus when waking up from these sleep modes. Table 91. Status Codes for Slave Transmitter Mode

Figure 103. Formats and States in the Slave Transmitter Mode Miscellaneous States There are two status codes that do not correspond to a defined TWI state, see Table 92.

Status $F8 indicates that no relevant information is available because the TWINT flag is not set. This occurs between other states, and when the TWI is not involved in a serial transfer. error occurs when a START or STOP condition occurs at an illegal position in the format frame. are affected). The SDA and SCL lines are released, and no STOP condition is transmitted. In some cases, several TWI modes must be combined in order to complete the desired action.

1. The transfer must be initiated
2. The EEPROM must be instructed what location should be read
3. The reading must be performed
4. The transfer must be finished

figure shows the flow in this transfer. Figure 104. Combining Several TWI Modes to Access a Serial EEPROM Table 92. Miscellaneous States

Figure 107. Analog Comparator Block Diagram Notes: 1. See Table 94 on page 229.

1. Refer to Figure 1 on page 2 and Table 39 on page 81 for Analog Comparator pin placement.

description of this bit, see “Analog Comparator Multiplexed Input” on page 228.

ator. See “Internal Voltage Reference” on page 54. synchronization introduces a delay of 1 – 2 clock cycles. rupt handling vector. Alternatively, ACI is cleared by writing a logic one to the flag. parator interrupt is activated. When written logic zero, the interrupt is disabled. Register (TIMSK) must be set. different settings are shown in Table 93. Table 93. ACIS1/ACIS0 Settings

1. If ACME is cleared or ADEN is set, AIN1 is applied to the negative input to the Analog

Table 94. Analog Comparator Multiplexed Input

2467R–AVR–06/08 ATmega128 Analog to Digital Converter Features  10-bit Resolution  0.5 LSB Integral Non-linearity  ±2 LSB Absolute Accuracy  13 - 260 µs Conversion Time  Up to 76.9 kSPS (Up to 15 kSPS at Maximum Resolution)  8 Multiplexed Single Ended Input Channels  7 Differential Input Channels  2 Differential Input Channels with Optional Gain of 10x and 200x  Optional Left Adjustment for ADC Result Readout  0 - VCC ADC Input Voltage Range  Selectable 2.56 V ADC Reference Voltage  Free Running or Single Conversion Mode  Interrupt on ADC Conversion Complete  Sleep Mode Noise Canceler The ATmega128 features a 10-bit successive approximation ADC. The ADC is connected to an 8-channel Analog Multiplexer wh ich allows 8 single-ended voltage inputs constructed from the pins of Port F. The single-ended voltage inputs refer to 0V (GND). The device also supports 16 differential voltage input combinations. Two of the differential inputs (ADC1, ADC0 and ADC3, ADC2) are equipped wi th a programmable gain stage, providing amplification steps of 0 dB (1x), 20 dB (10x), or 46 dB (200x) on the differential input voltage before the A/D conversion. Seven differential analog input channels share a common negative terminal (ADC1), while any other ADC input can be selected as the positive input terminal. If 1x or 10x gain is used, 8-bit resolution can be expected. If 200x gain is used, 7-bit resolution can be expected. The ADC contains a Sample and Hold circuit whic h ensures that the input voltage to the ADC is held at a constant level during conversion. A block diagram of the ADC is shown in Figure 108. The ADC has a separate analog supply voltage pin, AVCC. AVCC must not differ more than ± 0.3V from V CC. See the paragraph “ADC Noise Canceler” on page 236 on how to connect this pin. Internal reference voltages of nominally 2.56V or AVCC are provided On-chip. The voltage refer- ence may be externally decoupled at the AREF pin by a capacitor for better noise performance.

Figure 108. Analog to Digital Converter Block Schematic

2467R–AVR–06/08 ATmega128 Operation The ADC converts an analog input voltage to a 10-bit digital value through successive approxi- mation. The minimum value represents GND and the maximum value represents the voltage on the AREF pin minus 1 LSB. Optionally, AVCC or an internal 2.56V reference voltage may be connected to the AREF pin by writing to the REFSn bits in the ADMUX Register. The internal voltage reference may thus be decoupled by an external capacitor at the AREF pin to improve noise immunity. The analog input channel and diff erential gain are selected by writing to the MUX bits in ADMUX. Any of the ADC input pins, as well as GND and a fixed bandgap voltage reference, can be selected as single ended inputs to the ADC. A selection of ADC input pins can be selected as positive and negative inputs to the differential gain amplifier. If differential channels are selected, the differential gain stage amplifies the voltage difference between the selected input channel pair by the se lected gain factor. This amplified value then becomes the analog input to the ADC. If single ended channels are used, the gain amplifier is bypassed altogether. The ADC is enabled by setting the ADC Enable bit, ADEN in ADCSRA. Voltage reference and input channel selections will not go into effect until ADEN is set. The ADC does not consume power when ADEN is cleared, so it is recommended to switch off the ADC before entering power saving sleep modes. The ADC generates a 10-bit result which is pr esented in the ADC Data Registers, ADCH and ADCL. By default, the result is presented right adjusted, but can optionally be presented left adjusted by setting the ADLAR bit in ADMUX. If the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH, to ensure that the content of the data registers belongs to the same conversion. Once ADCL is read, ADC access to data registers is blocked. This means that if ADCL has been r ead, and a conversion completes before ADCH is read, neither register is updated and the result fr om the conversion is lost. When ADCH is read, ADC access to the ADCH and ADCL Registers is re-enabled. The ADC has its own interrupt which can be triggered when a conversion completes. When ADC access to the data registers is prohibited between reading of ADCH and ADCL, the interrupt will trigger even if the result is lost. Starting a Conversion A single conversion is started by writing a l ogical one to the ADC Start Conversion bit, ADSC. This bit stays high as long as the conversi on is in progress and will be cleared by hardware when the conversion is completed. If a different data channel is selected while a conversion is in progress, the ADC will finish the current conversion before performing the channel change. In Free Running mode, the ADC is constantly sampling and updating the ADC Data Register. Free Running mode is selected by writing the ADFR bit in ADCSRA to one. The first conversion must be started by writing a logical one to the ADSC bit in ADCSRA. In this mode the ADC will perform successive conversions independently of whether the ADC Interrupt Flag, ADIF is cleared or not.

Figure 109. ADC Prescaler input clock frequency to the ADC can be higher than 200 kHz to get a higher sample rate. from any CPU frequency above 100 kHz. The presca ling is set by the ADPS bits in ADCSRA. page 235 for details on differential conversion timing. on (ADEN in ADCSRA is set) takes 25 ADC clock cycles in order to initialize the analog circuitry. conversion will be initiated on the first rising ADC clock edge. pletes, while ADSC remains high. For a summary of conversion times, see Table 95.

to ADMUX until one ADC clock cycle after ADSC is written. has been selected, the gain stage may take as much as 125 µs to stabilize to the new value. channel. Alternatively, conversion results obtained within this period should be discarded. ADC reference (by changing the REFS1:0 bits in ADMUX). If the JTAG Interface is enabled, the functi on of ADC channels on PORTF7:4 is overridden. Refer to Table 42, “Port F Pins Alternate Functions,” on page 83. Table 95. ADC Conversion Time

2467R–AVR–06/08 ATmega128 ADC Input Channels When changing channel selections, the user should observe the following guidelines to ensure that the correct channel is selected: In Single Conversion mode, always select the channel before starting the conversion. The chan- nel selection may be changed one ADC clock cycle after writing one to ADSC. However, the simplest method is to wait for the conversion to complete before changing the channel selection. In Free Running mode, always select the channel before starting the first conversion. The chan- nel selection may be changed one ADC clock cycle after writing one to ADSC. However, the simplest method is to wait for the first conversion to complete, and then change the channel selection. Since the next conversion has already started automatically, the next result will reflect the previous channel selection. Subsequent conversions will reflect the new channel selection. When switching to a differential gain channel, the first conversion result may have a poor accu- racy due to the required settling time for the automatic offset cancellation circuitry. The user should preferably disregard the first conversion result. ADC Voltage Reference The reference voltage for the ADC (V REF) indicates the conversion range for the ADC. Single ended channels that exceed V REF will result in code s close to 0x3FF. V REF can be selected as either AVCC, internal 2.56V reference, or external AREF pin. AVCC is connected to the ADC through a passive switch. The internal 2.56V reference is gener- ated from the internal bandgap reference (V BG) through an internal amplifier. In either case, the external AREF pin is directly connected to the ADC, and the reference voltage can be made more immune to noise by connecting a capacitor between the AREF pin and ground. V REF can also be measured at the AREF pin with a high impedant voltmeter. Note that V REF is a high impedant source, and only a capacitive load should be connected in a system. If the user has a fixed voltage source connected to the AREF pin, the user may not use the other reference voltage options in the application, as they will be shorted to the external voltage. If no external voltage is applied to the AREF pin, the user may switch between AVCC and 2.56 V as reference selection. The first ADC conversion result after switching reference voltage source may be inaccurate, and the user is advised to discard this result. If differential channels are used, the selected reference should not be closer to AVCC than indicated in Table 136 on page 326. ADC Noise Canceler The ADC features a noise canceler that enables conversion during sleep mode to reduce noise induced from the CPU core and other I/O peripherals. The noise canceler can be used with ADC Noise Reduction and Idle mode. To make use of this feature, the following procedure should be used: 1. Make sure that the ADC is enabled and is not busy converting. Single Conversion mode must be selected and the ADC conversion complete interrupt must be enabled. 2. Enter ADC Noise Reduction mode (or Id le mode). The ADC will start a conversion once the CPU has been halted. 3. If no other interrupts occur before the ADC conversion completes, the ADC interrupt will wake up the CPU and execute the ADC Conversion Complete interrupt routine. If another interrupt wakes up the CPU before the ADC conversion is complete, that interrupt will be executed, and an ADC Conversion Complete interrupt request will be generated when the ADC conversion completes. The CPU will remain in active mode until a new sleep command is executed. Note that the ADC will not be automatically turned off when entering other sleep modes than Idle mode and ADC Noise Reduction mode. The user is advised to write zero to ADEN before enter- ing such sleep modes to avoid excessive power consumption. If the ADC is enabled in such

source impedances of a few hundred kΩ or less is recommended. Figure 113. Analog Input Circuitry

1. Keep analog signal paths as short as possible. Make sure analog tracks run over the

ground plane, and keep them well away from high-speed switching digital tracks.

1. The AVCC pin on the device should be connected to the digital V

via an LC network as shown in Figure 114.

1. Use the ADC noise canceler function to reduce induced noise from the CPU.
2. If any ADC port pins are used as digital outputs, it is essential that these do not

switch while a conversion is in progress.

Figure 114. ADC Power Connections correction, offset on any channel can be reduced below one LSB.

Figure 117. Integral Non-linearity (INL) Figure 118. Differential Non-linearity (DNL) a range of input voltages (1 LSB wide) will code to the same value. Always ±0.5 LSB. differential error, non-linearity, and quantization error. Ideal value: ±0.5 LSB.

0 VREF Input Voltage

1 LSB

Result Registers (ADCL, ADCH). sents the selected reference voltage minus one LSB. tive. Figure 119 shows the decoding of the differential input range. Figure 119. Differential Measurement Range

Voltage on ADC3 is 300 mV, voltage on ADC2 is 500 mV. result: ADCL = 0x70, ADCH = 0x02. reference voltage is being applied to the AREF pin. The ADLAR bit affects the presentation of the ADC conversion result in the ADC Data Register. Table 96. Correlation Between Input Voltage and Output Codes Table 97. Voltage Reference Selections for ADC

10 R e s e r v e d

The value of these bits selects which combination of analog inputs are connected to the ADC. complete (ADIF in ADCSRA is set). Table 98. Input Channel and Gain Selections

00000 ADC0

00001 ADC1

00010 ADC2

00011 ADC3 N/A

00100 ADC4

00101 ADC5

00110 ADC6

00111 ADC7

01001 ADC1 ADC0 10x

01011 ADC1 ADC0 200x

01100 ADC2 ADC2 10x

01101 ADC3 ADC2 10x

01110 ADC2 ADC2 200x

01111 ADC3 ADC2 200x

10000 ADC0 ADC1 1x

10001 ADC1 ADC1 1x

10010 N/A ADC2 ADC1 1x

10011 ADC3 ADC1 1x

10100 ADC4 ADC1 1x

10101 ADC5 ADC1 1x

10110 ADC6 ADC1 1x

10111 ADC7 ADC1 1x

11000 ADC0 ADC2 1x

11001 ADC1 ADC2 1x

11010 ADC2 ADC2 1x

11011 ADC3 ADC2 1x

11100 ADC4 ADC2 1x

Note: 1. Can be used for offset calibration. ADC off while a conversion is in progress, will terminate this conversion. it returns to zero. Writing zero to this bit has no effect.

11101 ADC5 ADC2 1x

Table 98. Input Channel and Gain Selections (Continued)

channels are used, the result is presented in two’s complement form. ADCH. Otherwise, ADCL must be read first, then ADCH. Table 99. ADC Prescaler Selections

2467R–AVR–06/08 ATmega128 JTAG Interface and On-chip Debug System Features  JTAG (IEEE std. 1149.1 Compliant) Interface  Boundary-scan Capabilities According to the IEEE std. 1149.1 (JTAG) Standard  Debugger Access to: – All Internal Peripheral Units – Internal and External RAM – The Internal Register File – Program Counter – EEPROM and Flash Memories  Extensive On-chip Debug Support for Break Conditions, Including –A V R Break Instruction – Break on Change of Program Memory Flow – Single Step Break – Program Memory Breakpoints on Single Address or Address Range – Data Memory Breakpoints on Si ngle Address or Address Range  Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface  On-chip Debugging Supported by AVR Studio Overview The AVR IEEE std. 1149.1 compliant JTAG interface can be used for  Testing PCBs by using the JTAG Boundary-scan capability  Programming the non-volatile memories, Fuses and Lock bits  On-chip debugging A brief description is given in the following se ctions. Detailed descriptions for Programming via the JTAG interface, and using the Boundary-scan Chain can be found in the sections “Program- ming Via the JTAG Interface” on page 305 and “IEEE 1149.1 (JTAG) Boundary-scan” on page 252, respectively. The On-chip Debug support is considered being private JTAG instructions, and distributed within ATMEL and to selected third party vendors only. Figure 120 shows a block diagram of the JTAG interface and the On-chip Debug system. The TAP Controller is a state machine controlled by the TCK and TMS signals. The TAP Controller selects either the JTAG Instruction Register or one of several Data Registers as the scan chain (Shift Register) between the TDI – input and TDO – output. The Instruction Register holds JTAG instructions controlling the behavior of a Data Register. The ID-Register, Bypass Register, and the Boundary-scan Chain are the data registers used for board-level testing. The JTAG Programming Interf ace (actually consisting of several physical and virtual Data Registers) is used for serial programming via the JTAG interface. The Internal Scan Chain and Break Point Scan Chain are used for On-chip debugging only. Test Access Port – TAP The JTAG interface is accessed through four of the AVR’s pins. In JTAG terminology, these pins constitute the Test Access Port –– TAP. These pins are:  TMS: Test mode select. This pin is used for navigating through the TAP-controller state machine.  TCK: Test clock. JTAG operation is synchronous to TCK.  TDI: Test Data In. Serial input data to be shifted in to the Instruction Register or Data Register (Scan Chains).  TDO: Test Data Out. Serial output data from Instruction Register or Data Register.

device is shipped with this fuse programmed. are used in the application. Figure 120. Block Diagram

Figure 121. TAP Controller State Diagram As a definition in this document, the LSB is shifted in and out first for all Shift Registers. instructions into the JTAG instruction register from the TDI input at the rising edge of TCK. state. The MSB of the instruction is shifted in when this state is left by setting TMS high.

2467R–AVR–06/08 ATmega128 on the TDO pin. The JTAG Instruction selects a particular Data Register as path between TDI and TDO and controls the circuitry surrounding the selected Data Register.  Apply the TMS sequence 1, 1, 0 to re-enter the Run-Test/Idle state. The instruction is latched onto the parallel output from the Shift Register path in the Update-IR state. The Exit- IR, Pause-IR, and Exit2-IR states are only used for navigating the state machine.  At the TMS input, apply the sequence 1, 0, 0 at the rising edges of TCK to enter the Shift Data Register – Shift-DR state. While in this state, upload the selected Data Register (selected by the present JTAG instruction in the JTAG Instruction Register) from the TDI input at the rising edge of TCK. In order to remain in the Shift-DR state, the TMS input must be held low during input of all bits except the MSB. The MSB of the data is shifted in when this state is left by setting TMS high. While the Data Register is shifted in from the TDI pin, the parallel inputs to the Data Register captured in the Capture-DR state is shifted out on the TDO pin.  Apply the TMS sequence 1, 1, 0 to re-enter the Run-Test/Idle state. If the selected Data Register has a latched parallel-output, the latching takes place in the Update-DR state. The Exit-DR, Pause-DR, and Exit2-DR states are only used for navigating the state machine. As shown in the state diagram, the Run-Test/Idle state need not be entered between selecting JTAG instruction and using Data Registers, and some JTAG instructions may select certain functions to be performed in the Run-Test/Idle, making it unsuitable as an Idle state. Note: Independent of the initial state of the TAP C ontroller, the Test-Logic-Reset state can always be entered by holding TMS high for 5 TCK clock periods. For detailed information on the JTAG specification, refer to the literature listed in “Bibliography” on page 251. Using the Boundary-scan Chain A complete description of the Boundary-sc an capabilities are given in the section “IEEE 1149.1 (JTAG) Boundary-scan” on page 252. Using the On-chip Debug System As shown in Figure 120, the hardware support for On-chip Debugging consists mainly of  A scan chain on the interface between the internal AVR CPU and the internal peripheral units  Break point unit  Communication interface between the CPU and JTAG system All read or modify/write operations needed for implementing the Debugger are done by applying AVR instructions via the internal AVR CPU Scan Chain. The CPU sends the result to an I/O memory mapped location which is part of the communication interface between the CPU and the JTAG system. The Break point Unit implements Break on Change of Program Flow, Single Step Break, two Program Memory Breakpoints, and two combined br eak points. Together, the four break points can be configured as either:  4 single Program Memory break points  3 Single Program Memory break point + 1 single Data Memory break point  2 single Program Memory break points + 2 single Data Memory break points  2 single Program Memory break points + 1 Program Memory break point with mask (“range break point”)  2 single Program Memory break points + 1 Data Memory break point with mask “range break point”.

2467R–AVR–06/08 ATmega128 A debugger, like the AVR Studio®, may however use one or more of these resources for its inter- nal purpose, leaving less flexibility to the end-user. A list of the On-chip Debug specific JTAG instructions is given in “On-chip Debug Specific JTAG Instructions” on page 250. The JTAGEN fuse must be programmed to enable the JTAG Test Access Port. In addition, the OCDEN fuse must be programmed and no Lock bits must be set for the On-chip Debug system to work. As a security feature, the On-chip Debug system is disabled when any Lock bits are set. Otherwise, the On-chip Debug system would have provided a back-door into a secured device. The AVR Studio enables the user to fully contro l execution of programs on an AVR device with On-chip Debug capability, AVR In-Circuit Emulator, or the built-in AVR Instruction Set Simulator. AVR Studio supports source level execution of Assembly programs assembled with Atmel Cor- poration’s AVR Assembler and C programs compiled with third party vendors’ compilers. AVR Studio runs under Microsoft ® Windows® 95/98/2000 and Windows NT® and Windows XP®. For a full description of the AVR Studio, please refer to the AVR Studio User Guide found in the Online Help in AVR Studio. Only highlights are presented in this document. All necessary execution commands are available in AVR Studio, both on source level and on disassembly level. The user can execute the program, single step through the code either by tracing into or stepping over functions, step out of functions, place the cursor on a statement and execute until the statement is reached, stop th e execution, and reset the execution target. In addition, the user can have an unlimited number of code break points (using the BREAK instruc- tion) and up to two data memory break points, alternatively combined as a mask (range) break point. On-chip Debug Specific JTAG Instructions The On-chip debug support is considered being private JTAG instructions, and distributed within ATMEL and to selected third-party vendors only. Instruction opcodes are listed for reference. PRIVATE0; $8 Private JTAG instruction for accessing On-chip Debug system. PRIVATE1; $9 Private JTAG instruction for accessing On-chip Debug system. PRIVATE2; $A Private JTAG instruction for accessing On-chip Debug system. PRIVATE3; $B Private JTAG instruction for accessing On-chip Debug system.

2467R–AVR–06/08 ATmega128 On-chip Debug Related Register in I/O Memory On-chip Debug Register – OCDR The OCDR Register provides a co mmunication channel from the running program in the micro- controller to the debugger. The CPU can transfer a byte to the debugger by writing to this location. At the same time, an in ternal flag; I/O Debug Register Dirty – IDRD – is set to indicate to the debugger that the register has been written. When the CPU reads the OCDR Register the 7 LSB will be from the OCDR Regi ster, while the MSB is the IDRD bit. The debugger clears the IDRD bit when it has read the information. In some AVR devices, this register is shared with a standard I/O location. In this case, the OCDR Register can only be accessed if the OCDEN fuse is programmed, and the debugger enables access to the OCDR Register. In all other cases, the standard I/O location is accessed. Refer to the debugger documentation for further information on how to use this register. Using the JTAG Programming Capabilities Programming of AVR parts via JTAG is performed via the four-pin JTAG port, TCK, TMS, TDI, and TDO. These are the only pins that need to be controlled/observed to perform JTAG pro- gramming (in addition to power pins). It is not required to apply 12V externally. The JTAGEN fuse must be programmed and the JTD bit in the MCUCSR Register must be cleared to enable the JTAG Test Access Port. The JTAG programming capability supports:  Flash programming and verifying  EEPROM programming and verifying  Fuse programming and verifying  Lock bit programming and verifying The Lock bit security is exactly as in Parallel Programming mode. If the Lock bits LB1 or LB2 are programmed, the OCDEN Fuse cannot be programmed unless first doing a chip erase. This is a security feature that ensures no back-door exists for reading out the content of a secured device. The details on programming through the JTAG interface and programming specific JTAG instructions are given in the section “Programming Via the JTAG Interface” on page 305. Bibliography For more information about general Boundary-scan, the following literature can be consulted:  IEEE: IEEE Std 1149.1-1990. IEEE Standard Test Access Port and Boundary-scan Architecture, IEEE, 1993  Colin Maunder: The Board Designers Guide to Testable Logic Circuits, Addison-Wesley, 1992 B i t 7 6 543210 MSB/IDRD LSB OCDR Read/Write R/W R/W R/W R/W R/W R/W R/W R/W I n i t i a l V a l u e 0 0 000000

2467R–AVR–06/08 ATmega128 IEEE 1149.1 (JTAG) Boundary- scan Features  JTAG (IEEE std. 1149.1 Compliant) Interface  Boundary-scan Capabilities According to the JTAG Standard  Full Scan of all Port Functions as well as Analog Circuitry having Off-chip Connections  Supports the Optional IDCODE Instruction  Additional Public AVR_RESET Instruction to Reset the AVR System Overview The Boundary-scan Chain has the capability of driving and observing the logic levels on the dig- ital I/O pins, as well as the boundary between digital and analog logic for analog circuitry having off-chip connections. At system level, all ICs having JTAG capabilities are connected serially by the TDI/TDO signals to form a long Shift Register. An external controller sets up the devices to drive values at their output pins, and observe the input values received from other devices. The controller compares the received data with the expected result. In this way, Boundary-scan pro- vides a mechanism for testing interconnections and integrity of components on Printed Circuits Boards by using the four TAP signals only. The four IEEE 1149.1 defined mandatory JTAG instructions IDCODE, BYPASS, SAMPLE/PRE- LOAD, and EXTEST, as well as the AVR specif ic public JTAG instruction AVR_RESET can be used for testing the Printed Circuit Board. Initial scanning of the data register path will show the ID-code of the device, since IDCODE is the default JTAG instruction. It may be desirable to have the AVR device in reset during Test mode. If not reset, inputs to the device may be determined by the scan operations, and the internal software may be in an undetermined state when exiting the Test mode. Entering Reset, the outputs of any Port Pin will instantly enter the high imped- ance state, making the HIGHZ instruction redundant. If needed, the BYPASS instruction can be issued to make the shortest possible scan c hain through the device. The device can be set in the Reset state either by pulling the external RESET pin low, or issuing the AVR_RESET instruction with appropriate setting of the Reset Data Register. The EXTEST instruction is used for sampling external pins and loading output pins with data. The data from the output latch will be driven out on the pins as soon as the EXTEST instruction is loaded into the JTAG IR-register. Therefore, the SAMPLE/PRELOAD should also be used for setting initial values to the scan ring, to avoid damaging the board when issuing the EXTEST instruction for the first time. SAMPLE/PRELOAD c an also be used for taking a snapshot of the external pins during normal operation of the part. The JTAGEN fuse must be prog rammed and the JTD bit in th e I/O register MCUCSR must be cleared to enable the JTAG Test Access Port. When using the JTAG interface for Boundary-scan, using a JTAG TCK clock frequency higher than the internal chip frequency is possible. The chip clock is not required to run. Data Registers The data registers relevant for Boundary-scan operations are:  Bypass Register  Device Identification Register  Reset Register  Boundary-scan Chain

Figure 123. Reset Register See “Boundary-scan Chain” on page 255 for a complete description. using the AVR_RESET instruction, since the initial state for all port pins is tri-state. As a definition in this data sheet, the LSB is shifted in and out first for all Shift Registers. describes which data register is selected as path between TDI and TDO for each instruction. register is loaded with the EXTEST instruction.  Capture-DR: Data on the external pins are sampled into the Boundary-scan Chain.  Shift-DR: The Internal Scan Chain is shifted by the TCK input.  Update-DR: Data from the scan chain is applied to output pins. consists of a version number, a device number and the manufacturer code chosen by JEDEC. This is the default instruction after power-up.  Capture-DR: Data in the IDCODE Register is sampled into the Boundary-scan Chain.  Shift-DR: The IDCODE scan chai n is shifted by the TCK input.

2467R–AVR–06/08 ATmega128 SAMPLE_PRELOAD; Mandatory JTAG instruction for pre-loading the output latches and taking a snap-shot of the input/output pins without affecting the system operation. However, the output latched are not connected to the pins. The Boundary-scan Chain is selected as Data Register. The active states are:  Capture-DR: Data on the external pins are sampled into the Boundary-scan Chain.  Shift-DR: The Boundary-scan Chain is shifted by the TCK input.  Update-DR: Data from the Boundary-scan Chain is applied to the output latches. However, the output latches are not connected to the pins. AVR_RESET; $C The AVR specific public JTAG instruction for forcing the AVR device into the Reset mode or releasing the JTAG Reset source. The TAP controller is not reset by this instruction. The one bit Reset Register is selected as Data Register. Note that the Reset will be active as long as there is a logic 'one' in the Reset Chain. The output from this chain is not latched. The active states are:  Shift-DR: The Reset Register is shifted by the TCK input. BYPASS; $F Mandatory JTAG instruction selecting the Bypass Register for Data Register. The active states are:  Capture-DR: Loads a logic “0” into the Bypass Register.  Shift-DR: The Bypass Register cell between TDI and TDO is shifted. Boundary-scan Related Register in I/O Memory MCU Control and Status Register – MCUCSR The MCU Control and Status Register contains control bits for general MCU functions, and pro- vides information on which reset source caused an MCU Reset.  Bit 7 – JTD: JTAG Interface Disable When this bit is zero, the JTAG interface is enabled if the JTAGEN fuse is programmed. If this bit is one, the JTAG interface is disabled. In order to avoid unintentional disabling or enabling of the JTAG interface, a timed sequence must be followed when changing this bit: The application soft- ware must write this bit to the desired value twice within four cycles to change its value. If the JTAG interface is left unconnected to ot her JTAG circuitry, the JTD bit should be set to one. The reason for this is to avoid static current at the TDO pin in the JTAG interface.  Bit 4 – JTRF: JTAG Reset Flag This bit is set if a Reset is being caused by a logic one in the JTAG Reset Register selected by the JTAG instruction AVR_RESET. This bit is rese t by a Power-on Reset, or by writing a logic zero to the flag. Boundary-scan Chain The Boundary-scan chain has the capability of driving and observing the logic levels on the digi- tal I/O pins, as well as the boundary between digi tal and analog logic for analog circuitry having off-chip connection. B i t 76543210 JTD – –J T R F WDRF BORF EXTRF PORF MCUCSR Read/Write R/W R R R/W R/W R/W R/W R/W Initial Value 0 0 0 See Bit Description

Figure 125. General Port Pin Schematic diagram scan cell as shown in Figure 130 is attached to the TWIEN signal.

1. Make sure the OC and TWIEN signals are not asserted simultaneously, as this will lead to

Figure 128. Boundary-scan Cells for Oscillators and Clock Options XTAL1/XTAL2 connections as well as 32 kHz Timer Oscillator. Notes: 1. Do not enable more than one clock source as main clock at a time.

1. Scanning an Oscillator output gives unpredictable results as there is a frequency drift between
2. The clock configuration is programmed by fuses. As a fuse is not changed run-time, the clock

nal capacitors to run unless the fuse is correctly programmed. shared with a digital port pin as well. Table 102. Scan Signals for the Oscillators(1)(2)(3)

Figure 131. Analog to Digital Converter The signals are described briefly in Table 104. Table 103. Boundary-scan Signals for the Analog Comparator

1 Depends upon µC

0 Depends upon µC

Table 104. Boundary-scan Signals for the ADC

HOLD Input Sample & Hold signal. Table 104. Boundary-scan Signals for the ADC (Continued)

reference source, or Ground. on the digital DAC[9:0] lines, and verify the output from the comparator to be high. disabled to avoid signal contention.

scanning in the data on the same row in the table. Table 105. Algorithm for Using the ADC

1 SAMPLE_

2 EXTEST 1 0x200 0x08 0 1 0 0 0

not in the scan chain, since these pins constitute the TAP pins when the JTAG is enabled. Table 106. ATmega128 Boundary-scan Order

204 AC_IDLE Comparator

203 ACO

202 ACME

201 AINBG

200 COMP ADC

199 PRIVATE_SIGNAL1

198 ACLK

197 ACTEN

196 PRIVATE_SIGNAL1

195 ADCBGEN

194 ADCEN

193 AMPEN

192 DAC_9

191 DAC_8

190 DAC_7

189 DAC_6

188 DAC_5

187 DAC_4

186 DAC_3

185 DAC_2

184 DAC_1

183 DAC_0

182 EXTCH

181 G10

180 G20

179 GNDEN

178 HOLD

177 IREFEN

176 MUXEN_7

175 MUXEN_6 ADC

174 MUXEN_5

173 MUXEN_4

172 MUXEN_3

171 MUXEN_2

170 MUXEN_1

169 MUXEN_0

168 NEGSEL_2

167 NEGSEL_1

166 NEGSEL_0

165 PASSEN

164 PRECH

163 SCTEST

161 VCCREN

160 PEN Programming enable (observe only)

Table 106. ATmega128 Boundary-scan Order (Continued)

105 TOSC 32 kHz Timer Oscillator

104 TOSCON

103 RSTT Reset Logic

101 EXTCLKEN Enable signals for main Clock/Oscillators

100 OSCON

99 RCOSCEN

98 OSC32EN

97 EXTCLK (XTAL1) Clock input and Oscillators for the main clock

95 RCCK

94 OSC32CK

93 TWIEN TWI

Notes: 1. PRIVATE_SIGNAL1 should always scanned in as zero.

1. PRIVATE_SIGNAL2 should always scanned in as zero.

2467R–AVR–06/08 ATmega128 Boundary-scan Boundary-scan Description Language (BSDL) files describe Boundary-scan capable devices in a standard format used by automated test-generation software. The order and function of bits in the Boundary-scan Data Register are included in this description.

2467R–AVR–06/08 ATmega128 Boot Loader Support – Read- While-Write Self- Programming The Boot Loader Support provides a real Read- While-Write Self-Programming mechanism for downloading and uploading program code by the MCU itself. This feature allows flexible applica- tion software updates controlled by the MCU using a Flash-resident Boot Loader program. The Boot Loader program can use any available data interface and associated protocol to read code and write (program) that code into the Flash memory, or read the code from the program mem- ory. The program code within the Boot Loader section has the capability to write into the entire Flash, including the Boot Loader memory. The B oot Loader can thus even modify itself, and it can also erase itself from the code if the feature is not needed anymore. The size of the Boot Loader memory is configurable with fuses and t he Boot Loader has two separate sets of Boot Lock bits which can be set independently. This gives the user a unique flexibility to select differ- ent levels of protection. Boot Loader  Read-While-Write Self-Programming  Flexible Boot Memory Size  High Security (Separate Boot Lock Bits for a Flexible Protection)  Separate Fuse to Select Reset Vector  Optimized Page(1) Size  Code Efficient Algorithm  Efficient Read-Modify-Write Support Note: 1. A page is a section in the flash consisting of several bytes (see Table 123 on page 291) used during programming. The page organization does not affect normal operation. Application and Boot Loader Flash Sections The Flash memory is organized in two main sections, the Application section and the Boot Loader section (see Figure 133). The size of the different sections is configured by the BOOTSZ fuses as shown in Table on page 284 and Figure 133. These two sections can have different level of protection since they have different sets of Lock bits. Application Section The application section is the section of the Flash that is used for storing the application code. The protection level for the application section can be selected by the application Boot Lock bits (Boot Lock bits 0), see Table on page 275 . The application section can never store any Boot Loader code since the SPM instruction is disabled when executed from the application section. Boot Loader Section – BLS While the application section is used for storing the application code, the The Boot Loader soft- ware must be located in the BLS since the SPM instruction can initiate a programming when executing from the BLS only. The SPM instruct ion can access the entire Flash, including the BLS itself. The protection level for the Boot Loader section can be selected by the Boot Loader Lock bits (Boot Lock bits 1), see Table 109 on page 276. Read-While-Write and No Read- While-Write Flash Sections Whether the CPU supports Read-While-Write or if the CPU is halted during a Boot Loader soft- ware update is dependent on which address that is being programmed. In addition to the two sections that are configurable by the BOOTSZ fuses as described above, the Flash is also divided into two fixed sections, the Read-Whi le-Write (RWW) section and the No Read-While- Write (NRWW) section. The limit between the RWW- and NRWW sections is given in Table Note: on page 284 and Figure 133 on page 275. The main difference between the two sections is:  When erasing or writing a page located inside the RWW section, the NRWW section can be read during the operation.  When erasing or writing a page located inside the NRWW section, the CPU is halted during the entire operation. Note that the user software can never read any code that is located inside the RWW section dur- ing a Boot Loader software operation. The syntax “Read-While-Write section” refers to which

read during a Boot Loader software update. details on how to clear RWWSB. is halted during the entire page erase or page write operation. Figure 132. Read-While-Write vs. No Read-While-Write Table 107. Read-While-Write Features

Figure 133. Memory Sections(1) Note: 1. The parameters in the figure above are given in Table on page 284. the user a unique flexibility to select different levels of protection. Serial or Parallel Programming mode, but they can be cleared by a chip erase command only. control reading nor writing by LPM/SPM, if it is attempted.

changed through the serial or parallel programming interface. Table 108. Boot Lock Bit0 Protection Modes (Application Section)(1) 2 1 0 SPM is not allowed to write to the Application section. are disabled while executing from the Application section. are disabled while executing from the Application section. Table 109. Boot Lock Bit1 Protection Modes (Boot Loader Section)(1) 2 1 0 SPM is not allowed to write to the Boot Loader section. disabled while executing from the Boot Loader section. disabled while executing from the Boot Loader section. Table 110. Boot Reset Fuse(1)

1 Reset Vector = Application Reset (address $0000)

0 Reset Vector = Boot Loader Reset (see Table 112 on page 284)

2467R–AVR–06/08 ATmega128 Store Program Memory Control and Status Register – SPMCSR The Store Program Memory Control and Status Register contains the control bits needed to con- trol the Boot Loader operations.  Bit 7 – SPMIE: SPM Interrupt Enable When the SPMIE bit is written to one, and the I-bit in the Status Register is set (one), the SPM ready interrupt will be enabled. The SPM ready Interrupt will be executed as long as the SPMEN bit in the SPMCSR Register is cleared.  Bit 6 – RWWSB: Read-While-Write Section Busy When a Self-Programming (page erase or page write) operation to the RWW section is initiated, the RWWSB will be set (one) by hardware. When the RWWSB bit is set, the RWW section can- not be accessed. The RWWSB bit will be cleared if the RWWSRE bit is written to one after a self-programming operation is completed. Alternatively the RWWSB bit will automatically be cleared if a page load operation is initiated.  Bit 5 – Res: Reserved Bit This bit is a reserved bit in the ATmega128 and always read as zero.  Bit 4 – RWWSRE: Read-While-Write Section Read Enable When Programming (page erase or page write) to the RWW section, the RWW section is blocked for reading (the RWWSB will be set by hardware). To re-enable the RWW section, the user software must wait unt il the programming is complet ed (SPMEN will be cl eared). Then, if the RWWSRE bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles re-enables the RWW secti on. The RWW section cannot be re-enabled while the Flash is busy with a page erase or a page writ e (SPMEN is set). If the RWWSRE bit is writ- ten while the Flash is being loaded, the Flas h load operation will abort and the data loaded will be lost.  Bit 3 – BLBSET: Boot Lock Bit Set If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles sets Boot Lock bits, according to the data in R0. The data in R1 and the address in the Z- pointer are ignored. The BLBSET bit will automatically be cleared upon completion of the lock bit set, or if no SPM instruction is executed within four clock cycles. An LPM instruction within three cycles after BLBSET and SPMEN are set in the SPMCSR Reg- ister, will read either the Lock bits or the Fuse bits (depending on Z0 in the Z-pointer) into the destination register. See “Reading the Fuse and Lock Bits from Software” on page 281 for details.  Bit 2 – PGWRT: Page Write If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes page write, with the data stored in the temporary buffer. The page address is taken from the high part of the Z-pointer. The data in R1 and R0 are ignored. The PGWRT bit will auto-clear upon completion of a page write, or if no SPM instruction is executed within four clock cycles. The CPU is halted during the entire page write operation if the NRWW section is addressed.  Bit 1 – PGERS: Page Erase If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes page erase. The page address is taken from the high part of the Z-pointer. The data in R1 and R0 are ignored. The PGERS bit will auto-clear upon completion of a page erase, Bit 7 6 5 4 3 2 1 0 SPMIE RWWSB – RWWSRE BLBSET PGWRT PGERS SPMEN SPMCSR Read/Write R/W R R R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0

2467R–AVR–06/08 ATmega128 or if no SPM instruction is executed within four clock cycles. The CPU is halted during the entire page write operation if the NRWW section is addressed.  Bit 0 – SPMEN: Store Program Memory Enable This bit enables the SPM instruction for the next four clock cycles. If written to one together with either RWWSRE, BLBSET, PGWRT’ or PGERS, the following SPM instruction will have a spe- cial meaning, see description above. If only SPMEN is written, the following SPM instruction will store the value in R1:R0 in the temporary page buffer addressed by the Z-pointer. The LSB of the Z-pointer is ignored. The SPMEN bit will aut o-clear upon completion of an SPM instruction, or if no SPM instruction is executed within four clock cycles. During page erase and page write, the SPMEN bit remains high until the operation is completed. Writing any other combination than “10001”, “01001”, “00101”, “00011” or “00001” in the lower five bits will have no effect. Addressing the Flash During Self- Programming The Z-pointer together with RAMPZ are used to address the SPM commands. For details on how to use the RAMPZ, see “RAM Page Z Select Register – RAMPZ” on page 14. Since the Flash is organized in pages (see Table 123 on page 291), the program counter can be treated as having two different sect ions. One section, consisting of the least significant bits, is addressing the words within a page, while the most significant bits are addressing the pages. This is shown in Figure 134. Note that the page erase and page write operations are addressed independently. Therefore it is of major importance that the Boot Loader software addresses the same page in both the page erase and page write operation. Once a programming operation is initiated, the address is latched and the Z-pointer/RAMPZ can be used for other operations. The only SPM operation that does not use the Z-pointer/RAMPZ is setting the Boot Loader Lock bits. The content of the Z-pointer/RAMPZ is i gnored and will have no ef fect on the operation. The (E)LPM instruction does also use the Z-pointer/RAMPZ to store the address. Since this instruction addresses the Flash byte by byte, also the LSB (bit Z0) of the Z-pointer is used. B i t 1 51 41 31 21 11 0 9 8 ZH (R31) Z15 Z14 Z13 Z12 Z11 Z10 Z9 Z8 ZL (R30) Z7 Z6 Z5 Z4 Z3 Z2 Z1 Z0 76543210

Figure 134. Addressing the Flash During SPM(1) Notes: 1. The different variables used in Figure 134 are listed in Table 114 on page 285.

1. PCPAGE and PCWORD are listed in Table 124 on page 292.

2467R–AVR–06/08 ATmega128 Performing Page Erase by SPM To execute page erase, set up the address in the Z-pointer and RAMPZ, write “X0000011” to SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The data in R1 and R0 is ignored. The page address must be written to PCPAGE in the Z-register. Other bits in the Z-pointer must be written zero during this operation.  Page Erase to the RWW section: The NRWW section can be read during the page erase.  Page Erase to the NRWW section: The CPU is halted during the operation. Filling the Temporary Buffer (Page Loading) To write an instruction word, set up the address in the Z-pointer and data in R1:R0, write “00000001” to SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The content of PCWORD in the Z-register is used to address the data in the temporary buffer. The temporary buffer will auto-erase after a page writ e operation or by writ ing the RWWSRE bit in SPMCSR. It is also erased after a System Reset. Note that it is not possible to write more than one time to each address without erasing the temporary buffer. Note: If the EEPROM is written in the middle of an SPM Page Load operation, all data loaded will be lost. Performing a Page Write To execute page write, set up the address in the Z-pointer and RAMPZ, write “X0000101” to SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The data in R1 and R0 is ignored. The page address must be written to PCPAGE. Other bits in the Z-pointer must be written zero during this operation.  Page Write to the RWW section: The NRWW section can be read during the page write.  Page Write to the NRWW section: The CPU is halted during the operation. Using the SPM Interrupt If the SPM interrupt is en abled, the SPM interrupt will genera te a constant in terrupt when the SPMEN bit in SPMCSR is cleared. This means th at the interrupt can be used instead of polling the SPMCSR Register in software. When using the SPM interrupt, the interrupt vectors should be moved to the BLS section to avoid that an interrupt is accessing the RWW section when it is blocked for reading. How to move the interrupts is described in “Interrupts” on page 60. Consideration While Updating BLS Special care must be taken if the user allows the Boot Loader section to be updated by leaving Boot Lock bit11 unprogrammed. An accidental write to the Boot Loader itself can corrupt the entire Boot Loader, and further software updates might be impossible. If it is not necessary to change the Boot Loader software itself, it is recommended to program the Boot Lock bit11 to protect the Boot Loader software from any internal software changes. Prevent Reading the RWW Section During Self-Programming During Self-Programming (either page erase or page write), the RWW section is always blocked for reading. The user software itself must prevent that this section is addressed during the Self- Programming operation. The RWWSB in the SPMCSR will be set as long as the RWW section is busy. During Self-Programming the interrupt vector table should be moved to the BLS as described in “Interrupts” on page 60, or the interrupts must be disabled. Before addressing the RWW section after the programming is completed, the user software must clear the RWWSB by writing the RWWSRE. See “Simple Assembly Code Example for a Boot Loader” on page 282 for an example.

2467R–AVR–06/08 ATmega128 Setting the Boot Loader Lock Bits by SPM To set the Boot Loader Lock bits, write the desired data to R0, write “X0001001” to SPMCSR and execute SPM within four clock cycles afte r writing SPMCSR. The only accessible lock bits are the Boot Lock bits that may prevent the A pplication and Boot Loader section from any soft- ware update by the MCU. See Table 108 and Table 109 for how the different settings of the Boot Loader Bits affect the Flash access. If bits 5..2 in R0 are cleared (zero), the corresponding Boot Lock bit will be programmed if an SPM instruction is executed within four cycles after BLBSET and SPMEN are set in SPMCSR. The Z-pointer is don’t care during this operation, but for future compatibility it is recommended to load the Z-pointer with $0001 (same as used for reading the Lock bits). For future compatibility It is also recommended to set bits 7, 6, 1, and 0 in R0 to “1” when writing the lock-bits. When pro- gramming the Lock Bits the entire Flash can be read during the operation. EEPROM Write Prevents Writing to SPMCSR Note that an EEPROM write operation will block all software programming to Flash. Reading the Fuses and Lock bits from software will also be prevented during the EEPROM write operation. It is recommended that the user checks the status bit (EEWE) in the EECR Register and verifies that the bit is cleared before writing to the SPMCSR Register. Reading the Fuse and Lock Bits from Software It is possible to read both the Fuse and Lock bits from software. To read the Lock bits, load the Z-pointer with $0001 and set the BLBSET and SPMEN bits in SPMCSR. When an LPM instruc- tion is executed within three CPU cycles after the BLBSET and SPMEN bits are set in SPMCSR, the value of the Lock bits will be loaded in the destination register. The BLBSET and SPMEN bits will auto-clear upon completion of reading the Lo ck bits or if no LPM instruction is executed within three CPU cycles or no SPM instruction is executed within four CPU cycles. When BLB- SET and SPMEN are cleared, LPM will work as described in the Instruction set Manual. The algorithm for reading the Fuse Low bits is similar to the one described above for reading the Lock bits. To read the Fuse Lo w bits, load the Z-pointer with $0000 and set the BLBSET and SPMEN bits in SPMCSR. When an LPM instruction is executed within three cycles after the BLBSET and SPMEN bits are set in the SPMCSR, the value of the Fuse Low bits (FLB) will be loaded in the destination register as shown below. Refer to Table 119 on page 288 for a detailed description and mapping of the Fuse Low bits. Similarly, when reading the Fuse High bits, l oad $0003 in the Z-pointer. When an LPM instruc- tion is executed within three cycles after the BLBSET and SPMEN bits are set in the SPMCSR, the value of the Fuse High bits (FHB) will be lo aded in the destination register as shown below. Refer to Table 118 on page 288 for detailed description and mapping of the Fuse High bits. When reading the Extended Fuse bits, load $0002 in the Z-pointer. When an LPM instruction is executed within three cycles after the BLBSET and SPMEN bits are set in the SPMCSR, the value of the Extended Fuse bits (EFB) will be loaded in the destination register as shown below. Refer to Table 117 on page 287 for detailed description and mapping of the Fuse High bits. B i t 76543210 R0 1 1 BLB12 BLB11 BLB02 BLB01 1 1 B i t 76543210 Rd – – BLB12 BLB11 BLB02 BLB01 LB2 LB1 B i t 76543210 Rd FLB7 FLB6 FLB5 FLB4 FLB3 FLB2 FLB1 FLB0 B i t 76543210 Rd FHB7 FHB6 FHB5 FHB4 FHB3 FHB2 FHB1 FHB0 B i t 76543210

unprogrammed, will be read as one. systems using the Flash, and the same design solutions should be applied.

1. If there is no need for a Boot Loader update in the system, program the Boot Loader Lock

bits to prevent any Boot Loader software updates.

1. Keep the AVR RESET active (low) during pe riods of insufficient power supply voltage.

be completed provided that the power supply voltage is sufficient.

1. Keep the AVR core in Power-down Sleep mode during periods of low V CC. This will pre-

the SPMCSR Register and thus the Flash from unintentional writes. gramming time for Flash accesses from the CPU. ; be read during self-programming (page erase and page write). ; loader section or that the interrupts are disabled. Table 111. SPM Programming Time.

2467R–AVR–06/08 ATmega128 ; transfer data from RAM to Flash page buffer ldi looplo, low(PAGESIZEB);init loop variable ldi loophi, high(PAGESIZEB);not required for PAGESIZEB<=256 Wrloop: ld r0, Y+ ld r1, Y+ ldi spmcsrval, (1<<SPMEN) call Do_spm adiw ZH:ZL, 2 sbiw loophi:looplo, 2 ;use subi for PAGESIZEB<=256 brne Wrloop ; execute page write subi ZL, low(PAGESIZEB) ;restore pointer sbci ZH, high(PAGESIZEB) ;not required for PAGESIZEB<=256 ldi spmcsrval, (1<<PGWRT) | (1<<SPMEN) call Do_spm ; re-enable the RWW section ldi spmcsrval, (1<<RWWSRE) | (1<<SPMEN) call Do_spm ; read back and check, optional ldi looplo, low(PAGESIZEB);init loop variable ldi loophi, high(PAGESIZEB);not required for PAGESIZEB<=256 subi YL, low(PAGESIZEB) ;restore pointer sbci YH, high(PAGESIZEB) Rdloop: lpm r0, Z+ ld r1, Y+ cpse r0, r1 jmp Error sbiw loophi:looplo, 1 ;use subi for PAGESIZEB<=256 brne Rdloop ; return to RWW section ; verify that RWW section is safe to read Return: lds temp1, SPMCSR sbrs temp1, RWWSB ; If RWWSB is set, the RWW section is not ready yet ret ; re-enable the RWW section ldi spmcsrval, (1<<RWWSRE) | (1<<SPMEN) call Do_spm rjmp Return Do_spm: ; check for previous SPM complete Wait_spm: lds temp1, SPMCSR sbrc temp1, SPMEN rjmp Wait_spm ; input: spmcsrval determines SPM action ; disable interrupts if enabled, store status in temp2, SREG cli ; check that no EEPROM write access is present

Table 112. Boot Size Configuration Table 113. Read-While-Write Limit(1)

Notes: 1. The Z-register is only 16 bits wide. Bit 16 is located in the RAMPZ register in the I/O map.

1. Z0: should be zero for all SPM commands, byte select for the (E)LPM instruction.
2. See “Addressing the Flash During Self-Programming” on page 278 for details about the use of

Z-pointer during self-programming. Table 114. Explanation of Different Variables Used in Figure 134 and the Mapping to the Z-

6 Most significant bit which is used to address the

Z16(1) Bit in Z-register that is mapped to PCMSB. Z7 Bit in Z-register that is mapped to PAGEMSB.

erased to “1” with the Chip Erase command. Table 115. Lock Bit Byte Table 116. Lock Bit Protection Modes 1 1 1 No memory lock features enabled. Serial and Parallel Programming mode. 2 1 0 SPM is not allowed to write to the Application section. are disabled while executing from the Application section. are disabled while executing from the Application section.

Notes: 1. Program the fuse bits before programming the Lock bits.

1. “1” means unprogrammed, “0´means programmed

cal zero, “0”, if they are programmed. Notes: 1. See “ATmega103 and ATmega128 Compatibility” on page 4 for details.

1. See “Watchdog Timer Control Register – WDTCR” on page 56 for details.

2 1 0 SPM is not allowed to write to the Boot Loader section. are disabled while executing from the Boot Loader section. are disabled while executing from the Boot Loader section. Table 116. Lock Bit Protection Modes (Continued) Table 117. Extended Fuse Byte

Notes: 1. The SPIEN fuse is not accessi ble in SPI Serial Programming mode.

1. The CKOPT fuse functio nality depends on the setting of the CKSEL bits. See “Clock

Sources” on page 37 for details.

1. The default value of BOOTSZ1..0 results in maximum Boot Size. See Table 112 on page 284
2. Never ship a product with the OCDEN Fuse progra mmed regardless of the setting of lock bits

to be running in all sleep modes. This may increase the power consumption.

1. If the JTAG interface is left unconnected, the JTAGEN fuse should if possible be disabled. This

to avoid static current at the TDO pin in the JTAG interface.

1. The default setting of CKSEL3..0 results in Internal RC Oscillator @ 1 MHz. See Table 6 on

Lock bit1 (LB1) is programmed. Program the Fuse bits before programming the Lock bits. Table 118. Fuse High Byte Table 119. Fuse Low Byte

2467R–AVR–06/08 ATmega128 the EESAVE fuse which will take effect once it is programmed. The fuses are also latched on power-up in normal mode. Signature Bytes All Atmel microcontrollers have a three-byte signature code which identifies the device. This code can be read in both serial and parallel mode, also when the device is locked. The three bytes reside in a separate address space. For the ATmega128 the signature bytes are: 1. $000: $1E (indicates manufactured by Atmel) 2. $001: $97 (indicates 128KB Flash memory) 3. $002: $02 (indicates ATmega128 device when $001 is $97) Calibration Byte The ATmega128 stores four different calibration values for the internal RC Oscillator. These bytes resides in the signature row high byte of the addresses 0x000, 0x0001, 0x0002, and 0x0003 for 1, 2, 4, and 8 MHz respectively. During Reset, the 1 MHz value is automatically loaded into the OSCCAL Register. If other frequencies are used, the calibration value has to be loaded manually, see “Oscillator Calibration Register – OSCCAL” on page 42 for details.

least 250 ns unless otherwise noted. the following table are referenced by pin names. The XA1/XA0 pins determine the action executed when the XTAL1 pin is given a positive pulse. The bit coding is shown in Table 122. Commands are shown in Table 123. Figure 135. Parallel Programming Table 120. Pin Name Mapping

Table 121. Pin Values Used to Enter Programming Mode Table 122. XA1 and XA0 Coding Table 123. Command Byte Bit Coding Table 120. Pin Name Mapping (Continued)

1. Apply 4.5 - 5.5 V between V CC and GND, and wait at least 100 µs.
2. Set RESET to “0” and toggle XTAL1 at least SIX times.
3. Set the Prog_enable pins listed in Table 121 on page 291 to “0000” and wait at least 100
4. Apply 11.5 - 12.5V to RESET . Any activity on Prog_enable pins within 100 ns after +12V

has been applied to RESET, will cause the device to fail entering programming mode.

1. Set Prog_enable pins listed in Table on page 291 to “0000”.
2. Re-program the fuses to ensure that External Clock is selected as clock source

executed before changing the fuses.

1. Exit Programming mode by power the device down or by bringing RESET
2. Entering Programming mode with the original algorithm, as described above.

programming, the following should be considered. EESAVE fuse is programmed) and Flash after a Chip Erase. Note: 1. The EEPRPOM memory is preserved duri ng chip erase if the EESAVE fuse is programmed. Table 124. No. of Words in a Page and no. of Pages in the Flash Table 125. No. of Words in a Page and no. of Pages in the EEPROM

2467R–AVR–06/08 ATmega128 Load Command “Chip Erase” 1. Set XA1, XA0 to “10”. This enables command loading. 2. Set BS1 to “0”. 3. Set DATA to “1000 0000”. This is the command for Chip Erase. 4. Give XTAL1 a positive pulse. This loads the command. 5. Give WR a negative pulse. This starts the Chip Erase. RDY/BSY goes low. 6. Wait until RDY/BSY goes high before loading a new command. Programming the Flash The Flash is organized in pages, see Table 123 on page 291. When programming the Flash, the program data is latched into a page buffer. This allows one page of program data to be pro- grammed simultaneously. The following procedure describes how to program the entire Flash memory: A. Load Command “Write Flash” 1. Set XA1, XA0 to “10”. This enables command loading. 2. Set BS1 to “0”. 3. Set DATA to “0001 0000”. This is the command for Write Flash. 4. Give XTAL1 a positive pulse. This loads the command. B. Load Address Low byte 1. Set XA1, XA0 to “00”. This enables address loading. 2. Set BS1 to “0”. This selects low address. 3. Set DATA = Address low byte ($00 - $FF). 4. Give XTAL1 a positive pulse. This loads the address low byte. C. Load Data Low Byte 1. Set XA1, XA0 to “01”. This enables data loading. 2. Set DATA = Data low byte ($00 - $FF). 3. Give XTAL1 a positive pulse. This loads the data byte. D. Load Data High Byte 1. Set BS1 to “1”. This selects high data byte. 2. Set XA1, XA0 to “01”. This enables data loading. 3. Set DATA = Data high byte ($00 - $FF). 4. Give XTAL1 a positive pulse. This loads the data byte. E. Latch Data 1. Set BS1 to “1”. This selects high data byte. 2. Give PAGEL a positive pulse. This latches the data bytes. (See Figure 137 for signal waveforms) F. Repeat B through E until the entire buffer is filled or until all data within the page is loaded. While the lower bits in the address are mapped to words within the page, the higher bits address the pages within the FLASH. This is illustrated in Figure 136 on page 294. Note that if less than 8 bits are required to address words in the page (pagesize < 256), the most significant bit(s) in the address low byte are used to address the page when performing a page write. G. Load Address High byte 1. Set XA1, XA0 to “00”. This enables address loading. 2. Set BS1 to “1”. This selects high address.

1. Set DATA = Address high byte ($00 - $FF).
2. Give XTAL1 a positive pulse. This loads the address high byte.
3. Wait until RDY/BSY goes high. (See Figure 137 for signal waveforms)
4. 1. Set XA1, XA0 to “10”. This enables command loading.
5. Set DATA to “0000 0000”. This is the command for No Operation.
6. Give XTAL1 a positive pulse. This loads the command, and the internal write signals are

Figure 136. Addressing the Flash which is Organized in Pages Note: 1. PCPAGE and PCWORD are listed in Table 124 on page 292.

Figure 137. Programming the Flash Waveforms Note: “XX” is don’t care. The letters refer to the programming description above.

1. G: Load Address High Byte ($00 - $FF).
2. B: Load Address Low Byte ($00 - $FF).
3. E: Latch data (give PAGEL a positive pulse).

K: Repeat 3 through 5 until the entire buffer is filled.

1. Wait until to RDY/BSY goes high before programming the next page.

Figure 138. Programming the EEPROM Waveforms

1. G: Load Address High Byte ($00 - $FF).
2. B: Load Address Low Byte ($00 - $FF).

to “0”, and BS1 to “0”. The Flash word low byte can now be read at DATA.

1. Set BS1 to “1”. The Flash word high byte can now be read at DATA.
2. G: Load Address High Byte ($00 - $FF).
3. B: Load Address Low Byte ($00 - $FF).

to “0”, and BS1 to “0”. The EEPROM Data byte can now be read at DATA.

1. C: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit.

a negative pulse and wait for RDY/BSY to go high.

1. C: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit.
2. Set BS1 to “1” and BS2 to “0”. This selects high data byte.

a negative pulse and wait for RDY/BSY to go high.

1. Set BS1 to “0”. This selects low data byte.
2. C: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit.
3. Set BS2 to “1” and BS1 to “0”. This selects extended data byte.

a negative pulse and wait for RDY/BSY to go high.

1. Set BS2 to “0”. This selects low data byte.

Figure 139. Programming the Fuses

1. C: Load Data Low Byte. Bit n = “0” programs the Lock bit.

a negative pulse and wait for RDY/BSY to go high. The Lock bits can only be cleared by executing Chip Erase. read at DATA (“0” means programmed).

1. Set OE to “0”, BS2 to “1”, and BS1 to “1”. The status of the Fuse High bits can now be

read at DATA (“0” means programmed).

1. t WLRH_CE is valid for the Chip Erase command.

pins are mapped to PDI and PDO. ming mode as shown in Table 127. Table 126. Parallel Programming Characteristics, VCC = 5 V ± 10% (Continued) Table 127. Pin Mapping SPI Serial Programming

Figure 144. SPI Serial Programming and Verify(1) When writing serial data to the ATmega128, data is clocked on the rising edge of SCK. after SCK has been set to “0”. normal operation when using this method.

1. Wait for at least 20 ms and enable SPI Serial Programming by sending the Programming

Enable serial instruction to pin MOSI.

2467R–AVR–06/08 ATmega128 3. The SPI Serial Programming instructions will no t work if the communication is out of syn- chronization. When in sync. the second byte ($53), will echo back when issuing the third byte of the Programming Enable instruction. Whether the echo is correct or not, all FOUR bytes of the instruction must be transmitte d. If the $53 did not echo back, give RESET a positive pulse and issue a new Programming Enable command. 4. The Flash is programmed one page at a time. The page size is found in Table 124 on page 292. The memory page is loaded one byte at a time by supplying the 7 LSB of the address and data together with the Load Program Memory Page instruction. To ensure correct loading of the page, the data low byte must be loaded before data high byte is applied for given address. The Program Memory Page is stored by loading the Write Pro- gram Memory Page instruction with the 9 MSB of the address. If po lling is not used, the user must wait at least t WD_FLASH before issuing the next page. (See Table 128). Note: If other commands than polling (read) are applied before any write operation (Flash, EEPROM, Lock bits, Fuses) is completed, may result in incorrect programming. 5. The EEPROM array is programmed one byte at a time by supplying the address and data together with th e appropriate Writ e instruction. An EEPROM me mory location is first automatically erased before new data is written. If polling is not used, the user must wait at least t WD_EEPROM before issuing the next byte. (See Table 128). In a chip erased device, no $FFs in the data file(s) need to be programmed. 6. Any memory location can be verified by using the Read instruction which returns the con- tent at the selected address at serial output MISO. 7. At the end of the programming session, RESET can be set high to commence normal operation. 8. Power-off sequence (if needed): Set RESET to “1”. Tur n VCC power off. Data Polling Flash When a page is being programmed into the Flash, reading an address location within the page being programmed will give the va lue $FF. At the time the devic e is ready for a new page, the programmed value will read correctly. This is used to determine when the next page can be writ- ten. Note that the entire page is written simultaneously and any address within the page can be used for polling. Data polling of the Flash will not work for the value $FF, so when programming this value, the user will have to wait for at least t WD_FLASH before programming the next page. As a chip-erased device contains $FF in all locations, programming of addresses that are meant to contain $FF, can be skipped. See Table 128 for t WD_FLASH value Data Polling EEPROM When a new byte has been written and is being programmed into EEPROM, reading the address location being programmed will give the value $FF. At the time the device is ready for a new byte, the programmed value will read correctly. This is us ed to determine when the next byte can be written. This will not work for the value $FF, but the user should have the following in mind: As a chip-erased device contains $FF in all locations, programming of addresses that are meant to contain $FF, can be skipped. This does not apply if the EEPROM is re-programmed without chip-erasing the device. In this case, data polling cannot be used for the value $FF, and the user will have to wait at least t WD_EEPROM before programming the next byte. See Table 128 for tWD_EEPROM value.

Figure 145. .SPI Serial Programming Waveforms Table 128. Minimum Wait Delay before Writing the Next Flash or EEPROM Location, VCC = 5 V

Table 129. SPI Serial Programming Instruction Set Chip Erase 1010 1100 100x xxxx xxxx xxxx xxxx xxxx Chip Erase EEPROM and Flash.

0010 H000 aaaa aaaa bbbb bbbb oooo oooo Read H (high or low) data o from Program

0100 H000 xxxx xxxx x bbb bbbb iiii iiii Write H (high or low) data i to Program

applied within the same address. Write Program Memory Page at address a:b. bits. See Table 115 on page 286 for details. Read Signature Byte 0011 0000 xxxx xxxx xxxx xx bb oooo oooo Read Signature Byte o at address b. Write Fuse bits 1010 1100 1010 0000 xxxx xxxx iiii iiii Set bits = “0” to program, “1” to unprogram. See Table 119 on page 288 for details. Write Fuse High Bits 1010 1100 1010 1000 xxxx xxxx iiii iiii Set bits = “0” to program, “1” to unprogram. See Table 118 on page 288 for details. 1010 1100 1010 0100 xxxx xxxx xxxx xx ii Set bits = “0” to program, “1” to unprogram. See Table 119 on page 288 for details. Read Calibration Byte 0011 1000 xxxx xxxx 0000 00 bb oooo oooo Read Calibration Byte o at address b.

2467R–AVR–06/08 ATmega128 SPI Serial Programming Characteristics For characteristics of the SPI module, see “SPI Timing Characteristics” on page 323. Programming Via the JTAG Interface Programming through the JTAG interface requires control of the four JTAG specific pins: TCK, TMS, TDI, and TDO. Control of the Reset and clock pins is not required. To be able to use the JTAG interface, the JTAGEN fuse must be programmed. The device is default shipped with the Fuse programmed. In addition, the JTD bit in MCUCSR must be cleared. Alternatively, if the JTD bit is set, the external reset can be forced low. Then, the JTD bit will be cleared after two chip clocks, and the JTAG pins are available for programming. This pro- vides a means of using the JTAG pins as normal port pins in running mode while still allowing In- System Programming via the JTAG interface. Note that this technique can not be used when using the JTAG pins for Boundary-scan or On-chi p Debug. In these cases the JTAG pins must be dedicated for this purpose. As a definition in this data sheet, the LSB is shifted in and out first of all Shift Registers. Programming Specific JTAG Instructions The instruction register is 4-bit wide, supporti ng up to 16 instructions. The JTAG instructions useful for Programming are listed below. The OPCODE for each instruction is shown behind the instruction name in hex format. The text describes which data register is selected as path between TDI and TDO for each instruction. The Run-Test/Idle state of the TAP controller is used to generate internal clocks. It can also be used as an idle state between JTAG sequences. The state machine sequence for changing the instruction word is shown in Figure 146.

Figure 146. State Machine Sequence for Changing the Instruction Word is a logic 'one' in the Reset Chain. The output from this chain is not latched.  Shift-DR: The Reset Register is shifted by the TCK input.  Shift-DR: the programming enable signature is shifted into the data register. Programming mode is entered if the signature is valid.

2467R–AVR–06/08 ATmega128 PROG_COMMANDS ($5) The AVR specific public JTAG instruction for entering programming commands via the JTAG port. The 15-bit Programming Command Register is selected as data register. The active states are the following:  Capture-DR: the result of the previous command is loaded into the data register.  Shift-DR: the data register is shifted by the TCK input, shifting out the result of the previous command and shifting in the new command.  Update-DR: the programming command is applied to the Flash inputs.  Run-Test/Idle: one clock cycle is generated, executing the applied command. PROG_PAGELOAD ($6) The AVR specific public JTAG instruction to directly load the Flash data page via the JTAG port. The 2048-bit Virtual Flash Page Load Register is selected as data register. This is a virtual scan chain with length equal to the number of bits in one Flash page. Internally the Shift Register is 8- bit. Unlike most JTAG instructions, the Update-DR state is not used to transfer data from the Shift Register. The data are automatically transferred to the Flash page buffer byte by byte in the Shift-DR state by an internal state machine. This is the only active state:  Shift-DR: Flash page data are shifted in fr om TDI by the TCK input, and automatically loaded into the Flash page one byte at a time. Note: The JTAG instruction PROG_PAGELOAD can only be used if the AVR device is the first device in JTAG scan chain. If the AVR cannot be the first device in the scan chain, the byte-wise program- ming algorithm must be used. PROG_PAGEREAD ($7) The AVR specific public JTAG instruction to read one full Flash data page via the JTAG port. The 2056-bit Virtual Flash Page Read Register is selected as data register. This is a virtual scan chain with length equal to the number of bits in one Flash page plus 8. Internally the Shift Regis- ter is 8-bit. Unlike most JTAG instructions, the Capture-DR state is not used to transfer data to the Shift Register. The data are automatically transferred from the Flash page buffer byte by byte in the Shift-DR state by an internal state machine. This is the only active state:  Shift-DR: Flash data are automatically read one byte at a time and shifted out on TDO by the TCK input. The TDI input is ignored. Note: The JTAG instruction PROG_PAGEREAD can only be used if the AVR device is the first device in JTAG scan chain. If the AVR cannot be the first device in the scan chain, the byte-wise program- ming algorithm must be used. Data Registers The data registers are selected by the JTAG instruction registers described in section “Program- ming Specific JTAG Instructions” on page 305 . The data registers relevant for programming operations are:  Reset Register  Programming Enable Register  Programming Command Register  Virtual Flash Page Load Register  Virtual Flash Page Read Register

required to reset the part before entering programming mode. not latched, so the reset will take place immediately, as shown in Figure 123 on page 254. Figure 147. Programming Enable Register

the programming commands is illustrated in Figure 149. Figure 148. Programming Command Register

Table 130. JTAG Programming Instruction

Table 130. JTAG Programming Instruction (Continued)

1. Set bits to “0” to program the corresponding fuse, “1” to unprogram the Fuse.
2. Set bits to “0” to program the corresponding lock bit, “1” to leave the Lock bit unchanged.
3. “0” = programmed, “1” = unprogrammed.
4. The bit mapping for Fuses Extended byte is listed in Table 117 on page 287
5. The bit mapping for Fuses High byte is listed in Table 118 on page 288
6. The bit mapping for Fuses Low byte is listed in Table 119 on page 288
7. The bit mapping for Lock bits byte is listed in Table 115 on page 286
8. Address bits exceeding PCMSB and EEAMSB (Table 123 and Table 124) are don’t care

Figure 149. State Machine Sequence for Changing/Reading the Data Word

2467R–AVR–06/08 ATmega128 Entering Programming Mode 1. Enter JTAG instruction AVR_RESET and shift 1 in the Reset Register. 2. Enter instruction PROG_ENABLE and shift 1010_0011_0111_0000 in the Programming Enable Register. Leaving Programming Mode 1. Enter JTAG instruction PROG_COMMANDS. 2. Disable all programming instructions by using no operation instruction 11a. 3. Enter instruction PROG_ENABLE and shift 0000_0000_0000_0000 in the programming Enable Register. 4. Enter JTAG instruction AVR_RESET and shift 0 in the Reset Register. Performing Chip Erase 1. Enter JTAG instruction PROG_COMMANDS. 2. Start chip erase using programming instruction 1a. 3. Poll for chip erase complete using prog ramming instruction 1b, or wait for t WLRH_CE (refer to Table Note: on page 299). Programming the Flash Before programming the Flash a Chip Erase must be performed. See “Performing Chip Erase” on page 315. 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Flash write using programming instruction 2a. 3. Load address high byte using programming instruction 2b. 4. Load address low byte using programming instruction 2c. 5. Load data using programming instructions 2d, 2e and 2f. 6. Repeat steps 4 and 5 for all instruction words in the page. 7. Write the page using programming instruction 2g. 8. Poll for Flash write complete using programming instruction 2h, or wait for t WLRH (refer to Table Note: on page 299). 9. Repeat steps 3 to 7 until all data have been programmed. A more efficient data transfer can be achieved using the PROG_PAGELOAD instruction: 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Flash write using programming instruction 2a. 3. Load the page address using programming instructions 2b and 2c. PCWORD (refer to Table 123 on page 291) is used to address within one page and must be written as 0. 4. Enter JTAG instruction PROG_PAGELOAD. 5. Load the entire page by shifting in all instruction words in the page, starting with the LSB of the first instruction in the page and ending with the MSB of the last instruction in the page. 6. Enter JTAG instruction PROG_COMMANDS. 7. Write the page using programming instruction 2g. 8. Poll for Flash write complete using programming instruction 2h, or wait for t WLRH (refer to Table Note: on page 299). 9. Repeat steps 3 to 8 until all data have been programmed.

2467R–AVR–06/08 ATmega128 Reading the Flash 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Flash read using programming instruction 3a. 3. Load address using programming instructions 3b and 3c. 4. Read data using programming instruction 3d. 5. Repeat steps 3 and 4 until all data have been read. A more efficient data transfer can be achieved using the PROG_PAGEREAD instruction: 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Flash read using programming instruction 3a. 3. Load the page address using programming instructions 3b and 3c. PCWORD (refer to Table 123 on page 291) is used to address within one page and must be written as 0. 4. Enter JTAG instruction PROG_PAGEREAD. 5. Read the entire page by shifting out all instruction words in the page, starting with the LSB of the first instruction in the page and ending with the MSB of the last instruction in the page. Remember that the first 8 bits shifted out should be ignored. 6. Enter JTAG instruction PROG_COMMANDS. 7. Repeat steps 3 to 6 until all data have been read. Programming the EEPROM Before programming the EEPROM a Chip Erase must be performed. See “Performing Chip Erase” on page 315. 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable EEPROM write using programming instruction 4a. 3. Load address high byte using programming instruction 4b. 4. Load address low byte using programming instruction 4c. 5. Load data using programming instructions 4d and 4e. 6. Repeat steps 4 and 5 for all data bytes in the page. 7. Write the data using programming instruction 4f. 8. Poll for EEPROM write complete using pr ogramming instruction 4g, or wait for t WLRH (refer to Table Note: on page 299). 9. Repeat steps 3 to 8 until all data have been programmed. Note that the PROG_PAGELOAD instruction can not be used when programming the EEPROM Reading the EEPROM 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable EEPROM read using programming instruction 5a. 3. Load address using programming instructions 5b and 5c. 4. Read data using programming instruction 5d. 5. Repeat steps 3 and 4 until all data have been read. Note that the PROG_PAGEREAD instruction can not be used when reading the EEPROM

2467R–AVR–06/08 ATmega128 Programming the Fuses 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Fuse write using programming instruction 6a. 3. Load data byte using programming instructi ons 6b. A bit value of “0” will program the cor- responding fuse, a “1” will unprogram the fuse. 4. Write Extended Fuse byte using programming instruction 6c. 5. Poll for Fuse write complete using prog ramming instruction 6d, or wait for t WLRH (refer to Table Note: on page 299). 6. Load data byte using programm ing instructions 6e. A bit value of “0” will program the cor- responding fuse, a “1” will unprogram the fuse. 7. Write Fuse high byte using programming instruction 6f. 8. Poll for Fuse write complete using prog ramming instruction 6g, or wait for t WLRH (refer to Table Note: on page 299). 9. Load data byte using programming instruct ions 6h. A “0” will program the fuse, a “1” will unprogram the fuse. 10. Write Fuse low byte usin g programming instruction 6i. 11. Poll for Fuse write complete using pr ogramming instruction 6j, or wait for t WLRH (refer to Table Note: on page 299). Programming the Lock Bits 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Lock bit write using programming instruction 7a. 3. Load data using prog ramming instructions 7b. A bit va lue of “0” will program the corre- sponding lock bit, a “1” will leave the lock bit unchanged. 4. Write Lock bits using programming instruction 7c. 5. Poll for Lock bit write complete using programming instruction 7d, or wait for t WLRH (refer to Table Note: on page 299). Reading the Fuses and Lock Bits 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Fuse/Lock bit read using programming instruction 8a. 3. To read all Fuses and Lock bits, use programming instruction 8f. To only read Extended Fuse byte, use programming instruction 8b. To only read Fuse high byte, use programming instruction 8c. To only read Fuse low byte, use programming instruction 8d. To only read Lock bits, use programming instruction 8e. Reading the Signature Bytes 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Signature byte read using programming instruction 9a. 3. Load address $00 using programming instruction 9b. 4. Read first signature byte using programming instruction 9c. 5. Repeat steps 3 and 4 with address $01 and address $02 to read the second and third signature bytes, respectively. Reading the Calibration Byte 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Calibration byte read using programming instruction 10a. 3. Load address $00 using programming instruction 10b. 4. Read the calibration byte using programming instruction 10c.

2467R–AVR–06/08 ATmega128

Electrical Characteristics

Note: Typical values contained in this data sheet are based on simulations and characterization of other AVR microcontrollers manu- factured on the same process technology. Min and Max values will be available after the device is characterized. Absolute Maximum Ratings* DC Characteristics Maximum Ratings” may cause permanent dam- age to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Voltage on any Pin except RESET DC Current TA = -40°C to 85°C, VCC = 2.7V to 5.5V (unless otherwise noted) Symbol Parameter Condition Min Typ Max Units VIL Input Low Voltage except (1) V VIH Input High Voltage except XTAL1 and RESET pins VCC=2.7 - 5.5. 0.6 V CC (2) VCC + 0.5 V VIL1 Input Low Voltage (1) V VIH1 Input High Voltage XTAL1 pin VCC=2.7 - 5.5. 0.7 V CC (2) VCC + 0.5 V VIL2 Input Low Voltage (1) V VIH2 Input High Voltage RESET pin VCC=2.7 - 5.5. 0.85 V CC (2) VCC + 0.5 V VOL Output Low Voltage(3) (Ports A,B,C,D, E, F , G) IOL = 20 mA, VCC = 5V IOL = 10 mA, VCC = 3V 0.7 0.5 V V VOH Output High Voltage(4) (Ports A,B,C,D, E, F , G) IOH = -20 mA, VCC = 5V IOH = -10 mA, VCC = 3V 4.2 2.2 V V IIL Input Leakage Current I/O Pin Vcc = 5.5V, pin low (absolute value) 1.0 µA IIH Input Leakage Current I/O Pin Vcc = 5.5V, pin high (absolute value) 1.0 µA RRST Reset Pull-up Resistor 30 60 k Ω RPEN PEN Pull-up Resistor 30 60 k Ω RPU I/O Pin Pull-up Resistor 20 50 k Ω

2467R–AVR–06/08 ATmega128 Notes: 1. “Max” means the highest value where the pin is guaranteed to be read as low 2. “Min” means the lowest value where the pin is guaranteed to be read as high 3. Although each I/O port can sink more than the test conditions (20 mA at V CC = 5V, 10 mA at VCC = 3V) under steady state conditions (non-transient), the following must be observed: TQFP and QFN/MLF Package: 1] The sum of all IOL, for all ports, should not exceed 400 mA. 2] The sum of all IOL, for ports A0 - A7, G2, C3 - C7 should not exceed 100 mA. 3] The sum of all IOL, for ports C0 - C2, G0 - G1, D0 - D7, XTAL2 should not exceed 100 mA. 4] The sum of all IOL, for ports B0 - B7, G3 - G4, E0 - E7 should not exceed 100 mA. 5] The sum of all IOL, for ports F0 - F7, should not exceed 100 mA. If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test condition. 4. Although each I/O port can source more than the test condition s (20 mA at Vcc = 5V, 10 mA at Vcc = 3V) under steady state conditions (non-transient), the following must be observed: TQFP and QFN/MLF Package: 1] The sum of all IOH, for all ports, should not exceed 400 mA. 2] The sum of all IOH, for ports A0 - A7, G2, C3 - C7 should not exceed 100 mA. 3] The sum of all IOH, for ports C0 - C2, G0 - G1, D0 - D7, XTAL2 should not exceed 100 mA. 4] The sum of all IOH, for ports B0 - B7, G3 - G4, E0 - E7 should not exceed 100 mA. 5] The sum of all IOH, for ports F0 - F7, should not exceed 100 mA. If IOH exceeds the test condition, VOH may exceed the rela ted specification. Pins are not guaranteed to source current greater than the listed test condition. I CC Power Supply Current Active 4 MHz, VCC = 3V (ATmega128L) 5.5 mA Active 8 MHz, VCC = 5V (ATmega128) 19 mA Idle 4 MHz, VCC = 3V (ATmega128L) 2.5 mA Idle 8 MHz, VCC = 5V (ATmega128) 11 mA Power-down mode WDT enabled, VCC = 3V < 15 25 µA WDT disabled, VCC = 3V < 5 10 µA VACIO Analog Comparator Input Offset Voltage VCC = 5V Vin = VCC/2 40 mV IACLK Analog Comparator Input Leakage Current VCC = 5V Vin = VCC/2 -50 50 nA tACPD Analog Comparator Propagation Delay VCC = 2.7V VCC = 5.0V 750 500 ns TA = -40°C to 85°C, VCC = 2.7V to 5.5V (unless otherwise noted) (Continued) Symbol Parameter Condition Min Typ Max Units

Figure 153. External Clock Drive Waveforms

16 MHz

8 MHz

Table 131. External Clock Drive

the table includes pin capacitance. This will vary with package type.

1. The frequency will vary with package type and board layout.

Table 132. External RC Oscillator, Typical Frequencies

Interface meets or exceeds these requirements under the noted conditions. Timing symbols refer to Figure 154. Notes: 1. In ATmega128, this parameter is characterized and not 100% tested.

1. Required only for f SCL > 100 kHz.
2. C b = capacitance of one bus line in pF .
3. f CK = CPU clock frequency

Table 133. Two-wire Serial Bus Requirements

1. This requirement applies to all ATmega128 Two-wire Serial Interface operation. Other devices

connected to the Two-wire Serial Bus need only obey the general fSCL requirement.

1. The actual low period generated by the ATmega128 Two-wire Serial Interface is (1/fSCL - 2/fCK),
2. The actual low period generated by the ATmega128 Two-wire Serial Interface is (1/fSCL - 2/fCK),

ATmega128 devices, as well as any other device with a proper tLOW acceptance margin. Figure 154. Two-wire Serial Bus Timing See Figure 155 and Figure 156 for details. Table 134. SPI Timing Parameters

1 SCK period Master See Table 72

2 SCK high/low Master 50% duty cycle

4 Setup Master 10

5 Hold Master 10

7 SCK to out Master 10

8 SCK to out high Master 10

9 SS low to out Slave 15

10 SCK period Slave 4  t ck

11 SCK high/low (1) Slave 2  t ck

13 Setup Slave 10

14 Hold Slave 10

15 SCK to out Slave 15

16 SCK to SS

17 SS high to tri-state Slave 10

18 SS low to SCK Slave 2  t ck

Notes: 1. Values are guidelines only.

1. Minimum for AVCC is 2.7V.

Table 135. ADC Characteristics, Single Ended Channels

1.5 LSB

3.25 LSB

3.75 LSB

0.75 LSB

0.5 LSB

Table 136. ADC Characteristics, Differential Channels

17 LSB

Notes: 1. Values are guidelines only.

1. Minimum for AVCC is 2.7V.
2. Maximum for AVCC is 5.5V.

Table 136. ADC Characteristics, Differential Channels (Continued)

Notes: 1. This assumes 50% clock duty cycl e. The half period is actually the high time of the external clock, XTAL1.

1. This assumes 50% clock duty cycle. The half period is actually the low time of the external clock, XTAL1.

Table 137. External Data Memory Characteristics, 4.5 - 5.5 Volts, No Wait-state

8 MHz Oscillator Variable Oscillator

Table 138. External Data Memory Characteristics, 4.5 - 5.5 Volts, 1 Cycle Wait-state

Table 139. External Data Memory Characteristics, 4.5 - 5.5 Volts, SRWn1 = 1, SRWn0 = 0

4 MHz Oscillator Variable Oscillator

Table 140. External Data Memory Characteristics, 4.5 - 5.5 Volts, SRWn1 = 1, SRWn0 = 1 Table 141. External Data Memory Characteristics, 2.7 - 5.5 Volts, No Wait-state

Notes: 1. This assumes 50% clock duty cycl e. The half period is actually the high time of the external clock, XTAL1.

1. This assumes 50% clock duty cycle. The half period is actually the low time of the external clock, XTAL1.

Table 141. External Data Memory Characteristics, 2.7 - 5.5 Volts, No Wait-state (Continued) Table 142. External Data Memory Characteristics, 2.7 - 5.5 Volts, SRWn1 = 0, SRWn0 = 1 Table 143. External Data Memory Characteristics, 2.7 - 5.5 Volts, SRWn1 = 1, SRWn0 = 0 Table 144. External Data Memory Characteristics, 2.7 - 5.5 Volts, SRWn1 = 1, SRWn0 = 1

2467R–AVR–06/08 ATmega128 Typical Characteristics The following charts show typical behavior. T hese figures are not tested during manufacturing. All current consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. A sine wave generator with rail-to-rail output is used as clock source. The power consumption in Power-down mode is independent of clock selection. The current consumption is a function of several factors such as: operating voltage, operating frequency, loading of I/O pins, switching rate of I/O pins, code executed and ambient tempera- ture. The dominating factors are operating voltage and frequency. The current drawn from capacitive loaded pins may be estimated (for one pin) as C L*VCC*f where CL = load capacitance, VCC = operating voltage and f = average switching frequency of I/O pin. The parts are characterized at frequencies higher than test limits. Parts are not guaranteed to function properly at frequencies higher than the ordering code indicates. The difference between current consumption in Power-down mode with Watchdog Timer enabled and Power-down mode with Watchdog Timer disabled represents the differential cur- rent drawn by the Watchdog Timer. Active Supply Current Figure 161. Active Supply Current vs. Frequency (0.1 - 1.0 MHz) ACTIVE SUPPLY CURRENT vs. FREQUENCY 0.1 - 1.0 MHz 5.5 V 5.0 V 4.5 V 4.0 V 3.3 V 2.7 V 0.5 1.5 2.5 3.5 Frequency (MHz) ICC (mA)

Figure 169. Idle Supply Current vs. Frequency (1 - 20 MHz)

Figure 178. Standby Supply Current vs. VCC, Figure 179. Standby Supply Current vs. VCC (CKOPT programmed)

6 MHz Xtal

6 MHz Res

4 MHz Xtal

4 MHz Res

2 MHz Xtal

2 MHz Res

1 MHz Res

16 MHz Xtal

12 MHz Xtal

Figure 181. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7V)

Figure 183. I/O Pin Source Current vs. Output Voltage (VCC = 2.7V)

2467R–AVR–06/08 ATmega128 Register Summary Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page ($9D) UCSR1C – UMSEL1 UPM11 UPM10 USBS1 UCSZ11 UCSZ10 UCPOL1 191 ($9C) UDR1 USART1 I/O Data Register 189 ($9B) UCSR1A RXC1 TXC1 UDRE1 F E1 DOR1 UPE1 U2X1 MPCM1 189 ($9A) UCSR1B RXCIE1 TXCIE1 UDRIE1 RXEN1 TXEN1 UCSZ12 RXB81 TXB81 190 ($99) UBRR1L USART1 Baud Rate Register Low 192 ($98) UBRR1H – – – – USART1 Baud Rate Register High 192 ($95) UCSR0C – UMSEL0 UPM01 UPM00 USBS0 UCSZ01 UCSZ00 UCPOL0 191 ($90) UBRR0H – – – – USART0 Baud Rate Register High 192 ($8C) TCCR3C FOC3A FOC3B FOC3C – – – – – 137 ($8B) TCCR3A COM3A1 COM3A0 COM3B1 COM3B0 COM3C1 COM3C0 WGM31 WGM30 133 ($8A) TCCR3B ICNC3 ICES3 – WGM33 WGM32 CS32 CS31 CS30 136 ($89) TCNT3H Timer/Counter3 – Counter Register High Byte 138 ($88) TCNT3L Timer/Counter3 – Counter Register Low Byte 138 ($87) OCR3AH Timer/Counter3 – Output Compare Register A High Byte 138 ($86) OCR3AL Timer/Counter3 – Output Compare Register A Low Byte 138 ($85) OCR3BH Timer/Counter3 – Output Compare Register B High Byte 139 ($84) OCR3BL Timer/Counter3 – Output Compare Register B Low Byte 139 ($83) OCR3CH Timer/Counter3 – Output Compare Register C High Byte 139 ($82) OCR3CL Timer/Counter3 – Output Compare Register C Low Byte 139 ($81) ICR3H Timer/Counter3 – Input Capture Register High Byte 139 ($80) ICR3L Timer/Counter3 – Input Capture Register Low Byte 139 ($7F) Reserved ($7D) ETIMSK – – TICIE3 OCIE3A OCIE3B TOIE3 OCIE3C OCIE1C 140 ($7C) ETIFR – – ICF3 OCF3A OCF3B TOV3 OCF3C OCF1C 141 ($7A) TCCR1C FOC1A FOC1B FOC1C – – – – – 137 ($79) OCR1CH Timer/Counter1 – Output Compare Register C High Byte 138 ($78) OCR1CL Timer/Counter1 – Output Compare Register C Low Byte 138 ($74) TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN – TWIE 206 ($73) TWDR Two-wire Serial Interface Data Register 208 ($72) TWAR TWA6 TWA5 TWA4 TWA3 TWA2 TWA1 TWA0 TWGCE 208 ($71) TWSR TWS7 TWS6 TWS5 TWS4 TWS3 – TWPS1 TWPS0 207 ($70) TWBR Two-wire Serial Interface Bit Rate Register 206 ($6F) OSCCAL Oscillator Calibration Register 42 ($6D) XMCRA – SRL2 SRL1 SRL0 SRW01 SRW00 SRW11 31 ($6C) XMCRB XMBK – – – – XMM2 XMM1 XMM0 33 ($6A) EICRA ISC31 ISC30 ISC21 ISC20 ISC11 ISC10 ISC01 ISC00 90 ($68) SPMCSR SPMIE RWWSB – RWWSRE BLBSET PGWRT PGERS SPMEN 277 ($65) PORTG – – – PORTG4 PORTG3 PORTG2 PORTG1 PORTG0 89 ($64) DDRG – – – DDG4 DDG3 DDG2 DDG1 DDG0 89 ($63) PING – – – PING4 PING3 PING2 PING1 PING0 89 ($62) PORTF PORTF7 PORTF6 PORTF5 PO RTF4 PORTF3 PORTF2 PORTF1 PORTF0 88

2467R–AVR–06/08 ATmega128 ($61) DDRF DDF7 DDF6 DDF5 DDF4 DDF3 DDF2 DDF1 DDF0 89 $3F ($5F) SREG I T H S V N Z C 11 $3E ($5E) SPH SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 14 $3D ($5D) SPL SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 14 $3C ($5C) XDIV XDIVEN XDIV6 XDIV5 XDIV4 XDIV3 XDIV2 XDIV1 XDIV0 37 $3B ($5B) RAMPZ $3A ($5A) EICRB ISC71 ISC70 ISC61 ISC60 ISC51 ISC50 ISC41 ISC40 91 $39 ($59) EIMSK INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0 92 $38 ($58) EIFR INTF7 INTF6 INTF5 INTF4 INTF3 INTF INTF1 INTF0 92 $37 ($57) TIMSK OCIE2 TOIE2 TICIE1 OCIE1A OCIE1B TOIE1 OCIE0 TOIE0 109, 139, 159 $36 ($56) TIFR OCF2 TOV2 ICF1 OCF1A OCF1B TOV1 OCF0 TOV0 109, 141, 160 $35 ($55) MCUCR SRE SRW10 SE SM1 SM0 SM2 IVSEL IVCE 31, 45, 64 $34 ($54) MCUCSR JTD – – JTRF WDRF BORF EXTRF PORF 54, 254 $33 ($53) TCCR0 FOC0 WGM00 COM01 COM00 WGM01 CS02 CS01 CS00 104 $32 ($52) TCNT0 Timer/Counter0 (8 Bit) 106 $31 ($51) OCR0 Timer/Counter0 Output Compare Register 106 $30 ($50) ASSR – – – – AS0 TCN0UB OCR0UB TCR0UB 107 $2F ($4F) TCCR1A COM1A1 COM1A0 COM1B1 COM1B0 COM1C1 COM1C0 WGM11 WGM10 133 $2E ($4E) TCCR1B ICNC1 ICES1 – WGM13 WGM12 CS12 CS11 CS10 136 $2D ($4D) TCNT1H Timer/Counter1 – Counter Register High Byte 138 $2C ($4C) TCNT1L Timer/Counter1 – Counter Register Low Byte 138 $2B ($4B) OCR1AH Timer/Counter1 – Output Compare Register A High Byte 138 $2A ($4A) OCR1AL Timer/Counter1 – Output Compare Register A Low Byte 138 $29 ($49) OCR1BH Timer/Counter1 – Output Compare Register B High Byte 138 $28 ($48) OCR1BL Timer/Counter1 – Output Compare Register B Low Byte 138 $27 ($47) ICR1H Timer/Counter1 – Input Capture Register High Byte 139 $26 ($46) ICR1L Timer/Counter1 – Input Capture Register Low Byte 139 $25 ($45) TCCR2 FOC2 WGM20 COM21 COM20 WGM21 CS22 CS21 CS20 157 $24 ($44) TCNT2 Timer/Counter2 (8 Bit) 159 $23 ($43) OCR2 Timer/Counter2 Output Compare Register 159 $22 ($42) OCDR IDRD/OCDR7 OCDR6 OCDR5 OCDR4 OCDR3 OCDR2 OCDR1 OCDR0 251 $21 ($41) WDTCR – – – WDCE WDE WDP2 WDP1 WDP0 56 $20 ($40) SFIOR TSM – – – ACME PUD PSR0 PSR321 73, 110, 145, 227 $1F ($3F) EEARH – – – – EEPROM Address Register High 21 $1E ($3E) EEARL EEPROM Address Register Low Byte 21 $1D ($3D) EEDR EEPROM Data Register 22 $1C ($3C) EECR – – – – EERIE EEMWE EEWE EERE 22 $1B ($3B) PORTA PORTA7 PORTA6 PORTA5 PORTA4 PORTA3 PORTA2 PORTA1 PORTA0 87 $1A ($3A) DDRA DDA7 DDA6 DDA 5 DDA4 DDA3 DDA2 DDA1 DDA0 87 $19 ($39) PINA PINA7 PINA6 PINA5 PINA4 PINA3 PINA2 PINA1 PINA0 87 $18 ($38) PORTB PORTB7 PORTB6 PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 87 $17 ($37) DDRB DDB7 DDB6 DDB 5 DDB4 DDB3 DDB2 DDB1 DDB0 87 $16 ($36) PINB PINB7 PINB6 PINB5 PINB4 PINB3 PINB2 PINB1 PINB0 87 $15 ($35) PORTC PORTC7 PORTC6 PORTC5 PORTC4 PORTC3 PORTC2 PORTC1 PORTC0 87 $14 ($34) DDRC DDC7 DDC6 DDC5 DDC4 DDC3 DDC2 DDC1 DDC0 87 $13 ($33) PINC PINC7 PINC6 PINC5 PINC4 PINC3 PINC2 PINC1 PINC0 88 $12 ($32) PORTD PORTD7 PORTD6 PORTD5 PORTD4 PORTD3 PORTD2 PORTD1 PORTD0 88 $11 ($31) DDRD DDD7 DDD6 DDD5 DDD4 DDD3 DDD2 DDD1 DDD0 88 $10 ($30) PIND PIND7 PIND6 PIND5 PIND4 PIND3 PIND2 PIND1 PIND0 88 $0F ($2F) SPDR SPI Data Register 169 $0E ($2E) SPSR SPIF WCOL $0D ($2D) SPCR SPIE SPE DORD MSTR CPOL CPHA SPR1 SPR0 167 $0C ($2C) UDR0 USART0 I/O Data Register 189 $0B ($2B) UCSR0A RXC0 TXC0 UDRE0 FE0 DOR0 UPE0 U2X0 MPCM0 189 $0A ($2A) UCSR0B RXCIE0 TXCIE0 UDRI E0 RXEN0 TXEN0 UCSZ02 RXB80 TXB80 190 $09 ($29) UBRR0L USART0 Baud Rate Register Low 192 $08 ($28) ACSR ACD ACBG ACO ACI ACIE ACIC ACIS1 ACIS0 227 $07 ($27) ADMUX REFS1 REFS0 AD LAR MUX4 MUX3 MUX2 MUX1 MUX0 242 $06 ($26) ADCSRA ADEN ADSC ADFR ADIF ADIE ADPS2 ADPS1 ADPS0 244 $05 ($25) ADCH ADC Data Register High Byte 245 $04 ($24) ADCL ADC Data Register Low byte 245 $03 ($23) PORTE PORTE7 PORTE6 PORTE5 PORTE4 PORTE3 PORTE2 PORTE1 PORTE0 88 $02 ($22) DDRE DDE7 DDE6 DDE 5 DDE4 DDE3 DDE2 DDE1 DDE0 88 Register Summary (Continued) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page

2467R–AVR–06/08 ATmega128 Notes: 1. For compatibility with future devices, reserved bits shoul d be written to zero if accessed. Reserved I/O memory address es should never be written. 2. Some of the status flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on all bits in the I/O register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instruction s work with registers $00 to $1F only. $01 ($21) PINE PINE7 PINE6 PINE5 PINE4 PINE3 PINE2 PINE1 PINE0 88 $00 ($20) PINF PINF7 PINF6 PINF5 PINF4 PINF3 PINF2 PINF1 PINF0 89 Register Summary (Continued) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page

2467R–AVR–06/08 ATmega128 Instruction Set Summary Mnemonics Operands Description Operation Flags #Clocks ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd, Rr Add two Registers Rd ← Rd + Rr Z,C,N,V,H 1 ADC Rd, Rr Add with Carry two Registers Rd ← Rd + Rr + C Z,C,N,V,H 1 ADIW Rdl,K Add Immediate to Word Rdh:Rdl ← Rdh:Rdl + K Z,C,N,V,S 2 SUB Rd, Rr Subtract two Registers Rd ← Rd - Rr Z,C,N,V,H 1 SUBI Rd, K Subtract Constant from Register Rd ← Rd - K Z,C,N,V,H 1 SBC Rd, Rr Subtract with Carry two Registers Rd ← Rd - Rr - C Z,C,N,V,H 1 SBCI Rd, K Subtract with Carry Constant from Reg. Rd ← Rd - K - C Z,C,N,V,H 1 SBIW Rdl,K Subtract Immediate from Word Rdh:Rdl ← Rdh:Rdl - K Z,C,N,V,S 2 AND Rd, Rr Logical AND Registers Rd ← Rd • Rr Z,N,V 1 ANDI Rd, K Logical AND Register and Constant Rd ← Rd • K Z,N,V 1 OR Rd, Rr Logical OR Registers Rd ← Rd v Rr Z,N,V 1 ORI Rd, K Logical OR Register and Constant Rd ← Rd v K Z,N,V 1 EOR Rd, Rr Exclusive OR Registers Rd ← Rd ⊕ Rr Z,N,V 1 COM Rd One’s Complement Rd ← $FF − Rd Z,C,N,V 1 NEG Rd Two’s Complement Rd ← $00 − Rd Z,C,N,V,H 1 SBR Rd,K Set Bit(s) in Register Rd ← Rd v K Z,N,V 1 CBR Rd,K Clear Bit(s) in Register Rd ← Rd • ($FF - K) Z,N,V 1 INC Rd Increment Rd ← Rd + 1 Z,N,V 1 DEC Rd Decrement Rd ← Rd − 1 Z,N,V 1 TST Rd Test for Zero or Minus Rd ← Rd • Rd Z,N,V 1 CLR Rd Clear Register Rd ← Rd ⊕ Rd Z,N,V 1 SER Rd Set Register Rd ← $FF None 1 MUL Rd, Rr Multiply Unsigned R1:R0 ← Rd x Rr Z,C 2 MULS Rd, Rr Multiply Signed R1:R0 ← Rd x Rr Z,C 2 MULSU Rd, Rr Multiply Signed with Unsigned R1:R0 ← Rd x Rr Z,C 2 FMUL Rd, Rr Fractional Multiply Unsigned R1:R0 ← (Rd x Rr) << 1 Z,C 2 FMULS Rd, Rr Fractional Multiply Signed R1:R0 ← (Rd x Rr) << 1 Z,C 2 FMULSU Rd, Rr Fractional Multiply Signed with Unsigned R1:R0 ← (Rd x Rr) << 1 Z,C 2 BRANCH INSTRUCTIONS RJMP k Relative Jump PC ← PC + k + 1 None 2 IJMP Indirect Jump to (Z) PC ← Z None 2 JMP k Direct Jump PC ← kN o n e 3 RCALL k Relative Subroutine Call PC ← PC + k + 1 None 3 ICALL Indirect Call to (Z) PC ← ZN o n e 3 CALL k Direct Subroutine Call PC ← kN o n e 4 RET Subroutine Return PC ← STACK None 4 RETI Interrupt Return PC ← STACK I 4 CPSE Rd,Rr Compare, Skip if Equal if (Rd = Rr) PC ← PC + 2 or 3 None 1 / 2 / 3 CP Rd,Rr Compare Rd − Rr Z, N,V,C,H 1 CPC Rd,Rr Compare with Carry Rd − Rr − C Z, N,V,C,H 1 CPI Rd,K Compare Register with Immediate Rd − K Z, N,V,C,H 1 SBRC Rr, b Skip if Bit in Register Cleared if (Rr(b)=0) PC ← PC + 2 or 3 None 1 / 2 / 3 SBRS Rr, b Skip if Bit in Register is Set if (Rr(b)=1) PC ← PC + 2 or 3 None 1 / 2 / 3 SBIC P, b Skip if Bit in I/O Register Cleared if (P(b)=0) PC ← PC + 2 or 3 None 1 / 2 / 3 SBIS P, b Skip if Bit in I/O Register is Set if (P(b)=1) PC ← PC + 2 or 3 None 1 / 2 / 3 BRBS s, k Branch if Status Flag Set if (SREG(s) = 1) then PC ←PC+k + 1 None 1 / 2 BRBC s, k Branch if Status Flag Cleared if (SREG(s) = 0) then PC ←PC+k + 1 None 1 / 2 BREQ k Branch if Equal if (Z = 1) then PC ← PC + k + 1 None 1 / 2 BRNE k Branch if Not Equal if (Z = 0) then PC ← PC + k + 1 None 1 / 2 BRCS k Branch if Carry Set if (C = 1) then PC ← PC + k + 1 None 1 / 2 BRCC k Branch if Carry Cleared if (C = 0) then PC ← PC + k + 1 None 1 / 2 BRSH k Branch if Same or Higher if (C = 0) then PC ← PC + k + 1 None 1 / 2 BRLO k Branch if Lower if (C = 1) then PC ← PC + k + 1 None 1 / 2 BRMI k Branch if Minus if (N = 1) then PC ← PC + k + 1 None 1 / 2 BRPL k Branch if Plus if (N = 0) then PC ← PC + k + 1 None 1 / 2 BRGE k Branch if Greater or Equal, Signed if (N ⊕ V= 0) then PC ← PC + k + 1 None 1 / 2 BRLT k Branch if Less Than Zero, Signed if (N ⊕ V= 1) then PC ← PC + k + 1 None 1 / 2 BRHS k Branch if Half Carry Flag Set if (H = 1) then PC ← PC + k + 1 None 1 / 2 BRHC k Branch if Half Carry Flag Cleared if (H = 0) then PC ← PC + k + 1 None 1 / 2 BRTS k Branch if T Flag Set if (T = 1) then PC ← PC + k + 1 None 1 / 2 BRTC k Branch if T Flag Cleared if (T = 0) then PC ← PC + k + 1 None 1 / 2 BRVS k Branch if Overflow Flag is Set if (V = 1) then PC ← PC + k + 1 None 1 / 2 BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC ← PC + k + 1 None 1 / 2

2467R–AVR–06/08 ATmega128 Mnemonics Operands Description Operation Flags #Clocks BRIE k Branch if Interrupt Enabled if ( I = 1) then PC ← PC + k + 1 None 1 / 2 BRID k Branch if Interrupt Disabled if ( I = 0) then PC ← PC + k + 1 None 1 / 2 DATA TRANSFER INSTRUCTIONS MOV Rd, Rr Move Between Registers Rd ← Rr None 1 MOVW Rd, Rr Copy Register Word Rd+1:Rd ← Rr+1:Rr None 1 LDI Rd, K Load Immediate Rd ← KN o n e 1 LD Rd, X Load Indirect Rd ← (X) None 2 LD Rd, X+ Load Indirect and Post-Inc. Rd ← (X), X ← X + 1 None 2 LD Rd, - X Load Indirect and Pre-Dec. X ← X - 1, Rd ← (X) None 2 LD Rd, Y Load Indirect Rd ← (Y) None 2 LD Rd, Y+ Load Indirect and Post-Inc. Rd ← (Y), Y ← Y + 1 None 2 LD Rd, - Y Load Indirect and Pre-Dec. Y ← Y - 1, Rd ← (Y) None 2 LDD Rd,Y+q Load Indirect with Displacement Rd ← (Y + q) None 2 LD Rd, Z Load Indirect Rd ← (Z) None 2 LD Rd, Z+ Load Indirect and Post-Inc. Rd ← (Z), Z ← Z+1 None 2 LD Rd, -Z Load Indirect and Pre-Dec. Z ← Z - 1, Rd ← (Z) None 2 LDD Rd, Z+q Load Indirect with Displacement Rd ← (Z + q) None 2 LDS Rd, k Load Direct from SRAM Rd ← (k) None 2 ST X, Rr Store Indirect (X) ← Rr None 2 ST X+, Rr Store Indirect and Post-Inc. (X) ← Rr, X ← X + 1 None 2 ST - X, Rr Store Indirect and Pre-Dec. X ← X - 1, (X) ← Rr None 2 ST Y, Rr Store Indirect (Y) ← Rr None 2 ST Y+, Rr Store Indirect and Post-Inc. (Y) ← Rr, Y ← Y + 1 None 2 ST - Y, Rr Store Indirect and Pre-Dec. Y ← Y - 1, (Y) ← Rr None 2 STD Y+q,Rr Store Indirect with Displacement (Y + q) ← Rr None 2 ST Z, Rr Store Indirect (Z) ← Rr None 2 ST Z+, Rr Store Indirect and Post-Inc. (Z) ← Rr, Z ← Z + 1 None 2 ST -Z, Rr Store Indirect and Pre-Dec. Z ← Z - 1, (Z) ← Rr None 2 STD Z+q,Rr Store Indirect with Displacement (Z + q) ← Rr None 2 STS k, Rr Store Direct to SRAM (k) ← Rr None 2 LPM Load Program Memory R0 ← (Z) None 3 LPM Rd, Z Load Program Memory Rd ← (Z) None 3 LPM Rd, Z+ Load Program Memory and Post-Inc Rd ← (Z), Z ← Z+1 None 3 ELPM Extended Load Program Memory R0 ← (RAMPZ:Z) None 3 ELPM Rd, Z Extended Load Program Memory Rd ← (RAMPZ:Z) None 3 ELPM Rd, Z+ Extended Load Program Memory and Post-Inc Rd ← (RAMPZ:Z), RAMPZ:Z ← RAMPZ:Z+1 None 3 SPM Store Program Memory (Z) ← R1:R0 None - IN Rd, P In Port Rd ← PN o n e 1 OUT P, Rr Out Port P ← Rr None 1 PUSH Rr Push Register on Stack STACK ← Rr None 2 POP Rd Pop Register from Stack Rd ← STACK None 2 BIT AND BIT-TEST INSTRUCTIONS SBI P,b Set Bit in I/O Register I/O(P,b) ← 1N o n e 2 CBI P,b Clear Bit in I/O Register I/O(P,b) ← 0N o n e 2 LSL Rd Logical Shift Left Rd(n+1) ← Rd(n), Rd(0) ← 0 Z,C,N,V 1 LSR Rd Logical Shift Right Rd(n) ← Rd(n+1), Rd(7) ← 0 Z,C,N,V 1 ROL Rd Rotate Left Through Carry Rd(0) ←C,Rd(n+1)← Rd(n),C←Rd(7) Z,C,N,V 1 ROR Rd Rotate Right Through Carry Rd(7) ←C,Rd(n)← Rd(n+1),C←Rd(0) Z,C,N,V 1 ASR Rd Arithmetic Shift Right Rd(n) ← Rd(n+1), n=0..6 Z,C,N,V 1 BSET s Flag Set SREG(s) ← 1 SREG(s) 1 BCLR s Flag Clear SREG(s) ← 0 SREG(s) 1 BST Rr, b Bit Store from Register to T T ← Rr(b) T 1 BLD Rd, b Bit load from T to Register Rd(b) ← TN o n e 1 SEC Set Carry C ← 1C 1 CLC Clear Carry C ← 0 C 1 SEN Set Negative Flag N ← 1N 1 CLN Clear Negative Flag N ← 0 N 1 SEZ Set Zero Flag Z ← 1Z 1 CLZ Clear Ze ro Flag Z ← 0 Z 1 SEI Global Interrupt Enable I ← 1I 1 CLI Global Interrupt Disable I ← 0 I 1 SES Set Signed Test Flag S ← 1S 1 CLS Clear Signed Test Flag S ← 0 S 1 Instruction Set Summary (Continued)

2467R–AVR–06/08 ATmega128 Mnemonics Operands Description Operation Flags #Clocks SEV Set Twos Complement Overflow. V ← 1V 1 CLV Clear Twos Complement Overflow V ← 0 V 1 SET Set T in SREG T ← 1T 1 CLT Clear T in SREG T ← 0 T 1 SEH Set Half Carry Flag in SREG H ← 1H 1 CLH Clear Half Carry Flag in SREG H ← 0 H 1 MCU CONTROL INSTRUCTIONS NOP No Operation None 1 SLEEP Sleep (see specific descr. for Sleep function) None 1 WDR Watchdog Reset (see specific descr. for WDR/timer) None 1 BREAK Break For On-chip Debug Only None N/A Instruction Set Summary (Continued)

2467R–AVR–06/08 ATmega128

Ordering Information

Notes: 1. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green. 2. The device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. Speed (MHz) Power Supply Ordering Code (1) Package(2) Operation Range 8 2.7 - 5.5V ATmega128L-8AU ATmega128L-8MU 64A 64M1 Industrial (-40oC to 85oC) 16 4.5 - 5.5V ATmega128-16AU ATmega128-16MU 64A 64M1 Industrial (-40oC to 85oC) Package Type 64A 64-lead, 14 x 14 x 1.0 mm, Thin Profile Plastic Quad Flat Package (TQFP) 64M1 64-pad, 9 x 9 x 1.0 mm, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)

2467R–AVR–06/08 ATmega128 Packaging Information 64A

2325 Orchard Parkway

San Jose, CA 95131 TITLE DRAWING NO. R REV. 64A, 64-lead, 14 x 14 mm Body Size, 1.0 mm Body Thickness, 0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) B64A 10/5/2001 PIN 1 IDENTIFIER 0°~7° PIN 1 L C A1 A2 A D e E1 E B COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE Notes: 1.This package conforms to JEDEC reference MS-026, Variation AEB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10 mm maximum. A – – 1.20 A1 0.05 – 0.15 A2 0.95 1.00 1.05 D 15.75 16.00 16.25 D1 13.90 14.00 14.10 Note 2 E 15.75 16.00 16.25 E1 13.90 14.00 14.10 Note 2 B 0.30 – 0.45 C 0.09 – 0.20 L 0.45 – 0.75 e 0. 80 TYP

2467R–AVR–06/08 ATmega128 64M1 San Jose, CA 95131 TITLE DRAWING NO. R REV. 64M1, 64-pad, 9 x 9 x 1.0 mm Body, Lead Pitch 0.50 mm, G64M1 5/25/06 COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE A 0. 80 0.90 1.00 A1 – 0.02 0.05 b 0.1 8 0.25 0. 30 D D2 5.20 5.40 5.60 8.90 9.00 9.10 8.90 9.00 9.10 E E2 5.20 5.40 5.60 e 0.50 B SC L0 . 35 0.40 0.45 Note: 1. JEDEC Standard MO-220, (SAW Singulation) Fig. 1, VMMD. 2. Dimension and tolerance conform to ASMEY14.5M-1994. TOP VIEW SIDE VIEW BOTTOM VIEW D E Marked Pin# 1 ID SEATING PLANE C A C0.08 K 1.25 1.40 1.55 b e Pin #1 CornerL Pin #1 Tr iangle Pin #1 Chamfer (C 0.30) Option A Option B Pin #1 Notch (0.20 R) Option C K K 5.40 mm Exposed Pad, Micro Lead Frame Package (MLF)

2467R–AVR–06/08 ATmega128 Errata The revision letter in this section refers to the revision of the ATmega128 device. ATmega128 Rev. F to M  First Analog Comparator conversion may be delayed  Interrupts may be lost when writing the timer registers in the asynchronous timer  Stabilizing time needed when changing XDIV Register  Stabilizing time needed when changing OSCCAL Register  IDCODE masks data from TDI input  Reading EEPROM by using ST or STS to set EERE bit triggers unexpected interrupt request 1. First Analog Comparator conversion may be delayed If the device is powered by a slow rising V CC, the first Analog Comparator conversion will take longer than expected on some devices. Problem Fix/Workaround When the device has been powered or reset, disable then enable theAnalog Comparator before the first conversion. 2. Interrupts may be lost when writing the timer registers in the asynchronous timer If one of the timer registers which is synchroni zed to the asynchronous timer2 clock is writ- ten in the cycle before a overflow interrupt occurs, the interrupt may be lost. Problem Fix/Workaround Always check that the Timer2 Timer/Counter register, TCNT2, does not have the value 0xFF before writing the Timer2 Control Register, TCCR2, or Output Compare Register, OCR2 3. Stabilizing time needed when changing XDIV Register After increasing the source clock frequency more than 2% with settings in the XDIV register, the device may execute some of the subsequent instructions incorrectly. Problem Fix / Workaround The NOP instruction will always be executed correctly also right after a frequency change. Thus, the next 8 instructions after the change s hould be NOP instructions. To ensure this, follow this procedure: 1.Clear the I bit in the SREG Register. 2.Set the new pre-scaling factor in XDIV register. 3.Execute 8 NOP instructions 4.Set the I bit in SREG This will ensure that all subsequent instructions will execute correctly. Assembly Code Example: CLI ; clear global interrupt enable OUT XDIV, temp ; set new prescale value NOP ; no operation NOP ; no operation NOP ; no operation NOP ; no operation NOP ; no operation NOP ; no operation NOP ; no operation NOP ; no operation SEI ; set global interrupt enable

2467R–AVR–06/08 ATmega128 4. Stabilizing time needed when changing OSCCAL Register After increasing the source clock frequency more than 2% with settings in the OSCCAL reg- ister, the device may execute some of the subsequent instructions incorrectly. Problem Fix / Workaround The behavior follows errata number 3., and the same Fix / Workaround is applicable on this errata. 5. IDCODE masks data from TDI input The JTAG instruction IDCODE is not working correctly. Data to succeeding devices are replaced by all-ones during Update-DR. Problem Fix / Workaround – If ATmega128 is the only device in the scan chain, the problem is not visible. – Select the Device ID Register of the ATmega128 by issuing the IDCODE instruction or by entering the Test-Logic-Reset state of the TAP controller to read out the contents of its Device ID Register and possibly data from succeeding devices of the scan chain. Issue the BYPASS instructio n to the ATmega128 while reading the Device ID Registers of preceding devices of the boundary scan chain. – If the Device IDs of all devices in the boundary scan chain must be captured simultaneously, the ATmega128 must be the fist device in the chain. 6. Reading EEPROM by using ST or STS to set EERE bit triggers unexpected interrupt request. Reading EEPROM by using the ST or STS command to set th e EERE bit in the EECR reg- ister triggers an unexpected EEPROM interrupt request. Problem Fix / Workaround Always use OUT or SBI to set EERE in EECR.

2467R–AVR–06/08 ATmega128 Datasheet Revision History Please note that the referring page numbers in th is section are referred to this document. The referring revision in this section are referring to the document revision. Rev. 2467R-06/08 1. Removed “Not recommended from new designs“ from the front page. Rev. 2467Q-05/08 1. Updated “Preventing EEPROM Corruption” on page 25. Removed sentence “If the detection level of the internal BOD does not match the needed detection level, and external low VCC Reset Protection circuit can be used.“ 2. Updated Table 85 on page 197 in “Examples of Baud Rate Setting” on page 194. Remomved examples of frequencies above 16 MHz. 3. Updated Figure 114 on page 238. Inductor value corrected from 10 mH to 10 µH. 4. Updated description of “Version” on page 253. 5. ATmega128L removed from “DC Characteristics” on page 318. 6. Added “Speed Grades” on page 320. 7. Updated “Ordering Information” on page 368. Pb-Plated packages are no longer offered, and the ordering information for these packages are removed. There will no longer exist separ ate ordering codes for comm ercial operation range, only industrial operation range. 8. Updated “Errata” on page 371: Merged errata description for rev.F to rev.M in “ATmega128 Rev. F to M”. Rev. 2467P-08/07 1. Updated “Features” on page 1. 2. Added “Data Retention” on page 8. 3. Updated Table 60 on page 134 and Table 95 on page 235. 4. Updated “C Code Example(1)” on page 177. 5. Updated Figure 114 on page 238. 6. Updated “XTAL Divide Control Register – XDIV” on page 37. 7. Updated “Errata” on page 371. 8. Updated Table 34 on page 77. 9. Updated “Slave Mode” on page 167. Rev. 2467O-10/06 1. Added note to “Timer/Counter Oscillator” on page 44.

2467R–AVR–06/08 ATmega128 2. Updated “Fast PWM Mode” on page 125. 3. Updated Table 52 on page 105, Table 54 on page 105, Table 59 on page 134, Table 61 on page 135, Table 64 on page 157, and Table 66 on page 158. 4. Updated “Errata” on page 371. Rev. 2467N-03/06 1. Updated note for Figure 1 on page 2. 2. Updated “Alternate Functions of Port D” on page 78. 3. Updated “Alternate Functions of Port G” on page 85. 4. Updated “Phase Correct PWM Mode” on page 101. 5. Updated Table 59 on page 134, Table 60 on page 134. 6. Updated “Bit 2 – TOV3: Timer/Counter3, Overflow Flag” on page 142. 7. Updated “Serial Peripheral Interface – SPI” on page 163. 8. Updated Features in “Analog to Digital Converter” on page 230 9. Added note in “Input Channel and Gain Selections” on page 243. 10. Updated “Errata” on page 371. Rev. 2467M-11/04 1. Removed “analog ground”, replaced by “ground”. 2. Updated Table 11 on page 41 , Table 114 on page 285 , Table 128 on page 303 , and Table 132 on page 321. Updated Figure 114 on page 238. 3. Added note to “Port C (PC7..PC0)” on page 5. 4. Updated “Ordering Information” on page 368. Rev. 2467L-05/04 1. Removed “Preliminary” and “TBD” from the datasheet, replaced occurrences of ICx with ICPx. 2. Updated Table 8 on page 39 , Table 19 on page 51 , Table 22 on page 57 , Table 96 on page 242, Table 126 on page 299, Table 128 on page 303, Table 132 on page 321, and Table 134 on page 323. 3. Updated “External Memory Interface” on page 26. 4. Updated “Device Identification Register” on page 253. 5. Updated “Electrical Characteristics” on page 318. 6. Updated “ADC Characteristics” on page 325. 7. Updated “ATmega128 Typical Characteristics” on page 332.

2467R–AVR–06/08 ATmega128 8. Updated “Ordering Information” on page 368. Rev. 2467K-03/04 1. Updated “Errata” on page 371. Rev. 2467J-12/03 1. Updated “Calibrated Internal RC Oscillator” on page 42. Rev. 2467I-09/03 1. Updated note in “XTAL Divide Control Register – XDIV” on page 37. 2. Updated “JTAG Interface and On-chip Debug System” on page 49. 3. Updated values for V BOT (BODLEVEL = 1) in Table 19 on page 51. 4. Updated “Test Access Port – TAP” on page 246 regarding JTAGEN. 5. Updated description for the JTD bit on page 255. 6. Added a note regarding JTAGEN fuse to Table 118 on page 288. 7. Updated R PU values in “DC Characteristics” on page 318. 8. Added a proposal for solving problems regarding the JTAG instruction IDCODE in “Errata” on page 371. Rev. 2467H-02/03 1. Corrected the names of the two Prescaler bits in the SFIOR Register. 2. Added Chip Erase as a first step under “Programming the Flash” on page 315 and “Programming the EEPROM” on page 316. 3. Removed reference to the “Multipurpose Oscillator” application note and the “32 kHz Crystal Oscillator” application note, which do not exist. 4. Corrected OCn waveforms in Figure 52 on page 126. 5. Various minor Timer1 corrections. 6. Added information about PWM symmetry for Timer0 and Timer2. 7. Various minor TWI corrections. 8. Added reference to Table 124 on page 292 from both SPI Serial Programming and Self Programming to inform about the Flash Page size. 9. Added note under “Filling the Temporary Buffer (Page Loading)” on page 280 about writing to the EEPROM during an SPM Page load. 10. Removed ADHSM completely. 11. Added section “EEPROM Write During Power-down Sleep Mode” on page 25. 12. Updated drawings in “Packaging Information” on page 369. Rev. 2467G-09/02 1. Changed the Endurance on the Flash to 10,000 Write/Erase Cycles.

2467R–AVR–06/08 ATmega128 Rev. 2467F-09/02 1. Added 64-pad QFN/MLF Package and updated “Ordering Information” on page 368. 2. Added the section “Using all Locations of External Memory Smaller than 64 KB” on page 33. 3. Added the section “Default Clock Source” on page 38. 4. Renamed SPMCR to SPMCSR in entire document. 5. When using external clock there are some limitations regards to change of frequency. This is descried in “External Clock” on page 43 and Table 131, “External Clock Drive,” on page 320. 6. Added a sub section regarding OCD-system and power consumption in the section “Minimizing Power Consumption” on page 48. 7. Corrected typo (WGM-bit setting) for: “Fast PWM Mode” on page 99 (Timer/Counter0). “Phase Correct PWM Mode” on page 101 (Timer/Counter0). “Fast PWM Mode” on page 152 (Timer/Counter2). “Phase Correct PWM Mode” on page 153 (Timer/Counter2). 8. Corrected Table 81 on page 192 (USART). 9. Corrected Table 102 on page 259 (Boundary-Scan) 10. Updated Vil parameter in “DC Characteristics” on page 318. Rev. 2467E-04/02 1. Updated the Characterization Data in Section “ATmega128 Typical Characteristics” on page 332. 2. Updated the following tables: Table 19 on page 51, Table 20 on page 55, Table 68 on page 158, Table 102 on page 259, and Table 136 on page 328. 3. Updated Description of OSCCAL Calibration Byte. In the data sheet, it was not explained how to take advantage of the calibration bytes for 2, 4, and 8 MHz Oscillator selections. This is now added in the following sections: Improved description of “Oscillator Calibration Register – OSCCAL” on page 42 and “Cali- bration Byte” on page 289. Rev. 2467D-03/02 1. Added more information about “ATmega103 Compatibility Mode” on page 5. 2. Updated Table 2, “EEPROM Programming Time,” on page 23. 3. Updated typical Start-up Time in Table 7 on page 38, Table 9 and Table 10 on page 40, Table 12 on page 41, Table 14 on page 42, and Table 16 on page 43. 4. Updated Table 22 on page 57 with typical WDT Time-out.

2467R–AVR–06/08 ATmega128 5. Corrected description of ADSC bit in “ADC Control and Status Register A – ADCSRA” on page 244. 6. Improved description on how to do a polarity check of the ADC differential results in “ADC Conversion Result” on page 241. 7. Corrected JTAG version numbers in “JTAG Version Numbers” on page 256. 8. Improved description of addressing during SPM (usage of RAMPZ) on “Addressing the Flash During Self-Programming” on page 278 , “Performing Page Erase by SPM” on page 280, and “Performing a Page Write” on page 280. 9. Added not regarding OCDEN Fuse below Table 118 on page 288. 10. Updated Programming Figures: Figure 135 on page 290 and Figure 144 on page 301 are updated to also reflect that AVCC must be connected during Programming mode. Figure 139 on page 297 added to illustrate how to program the fuses. 11. Added a note regarding usage of the PROG_PAGELOAD and PROG_PAGEREAD instructions on page 307. 12. Added Calibrated RC Oscillator characterization curves in section “ATmega128 Typi- cal Characteristics” on page 332. 13. Updated “Two-wire Serial Interface” section. More details regarding use of the TWI Powe r-down operation and using the TWI as master with low TWBRR values are added into the data sheet. Added the note at the end of the “Bit Rate Generator Unit” on page 204. Added the description at the end of “Address Match Unit” on page 205. 14. Added a note regarding usage of Timer/Counter0 combined with the clock. See “XTAL Divide Control Register – XDIV” on page 37. Rev. 2467C-02/02 1. Corrected Description of Alternate Functions of Port G Corrected description of TOSC1 and TOSC2 in “Alternate Functions of Port G” on page 85. 2. Added JTAG Version Numbers for rev. F and rev. G Updated Table 100 on page 256.

3 Added Some Preliminary Test Li mits and Characterization Data

Removed some of the TBD's in the following tables and pages: Table 19 on page 51, Table 20 on page 55, “DC Characteristics” on page 318, Table 131 on page 320, Table 134 on page 323, and Table 136 on page 328. 4. Corrected “Ordering Information” on page 368. 5. Added some Characterization Data in Section “ATmega128 Typical Characteristics” on page 332. 6. Removed Alternative Algortihm for Leaving JTAG Programming Mode. See “Leaving Programming Mode” on page 315.

2467R–AVR–06/08 ATmega128 7. Added Description on How to Access the Extended Fuse Byte Through JTAG Pro- gramming Mode. See “Programming the Fuses” on page 317 and “Reading the Fuses and Lock Bits” on page 317.

2467R–AVR–06/08 ATmega128 Power-down Mode 46 Power-save Mode 46 Standby Mode 47 Extended Standby Mode 47 Minimizing Power Consumption 48 System Control and Reset 50 Internal Voltage Reference 54 Watchdog Timer 55 Timed Sequences for Changing the Configuration of the Watchdog Timer 58 Interrupts 60 Interrupt Vectors in ATmega128 60 I/O Ports 66 Introduction 66 Ports as General Digital I/O 67 Alternate Port Functions 71 Register Description for I/O Ports 87 External Interrupts 90 8-bit Timer/Counter0 with PWM and Asynchronous Operation 93 Overview 93 Timer/Counter Clock Sources 94 Counter Unit 94 Output Compare Unit 95 Compare Match Output Unit 97 Modes of Operation 98 Timer/Counter Timing Diagrams 102 8-bit Timer/Counter Register Description 104 Asynchronous Operation of the Timer/Counter 107 Timer/Counter Prescaler 110 16-bit Timer/Counter (Timer/Counter1 and Timer/Counter3) 112 Overview 112 Accessing 16-bit Registers 115 Timer/Counter Clock Sources 118 Counter Unit 118 Input Capture Unit 119 Output Compare Units 121 Compare Match Output Unit 123 Modes of Operation 124 Timer/Counter Timing Diagrams 131 16-bit Timer/Counter Register Description 133

2467R–AVR–06/08 ATmega128 Timer/Counter3, Timer/Counter2, and Timer/Counter1 Prescalers 143 8-bit Timer/Counter2 with PWM 145 Overview 145 Timer/Counter Clock Sources 146 Counter Unit 146 Output Compare Unit 147 Compare Match Output Unit 148 Modes of Operation 149 Timer/Counter Timing Diagrams 155 8-bit Timer/Counter Register Description 157 Output Compare Modulator (OCM1C2) 161 Overview 161 Description 161 Serial Peripheral Interface – SPI 163 SS Pin Functionality 167 Data Modes 170 USART 171 Overview 171 Clock Generation 173 Frame Formats 176 USART Initialization 177 Data Transmission – The USART Transmitter 178 Data Reception – The USART Receiver 180 Multi-processor Communication Mode 187 USART Register Description 189 Examples of Baud Rate Setting 194 Two-wire Serial Interface 198 Features 198 Two-wire Serial Interface Bus Definition 198 Data Transfer and Frame Format 199 Multi-master Bus Systems, Arbitration and Synchronization 201 Overview of the TWI Module 204 TWI Register Description 206 Using the TWI 208 Transmission Modes 213 Multi-master Systems and Arbitration 225 Analog Comparator 227 Analog Comparator Multiplexed Input 228

2467R–AVR–06/08 ATmega128 Analog to Digital Converter 230 Features 230 Operation 232 Starting a Conversion 232 Prescaling and Conversion Timing 233 Changing Channel or Reference Selection 235 ADC Noise Canceler 236 ADC Conversion Result 241 JTAG Interface and On-chip Debug System 246 Features 246 Overview 246 Test Access Port – TAP 246 TAP Controller 248 Using the Boundary-scan Chain 249 Using the On-chip Debug System 249 On-chip Debug Specific JTAG Instructions 250 On-chip Debug Related Register in I/O Memory 251 Using the JTAG Programming Capabilities 251 Bibliography 251 IEEE 1149.1 (JTAG) Boundary-scan 252 Features 252 System Overview 252 Data Registers 252 Boundary-scan Specific JTAG Instructions 254 Boundary-scan Related Register in I/O Memory 255 Boundary-scan Chain 255 ATmega128 Boundary-scan Order 266 Boundary-scan Description Language Files 272 Boot Loader Support – Read-While-Write Self-Programming 273 Boot Loader Features 273 Application and Boot Loader Flash Sections 273 Read-While-Write and No Read-While-Write Flash Sections 273 Boot Loader Lock Bits 275 Entering the Boot Loader Program 276 Addressing the Flash During Self-Programming 278 Self-Programming the Flash 279 Memory Programming 286 Program and Data Memory Lock Bits 286 Fuse Bits 287 Signature Bytes 289 Calibration Byte 289 Parallel Programming Parameters, Pin Mapping, and Commands 290 Parallel Programming 292

v 2467R–AVR–06/08 ATmega128 Serial Downloading 300 SPI Serial Programming Pin Mapping 300 Programming Via the JTAG Interface 305 Electrical Characteristics 318 Absolute Maximum Ratings* 318 DC Characteristics 318 Speed Grades 320 External Clock Drive Waveforms 320 External Clock Drive 320 Two-wire Serial Interface Characteristics 322 SPI Timing Characteristics 323 ADC Characteristics 325 External Data Memory Timing 328 Typical Characteristics 333 Register Summary 362 Instruction Set Summary 365 Ordering Information 368 368 Packaging Information 369 64A 369 64M1 370 Errata 371 ATmega128 Rev. F to Q 371 Datasheet Revision History 373 Rev. 2467Q-03/08 373 Rev. 2467P-08/07 373 Rev. 2467O-10/06 374 Rev. 2467N-03/06 374 Rev. 2467M-11/04 374 Rev. 2467L-05/04 374 Rev. 2467K-03/04 375 Rev. 2467J-12/03 375 Rev. 2467I-09/03 375 Rev. 2467H-02/03 375 Rev. 2467G-09/02 376 Rev. 2467F-09/02 376 Rev. 2467E-04/02 376 Rev. 2467D-03/02 376

2467R–AVR–06/08 ATmega128 Rev. 2467C-02/02 377 Table of Contents i

2467R–AVR–06/08 ATmega128

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