ATMEGA103

ATMEGA103_07 ATMEL

Document overview

• Manufacturer or author: Provided By digicamel.com
• PDF pages: 141

Technical content

Features

• Utilizes the AVR® RISC Architecture  AVR – High-performance and Low-power RISC Architecture – 121 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers + Peripheral Control Registers – Up to 6 MIPS Throughput at 6 MHz  Data and Nonvolatile Program Memory – 128K Bytes of In-System Programmable Flash Endurance: 1,000 Write/Erase Cycles – 4K Bytes Internal SRAM – 4K Bytes of In-System Programmable EEPROM Endurance: 100,000 Write/Erase Cycles – Programming Lock for Flash Program and EEPROM Data Security – SPI Interface for In -System Programming  Peripheral Features – On-chip Analog Comparator – Programmable Watchdog Timer with On-chip Oscillator – Programmable Serial UART – Master/Slave SPI Serial Interface – Real-time Counter (RTC) with Separate Oscillator – Two 8-bit Timer/Counters with Separate Prescaler and PWM – Expanded 16-bit Timer/Counter System with Separate Prescaler, Compare, Capture Modes and Dual 8-, 9-, or 10-bit PWM – Programmable Watchdog Timer with On-chip Oscillator – 8-channel, 10-bit ADC  Special Microcontroller Features – Low-power Idle, Power-save and Power-down Modes – Software Selectable Clock Frequency – External and Internal Interrupt Sources  Specifications – Low-power, High-speed CMOS Process Technology – Fully Static Operation  Power Consumption at 4 MHz, 3V, 25°C – Active: 5.5 mA – Idle Mode: 1.6 mA – Power-down Mode: < 1 µA  I/O and Packages – 32 Programmable I/O Lines, 8 Output Lines, 8 Input Lines – 64-lead TQFP  Operating Voltages – 2.7 - 3.6V for ATmega103L – 4.0 - 5.5V for ATmega103  Speed Grades – 0 - 4 MHz for ATmega103L – 0 - 6 MHz for ATmega103 8-bit Microcontroller with 128K Bytes In-System Programmable Flash ATmega103 ATmega103L Note: Not recommended in new designs. Rev. 0945I–AVR–02/07

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0945I–AVR–02/07 Pin Configuration TQFP /K50/K43/K30 /K28/K41/K38/K29 /K56/K43/K43 /K47/K4E/K44 /K28/K41/K44/K43/K30/K29 /K50/K46/K30 /K28/K41/K44/K43/K37/K29 /K50/K46/K37 /K28/K41/K44/K43/K31/K29 /K50/K46/K31 /K28/K41/K44/K43/K32/K29 /K50/K46/K32 /K28/K41/K44/K43/K33/K29 /K50/K46/K33 /K28/K41/K44/K43/K34/K29 /K50/K46/K34 /K28/K41/K44/K43/K35/K29 /K50/K46/K35 /K28/K41/K44/K43/K36/K29 /K50/K46/K36 /K41/K52/K45/K46 /K41/K47/K4E/K44 /K41/K56/K43/K43 /K33/K32 /K35/K32 /K35/K33 /K33/K31 /K35/K34 /K32/K39 /K35/K35 /K33/K30 /K32/K38 /K35/K36 /K32/K37 /K35/K37 /K32/K36 /K35/K38 /K32/K35 /K35/K39 /K32/K34 /K36/K30 /K36/K31 /K32/K33 /K36/K31 /K36/K32 /K32/K32 /K36/K32 /K36/K33 /K32/K30 /K32/K31 /K36/K33 /K36/K34/K36/K34 /K31 /K35/K31 /K32 /K35/K30 /K33 /K34/K39 /K34 /K34/K38 /K35 /K34/K37 /K36 /K34/K36 /K37 /K34/K35 /K38 /K34/K34 /K39 /K34/K33 /K31/K30 /K34/K32 /K31/K31 /K34/K31 /K31/K32 /K34/K30 /K31/K33 /K33/K39 /K31/K34 /K33/K38 /K31/K35 /K33/K37 /K31/K36 /K33/K36 /K31/K37 /K33/K35 /K31/K38 /K33/K34 /K31/K39 /K33/K33 /K28/K50/K44/K49/K2F/K52/K58/K44/K29 /K50/K45/K30 /K28/K50/K44/K4F/K2F/K54/K58/K44/K29 /K50/K45/K31 /K50/K45/K4E /K28/K41/K43/K2B/K29 /K50/K45/K32 /K28/K41/K43/K2D/K29 /K50/K45/K33 /K28/K49/K4E/K54/K34/K29 /K50/K45/K34 /K28/K49/K4E/K54/K35/K29 /K50/K45/K35 /K28/K49/K4E/K54/K36/K29 /K50/K45/K36 /K28/K49/K4E/K54/K37/K29 /K50/K45/K37 /K28/K53/K53/K29 /K50/K42/K30 /K28/K53/K43/K4B/K29 /K50/K42/K31 /K28/K4D/K4F/K53/K49/K29 /K50/K42/K32 /K28/K4D/K49/K53/K4F/K29 /K50/K42/K33 /K28/K4F/K43/K30/K2F/K50/K57/K4D/K30/K29 /K50/K42/K34 /K50/K42/K37 /K28/K4F/K43/K32/K2F/K50/K57/K4D/K32/K29 /K54/K4F/K53/K43/K32 /K28/K4F/K43/K31/K42/K2F/K50/K57/K4D/K31/K42/K29 /K50/K42/K36 /K54/K4F/K53/K43/K31 /K28/K4F/K43/K31/K41/K2F/K50/K57/K4D/K31/K41/K29 /K50/K42/K35 /K50/K43/K31 /K28/K41/K39/K29 /K57/K52 /K50/K44/K37 /K28/K54/K32/K29 /K50/K43/K32 /K28/K41/K31/K30/K29 /K50/K43/K33 /K28/K41/K31/K31/K29 /K50/K43/K34 /K28/K41/K31/K32/K29 /K50/K43/K35 /K28/K41/K31/K33/K29 /K50/K43/K36 /K28/K41/K31/K34/K29 /K50/K43/K37 /K28/K41/K31/K35/K29 /K50/K41/K37 /K28/K41/K44/K37/K29 /K41/K4C/K45 /K50/K41/K36 /K28/K41/K44/K36/K29 /K50/K41/K35 /K28/K41/K44/K35/K29 /K50/K41/K34 /K28/K41/K44/K34/K29 /K50/K41/K33 /K28/K41/K44/K33/K29 /K28/K41/K44/K30/K29 /K50/K41/K30 /K28/K41/K44/K31/K29 /K50/K41/K31 /K28/K41/K44/K32/K29 /K50/K41/K32 /K52/K44 /K50/K44/K36 /K28/K54/K31/K29 /K50/K44/K35 /K50/K44/K34 /K28/K49/K43/K31/K29 /K50/K44/K33 /K28/K49/K4E/K54/K33/K29 /K50/K44/K32 /K28/K49/K4E/K54/K32/K29 /K50/K44/K31 /K28/K49/K4E/K54/K31/K29 /K50/K44/K30 /K28/K49/K4E/K54/K30/K29 /K58/K54/K41/K4C/K31 /K58/K54/K41/K4C/K32 /K52/K45/K53/K45/K54 /K47/K4E/K44 /K56/K43/K43 /K49/K4E/K44/K45/K58 /K43/K4F/K52/K4E/K45/K52

ATmega103(L) 0945I–AVR–02/07 Description The ATmega103(L) is a low-power, CMOS, 8-bit microcontroller based on the AVR RISC architecture. By executing powerful in structions in a single clock cycle, the ATmega103(L) achieves throughputs approaching 1 MIPS per MHz, allowing the sys- tem designer to optimize power consumption versus processing speed. The AVR core is based on an enhanced RISC architecture that combines a rich instruc- tion set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU ), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architec- ture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The ATmega103(L) provides the following features: 128K bytes of In-System Program- mable Flash, 4K bytes EEPROM, 4K bytes SRAM, 32 general purpose I/O lines, 8 input lines, 8 output lines, 32 general purpose working registers, Real Time Counter (RTC), 4 flexible Timer/Counters with compare modes and PWM, UART, programmable Watch- dog Timer with internal Oscillator, an SPI serial port and 3 software-selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next Interrupt or Hardware Reset. In Power- save mode, the Timer Oscillator continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping. The device is manufactured using Atmel’s high-density nonvolatile memory technology. The On-chip ISP Flash allows the Program memory to be reprogrammed In-System through a serial interface or by a conventional nonvolatile memory programmer. By combining an 8-bit RISC CPU with a large array of ISP Flash on a monolithic chip, the Atmel ATmega103(L) is a powerful microcontro ller that provides a highly flexible and cost-effective solution to many embedded control applications. The ATmega103(L) AVR is supported with a full suite of program and system develop- ment tools including: C compilers, macro assemblers, program debugger/simulators, In- Circuit Emulators and evaluation kits.

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0945I–AVR–02/07 Block Diagram Figure 1. The ATmega103(L) Block Diagram PROGRAM COUNTER INTERNAL OSCILLATOR WATCHDOG TIMER STACK POINTER PROGRAM FLASH MCU CONTROL REGISTER SRAM GENERAL PURPOSE REGISTERS INSTRUCTION REGISTER TIMER/ COUNTERS INSTRUCTION DECODER DATA DIR. REG. PORTB DATA DIR. REG. PORTE DATA DIR. REG. PORTA DATA DIR. REG. PORTD DATA REGISTER PORTB DATA REGISTER PORTE DATA REGISTER PORTA DATA REGISTER PORTC DATA REGISTER PORTD PROGRAMMING LOGIC TIMING AND CONTROL OSCILLATOR OSCILLATOR INTERRUPT UNIT EEPROM SPI UART STATUS REGISTER Z Y X ALU PORTB DRIVER/BUFFERSPORTE DRIVER/BUFFERS PORTA DRIVER/BUFFERSPORTF BUFFERS ANALOG MUX ADC PORTD DRIVER/BUFFERS PORTC DRIVERS PB0 - PB7PE0 - PE7 PA0 - PA7PF0 - PF7 RESET VCC VCC AGND GND GND AREF TOSC2 TOSC1 XTAL1 XTAL1 CONTROL LINES + - ANALOG COMP ARA TOR PD0 - PD7 PC0 - PC7 PEN ALE WR RD 8-BIT DATA BUS AVCC

ATmega103(L) 0945I–AVR–02/07 Pin Descriptions VCC Supply voltage. GND Ground. Port A (PA7..PA0) Port A is an 8-bit bi-directional I/O port. Port pins can provide internal pull-up resistors (selected for each bit). The Port A output buffers can sink 20 mA and can drive LED dis- plays directly. When pins PA0 to PA7 are us ed as inputs and are externally pulled low, they will source current if the internal pull-up resistors are activated. Port A serves as Multiplexed Address/Data bus when using external SRAM. The Port A pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B (PB7..PB0) Port B is an 8-bit bi-directional I/O port with internal pull-up resistors. The Port B output buffers can sink 20 mA. As in puts, Port B pins that are ex ternally pulled low, will source current if the pull-up resistors are activated. Port B also serves the functions of various special features. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port C (PC7..PC0) Port C is an 8-bit output port. The Port C output buffers can sink 20 mA. Port C also serves as Address output when using external SRAM. Since Port C is an output only port, the Port C pins are not tri-stated when a reset condi- tion becomes active. Port D (PD7..PD0) Port D is an 8-bit bi-directional I/O port with internal pull-up resistors. The Port D output buffers can sink 20 mA . As inputs, Port D pins that ar e externally pulled low will source current if the pull-up resistors are activated. Port D also serves the functions of various special features. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port E (PE7..PE0) Port E is an 8-bit bi-directional I/O port with internal pull-up resistors. The Port E output buffers can sink 20 mA. As i nputs, Port E pins that are ex ternally pulled low will source current if the pull-up resistors are activated. Port E also serves the functions of various special features. The Port E pins are tri-stated when a reset condition becomes active, even if the clock is not running Port F (PF7..PF0) Port F is an 8-bit input port. Port F also serves as the analog inputs for the ADC. RESET Reset input. An external reset is generated by a low level on the RESET pin. Reset pulses longer than 50 ns will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset. XTAL1 Input to the inverting Oscillator amplifier and input to the internal clock operating circuit. XTAL2 Output from the inverting Oscillator amplifier.

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TOSC1 Input to the inverting Timer/Counter Oscillator amplifier. TOSC2 Output from the inverting Timer/Counter Oscillator amplifier. access cycle, and the AD0 - 7 pins are used for data during the second access cycle. age in the range AGND to AVCC must be applied to this pin. ground plane. Otherwise, connect to GND. has no function during normal operation. crystal or a ceramic resonator may be used. Figure 2. Oscillator Connections connected as indicated in the figure.

while XTAL1 is driven as shown in Figure 3. Figure 3. External Clock Drive Configuration

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Figure 4. The ATmega103(L) AVR RISC Architecture address contains a single 16-bit instruction. ing modes supported in the AVR architecture.

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The registers R26..R31 have some added f unctions to their general purpose usage. Figure 6. X-, Y-, and Z-registers categories: arithmetic, logical and bit functions. Note: When using 64K of external SRAM, 60K will be available. Table 1. Memory Configurations

Figure 7. Memory Configurations

32 Registers

64 I/O Registers

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0945I–AVR–02/07 The 4096 first Data memory locations address both the Register File, the I/O memory and the internal Data SRAM. The first 96 locations address the Register File and I/O memory, and the next 4000 locations address the internal Data SRAM. An optional external Data SRAM can be used with the ATmega103(L). This SRAM will occupy an area in the remaining address locations in the 64K address space. This area starts at the address following the internal SRAM. If a 64K external SRAM is used, 4K of the external memory is lost as the addresses are occupied by internal memory. When the addresses accessing the SRAM me mory space exceeds the internal Data memory locations, the external Data SRAM is accessed using the same instructions as for the internal Data memory access. When the internal Data memories are accessed, the read and write strobe pins (RD and WR) are inactive during the whole access cycle. External SRAM operation is enabled by setting the SRE bit in the MCUCR Register. Accessing external SRAM takes one additional clock cycle per byte compared to access of the internal SRAM. This means that the commands LD, ST, LDS, STS, PUSH and POP take one additional clock cycle. If the Stack is placed in external SRAM, interrupts, subroutine calls and returns take two clock cycles extra because the 2-byte Program Counter is pushed and popped. When external SRAM interface is used with wait state, two additional clock cycles are used per byte. This has the following effect: Data transfer instructions take two extra clock cycles, w hereas interrupt, subroutine calls and returns will need four clock cycles more than specified in the “Instruction Set Summary” on page 135. The five different addressing modes for the Data memory cover: Direct, Indirect with Displacement, Indirect, Indirect with Pre-decrement and Indirect with Post-increment. In the Register File, registers R26 to R31 feature the indirect addressing pointer registers. The Indirect with Displacement mode features 63 address locations reached from the base address given by the Y- or Z-register. When using register indirect addressing modes with automatic Pre-decrement and Post- increment, the address registers X, Y, and Z are decremented and incremented. The entire Data address space including the 32 general purpose working registers and the 64 I/O Registers are all accessible through all these addressing modes. See the next section for a detailed description of the different addressing modes. Program and Data Addressing Modes The ATmega103(L) AVR RISC microcontroller supports powerful and efficient address- ing modes for access to the Program memory (Flash) and Data memory (SRAM, Register File and I/O memory). This sect ion describes the different addressing modes supported by the AVR architecture. In the figures, OP means the operation code part of the instruction word. To simplify, not all fi gures show the exact location of the address- ing bits.

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the destination or source register. Figure 12. Data Indirect with Displacement tained in six bits of the instruction word. Operand address is the contents of the X-, Y,- or the Z-register.

16 LSBs

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high memory page (RAMPZ0 = 0: Low Page, RAMPZ0 = 1: High Page). Figure 17. Direct Program Memory Addressing Program execution continues at the address immediate in the instruction words. Figure 18. Indirect Program Memory Addressing loaded with the contents of the Z-register). Figure 19. Relative Program Memory Addressing

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Figure 22. On-chip Data SRAM Access Cycles I/O Memory The I/O space definition of the ATmega103(L) is shown in Table 2. Table 2. ATmega103(L) I/O Space

Table 2. ATmega103(L) I/O Space (Continued)

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Note: Reserved and unused locations are not shown in the table. with the SRAM address in parentheses. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written.

ATmega103(L) 0945I–AVR–02/07 ied into T by the BST instruction and a bit in T can be copied into a bit in a register in the register file by the BLD instruction.  Bit 5 – H: Half-carry Flag The Half-carry Flag H indicates a Half-carry in some arithmetic operations. See the instruction set description on page 135 for detailed information.  Bit 4 – S: Sign Bit, S = N ⊕ V The S-bit is always an exclusive or between the Negative Flag N and the Two’s Comple- ment Overflow Flag V. See the instruction set description on page 135 for detailed information.  Bit 3 – V: Two’s Complement Overflow Flag The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See the instruction set description on page 135 for detailed information.  Bit 2 – N: Negative Flag The Negative Flag N indicates a negative result from an arithmetical or logical operation. See the Instruction set description on page 135 for detailed information.  Bit 1 – Z: Zero Flag The Zero Flag Z indicates a zero result from an arithmetical or logical operation. See the instruction set description on page 135 for detailed information.  Bit 0 – C: Carry Flag The Carry Flag C indicates a carry in an arithmetical or logical operation. See the instruction set description on page 135 for detailed information. Note that the Status Register is not automatically stored when entering an interrupt rou- tine or restored when returning from an interrupt routine. This must be handled by software. Stack Pointer – SP The general AVR 16-bit Stack Pointer is effectively built up of two 8-bit registers in the I/O space locations $3E ($5E) and $3D ($5D). As the ATmega103(L) supports up to 64K bytes memory, all 16 bits are used. The Stack Pointer points to the Data SRAM Stack area where the Subroutine and Inter- rupt Stacks are located. This Stack space in the Data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. The Stack Pointer must be set to point above $60. The Stack Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction and it is decremented by 2 when an address is pushed onto the Stack with subroutine calls and interrupts. The Stack Pointer is incremented by 1 when data is popped from the Stack with the POP B i t 1 51 41 31 21 11 0 9 8 $3E ($5E) SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SPH $3D ($5D) SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL 76543210 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 00000000

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0945I–AVR–02/07 instruction and it is incremented by 2 when an address is popped from the Stack with return from subroutine RET or return from interrupt RETI. RAM Page Z Select Register – RAMPZ The RAMPZ Register is normally used to select which 64K RAM page is accessed by the Z pointer. As the ATmega103(L) does not support more than 64K of SRAM memory, this register is used only to select which page in the Program memory is accessed when the ELPM instruction is used. The differen t settings of the RAMPZ0 bit have the follow- ing effects: Note that LPM is not affected by the RAMPZ setting. MCU Control Register – MCUCR The MCU Control Register contains control bits for general MCU functions.  Bit 7 – SRE: External SRAM Enable When the SRE bit is set (one), the external Data SRAM is enabled, and the pin functions AD0 - 7 (Port A), and A8 - 15 (Port C) are activated as the alternate pin functions. Then the SRE bit overrides any pin direction settings in the respective Data Direction Regis- ters. When the SRE bit is cleared (zero), t he external Data SRAM is disabled and the normal pin and data direction settings are used.  Bit 6 – SRW: External SRAM Wait State When the SRW bit is set (one), a one-cycle wait state is inserted in the external Data SRAM access cycle. When the SRW bit is cleared (zero), the external Data SRAM access is executed with a three-cycle scheme. See Figure 51 on page 85 and Figure 52 on page 85.  Bit 5 – SE: Sleep Enable The SE bit must be set (one) to make the MCU enter the sleep mode when the SLEEP instruction is executed. To avoid the MCU entering the sleep mode unless it is the pro- grammer’s purpose, it is recommended to set the Sleep Enable (SE) bit just before the execution of the SLEEP instruction. B i t 7654321 0 R e a d / W r i t e RRRRRRR R / W Initial Value 0 0 0 0 0 0 0 0 RAMPZ0 = 0: Program memory address $0000 - $7FFF (lower 64K bytes) is accessed by ELPM RAMPZ0 = 1: Program memory address $8000 - $FFFF (higher 64K bytes) is accessed by ELPM B i t 7654321 0 $35 ($55) SRE SRW SE SM1 SM0 – – – MCUCR Read/Write R/W R/W R/W R/W R/W R R R Initial Value 0 0 0 0 0 0 0 0

This bit selects between the three available sleep modes as shown in Table 3. These bits are reserved bits in the ATmega103(L) and always read as zero. the requirement for processing power is low. cleared run-time to vary the clock frequency as suitable to the application. speed of all peripherals is reduced when a division factor is used. with the I-bit in the Status Register in order to enable the interrupt. Table 3. Sleep Mode Select

01 R e s e r v e d

10 P o w e r - d o w n

11 P o w e r - s a v e

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Table 4. Reset and Interrupt Vectors

ATmega103(L) 0945I–AVR–02/07 $0012 jmp TIM2_COMP ; Timer2 Compare Handler $0014 jmp TIM2_OVF ; Timer2 Overflow Handler $0016 jmp TIM1_CAPT ; Timer1 Capture Handler $0018 jmp TIM1_COMPA ; Timer1 Compare A Handler $001A jmp TIM1_COMPB ; Timer1 Compare B Handler $001C jmp TIM1_OVF ; Timer1 Overflow Handler $001E jmp TIM0_COMP ; Timer0 Compare Handler $0020 jmp TIM0_OVF ; Timer0 Overflow Handler $0022 jmp SPI_STC ; SPI Transfer Complete Handler $0024 jmp UART_RXC ; UART RX Complete Handler $0026 jmp UART_DRE ; UDR Empty Handler $0028 jmp UART_TXC ; UART TX Complete Handler $002A jmp ADC ; ADC Conversion Complete Handler $002C jmp EE_RDY ; EEPROM Ready Handler $002E jmp ANA_COMP ; Analog Comparator Handler $0030 MAIN: ldi r16, high(RAMEND); Main program start $0031 out SPH,r16 $0032 ldi r16, low(RAMEND) $0033 out SPL,r16 $0034 <instr> xxx Reset Sources The ATmega103(L) has three sources of reset:  Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (VPOT).  External Reset. The MCU is reset when a low level is present on the RESET pin for more than 50 ns.  Watchdog Reset. The MCU is reset when the Watchdog Timer period expires and the Watchdog is enabled. During reset, all I/O Registers except the MCU Status Register are then set to their initial values and the program starts execution from address $0000. The instruction placed in address $0000 must be a JMP (absolute jump) instruction to the reset handling routine. If the program never enables an interrupt source, the Interrupt Vectors are not used and regular program code can be placed at these locations. The circuit diagram in Figure 23 shows the reset logic. Table 5 defines the timing and electrical parameters of the reset circuitry.

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Figure 23. Reset Logic

table indicates that the fuse is programmed. “Typical Characteristics” on page 123. ming specification starting on page 104. Table 5. Reset Characteristics (VCC = 5.0V) Table 6. Number of Watchdog Oscillator Cycles

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Figure 24. MCU Start-up, RESET Tied to VCC. Figure 25. MCU Start-up, RESET Controlled Externally Figure 26. External Reset during Operation

TOUT. Refer to page 55 for details on operation of the Watchdog. Figure 27. Watchdog Reset during Operation These bits are reserved bits in the ATmega103(L) and always read as zero. Watchdog reset will leave this bit unchanged.

1 XTAL Cycle

Table 7. PORF and EXTRF Values after Reset

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lowing truth table, Table 8. (External Interrupt Mask Register) and TIMSK (Timer/Counter Interrupt Mask Register). In addition, other enable and mask bits can be found in the peripheral control registers. rupts are disabled. The user software can set (one) the I-bit to enable nested interrupts. The I-bit is set (one) when a Return from Interrupt instruction (RETI) is executed. flag bit position(s) to be cleared. flag is cleared by software. Interrupt Enable bit is set (one), and will be executed by order of priority. as long as the interrupt condition is active. way of generating a software interrupt. Table 8. Reset Source Identification

request as long as the pin is held low. always cleared when INTF7 - INFT4 are configured as level interrupts. These bits are reserved bits in the ATmega103(L) and always read as zero. on the external pins that activate the interrupts are defined in Table 9. selected, pulses that last longer than one CPU clock period will generate an interrupt. Table 9. Interrupt Sense Control 0 0 The low level of INTX generates an interrupt request. 1 0 The falling edge of INTX gen erates an interrupt request. 1 1 The rising edge of INTX generates an interrupt request.

32 ATmega103(L)

0945I–AVR–02/07 cuting instruction to generate an interrupt. If enabled, a level-triggered interrupt will generate an interrupt request as long as the pin is held low.

ATmega103(L) 0945I–AVR–02/07 Timer/Counter Interrupt Mask Register – TIMSK  Bit 7 – OCIE2: Timer/Counter2 Output Compare Interrupt Enable When the OCIE2 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter2 Compare Match interrupt is enabled. The corresponding interrupt (at vector $0012) is executed if a compare matc h in Timer/Counter2 occurs, i.e., when the OCF2 bit is set in the Timer/Counter Interrupt Flag Register (TIFR).  Bit 6 – TOIE2: Timer/Counter2 Overflow Interrupt Enable When the TOIE2 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter2 Overflow interrupt is enabled. The corresponding interrupt (at vector $0014) is executed if an overflow in Timer/Counter2 occurs, i.e., when the TOV2 bit is set in the Timer/Counter Interrupt Flag Register (TIFR).  Bit 5 – TICIE1: Timer/Counter1 Input Capture Interrupt Enable When the TICIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Input Capture Event interrupt is enabled. The corresponding interrupt (at vector $0016) is executed if a capture-triggering event occurs on pin 29, PD4(IC1), i.e., when the ICF1 bit is set in the Timer/Counter Interrupt Flag Register.  Bit 4 – OCE1A: Timer/Counter1 Output Compare A Match Interrupt Enable When the OCIE1A bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Compare A Match interrupt is enabled. The corresponding interrupt (at vector $0018) is executed if a Compare A Match in Timer/Counter1 occurs, i.e., when the OCF1A bit is set in the Timer/Counter Interrupt Flag Register.  Bit 3 – OCIE1B: Timer/Counter1 Output Compare B Match Interrupt Enable When the OCIE1B bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Compare B Match interrupt is enabled. The corresponding interrupt (at vector $001A) is executed if a Compare B Match in Timer/Counter1 occurs, i.e., when the OCF1B bit is set in the Timer/Counter Interrupt Flag Register.  Bit 2 – TOIE1: Timer/Counter1 Overflow Interrupt Enable When the TOIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Overflow interrupt is enabled. The corresponding interrupt (at vector $001C) is executed if an overflow in Timer/Counter1 occurs, i.e., when the TOV1 bit is set in the Timer/Counter Interrupt Flag Register.  Bit 1 – OCIE0: Timer/Counter0 Output Compare Interrupt Enable When the OCIE0 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter0 Compare Match interrupt is enabled. The corresponding interrupt (at vector $001E) is executed if a compare match in Timer/Counter0 occurs, i.e., when the OCF0 bit is set in the Timer/Counter Interrupt Flag Register. Bit 7 6 5 4 3 2 1 0 $37 ($57) OCIE2 TOIE2 TICIE1 OCIE1A OCIE1B TOIE1 OCIE0 TOIE0 TIMSK Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0

34 ATmega103(L)

0945I–AVR–02/07  Bit 0 – TOIE0: Timer/Counter0 Overflow Interrupt Enable When the TOIE0 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt (at vector $0020) is executed if an overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is set in the Timer/Counter Interrupt Flag Register.

ATmega103(L) 0945I–AVR–02/07 Timer/Counter Interrupt Flag Register – TIFR  Bit 7 – OCF2: Output Compare Flag 2: The OCF2 bit is set (one) when compare match occurs between Timer/Counter2 and the data in OCR2 – Output Compare Register 2. OCF2 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCF2 is cleared by writing a logical “1” to the flag. When the I-bit in SREG, and OCIE2 (Timer/Counter2 Compare Interrupt Enable) and the OCF2 are set (one), the Timer/Counter2 Output Compare interrupt is executed.  Bit 6 – TOV2: Timer/Counter2 Overflow Flag The TOV2 bit is set (one) when an overflow occurs in Timer/Counter2. TOV2 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV2 is cleared by writing a logical “1” to the flag. When the I-bit in SREG, and TOIE2 (Timer/Counter1 Overflow Interrupt Enable) and TOV2 are set (one), the Timer/Counter2 Overflow interrupt is executed. In PWM mode, this bit is set when Timer/Counter2 advances from $00.  Bit 5 – ICF1: Input Capture Flag 1 The ICF1 bit is set (one) to flag an Input Capture event, indicating that the Timer/Counter1 value has been transferred to the Input Capture Register (ICR1). ICF1 is cleared by hardware when executing th e corresponding interrupt handling vector. Alternatively, ICF1 is cleared by writing a logical “1” to the flag. When the SREG I-bit, TICIE1 (Timer/Counter1 Input Capture Interrupt Enable) and ICF1 are set (one), the Timer/Counter1 Capture interrupt is executed.  Bit 4 – OCF1A: Output Compare Flag 1A The OCF1A bit is set (one) when compare match occurs between the Timer/Counter1 and the data in OCR1A – Output Compare Register 1A. OCF1A is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCF1A is cleared by writing a logical “1” to the flag. When the I-bit in SREG and OCIE1A (Timer/Counter1 Compare Interrupt Enable) and the OCF1A are set (one), the Timer/Counter1 Compare A Match interrupt is executed.  Bit 3 – OCF1B: Output Compare Flag 1B The OCF1B bit is set (one) when compare match occurs between the Timer/Counter1 and the data in OCR1B – Output Compare Register 1B. OCF1B is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCF1B is cleared by writing a logical “1” to the flag. When the I-bit in SREG and OCIE1B (Timer/Counter1 Compare Match Interrupt Enable) and the OCF1B are set (one), the Timer/Counter1 Compare B Match interrupt is executed.  Bit 2 – TOV1: Timer/Counter1 Overflow Flag The TOV1 is set (one) when an overflow occurs in Timer/Counter1. TOV1 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV1 is cleared by writing a logical “1” to the flag. When the I-bit in SREG and TOIE1 Bit 7 6 5 4 3 2 1 0 $36 ($56) OCF2 TOV2 ICF1 OCF1A OCF1B TOV1 OCF0 TOV0 TIFR Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0

36 ATmega103(L)

0945I–AVR–02/07 (Timer/Counter1 Overflow Interrupt Enable) and TOV1 are set (one), the Timer/Counter1 Overflow interrupt is executed. In PWM mode, this bit is set when Timer/Counter1 advances from $0000.  Bit 1 – OCF0: Output Compare Flag 0 The OCF0 bit is set (one) when compare match occurs between Timer/Counter0 and the data in OCR0 – Output Compare Register 0. OCF0 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCF0 is cleared by writing a logical “1” to the flag. When the I-bit in SREG and OCIE0 (Timer/Counter2 Compare Interrupt Enable) and the OCF0 are set (one), the Timer/Counter0 Output Compare interrupt is executed.  Bit 0 – TOV0: Timer/Counter0 Overflow Flag The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logical “1” to the flag. When the SREG I-bit and TOIE0 (Timer/Counter0 Overflow Interrupt Enable) and TOV0 are set (one), the Timer/Counter0 Overflow interrupt is executed. In PWM mode, this bit is set when Timer/Counter0 advances from $00. Interrupt Response Time The interrupt execution response for all the enabled AVR interrupts is four clock cycles minimum. Four clock cycles after the Interrupt Flag has been set, the Program Vector address for the actual interrupt handling routine is executed. During this four-clock-cycle period, the Program Counter (2 bytes) is pushed onto the Stack, and the Stack Pointer is decremented by 2. The vector is normally a jump to the interrupt routine, and this jump takes three clock cycles. If an interr upt occurs during execution of a multi-cycle instruction, this instruction is completed before the interrupt is served. A return from an interrupt handling routine (same as for a subroutine call routine) takes four clock cycles. During these four clock cycles, the Program Counter (2 bytes) is popped back from the Stack, and the Stack Pointer is incremented by 2. When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served. Sleep Modes To enter any of the three sleep modes, the SE bit in MCUCR must be set (one) and a SLEEP instruction must be executed. The SM1 and SM0 bits in the MCUCR Register select which sleep mode (Idl e, Power-down, or Power-sa ve) will be activated by the SLEEP instruction, see Table 3 on page 23. If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU awakes, exe- cutes the interrupt routine and resumes execution from the instruction following SLEEP. The contents of the Register File, SRAM, and I/O memory are unaltered. If a reset occurs during sleep mode, the MCU wakes up and executes from the Reset Vector. Idle Mode When the SM1/SM0 bits are set to 00, the SLEEP instruction makes the MCU enter the Idle mode, stopping the CPU but allowing SPI, UART, Analog Comparator, ADC, Timer/Counters, Watchdog and the interrupt system to continue operating. This enables the MCU to wake up from external triggered interrupts as well as internal ones like the Timer Overflow and UART Receive Complete interrupts. If wake-up from the Analog Comparator interrupt is not required, the Analog Comparator can be powered down by setting the ACD-bit in the Analog Comparator Control and Status Register (ACSR). This will reduce power consumption in Idle mode. When the MCU wakes up from Idle mode, the CPU starts program execution immediately.

ATmega103(L) 0945I–AVR–02/07 Power-down Mode When the SM1/SM0 bits are set to 10, the SLEEP instruction makes the MCU enter the Power-down mode. In this mo de, the external Oscillator is stopped while the external interrupts and the Watchdog (if enabled) conti nue operating. Only an External Reset, a Watchdog Reset (if enabled), or an external level interrupt can wake up the MCU. Note that if a level-triggered interrupt is used for wake-up from Power-down mode, the changed level must be held for some time to wake up the MCU. This makes the MCU less sensitive to noise. The changed level is sampled twic e by the Watchdog Oscillator clock and if the input has the required level during this time, the MCU will wake up. The period of the Watchdog Oscillator is 1 µs (nominal) at 5.0V and 25 °C. The frequency of the Watchdog Oscillator is vo ltage-dependent, as shown in “Typical Characteristics” on page 123. When waking up from Power-down mode, a delay from the wake-up condition occurs until the wake-up becomes effective. This allows the clock to restart and become stable after having been stopped. The wake-up period is defined by the same SUT fuses that define the Reset Time-out period. The wake-up period is equal to the clock reset period, as shown in Table 5 on page 27. If the wake-up condition disappears before the MCU wakes up and starts to execute, e.g., a low-level on is not held long enough, the interrupt causing the wake-up will not be executed. Power-save Mode When the SM1/SM0 bits are 11, the SLEEP instruction makes the MCU enter the Power-save mode. This mode is identical to Power-down, with one exception: If Timer/Counter0 is clocked asynchronously, i.e., the AS0 bit in ASSR is set, Timer/Counter0 will run during sleep. In ad dition to the Power- down wake-up sources, the device can also wake up from either Timer Overflow or Output Compare event from Timer/Counter0 if the corresponding Timer/Counter0 interrupt enable bits are set in TIMSK. To ensure that the part executes the interrupt routine when waking up, also set the Global Interrupt Enable bit i SREG. When waking up from Power-save mode by an external interrupt, two instruction cycles are executed before the Interrupt Flags are updated. When waking up by the asynchro- nous timer, three instruction cycles are executed before the flags are updated. During these cycles, the processor executes instructions, but the interrupt condition is not read- able and the interrupt routine has not started yet. If the asynchronous timer is not clocked asynchronously, Power-down mode is recommended instead of Power-save mode because the contents of the registers in the asynchronous timer should be consid- ered undefined after wake-up in Power-save mode if AS0 is 0.

38 ATmega103(L)

Figure 28. Prescaler for Timer/Counter1 and Timer/Counter2 Figure 29. The Timer/Counter0 Prescaler

40 ATmega103(L)

Figure 31. Timer/Counter2 Block Diagram bit Timer/Counter2 can select clock source from CK, prescaled CK or an external pin. Timer/Counter Control Registers – TCCR0 and TCCR2. settings are found in the Timer/Counter Interrupt Mask Register (TIMSK). units useful for lower speed functions or exact timing functions with infrequent actions. PB7(OC2/PWM2) – on compare match. PWM with centered pulses. Refer to page 43 for a detailed description of this function.

This bit is a reserved bit in the ATmega103(L) and always reads as zero. When set (one), this bit enables PWM mode for Timer/Counter0 or Timer/Counter2. This mode is described on page 43. Table 10. Compare Mode Select 0 1 Toggle the OCn/PWMn output line. 1 0 Clear the OCn/PWMn output line (to zero). 1 1 Set the OCn/PWMn output line (to one).

42 ATmega103(L)

In PWM mode, this bit has no effect. The Clock Select2 bits 2, 1 and 0 define the prescaling source of the Timer/Counter. ured as an output. This feature can give the user software control of the counting. Table 11. Timer/Counter0 Prescale Select 0 0 0 Timer/Counter0 is stopped. Table 12. Timer/Counter2 Prescale Select 0 0 0 Timer/Counter2 is stopped.

001 C K

010 C K / 8

011 C K / 6 4

100 C K / 2 5 6

101 C K / 1 0 2 4

These 8-bit registers contain the value of the Timer/Counters. tinues counting in the timer clock cycle after it is preset with the written value. The Output Compare Registers are 8-bit read/write registers. same value does not generate a compare match. Timer/Counter Control Registers TCCR0 and TCCR2. Refer to Table 13 for details. chronized OCR0 or OCR2 write. See Figure 32 for an example. Table 13. Compare Mode Select in PWM Mode counting (non-inverted PWM).

44 ATmega103(L)

Figure 32. Effects on Unsynchronized OCR Latching ten value always will read out of OCR0/2. or COM11/COM10. This is shown in Table 14. put Compare Flags and interrupts. The frequency of the PWM will be Timer Clock Frequency divided by 510. These bits are reserved bits in the ATmega103(L) and always read as zero. Table 14. PWM Outputs OCRn = $00 or $FF

ATmega103(L) 0945I–AVR–02/07  Bit 3 – AS0: Asynchronous Timer/Counter0 When set (one), Timer/Counter0 is clocked from the TOSC1 pin. When cleared (zero), Timer/Counter0 is clocked from the internal system clock, CK. When the value of this bit is changed, the contents of TCNT0 might get corrupted.  Bit 2 – TCN0UB: Timer/Counter0 Update Busy When Timer/Counter0 operates asynchronously and TCNT0 is written, this bit becomes set (one). When TCNT0 has been updated from the temporary storage register, this bit is cleared (zero) by hardware. A logical “0” in this bit indicates that TCNT0 is ready to be updated with a new value.  Bit 1 – OCR0UB: Output Co mpare Register0 Update Busy When Timer/Counter0 operates asynchronously and OCR0 is written, this bit becomes set (one). When OCR0 has been updated from the temporary storage register, this bit is cleared (zero) by hardware. A logical “0” in th is bit indicates that OCR0 is ready to be updated with a new value.  Bit 0 – TCR0UB: Timer/Counter Control Register0 Update Busy When Timer/Counter0 operates asynchronously and TCCR0 is written, this bit becomes set (one). When TCCR0 has been updated from the temporary storage register, this bit is cleared (zero) by hardware. A logical “0” in this bit indicates that TCCR0 is ready to be updated with a new value. If a write is performed to any of the three Timer/Counter0 Registers while its update busy flag is set (one), the updated value might get corrupted and cause an unintentional interrupt to occur. When reading TCNT0, OCR0 and TCCR0, there is a difference in result. When reading TCNT0, the actual timer value is read. When reading OCR0 or TCCR0, the value in the temporary storage register is read. Asynchronous Operation of Timer/Counter0 When Timer/Counter0 operates synchronously, all operations and timing are identical to Timer/Counter2. During asynchronous operatio n, however, some considerations must be taken.  WARNING: When switching between asynchronous and synchronous clocking of Timer/Counter0, the Timer Registers TCNT0, OCR0 and TCCR0 might get corrupted. The following is the safe procedure for switching clock source: 1. Disable the Timer0 interrupts OCIE0 and TOIE0. 2. Select clock source by setting ASO as appropriate. 3. Write new values to TCNT0, OCR0 and TCCR0. 4. If switching to asynchronous operat ion, wait for TCNT0UB, OCR0UB and TCR0UB to be cleared. 5. Clear the Timer/Counter0 Interrupt Flags. 6. Enable interrupts if needed.  The Oscillator is optimized for use with a 32,768 Hz watch crystal. An external clock signal applied to this pin goes through the same amplifier having a bandwidth of 256 kHz. The external clock signal should therefore be in the interval 0 Hz - 256 kHz. The frequency of the clock signal applied to the TOSC1 pin must be lower than one fourth of the CPU main clock frequency. Observe that CPU clock frequency can be lower than the XTAL frequency if the XTAL divider is enabled.

46 ATmega103(L)

0945I–AVR–02/07  When writing to one of the registers TCNT0, OCR0 or TCCR0, the value is transferred to a temporary register and latched after two positive edges on TOSC1. The user should not write a new value before the contents of the temporary register have been transferred to its destination. Each of the three mentioned registers have their individual temporary register, which means that e.g., writing to TCNT0 does not disturb an OCR0 write in progress. To detect that a transfer to the destination register has taken place, an Asynchronous Status Register (ASSR) has been implemented.  When entering Power-save mode after havi ng written to TCNT0, OCR0 or TCCR0, the user must wait until the written register has been updated if Timer/Counter0 is used to wake up the device. Otherwise, the MCU will go to sleep before the changes have had any effect. This is extremely important if the Output Compare0 interrupt is used to wake up the device; Output Compare is disabled during write to OCR0 or TCNT0. If the write cycle is not finished (i.e., the user goes to sleep before the OCR0UB bit returns to zero), the device will never get a compare match and the MCU will not wake up.  If Timer/Counter0 is used to wake up the device from Power-save mode, precautions must be taken if the user wants to reenter Power-save mode: The interrupt logic needs one TOSC1 cycle to get reset. If the time between wake-up and reentering Power-save mode is less than one TOSC1 cycle, the interrupt will not occur and the device will fail to wake up. If the user is in doubt whether the time before re-entering Power-save is sufficient, the following algorithm can be used to ensure that one TOSC1 cycle has elapsed: 1. Write a value to TCCR0, TCNT0 or OCR0. 2. Wait until the corresponding Update Busy Flag in ASSR returns to zero. 3. Enter Power-save mode.  When asynchronous operatio n is selected, the 32 kHz Oscillator for Timer/Counter0 is always running, except in Power-down mode. After a Power-up Reset or wake-up from Power-down, the user should be aware of the fact that this Oscillator might take as long as one second to stabilize. The user is advised to wait for at least one second before using Timer/Counter0 after Power-up or wake-up from Power-down. The content of all Timer/Counter0 Registers must be considered lost after a wake- up from Power-down due to the unstable clock signal upon start-up, no matter whether the Oscillator is in use or a clock signal is applied to the TOSC pin.  Description of wake-up from Power-save mode when the Timer is clocked asynchronously: When the interrupt condition is met, the wake-up process is started on the following cycle of the Timer clock, that is, the Timer is always advanced by at least one before the processor can read the counter value. To execute the corresponding Timer/Counter0 interrupt routine, the Global Interrupt bit in SREG must have been set. Otherwise, the part will still wake up from Power-down, but continues to execute the Sleep command. The Interrupt Flags are updated three processor cycles after the processor clock has started. During these cycles, the processor executes instructions, but the interrupt condition is not readable and the interrupt routine has not started yet.  During asynchronous operation, the synchronization of the Interrupt Flags for the asynchronous Timer takes three processor cycles plus one timer cycle. The Timer is therefore advanced by at least one before the processor can read the Timer value causing the setting of the Interrupt Flag. The Output Compare pin is changed on the Timer clock, and is not synchronized to the processor clock.  After waking up from Power-save mode with the asynchronous Timer enabled, there will be a short interval of which TCNT0 will read as the same value as before Power-

ATmega103(L) 0945I–AVR–02/07 save mode was entered. After an edge on the asynchronous clock, TCNT0 will read correctly. (The compare and overflow functions of the Timer are not affected by this behavior.) Safe procedure to ensure correct value is read: 1. Write any value to either of the registers OCR0 or TCCR0 2. Wait for the corresponding Update Busy Flag to be cleared 3. Read TCNT0 Note that OCR0 and TCCR0 are never modi fied by hardware, and will always read correctly. 16-bit Timer/Counter1 Figure 33 shows the block diagram for Timer/Counter1. The 16-bit Timer/Counter1 can select clock source from CK, prescaled CK or an exter- nal pin. In addition, it can be stopped as described in the specification for the Timer/Counter1 Control Register (TCCR1B). The different Status Flags (Overflow, Com- pare Match and Capture Event) are found in the Timer/Counter Interrupt Flag Register (TIFR). Control signals are found in the Timer/Counter1 Control Registers – TCCR1A and TCCR1B. The interrupt enable/disable settings for Timer/Counter1 are found in the Timer/Counter Interrupt Mask Register (TIMSK). When Timer/Counter1 is externally clocked, the external signal is synchronized with the Oscillator frequency of the CPU. To assure proper sampling of the external clock, the minimum time between two external clock transitions must be at least one internal CPU clock period. The external clock signal is sampled on the rising edge of the internal CPU clock. The 16-bit Timer/Counter1 features both a high-resolution and a high-accuracy usage with the lower prescaling opportunities. Si milarly, the high prescaling opportunities makes the Timer/Counter1 useful for lowe r speed functions or exact timing functions with infrequent actions. The Timer/Counter1 supports two Output Compare functions using the Output Compare Registers 1A and 1B (OCR1A and OCR1B) as the data sources to be compared to the Timer/Counter1 contents. The Output Comp are functions include optional clearing of the counter on Compare A Match, and actions on the Output Compare pins on both compare matches.

48 ATmega103(L)

Figure 33. Timer/Counter1 Block Diagram this. The ICP pin logic is shown in Figure 34. Figure 34. ICP Pin Schematic Diagram

These bits are reserved bits in the ATmega103(L) and always read as zero.

1. This mode is described on page 53.

Table 15. Compare1 Mode Select 0 1 Toggle the OC1X output line. 1 0 Clear the OC1X output line (to zero). 1 1 Set the OC1X output line (to one). Table 16. PWM Mode Select 0 0 PWM operation of Timer/Counter1 is disabled.

50 ATmega103(L)

Input Capture Register (ICR1) on the falling edge of the Input Capture pin – PD4(IC1). Input Capture Register on the rising edge of the Input Capture pin – PD4(IC1). These bits are reserved bits in the ATmega103(L) and always read as zero. In PWM mode, this bit has no effect. 0 1 Timer/Counter1 is an 8-bit PWM. 1 0 Timer/Counter1 is a 9-bit PWM. 1 1 Timer/Counter1 is a 10-bit PWM.

The lock Select1 bits 2, 1 and 0 define the prescaling source of Timer/Counter1. ured as an output. This feature can give the user software control of the counting. interrupt routines if interrupts are allowed from within interrupt routines). Timer/Counter1 as an 8-bit Timer, it is sufficient to write the Low Byte only. Table 17. Clock1 Prescale Select 0 0 0 Stop, the Timer/Counter1 is stopped.

52 ATmega103(L)

0945I–AVR–02/07 full 16-bit register read operation. When using Timer/Counter1 as an 8-bit Timer, it is sufficient to read the Low Byte only. The Timer/Counter1 is realized as an up or up/down (in PWM mode) counter with read and write access. If Timer/Counter1 is written to and a clock source is selected, the Timer/Counter1 continues counting in the clock cycle after it is preset with the written value. Timer/Counter1 Output Compare Register – OCR1AH and OCR1AL Timer/Counter1 Output Compare Register – OCR1BH and OCR1BL The Output Compare Registers are 16-bit read/write registers. The Timer/Counter1 Output Compare Registers contain the data to be continuously compared with Timer/Counter1. Actions on compare matches are specified in the Timer/Counter1 Control and Status Registers. A compare match occurs only if Timer/Counter1 counts to the OCR value. A software write that sets TCNT1 and OCR1A or OCR1B to the same value does not generate a compare match. A compare match will set the Compare Interr upt Flag in the CPU clock cycle following the compare event. Since the Output Compare Registers (OCR1A and OCR1B) are 16-bit registers, a tem- porary register TEMP is used when OCR1A/B ar e written to ensure that both bytes are updated simultaneously. When the CPU writes the High Byte, OCR1AH or OCR1BH, the data is temporarily stored in the TEMP Register. When the CPU writes the Low Byte, OCR1AL or OCR1BL, the TEMP Register is simultaneously written to OCR1AH or OCR1BH. Consequently, the High Byte OCR1AH or OCR1BH must be written first for a full 16-bit register write operation. The TEMP Register is also used when accessing TCNT1 and ICR1. If the main program and interrupt routines perform access to registers using TEMP, interrupts must be dis- abled during access from the main program. Timer/Counter1 Input Capture Register – ICR1H and ICR1L B i t 1 51 41 31 21 11 0 9 8 $2B MSB OCR1AH $2A LSB OCR1AL 76543210 R e a d / W r i t e R / WR / WR / WR / WR / WR / WR / WR / W R / WR / WR / WR / WR / WR / WR / WR / W Initial Value 0 0 0 0 0 0 0 0 00000000 B i t 1 51 41 31 21 11 0 9 8 $29 MSB OCR1BH $28 LSB OCR1BL 76543210 R e a d / W r i t e R / WR / WR / WR / WR / WR / WR / WR / W R / WR / WR / WR / WR / WR / WR / WR / W Initial Value 0 0 0 0 0 0 0 0 00000000 B i t 1 51 41 31 21 11 0 9 8 $27 ($37) MSB ICR1H $26 ($36) LSB ICR1L 76543210

The Input Capture Register is a 16-bit read-only register. the Input Capture Flag (ICF1) is set (one). Byte ICR1L must be accessed first for a full 16-bit register read operation. must be disabled during access from the main program. Control Register, TCCR1A. Refer to Table 19 for details. Table 18. Timer TOP Values and PWM Frequency Table 19. Compare1 Mode Select in PWM Mode down-counting (non-inverted PWM).

54 ATmega103(L)

event of an unsynchronized OCR1A/OCR1B write. See Figure 35 for an example. Figure 35. Effects on Unsynchronized OCR1 Latching recently written value always will read out of OCR1A/B. COM1A1/COM1A0 or COM1B1/COM1B0. This is shown in Table 20. Table 20. PWM Outputs OCR1X = $0000 or TOP

10 T O P H

11 T O P L

Table 21. See characterization data for typical values at other V Timer Control Register for details. Figure 36. Watchdog Timer These bits are reserved bits in the ATmega103(L) and will always read as zero. not be disabled. Once set, hardware will clear this bit to zero after four clock cycles. Refer to the description of the WDE bit for a Watchdog disable procedure.

1 MHz at VCC = 5V

56 ATmega103(L)

1. In the same operation, write a logical “1” to WDTOE and WDE. A logical “1” must

be written to WDE even though it is set to one before the disable operation starts.

1. Within the next four clock cycles, write a logical “0” to WDE. This disables the

Time-out periods are shown in Table 21. cal Characteristics section. Watchdog Timer may not start counting from zero. before changing the Watchdog Timer Prescale Select. Table 21. Watchdog Timer Prescale Select

ATmega103(L) 0945I–AVR–02/07 EEPROM Read/Write Access The EEPROM Access Registers are accessible in the I/O space. The write access time is in the range of 2.5 - 4 ms, depending on the V CC voltages. A self-timing function lets the user software detect when the next byte can be written. A special EEPROM Ready interrupt can be set to trigger when the EEPROM is ready to accept new data. In order to prevent unintentional EEPROM writes, a specific write procedure must be fol- lowed. Refer to the description of the EEPROM Control Register for details on this. When the EEPROM is written, the CPU is ha lted for two clock cycles before the next instruction is executed. When it is read, the CPU is halted for four clock cycles. EEPROM Address Register – EEARH, EEARL The EEPROM Address Registers (EEARH and EEARL) specify the EEPROM address in the 4 KB EEPROM space. The EEPROM Data bytes are addressed linearly between 0 and 4095. EEPROM Data Register – EEDR  Bits 7..0 – EEDR7..0: EEPROM Data: For the EEPROM write operation, the EEDR Register contains the data to be written to the EEPROM in the address gi ven by the EEAR Register. For the EEPROM read oper- ation, the EEDR contains the data read out from the EEPROM at the address given by EEAR. EEPROM Control Register – EECR  Bits 7..4 – Res: Reserved Bits These bits are reserved bits in the ATmega103(L) and will always be read as zero.  Bit 3 – EERIE: EEPROM Ready Interrupt Enable When the I-bit in SREG and EERIE are set (one), the EEPROM Ready interrupt is enabled. When cleared (zero), the interrupt is disabled. The EEPROM Ready interrupt constantly generates an interrupt request when EEWE is cleared (zero). B i t 1 51 41 31 2 1 1 1 0 9 8 $1F ($3F) – – – – EEAR11 EEAR10 EEAR9 EEAR8 EEARH $1E ($3E) EEAR7 EEAR6 EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 EEARL 7654 3 2 1 0 Read/Write R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 0000 0 0 0 0 B i t 76543210 $1D ($3D) MSB LSB EEDR Read/Write R/W R/W R/W R/W R/W R/W R/W R/W I n i t i a l V a l u e 00000000 B i t 76543 2 1 0 $1C ($3C) –––– E E R I E E E M W E E E W E E E R E E E C R Read/Write R R R R R/W R/W R/W R/W I n i t i a l V a l u e 00000 0 0 0

58 ATmega103(L)

0945I–AVR–02/07  Bit 2 – EEMWE: EEPROM Master Write Enable The EEMWE bit determines w hether setting EEWE to one causes the EEPROM to be written. When EEMWE is set (one), setting EEWE will write data to the EEPROM at the selected address. If EEMWE is zero, setti ng EEWE will have no effect. When EEMWE has been set (one) by so ftware, hardware clears the bit to zero after four clock cycles. See the description of the EEWE bit for a EEPROM write procedure.  Bit 1 – EEWE: EEPROM Write Enable The EEPROM Write Enable signal (EEWE) is the write strobe to the EEPROM. When address and data are correctly set up, the EEWE bit must be set to write the value into the EEPROM. The EEMWE bit must be set when the logical “1” is written to EEWE, oth- erwise no EEPROM write takes place. T he following procedure should be followed when writing the EEPROM (the order of steps 2 and 3 is unessential): 1. Wait until EEWE becomes zero. 2. Write new EEPROM addr ess to EEAR (optional). 3. Write new EEPROM Data to EEDR (optional). 4. Write a logical “1” to the EEMWE bit in EEC R (to be able to write an logical “1” to the EEMWE bit, the EEWE bit must be written to zero in the same cycle). 5. Within four clock cycles after setting EEMWE, write a logical “1” to EEWE. Caution: An interrupt between step 4 and step 5 will make the write cycle fail, since the EEPROM Master Write Enable will time-out. If an interrupt routine accessing the EEPROM is interrupting another EEPROM access, the EEAR and EEDR Registers will be modified, causing the interrupted EEPROM access to fail. It is recommended to have the Global Interrupt Flag cleared during the four last steps to avoid these problems. When the write access time (typically 2.5 ms at V CC = 5V or 4 ms at V CC = 2.7V) has elapsed, the EEWE bit is cleared (zero) by hardware. The user software can poll this bit and wait for a zero before writing the next byte. When EEWE has been set, the CPU is halted for two cycles before the next instruction is executed.  Bit 0 – EERE: EEPROM Read Enable The EEPROM Read Enable sign al (EERE) is the read strobe to the EEPROM. When the correct address is set up in the EEAR Register, the EERE bit must be set. When the EERE bit is cleared (zero) by hardware, requested data is found in the EEDR Register. The EEPROM read access takes one instruction and there is no need to poll the EERE bit. When EERE has been set, the CPU is halted for four cycles before the next instruc- tion is executed. The user should poll the EEWE bit before starting the read operation. If a write operation is in progress when new data or address is written to the EEPROM I/O Registers, the write operation will be interrupted and the result is undefined.

ATmega103(L) 0945I–AVR–02/07 Prevent EEPROM Corruption During periods of low VCC, the EEPROM Data can be corrupted because the supply volt- age is too low for the CPU and the EEPROM to operate properly. These issues are the same as for board-level systems using th e EEPROM and the same design solutions should be applied. An EEPROM Data corruption can be caused by two situations when the voltage is too low. First, a regular write sequence to the EEPROM requires a minimum voltage to operate correctly. Second, the CPU itself can execute instructions incorrectly if the sup- ply voltage for executing instructions is too low. EEPROM Data corruption can easily be avoided by following these design recommen- dations (one is sufficient): 1. Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This is best done by an external low V CC Reset Protection circuit, often referred to as a Brown-out Detector (BOD). Please refer to application note “AVR 180” for design considerations regarding Power-on Reset and low-voltage detection. 2. Keep the AVR core in Power-down sleep mode during periods of low V CC. This will prevent the CPU from attempting to decode and execute instructions, effec- tively protecting the EEPROM Registers from unintentional writes. 3. Store constants in Flash memory if the ability to change memory contents from software is not required. Flash memory cannot be updated by the CPU and will not be subject to corruption.

60 ATmega103(L)

between the ATmega103(L) and peripheral devices or between several AVR devices. Figure 37. SPI Block Diagram The interconnection between Master and Slav e CPUs with SPI is shown in Figure 38. the Master and the Slave are interchanged.

Figure 38. SPI Master-Slave Interconnection been completely shifted in. Otherwise, the first byte is lost. define the direction of the user-defined SPI pins.

1. The MSTR bit in SPCR is cleared and the SPI system becomes a Slave. As a

result of the SPI becoming a Slave, the MOSI and SCK pins become inputs.

1. The SPIF Flag in SPSR is set, and if the SPI interrupt is enabled and the I-bit in

SREG is set, the interrupt routine will be executed. user to re-enable SPI Master mode. Table 22. SPI Pin Overrides

62 ATmega103(L)

shown in Figure 39 and Figure 40. Figure 39. SPI Transfer Format with CPHA = 0 and DORD = 0 Figure 40. SPI Transfer Format with CPHA = 1 and DORD = 0 and the Global Interrupts are enabled. connected to pins PB0, PB1, PB2 and PB3.

• Not defined but normally MSB of character just received.
• Not defined but normally LSB of previously transmitted character.

When the DORD bit is set (one), the LSB of the data word is transmitted first. When the DORD bit is cleared (zero), the MSB of the data word is transmitted first. low when idle. Refer to Figure 39 and Figure 40 for additional information. Refer to Figure 39 or Figure 40 for the functionality of this bit. accessing the SPI Data Register (SPDR). The WCOL bit is set if the SPI Data Regist er (SPDR) is written during a data transfer. ister with WCOL set (one), and then accessing the SPI Data Register. Table 23. Relationship between SCK and the Oscillator Frequency

64 ATmega103(L)

0945I–AVR–02/07  Bits 5..0 – Res: Reserved Bits These bits are reserved bits in the ATmega103(L) and will always read as zero.

ATmega103(L) 0945I–AVR–02/07 SPI Data Register – SPDR The SPI Data Register is a read/write register used for data transfer between the Regis- ter File and the SPI Shift Register. Writing to the register initiates data transmission. Reading the register causes the Shift Register Receive buffer to be read. B i t 76543210 $0F ($2F) MSB LSB SPDR Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value X X X X X X X X Undefined

66 ATmega103(L)

0945I–AVR–02/07 UART The ATmega103(L) features a full duplex (separate Receive and Transmit Registers) Universal Asynchronous Receiver and Transmitter (UART). The main features are:  Baud Rate Generator that can Generate a large Number of Baud Rates (bps)  High Baud Rates at Low XTAL Frequencies  8 or 9 Bits Data  Noise Filtering  OverRun Detection  Framing Error Detection  False Start Bit Detection  Three separate Interrupts on TX Complete, TX Data Register Empty and RX Complete Data Transmission A block schematic of the UART Transmitter is shown in Figure 41. Data transmission is initiated by writing the data to be transmitted to the UART I/O Data Register, UDR. Data is transferred from UDR to the Transmit Shift Register when:  A new character has been written to UDR after the stop bit from the previous character has been shifted out. The Shift Register is loaded immediately.  A new character has been written to UDR before the stop bit from the previous character has been shifted out. The Shift Register is loaded when the stop bit of the character currently being transmitted has been shifted out. If the 10(11)-bit Tr ansmit Shift Register is empty, da ta is transferre d from UDR to the Shift Register. At this time the UDRE (UART Data Register Empty) bit in the UART Sta- tus Register, USR, is set. When this bit is set (one), the UART is ready to receive the next character. Writing to UDR clears UDRE. At the same time as the data is transferred from UDR to the 10(11)-bit Shift Register, bit 0 of the Shift Register is cleared (start bit) and bit 9 or 10 is set (stop bit). If 9-bit data word is selected (the CHR9 bit in the UART Control Register, UCR is set), the TXB8 bit in UCR is transferred to bit 9 in the Transmit Shift Register.

Figure 41. UART Transmitter the setting of the DDE1 bit in DDRE.

68 ATmega103(L)

0945I–AVR–02/07 Data Reception Figure 42. UART Receiver The Receiver front-end logic samples the signal on the RXD pin at a frequency 16 times the baud rate. While the line is idle, one single sample of logical “0” will be interpreted as the falling edge of a start bit, and the start bit detection sequence is initiated. Let sample 1 denote the first zero-sample. Following the 1-to-0 transition, the Receiver samples the RXD pin at samples 8, 9, and 10. If two or more of these three samples are found to be logical “1”s, the start bit is rejected as a noi se spike and the Receiver starts looking for the next 1-to-0 transition. If, however, a valid start bit is detected, sampling of the data bits following the start bit is performed. These bits are also sampled at samples 8, 9 and 10. The logical value found in at least two of the three samples is taken as the bit value. All bits are shifted into the Transmitter Shift Register as they are sampled. Sampling of an incoming character is shown in Figure 43. DATA BUS DATA BUS UART I/O DATA REGISTER (UDR) 10(11)-BIT RX SHIFT REGISTER UART CONTROL REGISTER (UCR) DATA RECOVERY LOGIC UART STATUS REGISTER (USR) BAUD RATE GENERATOR XTAL RXB8TXB8TXENCHR9RXEN TXC TXCIERXCIEUDRIE UDRERXC RXC FEDOR RXC IRQ /16BAUD X 16 BAUD STORE UDR PIN CONTROL LOGIC RXD

Figure 43. Sampling Received Data in the UART Status Register (USR) is set when the received byte is transferred to UDR. Framing Errors. FE is cleared when UDR is read. Register when data is transferred to UDR. OverRuns if the baud rate is high or CPU load is high. PORTE0 bit can still be used to control the pull-up resistor on the pin. by writing to the UDR Register.

70 ATmega103(L)

0945I–AVR–02/07 UART Control UART I/O Data Register – UDR The UDR Register is actually two physicall y separate registers sharing the same I/O address. When writing to the register, the UART Transmit Data Register is written. When reading from UDR, the UART Receive Data Register is read. UART Status Register – USR The USR Register is a read-only register providing information on the UART Status.  Bit 7 – RXC: UART Receive Complete This bit is set (one) when a received character is transferred from the Receiver Shift Register to UDR. The bit is set regardless of any detected framing errors. When the RXCIE bit in UCR is set, the UART Receive Complete interrupt will be executed when RXC is set (one). RXC is cleared by reading UDR. When interrupt-driven data reception is used, the UART Receive Complete Interrupt routine must read UDR in order to clear RXC, otherwise a new interrupt will occur once the interrupt routine terminates.  Bit 6 – TXC: UART Transmit Complete This bit is set (one) when the entire charac ter (including the stop bit) in the Transmit Shift Register has been shifted out and no new data has been written to the UDR. This flag is especially useful in half-duplex co mmunications interfaces, where a transmitting application must enter Receive mode and free the communications bus immediately after completing the transmission. When the TXCIE bit in UCR is set, setting of TXC causes the UART Transmit Complete interrupt to be executed. TXC is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, the TX C bit is cleared (zero) by writing a logical “1” to the bit.  Bit 5 – UDRE: UART Data Register Empty This bit is set (one) when a character written to UDR is transferred to the Transmit Shift Register. Setting of this bit indicates that the Transmitter is ready to receive a new char- acter for transmission. When the UDRIE bit in UCR is set, the UART Transmit Complete interrupt to be exe- cuted as long as UDRE is set. UDRE is clea red by writing UDR. When interrupt-driven data transmittal is used, the UART Data Register Empty Interrupt routine must write UDR in order to clear UDRE, otherwise a new interrupt will occur once the interrupt rou- tine terminates. UDRE is set (one) during reset to indicate that the Transmitter is ready. B i t 76543210 $0C ($2C) MSB LSB UDR Read/Write R/W R/W R/W R/W R/W R/W R/W R/W I n i t i a l V a l u e 00000000 B i t 76543210 $0B ($2B) RXC TXC UDRE FE OR – – – USR Read/Write R R/W R R R R R R I n i t i a l V a l u e 00100000

ATmega103(L) 0945I–AVR–02/07  Bit 4 – FE: Framing Error This bit is set if a Framing Error condition is detected, i.e., when the stop bit of an incom- ing character is zero. The FE bit is cleared when the stop bit of received data is one.  Bit 3 – OR: OverRun This bit is set if an OverRun condition is detected, i.e., when a character already present in the UDR Register is not read before the next character is transferred from the Receiver Shift Register. The OR bit is buffere d, which means that it will be set once the valid data still in UDRE is read. The OR bit is cleared (zero) when data is received and transferred to UDR.  Bits 2..0 – Res: Reserved Bits These bits are reserved bits in the ATmega103(L) and will always read as zero. UART Control Register – UCR  Bit 7 – RXCIE: RX Complete Interrupt Enable When this bit is set (one), a setting of t he RXC bit in USR will cause the Receive Com- plete Interrupt routine to be executed, provided that global interrupts are enabled.  Bit 6 – TXCIE: TX Complete Interrupt Enable When this bit is set (one), a setting of t he TXC bit in USR will cause the Transmit Com- plete Interrupt routine to be executed, provided that global interrupts are enabled.  Bit 5 – UDRIE: UART Data Register Empty Interrupt Enable When this bit is set (one), a setting of the UDRE bit in USR will cause the UART Data Register Empty Interrupt routine to be executed, provided that global interrupts are enabled.  Bit 4 – RXEN: Receiver Enable This bit enables the UART Receiver when set (one). When the Receiver is disabled, the RXC, OR and FE Status Flags cannot become set. If these flags are set, turning off RXEN does not cause them to be cleared.  Bit 3 – TXEN: Transmitter Enable This bit enables the UART Transmitter when se t (one). When disabling the Transmitter while transmitting a character, the Transmitter is not disabled before the character in the Shift Register plus any following character in UDR has been completely transmitted.  Bit 2 – CHR9: 9-bit Characters When this bit is set (one), transmitted and received characters are nine bits long, plus start and stop bits. The ninth bit is read and written by using the RXB8 and TXB8 bits in UCR, respectively. The ninth data bit can be used as an extra stop bit or a parity bit. B i t 76543210 $0A ($2A) RXCIE TXCIE UDRIE RXEN TXEN CHR9 RXB8 TXB8 UCR Read/Write R/W R/W R/W R/W R/W R/W R W I n i t i a l V a l u e 00000010

72 ATmega103(L)

0945I–AVR–02/07  Bit 1 – RXB8: Receive Data Bit 8 When CHR9 is set (one), RXB8 is the ninth data bit of the received character.  Bit 0 – TXB8: Transmit Data Bit 8 When CHR9 is set (one), TXB8 is the ninth data bit in the character to be transmitted.

ATmega103(L) 0945I–AVR–02/07 Baud Rate Generator The baud rate generator is a frequency divider that generates baud rates according to the following equation:  BAUD = baud rate f CK = CPU clock frequency  UBRR = contents of the UART Baud Rate Register, UBRR (0 - 255) For standard crystal frequencies, the most commonly used baud rates can be generated by using the UBRR settings in Table 24. Observe that CPU clock frequency can be lower than the XTAL frequency if the XTAL divider is enabled. UBRR values that yield an actual baud rate differing less than 2% from the target baud rate are in boldface in the table. However, using baud rates that have more than 1% error is not recommended. High error ratings give less noise resistance. BAUD f CK

74 ATmega103(L)

Table 24. UBRR Settings at Various CPU Frequencies the description on the previous page.

Figure 44. Analog Comparator Block Diagram occur when the bit is changed. This bit is a reserved bit in the ATmega103(L) and will always read as zero. ACO is directly connected to the comparator output.

76 ATmega103(L)

log Comparator interrupt is activated. When cleared (zero), the interrupt is disabled. interrupt, the TICIE1 bit in the Timer Interrupt Mask Register (TIMSK) must be set (one). rupt. The different settings are shown in Table 25. can occur when the bits are changed. a one back into ACI if it is read as set, thus clearing the flag. Table 25. ACIS1/ACIS0 Settings

diagram of the ADC is shown in Figure 45. Figure 45. Analog-to-Digital Converter Block Schematic

78 ATmega103(L)

0945I–AVR–02/07 Operation The ADC operates in Single Conversion mode, and each conversion will have to be ini- tiated by the user. The ADC is enabled by writing a logical “1” to the ADC Enable bit, ADEN in ADCSR. The first conversion that is started after enabling the ADC will be preceded by a dummy conversion to initialize the ADC. To the user, the only difference will be that this conver- sion takes 13 more ADC clock pulses than a normal conversion (see Figure 48). A conversion is started by writing a logical “1” to the ADC Start Conversion bit, ADSC. This bit will stay high as long as the conversion is in progress and be set to zero by hard- ware when the conversion is completed. If a different data channel is selected while a conversion is in progress, the ADC will finish the current conversion before performing the channel change. As the ADC generates a 10-bit result, two Data Registers, ADCH and ADCL, must be read to get the result when the conversion is complete. Special data protection logic is used to ensure that the contents of the Data Registers belong to the same result when they are read. This mechanism works as follows: When reading data, ADCL must be read first. Once ADCL is read, ADC access to Data Registers is blocked. This means that if ADCL has been read, and a conversion com- pletes before ADCH is read, none of the registers are updated and the result from the conversion is lost. When ADCH is read, ADC access to the ADCH and ADCL Registers is re-enabled. The ADC has its own interrupt, ADIF, which can be triggered when a conversion com- pletes. When ADC access to the Data Registers is prohibited between reading of ADCL and ADCH, the interrupt will trigger even if the result is lost. Prescaling Figure 46. ADC Prescaler The ADC contains a prescaler, which divides the system clock to an acceptable ADC clock frequency. The ADC accepts input clock frequencies in the range 50 - 200 kHz. Applying a higher input frequency will result in poorer ac curacy (see “ADC DC Charac- teristics” on page 83). The ADPS0 - ADPS2 bits in ADCSR are used to generate a proper ADC clock input fre- quency from any XTAL frequency above 100 kHz. The prescaler starts counting from the moment the ADC is switched on by setting the ADEN bit in ADCSR. The prescaler 7-BIT ADC PRESCALER ADC CLOCK SOURCE CK ADPS0 ADPS1 ADPS2 CK/128CK/2CK/4CK/8CK/16CK/32CK/64 ResetADEN

80 ATmega103(L)

0945I–AVR–02/07 ADC Noise Canceler Function The ADC features a noise canceler that enabl es conversion during Idle mode to reduce noise induced from the CPU core. To make use of this feature, the following procedure should be used: 1. Turn off the ADC by clearing ADEN. 2. Turn on the ADC and simultaneously start a conversion by setting ADEN and ADSC. This starts a dummy conversion that will be followed by a valid conversion. 3. Within 14 ADC clock cycles, enter Idle mode. 4. If no other interrupts occur before the ADC conversion completes, the ADC inter- rupt will wake up the MCU and execute the ADC conversion complete interrupt routine. ADC Multiplexer Select Register – ADMUX  Bits 7..3 – Res: Reserved Bits These bits are reserved bits in the ATmega103(L) and always read as zero.  Bits 2..0 – MUX2..MUX0: Analog Channel Select Bits 2 - 0 The value of these three bits selects which analog input 7 - 0 is connected to the ADC. ADC Control and Status Register – ADCSR  Bit 7 – ADEN: ADC Enable Writing a logical “1” to this bit enables the AD C. By clearing this bit to zero, the ADC is turned off. Turning the ADC of f while a conversion is in progress will terminate this conversion.  Bit 6 – ADSC: ADC Start Conversion A logical “1” must be written to this bit to start each conversion. The first time ADSC has been written after the ADC has been enabled, or if ADSC is written at the same time as the ADC is enabled, a dummy conversion will precede the initiated conversion. This dummy conversion performs initialization of the ADC. ADSC remains high during the conversion. ADSC goes low after the conversion is com- plete, but before the result is written to the ADC Data Registers. This allows a new conversion to be initiated before the current conversion is complete. The new conver- sion will then start immediately after the current conversion completes. When a dummy conversion precedes a real conversion, ADSC will stay high until the real conversion completes. Writing a zero to this bit has no effect. B i t 76543210 $07 ($27) – – – – – MUX2 MUX1 MUX0 ADMUX Read/Write R R R R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 B i t 76543210 $06 ($26) ADEN ADSC – ADIF ADIE ADPS2 ADPS1 ADPS0 ADCSR Read/Write R/W R/W R R/W R/W R/W R/W R/W I n i t i a l V a l u e 00000000

must be written to this bit. plete interrupt is activated. essential that both registers are read and that ADCL is read before ADCH. Table 27. ADC Prescaler Selections

000 I n v a l i d

82 ATmega103(L)

1. The analog part of the ATmega103(L) and all analog components in the applica-

is connected to the digital ground plane via a single point on the PCB.

1. Keep analog signal paths as short as possible. Make sure analog tracks run over
2. Use the ADC Noise Canceler function to reduce induced noise from the CPU.
3. If some Port F pins are used as digital inputs, it is essential that these do not

switch while a conversion is in progress. Figure 49. ADC Power Connections

ATmega103(L) 0945I–AVR–02/07 Notes: 1. Minimum for AV CC is 2.7V. 2. Maximum for AV CC is 6.0V. ADC DC Characteristics TA = -40°C to 85°C Symbol Parameter Condition Min Typ Max Units Resolution 10 Bits Absolute accuracy VREF = 4V, VCC = 4V ADC clock = 200 kHz 12 L S B Absolute accuracy VREF = 4V, VCC = 4V ADC clock = 1 MHz 4L S B Absolute accuracy VREF = 4V, VCC = 4V ADC clock = 2 MHz 16 LSB Integral Non-linearity VREF > 2V 0.5 LSB Differential Non-linearity VREF > 2V 0.5 LSB Zero Error (Offset) 1L S B Conversion Time 70 280 µs Clock Frequency 50 200 kHz AVCC Analog Supply Voltage V VREF Reference Voltage 2A V CC V RREF Reference Input Resistance 61 0 1 3 k Ω RAIN Analog Input Resistance 100 M Ω

84 ATmega103(L)

internal SRAM as AVR parts do not have an interface to the external SRAM. and WR are active when accessing the external SRAM only. are transparent when G is high. By default, the external SRAM access is a three-cycle scheme as depicted in Figure 51. A becomes a low-order address bus again. Figure 50. External SRAM Connected to the AVR

86 ATmega103(L)

0945I–AVR–02/07 I/O Ports All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without uninten- tionally changing the direction of any other pin with the SBI and CBI instructions. The same applies for changing drive value (if co nfigured as output) or enabling/disabling of pull-up resistors (if configured as input). Port A Port A is an 8-bit bi-directional I/O port with internal pull-ups. Three I/O memory address locations are allocated for Port A, one each for the Data Register – PORTA, $1B($3B), Data Direct ion Register – DDRA, $1A($3A) and the Port A Input Pins – PINA, $19($39). The Port A Input Pins address is read-only, while the Data Register and the Data Direction Register are read/write. All port pins have individually selectable pull-up resistors. The Port A output buffers can sink 20 mA and thus drive LED displays di rectly. When pins PA0 to PA7 are used as inputs and are externally pulled low, they will source current if the internal pull-up resis- tors are activated. The Port A pins have alternate functions re lated to the optional external data SRAM. Port A can be configured to be the multiplexed low-order address/data bus during accesses to the byte. When Port A is set to the alternate function by the SRE (External SRAM Enable) bit in the MCUCR (MCU Control Register), the alternate settings override the Data Direction Register. Port A Data Register – PORTA Port A Data Direction Register – DDRA Port A Input Pins Address – PINA The Port A Input Pins address (PINA) is not a register; this address enables access to the physical value on each Port A pin. When reading PORTA the Port A Data Latch is read and when reading PINA, the logical values present on the pins are read. Port A as General Digital I/O All eight pins in Port A have equal functionality when used as digital I/O pins. PAn, general I/O pin: The DDAn bit in the DDRA Register selects the direction of this pin. If DDAn is set (one), PAn is configured as an output pin. If DDAn is cleared (zero), PAn is configured as an input pin. If PORTAn is set (one) when the pin configured as an input pin, the MOS pull-up resistor is activated. To switch the pull-up resistor off, POR- TAn has to be cleared (zero) or the pin has to be configured as an output pin. The port B i t 76543210 $1B ($3B) PORTA7 PORTA6 PORTA5 PORTA4 PORTA3 PORTA2 PORTA1 PORTA0 PORTA Read/Write R/W R/W R/W R/W R/W R/W R/W R/W I n i t i a l V a l u e 00000000 B i t 76543210 $1A ($3A) DDA7 DDA6 DDA5 DDA4 DDA3 DDA2 DDA1 DDA0 DDRA Read/Write R/W R/W R/W R/W R/W R/W R/W R/W I n i t i a l V a l u e 00000000 B i t 76543210 $19 ($39) PINA7 PINA6 PINA5 PINA4 PI NA3 PINA2 PINA1 PINA0 PINA R e a d / W r i t e RRRRRRRR Initial Value N/A N/A N/A N/A N/A N/A N/A N/A

Figure 53. Port A Schematic Diagrams (Pins PA0 - PA7) Port B Port B is an 8-bit bi-directional I/O port with internal pull-ups. Register and the Data Direction Register are read/write. Table 28. DDAn Effects on Port A Pins 0 1 Input Y es PAn will source current if ext. pulled low.

88 ATmega103(L)

The Port B pins with alternate functions are shown in Table 29. have to be set according to the alternate function description. read and when reading PINB, the logical values present on the pins are read. Port B as General Digital I/O All eight pins in Port B have equal functionality when used as digital I/O pins. Table 29. Port B Pin Alternate Functions

PORTB3 bit. See the description of the SPI port for further details. enabled as a Slave, this pin is configured as an input regardless of the setting of DDB2. PORTB2 bit. See the description of the SPI port for further details. enabled as a Slave, this pin is configured as an input regardless of the setting of DDB1. Table 30. DDBn Effects on Port B Pins

90 ATmega103(L)

PORTB1 bit. See the description of the SPI port for further details. trolled by the PORTB0 bit. See the description of the SPI port for further details. Figure 54. Port B Schematic Diagram (Pin PB0)

92 ATmega103(L)

Figure 57. Port B Schematic Diagram (Pin PB3) Figure 58. Port B Schematic Diagram (Pin PB4)

94 ATmega103(L)

Port C Port C is an 8-bit output port. The Port C pins have alternate functions related to the optional external data SRAM. Port D Port D is an 8-bit bi-directional I/O port with internal pull-up resistors. Register and the Data Direction Register are read/write. pulled low will source current if the pull-up resistors are activated. Some Port D pins have alternate functions as shown in Table 31. Table 31. Port D Pin Alternate Functions

ATmega103(L) 0945I–AVR–02/07 When the pins are used for the alternate function, the DDRD and PORTD Registers have to be set according to the alternate function description. Port D Data Register – PORTD Port D Data Direction Register – DDRD Port D Input Pins Address – PIND The Port D Input Pins address (PIND) is not a register, and this address enables access to the physical value on each Port D pin. When reading PORTD, the Port D Data Latch is read, and when reading PIND, the logical values present on the pins are read. Port D as General Digital I/O PDn, General I/O pin: The DDDn bit in the DDRD Register se lects the direction of this pin. If DDDn is set (one), PDn is configured as an output pin. If DDDn is cleared (zero), PDn is configured as an input pin. If PDn is set (one) when configured as an input pin the MOS pull-up resistor is activated. To switch the pull-up resistor off the PDn has to be cleared (zero) or the pin has to be configured as an output pin. The port pins are tri- stated when a reset condition becomes active, even if the clock is not running. Note: n: 7,6...0, pin number Alternate Functions of Port D The alternate pin functions of Port D are: I N T 0..INT3 – Port D, Bits 0..3 External Interrupt sources 0 - 3. The PD0 - PD3 pins can serve as external active low interrupt sources to the MCU. The internal pull-up MOS resistors can be activated as described above. See the interrupt description for further details, and how to enable the sources. B i t 76543210 $12 PORTD7 PORTD6 PORTD5 PORTD4 PORTD3 PORTD2 PORTD1 PORTD0 PORTD Read/Write R/W R/W R/W R/W R/W R/W R/W R/W I n i t i a l V a l u e 00000000 B i t 76543210 $11 DDD7 DDD6 DDD5 DDD4 DDD3 DDD2 DDD1 DDD0 DDRD Read/Write R/W R/W R/W R/W R/W R/W R/W R/W I n i t i a l V a l u e 00000000 B i t 76543210 $10 PIND7 PIND6 PIND5 PIND4 PI ND3 PIND2 PIND1 PIND0 PIND R e a d / W r i t e RRRRRRRR Initial Value N/A N/A N/A N/A N/A N/A N/A N/ATable 32. DDDn Bits on Port D Pins DDDn PORTDn I/O Pull-up Comment 0 0 Input No Tri-state (high-Z) 0 1 Input Y es PDn will source current if ext. pulled low. 1 0 Output No Push-pull Zero Output 1 1 Output No Push-pull One Output

96 ATmega103(L)

serve this function. See the Timer/Counter1 description on how to operate this function. The internal pull-up MOS resistor can be activated as described above. T1, Timer/Counter1 counter source. See the Timer description for further details. T2, Timer/Counter2 counter source. See the Timer description for further details. Figure 62. Port D Schematic Diagram (Pins PD0, PD1, PD2 and PD3)

98 ATmega103(L)

Figure 65. Port D Schematic Diagram (Pins PD6 and PD7) Port E Port E is an 8-bit bi-directional I/O port with internal pull-up resistors. Register and the Data Direction Register are read/write. pulled low will source current if the pull-up resistors are activated. All Port E pins have alternate functions as shown in Table 33. have to be set according to the alternate function description. Table 33. Port E Pin Alternate Functions

ATmega103(L) 0945I–AVR–02/07 Port E Data Register – PORTE Port E Data Direction Register – DDRE Port E Input Pins Address – PINE The Port E Input Pins address (PINE) is not a register; this address enables access to the physical value on each Port E pin. When reading PORTE, the Port E Data Latch is read and when reading PINE, the logical values present on the pins are read. Port E as General Digital I/O PEn, general I/O pin: The DDEn bit in the DDRE Register selects the direction of this pin. If DDEn is set (one), PEn is configured as an output pin. If DDEn is cleared (zero), PEn is configured as an input pin. If PEn is set (one) when configured as an input pin, the MOS pull-up resistor is activated. To switch the pull-up resistor off, the PEn has to be cleared (zero) or the pin has to be configured as an output pin.The port pins are tri- stated when a reset condition becomes active, even if the clock is not running. Note: n: 7,6...0, pin number Alternate Functions of Port E The alternate pin functions of Port E are:  PDI/RXD – Port E, Bit 0 PDI, Serial Programming Data Input. During Serial Program downloading, this pin is used as data input line for the ATmega103(L). RXD, UART Receive Pin. Receive Data (Data input pin for the UART). When the UART Receiver is enabled, this pin is configured as an input regardless of the value of DDRD0. When the UART forces this pin to be an input, a logical “1” in PORTD0 will turn on the internal pull-up.  PDO/TXD – Port E, Bit 1 PDO, Serial Programming Data Output. During Serial Program downloading, this pin is used as data output line for the ATmega103(L). B i t 76543210 $03 ($23) PORTE7 PORTE6 PORTE5 PORTE4 PORTE3 PORTE2 PORTE1 PORTE0 PORTE Read/Write R/W R/W R/W R/W R/W R/W R/W R/W I n i t i a l V a l u e 00000000 B i t 76543210 $02 ($22) DDE7 DDE6 DDE5 DDE4 DDE3 DDE2 DDE1 DDE0 DDRE Read/Write R/W R/W R/W R/W R/W R/W R/W R/W I n i t i a l V a l u e 00000000 B i t 76543210 $01 ($21) PINE7 PINE6 PINE5 PINE4 PINE3 PINE2 PINE1 PINE0 PINE R e a d / W r i t e RRRRRRRR Initial Value N/A N/A N/A N/A N/A N/A N/A N/ATable 34. DDEn Bits on Port E Pins DDEn PORTEn I/O Pull-up Comment 0 0 Input No Tri-state (high-Z) 0 1 Input Y es PDn will source current if ext. pulled low. 1 0 Output No Push-pull Zero Output 1 1 Output No Push-pull One Output

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input of the analog comparator. input of the analog comparator. Figure 66. Port E Schematic Diagram (Pin PE0)

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Figure 69. Port E Schematic Diagram (Pin PE3) Figure 70. Port E Schematic Diagram (Pins PE4, PE5, PE6 and PE7)

Port F Port F is an 8-bit input port. One I/O memory location is allocated for Port F, the Port F Input Pins – PINF, $00 ($20). analog inputs, at the same time. the physical value on each Port F pin. Figure 71. Port F Schematic Diagram (Pins PF7 - PF0)

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bits can only be erased to “1” with the Chip Erase command. bits before programming the Lock bits. Fuse Bits The ATmega103(L) has four Fuse bits, SPIEN, SUT1..0 and EESAVE. cannot be programmed if any of the Lock bits are programmed. The status of the Fuse bits is not affected by Chip Erase.

1. $000: $1E (indicates manufactured by Atmel)
2. $001: $97 (indicates 128K bytes Flash memory)
3. $002: $01 (indicates ATmega103 when signature byte $001 is $97)

and 4K bytes of EEPROM Data memory. memory arrays in the erased state (i.e., contents = $FF) and ready to be programmed. This device supports a Parallel Programming mode and a Serial Programming mode. ATmega103(L) inside the user’s system. Table 35. Lock Bit Protection Modes 1 1 1 No memory lock features enabled. 3 0 0 Same as mode 2, and verify is also disabled.

EEPROM write instruction in the Serial Programming mode. During programming, the supply voltage must be in accordance with Table 36. assumed to be at least 500 ns unless otherwise noted. described in Table 37 are referenced by pin names. tive pulse. The bit coding is shown in Table 38. Figure 72. Parallel Programming Table 36. Supply Voltage during Programming

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Table 37. Pin Name Mapping Table 38. XA1 and XA0 Coding Table 39. Command Byte Bit Coding

1. Apply supply voltage according to Table 36, between V CC and GND.
2. Set RESET and BS1 pins to “0” and wait at least 100 ns.
3. Apply 11.5 - 12.5V to RESET . Any activity on BS1 within 100 ns after +12V has

been applied to RESET will cause the device to fail entering Programming mode.

1. Set XA1, XA0 to “10”. This enables command loading.
2. Set DATA to “1000 0000”. This is the command for Chip Erase.
3. Give XTAL1 a positive pulse. This loads the command.

tWLWH_CE value. Chip Erase does not generate any activity on the RDY/BSY pin. A: Load Command “Write Flash”.

1. Set XA1, XA0 to “10”. This enables command loading.
2. Set DATA to “0001 0000”. This is the command for Write Flash.
3. Give XTAL1 a positive pulse. This loads the command.
4. Set XA1, XA0 to “00”. This enables address loading.
5. Set BS1 to “0”. This selects low address.
6. Set DATA = Address Low Byte ($00 - $FF)
7. Give XTAL1 a positive pulse. This loads the address Low Byte.
8. Set BS1 to “0”. This selects low data.
9. Set XA1, XA0 to “01”. This enables data loading.
10. Set DATA = Data Low Byte ($00 - $FF).
11. Give XTAL1 a positive pulse. This loads the data byte.
12. Give PAGEL a positive pulse. This latches the data Low Byte.

Table 40. Minimum WR

108 ATmega103(L)

1. Set BS1 to “1”. This selects high data.
2. Set XA1, XA0 to “01”. This enables data loading.
3. Set DATA = Data High Byte ($00 - $FF).
4. Give XTAL1 a positive pulse. This loads the data High Byte.
5. Give PAGEL a positive pulse. This latches the data High Byte.

G: Repeat B through F 128 times to fill the page buffer.

1. Set XA1, XA0 to “00”. This enables address loading.
2. Set BS1 to “1”. This selects high address.
3. Set DATA = Address High Byte ($00 - $FF).
4. Give XTAL1 a positive pulse. This loads the address High Byte.

a negative pulse. This starts programming of the entire page of data.

1. Wait until RDY/BSY goes high.
2. Set XA1, XA0 to “10”. This enables command loading.
3. Set DATA = “0000 0000”. This is the command for No Operation.
4. Give XTAL1 a positive pulse. This loads the command and the internal write sig-

K: Repeat A through J 512 times or until all data has been programmed. Figure 73. Programming the Flash Waveforms

Figure 74. Programming the Flash Waveforms (Continued)

1. H: Load Address High Byte ($00 - $0F).
2. B: Load Address Low Byte ($00 - $FF).
3. E: Load Data Low Byte ($00 - $FF).
4. Set BS to “0”. This selects low data.
5. Wait until RDY/BSY goes high to program the next byte.

These considerations also apply to Flash, EEPROM and signature bytes reading.

110 ATmega103(L)

Figure 75. Programming the EEPROM Waveforms

1. H: Load Address High Byte ($00 - $FF).
2. B: Load Address Low Byte ($00 - $FF).
3. Set BS to “1”. The Flash word High Byte can now be read at DATA.
4. H: Load Address High Byte ($00 - $0F).
5. B: Load Address ($00 - $FF).
6. C: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit.

ATmega103(L) 0945I–AVR–02/07 Bit 1 = SUT1 Fuse bit Bit 0 = SUT0 Fuse bit Bit 7, 6, 4, 2 = “1”. These bits are reserved and should be left unprogrammed (“1”). 3. Give WR a tWLWH_PFB wide negative pulse to execute the programming. tWLWH_PFB is found in Table 41. Programming the Fuse bits does not generate any activity on the RDY/BSY pin. Programming the Lock Bits The algorithm for programming the Lock bits is as follows (refer to “Programming the Flash” on page 107 for details on command and data loading): 1. A: Load Command “0010 0000”. 2. D: Load Data Low Byte. Bit n = “0” programs the Lock bit. Bit 2 = Lock Bit2 Bit 1 = Lock Bit1 Bit 7 - 3, 0 = “1”. These bits are reserved and should be left unprogrammed (“1”). 3. L: Write Data Low Byte. The Lock bits can only be cleared by executing Chip Erase. Reading the Fuse and Lock Bits The algorithm for reading the Fuse and Lock bits is as follows (refer to “Programming the Flash” on page 107 for details on command loading): 1. A: Load Command “0000 0100”. 2. Set OE to “0”, and BS to “0”. The status of the Fuse bits can now be read at DATA (“0” means programmed). Bit 5 = SPIEN Fuse bit Bit 3 = EESAVE Fuse bit Bit 1 = SUT1 Fuse bit Bit 0 = SUT0 Fuse bit Set OE to “0”, and BS to “1”. The status of the Lock bits can now be read at DATA (“0” means programmed). Bit 2 = Lock Bit2 Bit 1 = Lock Bit1 3. Set OE to “1”. Reading the Signature Bytes The algorithm for reading the signature bytes is as follows (refer to “Programming the Flash” on page 107 for details on command and address loading): 1. A: Load Command “0000 1000”. 2. C: Load Address Low Byte ($00 - $02). Set OE to “0”, and BS to “0”. The selected signature byte can now be read at DATA. 3. Set OE to “1”.

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Figure 76. Parallel Programming Timing Notes: 1. Use t WLWH_CE for Chip Erase and tWLWH_PFB for programming the fuse bits.

1. If t WLWH is held longer than tWLRH, no RDY/BSY pulse will be seen.

Table 41. Parallel Programming Characteristics TA = 25°C ± 10%, VCC = 5V ± 10%

program/erase instructions can be executed. $FFFF for Program memory and $0000 to $0FFF for EEPROM memory. Figure 77. Serial Programming

1. Power-up sequence: Apply power between V

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0945I–AVR–02/07 As an alternative to using the RESET signal, PEN can be held low during Power- on Reset while SCK is set to “0”. In this case, only the PEN value at Power-on Reset is important. If a crystal is not connected across pins XTAL1 and XTAL2, apply a clock signal to the XTAL1 pin. If the programmer cannot guarantee that SCK is held low during power-up, the PEN method cannot be used. The device must be powered down in order to commence normal operation when using this method. 2. Wait for at least 20 ms and enable serial programming by sending the Program- ming Enable serial instruction to pin PE0(PDI/RXD). 3. The serial programming instructions will not work if the communication is out of synchronization. When in sync, the second byte ($53) will echo back when issu- ing the third byte of the Programming Enable instruction. Whether the echo is correct or not, all four bytes of the instruction must be transmitted. If the $53 did not echo back, give SCK a positive pulse and issue a new Programming Enable instruction. If the $53 is not seen within 32 attempts, there is no functional device connected. 4. If a chip erase is performed (must be done to erase the Flash), wait at least (2 x t WD_FLASH), give RESET a positive pulse of at least two XTAL1 cycles duration after SCK has been set to “0”, and start over from step 2. 5. The Flash is programmed one page at a time. The memory page is loaded one byte at a time by supplying the 7 LSB of the address and data together with the Load Program Memory Page instruction. The Program Memory Page is stored by loading the Write Program Memory Page instruction with the 9 MSB of the address. The next page can be written after t WD_FLASH, i.e., writing 256 bytes takes tWD_FLASH. Accessing the serial programming interface before the Flash write operation completes can result in incorrect programming. 6. The EEPROM array is programmed one byte at a time by supplying the address and data together with the appropriate Write instruction. An EEPROM memory location is first automatically erased before new data is written. If polling is not used, the user must wait at least tWD_EEPROM before issuing the next byte. (Please refer to Table 42.) 7. Any memory location can be verified by using the Read instruction, which returns the content at the selected address at serial output PE1(PDO/TXD). 8. At the end of the programming session, RESET can be set high to commence normal operation. 9. Power-off sequence (if needed): Set XTAL1 to “0” (if a crystal is not used). Set RESET to “1”. Turn VCC power off. Table 42 shows the actual delays used in this section. Please note: The MISO pin is not high-Z during serial programming. Data Polling for the EEPROM When a new EEPROM byte has been written and is being programmed into the EEPROM, reading the address location being pr ogrammed will first give the value P1 (please refer to Table 43) until the auto-erase is finished, and then the value P2. At the time the device is ready for a new EEPROM byte, the programmed value will read correctly. This is used to determine when the next byte can be written. This will not work for the values P1 and P2, so when programming these values, the user will have to wait for at least the prescribed time tWD_EEPROM (please refer to Table 42) before programming the next byte. As a chip-erased device contains $FF in all locations, programming of addresses that are meant to contain $FF can be skipped. This does not apply if the EEPROM is reprogrammed without chip erasing the device.

Data polling is not implemented for the Flash. Note: See Errata sheet for latest information. Table 42. Minimum Wait Delay before Writing the Next Flash or EEPROM Location Table 43. Read Back Value during EEPROM Polling

116 ATmega103(L)

Table 44. Serial Programming Instruction Set Chip Erase 1010 1100 100x xxxx xxxx xxxx xxxx xxxx Chip erase EEPROM and Flash. Program memory at word address a:b. memory page at word address b. Read Signature Byte 0011 0000 xxxx xxxx xxxx xx bb oooo oooo Read signature byte o at address b.

Figure 78. Serial Programming Waveforms

118 ATmega103(L)

0945I–AVR–02/07

Electrical Characteristics

Absolute Maximum Ratings* Maximum Ratings” may cause permanent dam- age to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Voltage on Any Pin except RESET DC Current DC Characteristics TA = -40°C to 85°C, VCC = 2.7V to 3.6V and 4.0V to 5.5V (unless otherwise noted) Symbol Parameter Condition Min Typ Max Units VIL Input Low Voltage Except (XTAL) -0.5 0.3 V CC (1) V VIL1 Input Low Voltage XTAL -0.5 0.2 V CC - 0.1(1) V VIH Input High Voltage Except (XTAL, RESET )0 . 6 V CC (2) VCC + 0.5 V VIH1 Input High Voltage XTAL 0.7 V CC (2) VCC + 0.5 V VIH2 Input High Voltage RESET 0.85 V CC (2) VCC + 0.5 V VOL Output Low Voltage(3) Ports A, B, C, D, E IOL = 20 mA, VCC = 5V IOL = 10 mA, VCC = 3V 0.6 0.5 V V VOH Output High Voltage(4) Ports A, B, C, D, E IOH = -3 mA, VCC = 5V IOH = -1.5 mA, VCC = 3V 4.3 2.2 V V IIL Input Leakage Current I/O Pin VCC = 6V, Pin Low (absolute value) 8.0 µA IIH Input Leakage Current I/O Pin VCC = 6V, Pin High (absolute value) 8.0 µA RRST Reset Pull-up 100 500 k Ω RI/O I/O Pin Pull-up 35 120 k Ω ICC Power Supply Current Active 4 MHz, VCC = 3V 5.0 mA Idle 4 MHz, VCC = 3V 2.0 mA Power-down(5), VCC = 3V WDT Enabled 40.0 µA Power-down(5), VCC = 3V WDT Disabled 25.0 µA Power-save(5), VCC = 3V WDT Disabled 35.0 µA

ATmega103(L) 0945I–AVR–02/07 Notes: 1. “Max” means the highest value where the pin is guaranteed to be read as low. 2. “Min” means the lowest value where t he pin is guaranteed to be read as high. 3. Although each I/O port can sink more than the test conditions (20 mA at V CC = 5V, 10 mA at VCC = 3V) under steady-state conditions (non-transient), the following must be observed: 1] The sum of all IOL, for all ports, should not exceed 400 mA. 2] The sum of all IOL, for ports A0 - A7, ALE, C3 - C7 should not exceed 100 mA. 3] The sum of all IOL, for ports C0 - C2, RD, WR, D0 - D7, XTAL2 should not exceed 100 mA. 4] The sum of all IOL, for ports B0 - B7, should not exceed 100 mA. 5] The sum of all IOL, for ports E0 - E7, should not exceed 100 mA. If IOL exceeds the test condition, V OL may exceed the related specification. Pi ns are not guaranteed to sink current greater than the listed test condition. 4. Although each I/O port can source more than the test conditions (3 mA at V CC = 5V, 1.5 mA at VCC = 3V) under steady-state conditions (non-transient), the following must be observed: 1] The sum of all IOH, for all ports, should not exceed 400 mA. 2] The sum of all IOH, for ports A0 - A7, ALE, C3 - C7 should not exceed 100 mA. 3] The sum of all IOH, for ports C0 - C2, RD, WR, D0 - D7, XTAL2 should not exceed 100 mA. 4] The sum of all IOH, for ports B0 - B7, should not exceed 100 mA. 5] The sum of all IOH, for ports E0 - E7, should not exceed 100 mA. If I OH exceeds the test condition, V OH may exceed the related specification. Pins are not guaranteed to source current greater than the listed test condition. 5. Minimum V CC for Power-down is 2V. VACIO Analog Comp Input Offset V VCC = 5V VIN = VCC/2 40 mV IACLK Analog Comp Input Leakage A VCC = 5V VIN = VCC/2 -50 50 nA tACPD Analog Comparator Propagation Delay VCC = 2.7V VCC = 4.0V 750 500 ns DC Characteristics (Continued) TA = -40°C to 85°C, VCC = 2.7V to 3.6V and 4.0V to 5.5V (unless otherwise noted) Symbol Parameter Condition Min Typ Max Units

120 ATmega103(L)

Notes: 1. This assumes 50% clock duty cycl e. The half period is actually the high time of the external clock, XTAL1.

1. This assumes 50% clock duty cycle. The half period is actually the low time of the external clock, XTAL1.

Table 45. External Data Memory Characteristics, 4.0 - 6.0 Volts, No Wait State

6 MHz Oscillator Variable Oscillator

Table 46. External Data Memory Characteristics, 4.0 - 6.0 Volts, 1 Cycle Wait State

Notes: 1. This assumes 50% clock duty cycl e. The half period is actually the high time of the external clock, XTAL1.

1. This assumes 50% clock duty cycle. The half period is actually the low time of the external clock, XTAL1.

Table 47. External Data Memory Characteristics, 2.7 - 3.6 Volts, No Wait State

4 MHz Oscillator Variable Oscillator

Table 48. External Data Memory Characteristics, 2.7 - 3.6 Volts, 1 Cycle Wait State

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Figure 79. External RAM Timing Figure 80. External Clock Drive Waveforms influences the timing for the external Data memory. Note: Clock cycle T3 is only present when external SRAM Wait State is enabled. Table 49. External Clock Drive

externally. A sine wave generator with rail-to-rail output is used as clock source. The power consumption in Power-down mode is independent of clock selection. ambient temperature. The dominating factors are operating voltage and frequency. teed to function properly at frequencies higher than the ordering code indicates. ferential current drawn by the Watchdog Timer. Figure 81. Active Supply Current vs. Frequency

124 ATmega103(L)

Figure 82. Active Supply Current vs. VCC Figure 83. Idle Supply Current vs. Frequency

126 ATmega103(L)

Figure 86. Power-down Supply Current vs. VCC Figure 87. Power-save Supply Current vs. VCC

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Figure 90. Analog Comparator Offset Voltage vs. Common Mode Voltage Figure 91. Analog Comparator Input Leakage Current 0 0.5 1 1.5 2 2.5 3ANALOG COMPARATOR OFFSET VOLTAGE vs.

130 ATmega103(L)

Figure 94. Pull-up Resistor Current vs. Input Voltage Figure 95. I/O Pin Sink Current vs. Output Voltage

132 ATmega103(L)

Figure 98. I/O Pin Source Current vs. Output Voltage Figure 99. I/O Pin Input Threshold Voltage vs. VCC

Figure 100. I/O Pin Input Hysteresis vs. VCC

134 ATmega103(L)

0945I–AVR–02/07 Note: For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. Some of the Status Flags are cleared by writing a logical “1” to them. Note that the CBI and SBI instruc- tions will operate on all bits in the I/O Register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions work with registers $00 to $1F only. Register Summary Address Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Page $3F ($5F) SREG I T H S V N Z C page 20 $3E ($5E) SPH SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 page 21 $3D ($5D) SPL SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 page 21 $3C ($5C) XDIV XDIVEN XDIV6 XDIV5 XDIV4 XDIV3 XDIV2 XDIV1 XDIV0 page 23 $3B ($5B) RAMPZ – – – – – – –R A M P Z 0 page 22 $3A ($5A) EICR ISC71 ISC70 ISC61 ISC60 ISC51 ISC50 ISC41 ISC40 page 31 $39 ($59) EIMSK INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0 page 30 $38 ($58) EIFR INTF7 INTF6 INTF5 INTF4 – – – – page 31 $37 ($57) TIMSK OCIE2 TOIE2 TIC IE1 OCIE1A OCIE1B TOIE1 OCIE0 TOIE0 page 33 $36 ($56) TIFR OCF2 TOV2 ICF1 OCF1A OCF1B TOV1 OCF0 TOV0 page 35 $35 ($55) MCUCR SRE SRW SE SM1 SM0 – – – page 22 $34 ($54) MCUSR – – – – – – EXTRF PORF page 29 $33 ($53) TCCR0 – PWM0 COM01 COM00 CTC0 CS02 CS01 CS00 page 41 $32 ($52) TCNT0 Timer/Counter0 (8-bit) page 42 $31 ($51) OCR0 Timer/Counter0 Output Compare Register page 43 $30 ($50) ASSR – – – – AS0 TCN0UB OCR0UB TCR0UB page 44 $2F ($4F) TCCR1A COM1A1 COM1A0 COM1B1 COM1B0 – –P W M 1 1 P W M 1 0 page 49 $2E ($4E) TCCR1B ICNC1 ICES1 – – CTC1 CS12 CS11 CS10 page 50 $2D ($4D) TCNT1H Timer/Counter1 – Counter Register High Byte page 51 $2C ($4C) TCNT1L Timer/Counter1 – Counter Register Low Byte page 51 $2B ($4B) OCR1AH Timer/Counter1 – Output Compare Register A High Byte page 52 $2A ($4A) OCR1AL Timer/Counter1 – Output Compare Register A Low Byte page 52 $29 ($49) OCR1BH Timer/Counter1 – Output Compare Register B High Byte page 52 $28 ($48) OCR1BL Timer/Counter1 – Output Compare Register B Low Byte page 52 $27 ($47) ICR1H Timer/Counter1 – Input Capture Register High Byte page 52 $26 ($46) ICR1L Timer/Counter1 – Input Capture Register Low Byte page 52 $25 ($45) TCCR2 – PWM2 COM21 COM20 CTC2 CS22 CS21 CS20 page 41 $24 ($44) TCNT2 Timer/Counter2 (8-bit) page 42 $23 ($43) OCR2 Timer/Counter2 Output Compare Register page 43 $21 ($47) WDTCR – – – WDTOE WDE WDP2 WDP1 WDP0 page 55 $1F ($3F) EEARH – – – – EEAR11 EEAR10 EEAR9 EEAR8 page 57 $1E ($3E) EEARL EEPROM Address Register L page 57 $1D ($3D) EEDR EEPROM Data Register page 57 $1C ($3C) EECR – – – – EERIE EEMWE EEWE EERE page 57 $1B ($3B) PORTA PORTA7 PORTA6 PORTA5 PORTA4 PORTA3 PORTA2 PORTA1 PORTA0 page 86 $1A ($3A) DDRA DDA7 DDA6 DDA5 DDA4 DDA3 DDA2 DDA1 DDA0 page 86 $19 ($39) PINA PINA7 PINA6 PINA5 PINA4 PINA3 PINA2 PINA1 PINA0 page 86 $18 ($38) PORTB PORTB7 PORTB6 PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 page 88 $17 ($37) DDRB DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 page 88 $16 ($36) PINB PINB7 PINB6 PINB5 PINB4 PINB3 PINB2 PINB1 PINB0 page 88 $15 ($35) PORTC PORTC7 PORTC6 PORTC5 PORTC4 PORTC3 PORTC2 PORTC1 PORTC0 page 94 $12 ($32) PORTD PORTD7 PORTD6 PORTD5 PORTD4 PORTD3 PORTD2 PORTD1 PORTD0 page 95 $11 ($31) DDRD DDD7 DDD6 DDD5 DDD4 DDD3 DDD2 DDD1 DDD0 page 95 $10 ($30) PIND PIND7 PIND6 PIND5 PIND4 PIND3 PIND2 PIND1 PIND0 page 95 $0F ($2F) SPDR SPI Data Register page 65 $0E ($2E) SPSR SPIF WCOL – – – – – – page 63 $0D ($2D) SPCR SPIE SPE DORD MSTR CPOL CPHA SPR1 SPR0 page 62 $0C ($2C) UDR UART I/O Data Register page 70 $0B ($2B) USR RXC TXC UDRE FE OR – – – page 70 $0A ($2A) UCR RXCIE TXCIE UDRIE RXEN TXEN CHR9 RXB8 TXB8 page 71 $09 ($29) UBRR UART Baud Rate Register page 74 $08 ($28) ACSR ACD – ACO ACI ACIE ACIC ACIS1 ACIS0 page 75 $07 ($27) ADMUX – – – – – MUX2 MUX1 MUX0 page 80 $06 ($26) ADCSR ADEN ADSC – ADIF ADIE ADPS2 ADPS1 ADPS0 page 80 $05 ($25) ADCH – – – – – – ADC9 ADC8 page 81 $04 ($24) ADCL ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADC1 ADC0 page 81 $03 ($23) PORTE PORTE7 PORTE6 PORTE5 PORTE4 PORTE3 PORTE2 PORTE1 PORTE0 page 99 $02 ($22) DDRE DDE7 DDE6 DDE5 DDE4 DDE3 DDE2 DDE1 DDE0 page 99 $01 ($21) PINE PINE7 PINE6 PINE5 PINE4 PINE3 PINE2 PINE1 PINE0 page 99 $00 ($20) PINF PINF7 PINF6 PINF5 PINF4 PINF3 PINF2 PINF1 PINF0 page 103

ATmega103(L) 0945I–AVR–02/07 Instruction Set Summary Mnemonic Operands Description Operation Flags # Clocks ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd, Rr Add Two Registers Rd ← Rd + Rr Z,C,N,V,H 1 ADC Rd, Rr Add with Carry Two Registers Rd ← Rd + Rr + C Z,C,N,V,H 1 ADIW Rdl, K Add Immediate to Word Rdh:Rdl ← Rdh:Rdl + K Z,C,N,V,S 2 SUB Rd, Rr Subtract Two Registers Rd ← Rd - Rr Z,C,N,V,H 1 SUBI Rd, K Subtract Constant from Register Rd ← Rd - K Z,C,N,V,H 1 SBC Rd, Rr Subtract with Carry Two Registers Rd ← Rd - Rr - C Z,C,N,V,H 1 SBCI Rd, K Subtract with Carry Constant from Reg. Rd ← Rd - K - C Z,C,N,V,H 1 SBIW Rdl, K Subtract Immediate from Word Rdh:Rdl ← Rdh:Rdl - K Z,C,N,V,S 2 AND Rd, Rr Logical AND Registers Rd ← Rd • Rr Z,N,V 1 ANDI Rd, K Logical AND Register and Constant Rd ← Rd • K Z,N,V 1 OR Rd, Rr Logical OR Registers Rd ← Rd v Rr Z,N,V 1 ORI Rd, K Logical OR Register and Constant Rd ← Rd v K Z,N,V 1 EOR Rd, Rr Exclusive OR Registers Rd ← Rd ⊕ Rr Z,N,V 1 COM Rd One’s Complement Rd ← $FF - Rd Z,C,N,V 1 NEG Rd Two’s Complement Rd ← $00 - Rd Z,C,N,V,H 1 SBR Rd, K Set Bit(s) in Register Rd ← Rd v K Z,N,V 1 CBR Rd, K Clear Bit(s) in Register Rd ← Rd • ($FF - K) Z,N,V 1 INC Rd Increment Rd ← Rd + 1 Z,N,V 1 DEC Rd Decrement Rd ← Rd - 1 Z,N,V 1 TST Rd Test for Zero or Minus Rd ← Rd • Rd Z,N,V 1 CLR Rd Clear Register Rd ← Rd ⊕ Rd Z,N,V 1 SER Rd Set Register Rd ← $FF None 1 BRANCH INSTRUCTIONS RJMP k Relative Jump PC ← PC + k + 1 None 2 IJMP Indirect Jump to (Z) PC ← Z None 2 JMP k Direct Jump PC ← kN o n e 3 RCALL k Relative Subroutine Call PC ← PC + k + 1 None 3 ICALL Indirect Call to (Z) PC ← ZN o n e 3 CALL k Direct Subroutine Call PC ← kN o n e 4 RET Subroutine Return PC ← STACK None 4 RETI Interrupt Return PC ← STACK I 4 CPSE Rd, Rr Compare, Skip if Equal if (Rd = Rr) PC ← PC + 2 or 3 None 1/2/3 CP Rd, Rr Compare Rd - Rr Z,N,V,C,H 1 CPC Rd, Rr Compare with Carry Rd - Rr - C Z,N,V,C,H 1 CPI Rd, K Compare Register with Immediate Rd - K Z,N,V,C,H 1 SBRC Rr, b Skip if Bit in Register Cleared if (Rr(b) = 0) PC ← PC + 2 or 3 None 1/2/3 SBRS Rr, b Skip if Bit in Register is Set if (Rr(b) = 1) PC ← PC + 2 or 3 None 1/2/3 SBIC P, b Skip if Bit in I/O Register Cleared if (P(b) = 0) PC ← PC + 2 or 3 None 1/2/3 SBIS P, b Skip if Bit in I/O Register is Set if (P(b) = 1) PC ← PC + 2 or 3 None 1/2/3 BRBS s, k Branch if Status Flag Set if (SREG(s) = 1) then PC ← PC + k + 1 None 1/2 BRBC s, k Branch if Status Flag Cleared if (SREG(s) = 0) then PC ← PC + k + 1 None 1/2 BREQ k Branch if Equal if (Z = 1) then PC ← PC + k + 1 None 1/2 BRNE k Branch if Not Equal if (Z = 0) then PC ← PC + k + 1 None 1/2 BRCS k Branch if Carry Set if (C = 1) then PC ← PC + k + 1 None 1/2 BRCC k Branch if Carry Cleared if (C = 0) then PC ← PC + k + 1 None 1/2 BRSH k Branch if Same or Higher if (C = 0) then PC ← PC + k + 1 None 1/2 BRLO k Branch if Lower if (C = 1) then PC ← PC + k + 1 None 1/2 BRMI k Branch if Minus if (N = 1) then PC ← PC + k + 1 None 1/2 BRPL k Branch if Plus if (N = 0) then PC ← PC + k + 1 None 1/2 BRGE k Branch if Greater or Equal, Signed if (N ⊕ V = 0) then PC ← PC + k + 1 None 1/2 BRLT k Branch if Less Than Zero, Signed if (N ⊕ V = 1) then PC ← PC + k + 1 None 1/2 BRHS k Branch if Half-carry Flag Set if (H = 1) then PC ← PC + k + 1 None 1/2 BRHC k Branch if Half-carry Flag Cleared if (H = 0) then PC ← PC + k + 1 None 1/2 BRTS k Branch if T-flag Set if (T = 1) then PC ← PC + k + 1 None 1/2 BRTC k Branch if T-flag Cleared if (T = 0) then PC ← PC + k + 1 None 1/2 BRVS k Branch if Overflow Flag is Set if (V = 1) then PC ← PC + k + 1 None 1/2 BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC ← PC + k + 1 None 1/2 BRIE k Branch if Interrupt Enabled if (I = 1) then PC ← PC + k + 1 None 1/2 BRID k Branch if Interrupt Disabled if (I = 0) then PC ← PC + k + 1 None 1/2 DATA TRANSFER INSTRUCTIONS ELPM Extended Load Program Memory R0 ← (Z + RAMPZ) None 3 MOV Rd, Rr Move between Registers Rd ← Rr None 1 LDI Rd, K Load Immediate Rd ← KN o n e 1

136 ATmega103(L)

0945I–AVR–02/07 LD Rd, X Load Indirect Rd ← (X) None 2 LD Rd, X+ Load Indirect and Post-increment Rd ← (X), X ← X + 1 None 2 LD Rd, -X Load Indirect and Pre-decrement X ← X - 1, Rd ← (X) None 2 LD Rd, Y Load Indirect Rd ← (Y) None 2 LD Rd, Y+ Load Indirect and Post-increment Rd ← (Y), Y ← Y + 1 None 2 LD Rd, -Y Load Indirect and Pre-decrement Y ← Y - 1, Rd ← (Y) None 2 LDD Rd, Y+q Load Indirect with Displacement Rd ← (Y + q) None 2 LD Rd, Z Load Indirect Rd ← (Z) None 2 LD Rd, Z+ Load Indirect and Post-increment Rd ← (Z), Z ← Z + 1 None 2 LD Rd, -Z Load Indirect and Pre-decrement Z ← Z - 1, Rd ← (Z) None 2 LDD Rd, Z+q Load Indirect with Displacement Rd ← (Z + q) None 2 LDS Rd, k Load Direct from SRAM Rd ← (k) None 2 ST X, Rr Store Indirect (X) ← Rr None 2 ST X+, Rr Store Indirect and Post-increment (X) ← Rr, X ← X + 1 None 2 ST -X, Rr Store Indirect and Pre-decrement X ← X - 1, (X) ← Rr None 2 ST Y, Rr Store Indirect (Y) ← Rr None 2 ST Y+, Rr Store Indirect and Post-increment (Y) ← Rr, Y ← Y + 1 None 2 ST -Y, Rr Store Indirect and Pre-decrement Y ← Y - 1, (Y) ← Rr None 2 STD Y+q, Rr Store Indirect with Displacement (Y + q) ← Rr None 2 ST Z, Rr Store Indirect (Z) ← Rr None 2 ST Z+, Rr Store Indirect and Post-increment (Z) ← Rr, Z ← Z + 1 None 2 ST -Z, Rr Store Indirect and Pre-decrement Z ← Z - 1, (Z) ← Rr None 2 STD Z+q, Rr Store Indirect with Displacement (Z + q) ← Rr None 2 STS k, Rr Store Direct to SRAM (k) ← Rr None 2 LPM Load Program Memory R0 ← (Z) None 3 IN Rd, P In Port Rd ← PN o n e 1 OUT P, Rr Out Port P ← Rr None 1 PUSH Rr Push Register on Stack STACK ← Rr None 2 POP Rd Pop Register from Stack Rd ← STACK None 2 BIT AND BIT-TEST INSTRUCTIONS SBI P, b Set Bit in I/O Register I/O(P,b) ← 1N o n e 2 CBI P, b Clear Bit in I/O Register I/O(P,b) ← 0N o n e 2 LSL Rd Logical Shift Left Rd(n+1) ← Rd(n), Rd(0) ← 0 Z,C,N,V 1 LSR Rd Logical Shift Right Rd(n) ← Rd(n+1), Rd(7) ← 0 Z,C,N,V 1 ROL Rd Rotate Left through Carry Rd(0) ← C, Rd(n+1) ← Rd(n), C ← Rd(7) Z,C,N,V 1 ROR Rd Rotate Right through Carry Rd(7) ← C, Rd(n) ← Rd(n+1), C ← Rd(0) Z,C,N,V 1 ASR Rd Arithmetic Shift Right Rd(n) ← Rd(n+1), n = 0..6 Z,C,N,V 1 BSET s Flag Set SREG(s) ← 1 SREG(s) 1 BCLR s Flag Clear SREG(s) ← 0 SREG(s) 1 BST Rr, b Bit Store from Register to T T ← Rr(b) T 1 BLD Rd, b Bit Load from T to Register Rd(b) ← TN o n e 1 SEC Set Carry C ← 1C 1 CLC Clear Carry C ← 0C 1 SEN Set Negative Flag N ← 1N 1 CLN Clear Negative Flag N ← 0N 1 SEZ Set Zero Flag Z ← 1Z 1 CLZ Clear Zero Flag Z ← 0Z 1 SEI Global Interrupt Enable I ← 1I 1 CLI Global Interrupt Disable I ← 0I 1 SES Set Signed Test Flag S ← 1S 1 CLS Clear Signed Test Flag S ← 0S 1 SEV Set Two’s Complement Overflow V ← 1V 1 CLV Clear Two’s Complement Overflow V ← 0V 1 SET Set T in SREG T ← 1T 1 CLT Clear T in SREG T ← 0T 1 SEH Set Half-carry Flag in SREG H ← 1H 1 CLH Clear Half-carry Flag in SREG H ← 0H 1 NOP No Operation None 1 SLEEP Sleep (see specific descr. for Sleep function) None 1 WDR Watchdog Reset (see specific descr. for WD Timer) None 1 Instruction Set Summary (Continued) Mnemonic Operands Description Operation Flags # Clocks

ATmega103(L) 0945I–AVR–02/07

Ordering Information

Speed (MHz) Power Supply Ordering Code Package Operation Range 4 2.7 - 3.6V ATmega103L-4AC 64A Commercial (0°C to 70°C) ATmega103L-4AI 64A Industrial (-40°C to 85°C) 6 4.0 - 5.5V ATmega103-6AC 64A Commercial (0°C to 70°C) ATmega103-6AI 64A Industrial (-40°C to 85°C) Package Type 64A 64-lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP)

138 ATmega103(L)

0945I–AVR–02/07 Packaging Information 64A

2325 Orchard Parkway

San Jose, CA 95131 TITLE DRAWING NO. R REV. 64A, 64-lead, 14 x 14 mm Body Size, 1.0 mm Body Thickness, 0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) B64A 10/5/2001 PIN 1 IDENTIFIER 0°~7° PIN 1 L C A1 A2 A D e E1 E B COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE Notes: 1.This package conforms to JEDEC reference MS-026, Variation AEB. 2. Dimensions D1 and E1 do not incl ude mold protrusion. Allowable protr usion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10 mm maxim um. A – – 1.20 A1 0.05 – 0.15 A2 0.95 1.00 1.05 D 15.75 16.00 16.25 D1 13.90 14.00 14.10 Note 2 E 15.75 16.00 16.25 E1 13.90 14.00 14.10 Note 2 B 0.30 – 0.45 C 0.09 – 0.20 L 0.45 – 0.75 e 0. 80 TYP

i ATmega103(L) 0945I–AVR–02/07

ii ATmega103(L) 0945I–AVR–02/07

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