Download PDFATSAM4S-EK ATMEL
Document overview
- Manufacturer or author: Provided By digicamel.com
- PDF pages: 49
Technical content
11139A–ATARM–29-Nov-11 SAM4S-EK Development Board User Guide
1-2 SAM4S-EK Development Board User Guide 11139A–ATARM–29-Nov-11
SAM4S-EK Development Board User Guide 1-1 11139A–ATARM–29-Nov-11 Section 1 Section 2 Section 3 Section 4
1-2 SAM4S-EK Development Board User Guide 11139A–ATARM–29-Nov-11 Section 5 Section 6 Section 7
SAM4S-EK Development Board User Guide 1-1 11139A–ATARM–29-Nov-11 Section 1 Introduction
1.1 SAM4S Evaluation Kit
The SAM4S Evaluation Kit (SAM4S-EK) enables evaluation capabilities and code development of appli- cations running on a SAM4S16 device.
1.2 User Guide
This guide focuses on the SAM4S-EK board as an evaluation platform. It is made up of 6 sections: Section 1 includes references, applicable documents, acronyms and abbreviations. Section 2 describes the kit contents, its main features and specifications. Section 3 provides board specifications. Section 4 describes the development environment. Section 5 provides instructions to power up the SAM4S-EK and describes how to use it. Section 6 describes the hardware resources, default jumper and switch settings, and connectors. Section 7 provides schematics. Section 8 describes the troubleshooting.
1.3 References and Applicable Documents
Table 1-1. References and Applicable Documents Title Comment SAM4S Datasheet http://www.atmel.com/dyn/resources/prod_documents/11100.pdf
SAM4S-EK Development Board User Guide 2-1 11139A–ATARM–29-Nov-11 Section 2 Kit Contents
2.1 Deliverables
The Atmel® SAM4S-EK toolkit contains the following items: Board: – a SAM4S-EK board – a universal input AC/DC power supply with US, Europe and UK plug adapters Cables: – one USB cable – one serial RS232 cable A Welcome Letter Figure 2-1. Unpacked SAM4S-EK Unpack and inspect the kit carefully. Contact your local Atmel distributor, should you have issues con- cerning the contents of the kit.
2-2 SAM4S-EK Development Board User Guide 11139A–ATARM–29-Nov-11
2.2 Electrostatic Warning
The SAM4S-EK board is shipped in a protective anti-static package. The board must not be subjected to high electrostatic potentials. A grounding strap or similar protective device should be worn when han- dling the board. Avoid touching the components or any other metallic element of the board.
SAM4S-EK Development Board User Guide 3-1 11139A–ATARM–29-Nov-11 Section 3 Power Up
3.1 Power up the Board
Unpack the board taking care to avoid electrostatic discharge. Unpack the power supply, select the right power plug adapter corresponding to that of your country, and insert it in the power supply. Connect the power supply DC connector to the board and plug the power supply to an AC power plug. The board LCD should light up and display a welcome page. Then, click or touch icons displayed on the screen and enjoy the demo.
3.2 Sample Code and Technical Support
After boot up, you can run some sample code or your own application on the development kit. You can download sample code and get technical support from Atmel website http://www.atmel.com/dyn/products/tools.asp?category_id=163&family_id=605&subfamily_id=2404 Figure 3-1. Atmel Website for AT91SAM Products
SAM4S-EK Development Board User Guide 4-1 11139A–ATARM–29-Nov-11 Section 4 Evaluation Kit Hardware
4.1 Board Overview
This section introduces the Atmel SAM4S Evaluation Kit design. It introduces system-level concepts, such as power distribution, memory, and interface assignments. The SAM4S-EK board is based on the integration of an ARM ® Cortex®-M3 processor with on-board NAND Flash and a set of popular peripherals. It is designed to provide a high performance processor evaluation solution with high flexibility for various kinds of applications. Figure 4-1. SAM4S-EK Block Diagram
4-2 SAM4S-EK Development Board User Guide 11139A–ATARM–29-Nov-11
4.2 Features List
Here is the list of the main board components and interfaces: SAM4S16 chip LQFP100 package with optional socket footprint 12 MHz crystal 32.768 KHz crystal Optional SMB connector for external system clock input NAND Flash 2.8 inch TFT color LCD display with touch panel and backlight UART port with level shifter circuit USART port with level shifter circuit multiplexed with RS485 port with level shifter circuit Microphone input and mono/stereo headphone jack output SD/MMC interface Reset button: NRST User buttons: Left and Right QTouch® buttons: Up, Down, Left, Right, Valid and Slider Full Speed USB device port JTAG/ICE port On-board power regulation Two user LEDs Power LED BNC connector for ADC input BNC connector for DAC output User potentiometer connected to the ADC input ZigBEE connector 2x32 bit PIO connection interfaces (PIOA, PIOC) and 1x16 bit PIO connection interface (PIOB)
4.3 Function Blocks
4.3.1 Processor
The SAM4S-EK is equipped with a SAM4S16 device in LQFP100 package.
4.3.2 Memory
The SAM4S16 chip embeds: 1024 Kbytes of embedded Flash 128 Kbytes of embedded SRAM 16 Kbytes of ROM with embedded BootLoader routines (UART, USB) and In-Application Programming functions (IAP) routines.
SAM4S-EK Development Board User Guide 4-3 11139A–ATARM–29-Nov-11 The SAM4S features an External Bus Interface (EBI) that permits interfacing to a broad range of external memories and virtually to any parallel peripheral. The SAM4S-EK board is equipped with a memory device connected to the SAM4 EBI: One NAND Flash MT29F2G08ABAEA. Figure 4-2. NAND Flash NCS0 chip select signal is used for NAND Flash chip selection. Furthermore, a dedicated jumper (JP9) can disconnect it from the on-board memories, thereby letting NCS0 free for other custom purpose.
4.3.3 Clock Circuitry
The clock generator of a SAM4S microcontroller is made up of: A Low Power 32.768 Hz Slow Clock Oscillator with bypass mode. A 3 to 20 MHz Crystal Oscillator, which can be bypassed (12 MHz needed in case of USB). A factory programmed fast internal RC Oscillator. 3 output frequencies can be selected: 4 (default value), 8 or 12 MHz. A 60 to 130 MHz PLL (PLLB) providing a clock for the USB Full Speed Controller. A 60 to 130 MHz programmable PLL (PLLA), capable to provide the clock MCK to the processor and to the peripherals. The input frequency of PLLA is from 7.5 and 20 MHz. The SAM4S-EK board is equipped with one 12 MHz crystal, optional Piezoelectric Ceramic Resonator 12 Mhz (Murata ref. CSTCE12M0G15L99-R0), one 32.768 Hz crystal and an external clock input con- nector (optional, not populated by default). Figure 4-3. External Clock Source MT29F2G08ABAEA NAND FLASH PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PC10 PC9 PC16 PC17 PC18 PC14 +3V3 DGND +3V3 DGND +3V3 +3V3 MN3MN3 WE18 N.C66 VCC 37 CE9 RE8 N.C1120 WP19 N.C55 N.C11 N.C22 N.C33 N.C44 N.C1221 N.C1322 N.C1423 N.C1524 R/B7 N.C1726 N.C18 27N.C19 28 I/O0 29 N.C21 34N.C22 35 VSS 36 PRE 38N.C23 39 VCC 12 VSS 13 ALE17 N.C811 N.C710 N.C914 N.C1015 CLE16 N.C1625 N.C20 33 I/O1 30 I/O3 32I/O2 31 N.C27 47 N.C26 46 N.C25 45 I/O7 44I/O6 43I/O5 42I/O4 41 N.C24 40 N.C28 48 C27 100nF C27 100nF R15 47K R15 47K R21 47KR21 47K R16 47K R16 47K C29 1uF C29 1uF R19 0RR19 0R R22 0R nm R22 0R nm JP9 Header2 JP9 Header2 C28 100nF C28 100nF NOT POPULATED DNP XOUT32 XIN32 XIN32 XOUT32 PA7 PA8 XIN XOUT PB8 PB9 DGND DGND DGND DGND DGND R3D N PR3D N P R6 DN PR6 DN P R9 DNPR9 DNP R1 D NPR1 D NP 20pF 20pF R4 0RR4 0R 20pF 20pF 49.9R 1% 49.9R 1% Y1Y1 R8 DN PR8 DN PR7D N PR7D N P MN1 SAM4S MN1 PA7_RTS0_PWMH3 49 PA8_CTS0_AD12BTRG 48PB8_XOUT96 PB9_XIN97 R11 R11 Y21 2MHzY21 2MHz C1 20pFC1 20pF R10D N PR10D N P 32.768KHz 32.768KHz R5 0RR5 0R R12 R12 J1J1 2 3 C2 20pFC2 20pF
4-4 SAM4S-EK Development Board User Guide 11139A–ATARM–29-Nov-11 The SAM4S chip internally generates the following clocks: SLCK, the Slow Clock, which is the only permanent clock of the system MAINCK, the output of the Main Clock Oscillator selection: either a Crystal Oscillator or a 4/8/12 MHz Fast RC Oscillator PLLACK, the output of the Divider and 60 to 130 MHz programmable PLL (PLLA) PLLBCK, the output of the Divider and 60 to 130 MHz programmable PLL (PLLB)
4.3.4 Reset Circuitry
On-board NRST button BP1 provides an external reset control of the SAM4S. The NRST pin is bidirectional. It is handled by the on-chip reset controller. It can be driven low to provide a reset signal out to the external components. Conversely, it can be asserted low from the outside to reset the microcontroller Core and the peripherals. The NRST pin integrates a permanent pull-up resistor of about 100 kOhm to VDDIO. On the SAM4S-EK board, the NRST signal is connected to the LCD module and JTAG port. Note: At power-on, the NRST signal is asserted with a default duration of 2 clock cycles. That duration may not be sufficient to correctly reset any other system or board devices connected to that signal. First, in your custom application, you need to check for these devices' datasheets about reset duration requirements. Then, you need to set an appropriate configuration in the NRST Manager. This is done through the ERSTL field in the RSTC_MR register. The NRST duration is thereby configurable between 60 µs and 2 s, whether it is subse- quently activated by a software reset or a user reset. Refer to the SAM4S datasheet for in depth information.
4.3.5 Power Supply and Management
The SAM4S-EK board is supplied with an external 5V DC block through input J9. It is protected by a PolyZen diode MN9 and an LC combinatory filter MN10. The PolyZen is used in the event of an incorrect power supply connection. The adjustable LDO regulator MN12 is used for the 3.3V rail main supply. It powers all the 3.3V compo- nents on the board. Figure 4-4. Power Block The SAM4S product series has different types of power supply pins: VDDIN pin: Power for the internal voltage regulator, ADC, DAC, and analog comparator power supplies. The voltage ranges from 1.8V to 3.6V. DGND +5V DGND +5V +3V3 + C75 100uF-TAN-6.3V + C75 100uF-TAN-6.3V + C65 22uF + C65 22uF C64 100nF C64 100nF MN10 BNX002-01 MN10 BNX002-01 SV1 SG2 CV 3 CG1 4 CG2 5 CG3 6 C76 100nF C76 100nF + C66 22uF + C66 22uF MN9 ZEN056V130A24LS MN9 ZEN056V130A24LS R92 102K 1% R92 102K 1% + C98 220uF-ELE-16V + C98 220uF-ELE-16V MN12 MIC29152WU Micrel's 1.5A LDO, TO263-5 MN12 MIC29152WU Micrel's 1.5A LDO, TO263-5VIN2 VOUT 4 SD1 GND13 ADJ 5 GND26 R89 169K 1% R89 169K 1% Power Jack 2.1mm Power Jack 2.1mm
SAM4S-EK Development Board User Guide 4-5 11139A–ATARM–29-Nov-11 VDDIO pins: Power for the Peripherals I/O lines. The voltage ranges from 1.62V to 3.6V. VDDOUT pin: Output of the internal voltage regulator. VDDCORE pins: Power for the core, including the processor, embedded memories and peripherals. The voltage ranges from 1.62V to 1.95V. VDDPLL pin: Power for the PLL A, PLL B and 12 MHz oscillator. The voltage ranges from 1.62V to 1.95V. Note: VDDPLL should be decoupled and filtered from VDDCORE.
4.3.6 UART
The Universal Asynchronous Receiver Transmitter fe atures a two-pin UART that can be used for com- munication and trace purposes. It offers an ideal channel for in-situ programming solutions. This UART is associated with two PDC channels to reduce the processor time on packet handling. This two-pin UART (TXD and RXD only) is buffered through an RS232 Transceiver MN6 and brought to the DB9 male connector J7. Figure 4-5. UART
4.3.7 USART
The Universal Synchronous/Asynchronous Receiver Transmitter (USART) provides one full duplex uni- versal synchronous/asynchronous serial link. The data frame format is extensively configurable (data length, parity, number of stop bits) to support a broad range of serial communication standards. The USART is also associated with PDC channels for TX/RX data access. Note: For design optimization purposes, both transmitters have been implemented on the same PIO lines, that is PA21, 22, 23, 24 25. To avoid any electrical conflict, the RS485 transceiver is isolated from the receiving line PA21. Should you need to implement an RS485 channel in place of the RS232, follow the procedure below: 1. make sure your software will permanently set PA23 to a high level - this will permanently disable the RS232 receiver. 2. solder a shunt resistor in place of R25 (a solder drop will do). +3V3 DGND DGND +3V3 +3V3 FGND PA10 PA9 C39 100nF C39 100nF C40 100nF C40 100nF TP5 SMD TP5 SMD J7J7 R46 100K R46 100K C38 100nF C38 100nF TP6 SMD TP6 SMD C41 100nF C41 100nF R47 0RR47 0R R48 0RR48 0R C42 100nF C42 100nF MN6 MAX3232CSE MN6 MAX3232CSE T1IN11 T2IN10 R1OUT12 R2OUT9 T1OUT 14 T2OUT 7R1IN 13 R2IN 8 V+2 C1+ 1 C1- 3 C2+ 4 C2- 5 V-6 VCC16 GND15 R45 100K R45 100K
4-6 SAM4S-EK Development Board User Guide 11139A–ATARM–29-Nov-11
4.3.8 RS232
SAM4S-EK connects the USART1 bus (including TXD, RXD, RTS, CTS handshake signal controls and EN command) to the DB9 male connector J5 through the RS232 Transceiver MN5. Figure 4-6. USART
4.3.9 RS485
As noticed above, the USART1 is shared with the RS485 port, connected to the transceiver MN4, con- nected to the 3-point connector J4 . The design includes selectable jumpers for RS485 bus termination resistors selection (JP10, JP11, JP12). Figure 4-7. RS485
4.3.10 Display Interface
The SAM4S-EK carries a TFT Transmissive LCD module with touch panel, FTM280C34D. Its integrated driver IC is ILI9325. The LCD display area is 2.8 inches diagonally measured, with a native resolution of 240 x 320 dots.
4.3.11 LCD Module
The LCD module gets reset from the NRST signal. As explained, this NRST is shared with the JTAG port and the push-button BP1. The LCD chip select signal is connected to NCS1; the jumper JP13 can dis- connect it so that this PIO line is available for other custom usage. The SAM4S communicates with the LCD through PIOC where an 8-bit parallel “8080-like” protocol data bus has to be implemented by software. USART RXD1 TXD1 RTS1 CTS1 PA25 PA24 PA21_232 PA22 PA23 PA21 PA21_232 PA21_485 FGND DGND +3V3 DGND +3V3 +3V3 DGND R36 0RR36 0R C34 100nF C34 100nF C35 100nF C35 100nFC36 100nF C36 100nF R32 47K R32 47K MN5 ADM3312EARU MN5 ADM3312EARU C1+ 6 C1- 20 C2+ 2 C2- 4 C3+ 24 C3- 22 VCC3 V+1 V-21 GND23 SD19 EN5 T1IN7 T1OUT 18 R1IN 15R1OUT10 T2IN8 T2OUT 17 R2IN 14R2OUT11 T3IN9 T3OUT 16 R3IN 13R3OUT12 R38 0RR38 0R JP31JP31 C31 4.7uF C31 4.7uF C32 100nF C32 100nF R35 0RR35 0R C37 100nF C37 100nF C33 100nF C33 100nF J5J5 R34 0RR34 0R R33 0RR33 0R R31 0RR31 0R R37 47KR37 47K RS 485 RXD1 TXD1 RTS1 CTS1 PA22 PA24 PA25 PA21_485 DGND +3V3 +3V3 +3V3 DGND FGND JP28Header2 nmJP28Header2 nm MN4 ADM3485ARZ MN4 ADM3485ARZ RO1 RE2 DE3 DI4 VCC 8 GND 5 A 6 B 7 R28 0RR28 0R R30 0R nm R30 0R nm J4J4 R29 120R R29 120R C30 100nF C30 100nFR26 0RR26 0R JP11 Header2 JP11 Header2 JP12 Header2 JP12 Header2 JP10 Header2 JP10 Header2 R27 0RR27 0R R23 10K R23 10KR25 0R nmR25 0R nm R24 0R nm R24 0R nm
SAM4S-EK Development Board User Guide 4-7 11139A–ATARM–29-Nov-11 Figure 4-8. LCD Block
4.3.12 Backlight Control
The LCD backlight is made of four integrated white chip-LEDs arranged in parallel. These are driven by an AAT3155 charge pump, MN8.The AAT3155 is controlled by the SAM4S through a single PIO line PC13 interface; the 0 Ohm resistor R68 is mounted in series on this line, which permits to use it for other custom purposes. In that case, the pull-up resistor R64 maintains the charge pump permanently enabled by default. On the anode drive line, a 0 Ohm resistor R59 is implemented in series for an optional current limitation. Figure 4-9. Backlight Control The part is placed as close as possible to J8 NOT POPULATED LCD_DB10 LCD_DB11 LCD_DB12 LCD_DB13 LCD_DB14 LCD_DB15 LCD_DB16 LCD_DB17 LCD Six slots on PCB for LCD shield X_RIGHT X_LEFT Y_UP Y_DOWN X_LEFT X_RIGHT Y_DOWN Y_UP LED_K4 LED_K3 LED_K2 LED_K1 LED_A PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 NRST PC15 PC19 PC11 PC8 PC13 PC24 PC25 PC26 PC27 PC28 PC29 PC30 PC31 LCD_DB9 LCD_DB8 LCD_DB7 LCD_DB6 LCD_DB5 LCD_DB4 LCD_DB3 LCD_DB2 LCD_DB1 LCD_DB0 LCD_DB0 LCD_DB4 LCD_DB9 LCD_DB5 LCD_DB7 LCD_DB6 LCD_DB8 LCD_DB1 LCD_DB3 LCD_DB2 PC23 PC22 DGND DGND +3V3 DGND +3V3 DGND DGND DGNDDGND DGND DGND DGND DGND NRST PC[0..31] PACDN044Y5R nm TVS, SOT23-5 PACDN044Y5R nm TVS, SOT23-5 R56 10K R56 10K R61 4.7K nmR61 4.7K nm RA3 4.7Kx4 nm RA3 4.7Kx4 nm 4 5 JP13 Header2JP13 Header2 + C43 10uF + C43 10uF C44 100nF C44 100nF PINs on BOT PIN 39 PIN 1 FTM280C34D PINs on BOT PIN 39 PIN 1 FTM280C34D R58 4.7K R58 4.7K FH26-39S-0.3SHW FH26-39S-0.3SHW VDD1 DB172 DB163 DB154 DB145 DB136 DB127 DB118 DB109 DB910 DB811 DB712 DB613 DB514 DB415 DB316 DB217 DB118 DB019 VDD20 RD21 WR22 RS23 CS24 RESET25 IM026 IM127 GND28 LED-A29 LEDK130 LEDK231 LEDK332 LEDK433 Y+34 Y-35 X+36 X-37 NC38 GND39 R63 4.7K nmR63 4.7K nm C45 100nF C45 100nF R49 47K R49 47K R59 0RR59 0R RA2 4.7Kx4 nm RA2 4.7Kx4 nm 4 5 LCD BACKLIGHT LED_A LED_K1 LED_K2 LED_K3 LED_K4 PC13 +3V3 +3V3 DGND DGND R68 R68 C57 4.7uF C57 4.7uF C55 1uF C55 1uF MN8 AAT3155ITP-T1 MN8 AAT3155ITP-T1 C1+10 C1-9 EN/SET11 C2+ 7 C2- 6 OUTCP 8 IN5 GND4 D1 3 D2 2 D3 1 D4 12 FB1 BN03K314S300R FB1 BN03K314S300R R64 47K R64 47K C56 1uF C56 1uF C54 1uF C54 1uF TP7TP7
4-8 SAM4S-EK Development Board User Guide 11139A–ATARM–29-Nov-11
4.3.13 Touch Screen Interface
The LCD module integrates a 4-wire touch panel controlled by MN7 (ADS7843) which is a slave device on the SAM4S SPI bus. The controller sends back the information about the X and Y positions, as well as a measurement for the pressure applied to the touch panel. The touch panel can be used with either a stylus or a finger. The ADS7843 touch panel controller connects to the SPI0 interface via the NPCS0 control signal. Two interrupt signals are connected and provide events in formation back to the microcontroller: PenIrq and Busy. Note: PenIrq (PA16) is shared with ZigBEE signal IRQ0. Busy (PA17) is shared with ZigBEE signal IRQ1. Therefore, if using a ZigBEE interface in concurrence with the TouchScreen controller, take care not to have both drivers enabled at the same time on either PA16 or PA17. For that purpose, 0 Ohm resistors have been implemented on these PIO lines in order to disconnect either end driver from the other: On the touch panel controller side, R67 and R69. On ZigBEE side, R117 and R120. for further information, refer to the “Schematics” section. Touch ADC auxiliary inputs IN3/IN4 of the ADS7843 are connected to test point (TP8, TP9) for optional function extension. Figure 4-10. Touch Panel Control
4.3.14 JTAG/ICE
A standard 20-pin JTAG/ICE connector is implemented on the SAM4S-EK for the connection of a com- patible ARM JTAG emulator interface, such as the SAM-ICE from Segger. Notes: 1. The NRST signal is connected to BP1 system button and is also used to reset the LCD module. The 0 ohm resistor R44 may be removed in order to isolate the JTAG port from this system reset signal. 2. The TDO pin is in input mode with the pull-up resistor disabled when the Cortex M3 is not in debug mode. To avoid current consumption on VDDIO and/or VDDCORE due to floating input, the internal pull-up resistor corresponding to this PIO line must be enabled. PA12 PA13 PA14 PA17 PA11 X_RIGHT Y_UP X_LEFT Y_DOW N PA16 DGND +3V3 +3V3 +3V3 AGND_TP AGND_TP R62 100K R62 100K R70 0RR70 0R R67 0RR67 0R R66 0RR66 0R R65 100K R65 100K C60 100nF C60 100nF C58 100nF C58 100nF 10uH/100mA 10uH/100mA R72 100K R72 100K R69 0RR69 0R C61 4.7uF C61 4.7uF TP9 SMD TP9 SMD R71 R71 1RC59 100nF C59 100nF TP8 SMD TP8 SMD R74 R74 R73 100K R73 100K MN7 ADS7843E MN7 ADS7843E XP2 YP3 XM4 YM5 DCLK 16 DIN 14 DOUT 12 CS 15 BUSY 13 PENIRQ 11 VREF 9 VCC1 1 VCC2 10 GND 6 IN37 IN48
SAM4S-EK Development Board User Guide 4-9 11139A–ATARM–29-Nov-11 Figure 4-11. JTAG Interface
4.3.15 Audio Interface
The SAM4S-EK board supports both audio recording and playback. The audio volume can be adjusted using the potentiometer RV1, and the microphone amplifier gain can be adjusted via jumpers (fixed gain of 24 or 26 dB).
4.3.16 Microphone Input
The embedded microphone is connected to an audio pre-amplifier using the TS922 operational amplifier (MN11). The gain is set by using JP14 and JP15 jumpers; both must be set or removed at the same time. By modifying the jumper positions, you can select each of the following gain values: 20 dB (default setting, both JP14 and JP15 are off) 26 dB (both JP14 and JP15 are on). Note: 3. The TB1 series 0 Ohm resistor is a reservation for future impedance adaptation facility. Under specific amplifier settings conditions, this enables the easy insertion of a capaci- tor or any other bipolar device on the audio path. On the other hand, R83 is a default
0 Ohm resistor that enables the disconnection of PB0 from the audio input path for cus-
tom usage. 4. The audio pre-amplifier MN11 is powered by a dedicated low dropout regulator MIC5219-3.3 (MN14). +3V3 DGND NRST PB5 PB7 PB6 PB4 R43 100K R43 100K R41 100K R41 100K R39 100K R39 100K J6J6 VTref1 Vsupply 2 nTRST3 GND1 4 TDI5 GND2 6 TMS7 GND3 8 TCK9 GND4 10 RTCK11 GND5 12 TDO13 GND6 14 nSRST15 GND7 16 DBGRQ17 GND8 18 DBGACK19 GND9 20 R42 100K R42 100K R40 100K R40 100K R44 0RR44 0R
4-10 SAM4S-EK Development Board User Guide 11139A–ATARM–29-Nov-11 Figure 4-12. Microphone Input
4.3.16.1 Headphone Output
The SAM4S-EK evaluation kit supports mono/stereo audio playback driven by a TPA0223 audio ampli- fier connected to two DAC channels of the microcontroller. The TPA0223 is a 2W mono Bridge-Tied-Load (BTL) amplifier designed to drive speakers with as low as 4 Ohm impedance. The amplifier can be reconfigured on the fly to d rive two stereo Single-Ended (SE) signals into head phones. Figure 4-13. Headphone Output JP14 and JP15 should be set or removed together AUDIO IN AGND AGND AGND AVDD AGND AGND AGND AVDD AGND AGND DGND AVDD AGND VCC33 PB0 C72 1nF C72 1nF R80 R80 R90 100K R90 100K C67 1uF C67 1uF C74 100nF C74 100nF R84 R84 R87 47K R87 47K R79 R79 R78 R78 R77 470R R77 470R C71 22nF C71 22nF R83 R83 R88 470R R88 470R C63 22uF C63 22uF C62 100pF C62 100pF C77 4.7uF C77 4.7uF R85 R85 C73 22uF C73 22uF R75 47KR75 47K MN11 TS922 MN11 TS922 IN1-2 IN1+3 OUT27 IN2-6 IN2+5 GND 4 VCC 8 OUT1 1 JP14 Header2JP14 Header2 R76 47KR76 47K R93 100K R93 100K R91 R91 JP15 Header2 JP15 Header2 C69 1nF C69 1nF R86 47K R86 47K R82 R82 C68 1uF C68 1uF MIC1 SVB6050 MIC1 SVB6050 R81 100R R81 100R FB2 BN03K314S300R FB2 BN03K314S300R AUDIO OUT AUDIO_OUTL AGND VDD_AMP AGND AGND AGND AGND AGNDDGND VDD_AMP AGND DGND VCC33+5V DGND DGND DGND +5V VCC33 PB13 JP19 Header2JP19 Header2 C82 100nF C82 100nF C88 0.47uFC88 0.47uF C93 470pF C93 470pF C91 4.7uF C91 4.7uF +C81 220uF-TAN-6.3V +C81 220uF-TAN-6.3V R103 100KR103 100K FB3 BN03K314S300R FB3 BN03K314S300R R95 1KR95 1K MN14 MIC5219-3.3YMM MN14 MIC5219-3.3YMM IN2 EN1 BYP4 GND 5 GND 6 GND 7 GND 8 OUT 3 C87 1uF C87 1uF R99 47KR99 47K JP20 Header2 JP20 Header2 R98 33KR98 33K C86 0.47uFC86 0.47uF MN13 TPA0223DGQ MN13 TPA0223DGQ VDD3 RIN5 MONO-IN1 LIN9 LO/MO- 10 RO/MO+ 6 ST/MN 7 SHUTD0WN 2 BYPASS 4 GND 8 PAD11 + C80 10uF + C80 10uF C85 0.47uFC85 0.47uF R100 33KR100 33K R105 33KR105 33K +C83 220uF-TAN-6.3V +C83 220uF-TAN-6.3V JP29JP29 J11 Phonejack Stereo 3.5 J11 Phonejack Stereo 3.55 1R97 1KR97 1K R102 100KR102 100KTP12 Test Pad SQ-40TH TP12 Test Pad SQ-40TH C84 0.47uFC84 0.47uF JP17 Header2JP17 Header2 J10J10 R104 47KR104 47K R101 100KR101 100K C79 1uF C79 1uF + C92 100uF-TAN-6.3V + C92 100uF-TAN-6.3V
SAM4S-EK Development Board User Guide 4-11 11139A–ATARM–29-Nov-11 Using a readily available 1/8-in. (3,5 mm) stereo headphone jack, the co ntrol switch is closed when no plug is inserted. When closed, a 100-kOhm/1-kOhm divider pulls the ST/MN input low. When a jack plug is inserted, the 1-kOhm resistor is disconnected and the ST/MN input is pulled high. The mono speaker (J10 connector) is also physically disconnected from the RO/MO+ output so that no sound is heard from the speaker while the headphones are inserted.
4.3.17 USB Device
The SAM4S UDP port is compliant with the Universal Serial Bus (USB) rev 2.0 Full Speed device speci- fication. J15 is a micro B-type receptacle for USB device. Both 27-Ohm resistors R114 and R116 build up a 90-Ohm differential impedance together with the (embedded) 6-Ohm output impedance of the SAM4S full speed channel drivers. R110 and R112 build up a divider bridge from VBUS +5V to implement plug-in detection (5V level gets lowered to a PIO compatible 3.3V level) through PC21. Figure 4-14. USB
4.3.18 Analog Interface
4.3.18.1 Analog Reference
The 3V voltage reference is based on an LM4040 (Precision Micropower Shunt Voltage Reference). This ADVREF level can be set as 3V or 3.3V via the jumper JP2. Figure 4-15. Analog Vref PC21 PB10 PB11 DGND DGND FGND FGND C94 10pF C94 10pF R110 47KR110 47K R116 27RR116 27R 5V D- D+ ID G J15 USB Micro B 5V D- D+ ID G J15 USB Micro B RV1 V5.5MLA0603 RV1 V5.5MLA0603 RV2 V5.5MLA0603 RV2 V5.5MLA0603 R112 68KR112 68K R1142 7RR1142 7R ADVREF DGND DGND VCC33 +5V JP2JP2 3C5 100nF 100nF SAM4SSAM ADVREF 1 R13 2.2K R13 2.2K MN2 LM4040-2.5 MN2 LM4040-2.5
4-12 SAM4S-EK Development Board User Guide 11139A–ATARM–29-Nov-11
4.3.18.2 Analog Input
The BNC connector CN1 is connected to the ADC port PB1 as an external analog input. An on-board 50- Ohm resistor termination can be applied by closing jumper JP16. A low pass filter can be implemented for the BNC connector CN1 by replacing R94 and C78 with custom resistor and capacitor values, depending on your application requirements. A 10-KOhm potentiometer (VR1) is also connected to this channel to implement an easy access to ADC programming and debugging (or implement an analog user control like display brightness, volume, etc.). Either of these two functions can be selected by jumper JP18. Figure 4-16. ADC Input
4.3.18.3 Analog Output
The BNC connector CN2 is connected to the DAC port PB14 and provides an external analog output. An on-board 50-Ohm resistor termination can be enabled by closing jumper JP21. A filter can be imple- mented on this output channel by replacing R106 and C90 with appropriate resistor and capacitor values, depending on the application requirements. Figure 4-17. DAC Output
4.3.19 QTouch Elements
QTouch keys consist in a series of sensors formed by the association of a copper area and the capaci- tive effect of human fingers approaching it.
4.3.19.1 Keys
The SAM4S-EK implements five individual capacitive touch keys (UP, DOWN, RIGHT, LEFT and VALID) using five pairs of PIO. Potentiometer AD5 ADC DGND DGND VCC33 PB1JP18JP18 CN1 BNC CN1 BNC JP16 Header2 JP16 Header2 VR1 10K VR VR1 10K VR R96 49.9R R96 49.9R C89 10nF C89 10nF R94 R94 C78 10nF C78 10nF SOLDER DROP 2 pins open.Normal DAC01 DAC AUDIO_OUTL DGND PB14 C90 2.2uFC90 2.2uFJP21JP21 R109 49.9R 1% R109 49.9R 1% SD1SD1 1 2 R106 R106 CN2 BNC CN2 BNC SD2SD2 1 2
SAM4S-EK Development Board User Guide 4-13 11139A–ATARM–29-Nov-11 Figure 4-18. QST Keys
4.3.19.2 Slider
A group of channels forms a Slider. A Slider is composed of three channels for a QTouch acquisition method using three pairs of PIO. Such a sensor is used to detect a linear finger displacement on a sen- sitive area. A typical implementation is volume control. Figure 4-19. QT_Slider
4.3.20 User Buttons
There are two mechanical user buttons on the SAM4S-EK, which are connected to PIO lines and defined to be "left" and "right" buttons by default. In addition, a mechanical button controls the system reset, signal NRST. Figure 4-20. System Buttons QTOUCH PC25 PC24 PC31 PC30 PC29 PC28 PC23 PC22 PC27 PC26 R53 1KR53 1K C49 22nF C49 22nF R60 1KR60 1K R51 1KR51 1K C51 22nF C51 22nF R57 1KR57 1K C47 22nF C47 22nF R55 1KR55 1K QTouch Key QTouch Key C53 22nF C53 22nF C52 22nF C52 22nF 22nF use X7R PA1 PA0 PA3 PA2 PA5 PA4 R54 1KR54 1K R50 1KR50 1K C50 22nF C50 22nF C46 22nF C46 22nF QTouch Slider QTouch Slider SL SM SR SR R52 1KR52 1K C48 22nF C48 22nF PB3 PC12 DGND NRST JP26JP26 BP1BP1 BP3BP3 JP25JP25BP2BP2
4-14 SAM4S-EK Development Board User Guide 11139A–ATARM–29-Nov-11
4.3.21 LEDs
There are three LEDs on the SAM4S-EK board: A blue LED (D2) and a green LED (D3), which are user defined and controlled by the GPIO. A red LED (D4), which is a power LED indicating that the 3.3V power rail is active. It is also controlled by the GPIO and can be treated as a user LED as well. The only difference with the two others is that it is controlled through a MOS transistor. By default, the PIO line is disabled; a pull-up resistor controls the MOS to light the LED when the power is ON). Figure 4-21. LEDs
4.3.22 SD/MMC Card
The SAM4S EK has a high-speed 4-bit multimedia MMC interface, which is connected to a 4-bit SD/MMC micro card slot featuring a card detection switch. Figure 4-22. SD Card
4.3.23 ZigBEE
SAM4S has a 10-pin male connector for the RZ600 ZigBEE module. Note: 0 Ohm resistors have been implemented in series with the PIO lines that are used else- where in the design, thereby enabling their individual disconnection, should a conflict occur in your application. PA19 PA20 PC20 +3V3 DGND D4R e d - l e dD4R e d - l e d R113 220R R113 220R IRLML2502 IRLML2502 R115 100KR115 100K D3 Green-ledD3 Green-led R117 220R R117 220R R111 220R R111 220R D2B l ue-ledD2B l ue-led PA28 PA29 PA6 PA26 PA27 PA30 PA31 DGND +3V3 DGND + C25 10uF + C25 10uF RA1 68KX4 RA1 68KX4 R18 10K R18 10K R17 10K R17 10K C26 100nF C26 100nF TF01A TF01A DAT21 DAT32 CMD3 VCC4 CLK5 VSS6 DAT07 DAT18 GND10 CD9 Sh1 11 Sh2 12 Sh3 13 R20 0RR20 0R
SAM4S-EK Development Board User Guide 4-15 11139A–ATARM–29-Nov-11 Figure 4-23. ZigBEE Interface
4.3.24 PIO Expansion
The SAM4S product features three PIO controllers, PIOA, PIOB and PIOC, which are multiplexed with the I/O lines of the embedded peripherals. Each PIO Controller controls up to 32 lines (16 for PIOB). Expansion ports J12, J13 and J14 provide PIO lines access for customer defined usage. Figure 4-24. PIO Expansion Note: All PIO lines are available on these expansion connectors, except those that are used for the QTouch elements. IRQ0_ZBEE IRQ1_ZBEE SPIO_NPCS2# MISO MOSI SPCK SLP_TR ZB_RSTN PA13 PA16 PB2 PA12 PA14 PA15PA17 PA18 DGND +3V3 C95 18pF C95 18pF R120 0RR120 0R J16J16 1 2 3 4 5 6 7 8 9 10 R119 0RR119 0R R118 0RR118 0R JP27JP27 R121 0RR121 0R C96 2.2nF C96 2.2nF C97 2.2uF C97 2.2uF PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8 PC9 PC10 PC11 PC12 PC13 PC14 PC15 PC19 PC17 PC21 PC16 PC20 PC18 PB6 PB1 PB3 PB7 PB4 PB0 PB5 PB2 PB14 PB9 PB11 PB12 PB8 PB13 PB10 PA6 PA9 PA11 PA14 PA13 PA7 PA8 PA12 PA10 PA15 PA22 PA27 PA23 PA29 PA30 PA25 PA21 PA28 PA24 PA26 PA31 PA16 PA17 PA18 PA19 PA20 +3V3 +3V3 +3V3+3V3 DGND DGND DGND DGND DGND +3V3 +3V3 DGND +5V +3V3 +5V +5V+3V3 +3V3 PC[0..31] PB[0..14] PA[0..31] JP23JP23 JP22JP22 J14J14 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 J13J13 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 J12J12 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 JP24JP24
4-16 SAM4S-EK Development Board User Guide 11139A–ATARM–29-Nov-11
4.4 Configuration
This section describes the PIO usage, the jumpers, the test points and the solder drops of a SAM4S-EK board.
4.4.1 PIO Usage
Table 4-1. PIO Port A Pin Assignments and Signal Descriptions No I/O Line Peripheral A Peripheral B Peripheral C Extra Function System Function Comment
1 PA0 PWMH0 TIOA0 A17 WKUP0 QTouch slider (left) SNS
2 PA1 PWMH1 TIOB0 A18 WKUP1 QTouch slider (left) SNSK
3 PA2 PWMH2 SCK0 DATRG WKUP2 QTouch slider (middle) SNS
4 PA3 TWD0 NPCS3 QTouch slider (middle) SNSK
5 PA4 TWCK0 TCLK0 WKUP3 QTouch slider (right) SNS
6 PA5 RXD0 NPCS3 WKUP4 QTouch slider (right) SNSK
7 PA6 TXD0 PCK0 MCI card detection
8 PA7 RTS0 PWMH3 XIN32 CLK32KHz
9 PA8 CTS0 AD12BTR
10 PA9 URXD0 NPCS1 PWMFI0 WKUP6 UART receive data
11 PA10 UTXD0 NPCS2 UART transmit data
12 PA11 NPCS0 PWMH0 WKUP7 NPCS0# (TSC)
13 PA12 MISO PWMH1 MISO_TSC ZigBEE MISO
14 PA13 MOSI PWMH2 MOSI_TSC ZigBEE MOSI
15 PA14 SPCK PWMH3 WKUP8 SPCK_TSC ZigBEE CLK
16 PA15 TF TIOA1 PWML3 WKUP14 / PIO_DCEN1 ZigBEE SLPTR
17 PA16 TK TIOB1 PWML2 WKUP15 / PIO_DCEN2 IRQ_TSC ZigBEE IRQ0
18 PA17 TD PCK1 PWMH3 AD0 BUSY_TSC ZigBEE IRQ1
19 PA18 RD PCK2 A14 AD1 ZigBEE RSTN
20 PA19 RK PWML0 A15 AD2/ WKUP9 Blue LED (UserLED1)
21 PA20 RF PWML1 A16 AD3/ WKUP10 Green LED (UserLED2)
22 PA21 RXD1 PCK1 AD8 USART RXD
23 PA22 TXD1 NPCS3 NCS2 AD9 USART TXD
24 PA23 SCK1 PWMH0 A19 POI_DCCLK USART transceiver enable
25 PA24 RTS1 PWMH1 A20 POI_DC0 USART RTS
26 PA25 CTS1 PWMH2 A23 POI_DC1 USART CTS
27 PA26 DCD1 TIOA2 MCDA2 POI_DC2 MCI data bit 2
28 PA27 DTR1 TIOB2 MCDA3 POI_DC3 MCI data bit 3
29 PA28 DSR1 TCLK1 MCCDA POI_DC4 MCI command
SAM4S-EK Development Board User Guide 4-17 11139A–ATARM–29-Nov-11
30 PA29 RI1 TCLK2 MCCK POI_DC5 MCI clock
31 PA30 PWML2 NPCS2 MCDA0 WKUP11 / POI_DC6 MCI data bit 0
32 PA31 NPCS1 PCK2 MCDA1 POI_DC7 MCI data bit 1
Table 4-1. PIO Port A Pin Assignments and Signal Descriptions (Continued) No I/O Line Peripheral A Peripheral B Peripheral C Extra Function System Function Comment Table 4-2. PIO Port B Pin Assignments and Signal Descriptions No I/O Line Peripheral A Peripheral B Peripheral C Extra Function System Function Comment
1 PB0 PWMH0 AD4 Microphone input
2 PB1 PWMH1 AD5 Analog input
3 PB2 URXD1 NPCS2 AD6 / WKUP12 ZigBee chip select
4 PB3 UTXD1 PCK2 AD7 User push-button 1
5 PB4 TWD1 PWMH2 TDI JTAG data in
6 PB5 TWCK1 PWML0 WKUP13 TDO/
7 PB6 TMS/SWDIO JTAG test mode select
8 PB7 TCK/SWCLK JTAG clock
9 PB8 XOUT CLK12MHz
10 PB9 XIN CLK12MHz
11 PB10 DDM USB DM
12 PB11 DDP USB DP
13 PB12 PWML1 ERASE Flash erase selector
14 PB13 PWML2 PCK0 DAC0 Audio Output R
15 PB14 NPCS1 PWMH3 DAC1 Audio Output L
4-18 SAM4S-EK Development Board User Guide 11139A–ATARM–29-Nov-11 Table 4-3. PIO Port C Pin Assignments and Signal Descriptions No I/O Line Peripheral A Peripheral B Peripheral C Extra Function System Function Comments
1 PC0 D0 PWML0 EBI D0
2 PC1 D1 PWML1 EBI D1
3 PC2 D2 PWML2 EBI D2
4 PC3 D3 PWML3 EBI D3
5 PC4 D4 NPCS1 EBI D4
6 PC5 D5 EBI D5
7 PC6 D6 EBI D6
8 PC7 D7 EBI D7
9 PC8 NWR0/NWE TFT LCD write enable
10 PC9 NANDOE NAND Flash output enable
11 PC10 NANDWE NAND Flash write enable
12 PC11 NRD TFT LCD read enable
13 PC12 NCS3 AD12 User push-button 2
14 PC13 NWAIT PWML0 AD10 LCD backlight control
15 PC14 NCS0 NAND Flash chip select
16 PC15 NCS1 PWML1 AD11 TFT LCD chip select
17 PC16 A21/NANDALE NAND Flash ALE
18 PC17 A22/NANDCLE NAND Flash CLE
19 PC18 A0/NBS0 PWMH0 RDYBSY NAND Flash RDY/BSY
20 PC19 A1 PWMH1 TFT LCD RegSel
21 PC20 A2 PWMH2 Red LED (Power)
22 PC21 A3 PWMH3 USB Vbus detection
23 PC22 A4 PWML3 QTouch valid button SNS
24 PC23 A5 TIOA3 QTouch valid button SNSK
25 PC24 A6 TIOB3 QTouch up button SNS
26 PC25 A7 TCLK3 QTouch up button SNSK
27 PC26 A8 TIOA4 QTouch down button SNS
28 PC27 A9 TIOB4 QTouch down button SNSK
29 PC28 A10 TCLK4 AD13 QTouch left button SNS
30 PC29 A11 TIOA5 AD14 QTouch left button SNSK
31 PC30 A12 TIOB5 QTouch right button SNS
32 PC31 A13 TCLK5 QTouch right button SNSK
SAM4S-EK Development Board User Guide 4-19 11139A–ATARM–29-Nov-11
4.4.2 Jumpers
The SAM4S-EK board jumpers are essentially used fo r two main purposes: functional selection or cur- rent measurement. Details are given below. Table 4-4. Jumpers Setting Designation Label Default Setting Feature JP1 JTAG OPEN Close to select the JTAG boundary scan of the SAM4S JP2 ADVREF 1-2 Analog reference voltage selection between 3.3V (close 1-2) and 2.5V (close 2-3) JP3 ERASE OPEN Close to reinitialize the Flash contents and some of its NVM bits. JP4 TEST Not populated (OPEN) Close for manufacturing test or fast programming mode JP5 VDDPLL CLOSE Access for current measurement on VDDPLL JP6 VDDIO CLOSE Access for current measurement on VDDIO JP7 VDDIN CLOSE Access for current measurement on VDDIN JP8 VDDCORE CLOSE Access for current measurement on VDDCORE JP9 CE FLASH CLOSE NCS0 enable NAND Flash chip select JP10 RS485 OPEN Maintain differential impedance for RS485 interface JP11 RS485 CLOSE Maintain impedance matching for RS485 interface JP12 RS485 OPEN Maintain differential impedance for RS485 interface JP13 CS CLOSE NCS1 chip select LCD JP14 - JP15 MIC GAIN0 CLOSE (both) 20db OPEN (both) 26db Close both to lower gain stage on microphone input. JP16 ADC input OPEN Close for impedance matching on ADC BNC port JP17 – JP19 MIC Gain stage Close to mux RIN/LIN into MONO-IN path within audio PA JP18 SELECT ADC INP 1-2 2-3 ADC input potentiometer ADC input BNC JP20 MONO/STEREO CLOSE Close to fix in mono speaker, no matter the stereo plug state JP21 DAC output OPEN Close for impedance matching on DAC BNC port JP22 PIO expansion J12 voltage supply 2-3 Set to 3.3V (position 1-2 sets to 5V) JP23 PIO expansion J13 voltage supply 2-3 Set to 3.3V (position 1-2 sets to 5V) JP24 PIO expansion J14 voltage supply 2-3 Set to 3.3V (position 1-2 sets to 5V) JP25 BP2 CLOSE Open to disconnect and free PB3 for custom usage JP26 BP3 CLOSE Open to disconnect and free PC12 for custom usage JP27 ZIGBEE CLOSE Power supply connection/disconnection for the ZigBEE module May also be used as a current measurement point
4-20 SAM4S-EK Development Board User Guide 11139A–ATARM–29-Nov-11
4.4.3 Test Points
Some test points have been placed on the SAM4S-EK board for the verification of important signals.
4.4.4 Solder Drops
There are two solder drops designed on the SAM4S-EK for isolation.
4.4.5 Assigned PIO Lines, Disconnection Possibility
As pointed out in some previous interface description, 0 Ohm resistors have been inserted on the path of the receiver PIO lines of the SAM4S-EK. These are the PIO lines connected to an external driver on the board. The 0 Ohm resistors allow disconnecting each of these for custom usage (through PIO expansion connectors for example). This feature gives the user an added level of versatility for prototyping a system of his own. See the table below. Table 4-5. Audio Input Configuration JP17 JP19 MONO-STEREO INPUT OFF OFF PIN test point (TP12) OFF ON Left-in only ON OFF Right-in only ON ON Sum of Left-in and Right-in Table 4-6. Test Points Designation Part Description TP1 Ring Hook GND TP2 Ring Hook GND TP3 Ring Hook GND TP4 Ring Hook GND TP5 Pad UART TXD TP6 Pad UART RXD TP7 Pad LCD Backlight driver anode TP8 Pad Aux ADC input for Touch Screen controller TP9 Pad Aux ADC input for Touch Screen controller TP10 Ring Hook +5V TP11 Ring Hook +3V3 TP12 Pad Optional Audio PA input Table 4-7. Solder Drops Designation Default Setting Feature SD1 OPEN Isolation of DAC output from shared channel (PB14) SD2 CLOSE Connects PB14 to the AUDIO_OUTL channel
SAM4S-EK Development Board User Guide 4-21 11139A–ATARM–29-Nov-11 Table 4-8. Disconnecting Possibility Designation Default Assignment PIO R19 0R PC18, RDY/BSY on NAND Flash R20 0R PA29 R22 DNP Optional write protection on NAND Flash R25 0R PA21 R26 0R PA25 R27 0R PA24 R28 0R PA22 R31 0R PA23 R33 0R PA22 R34 0R PA21 R35 0R PA24 R36 0R PA25 R44 0R NRST R47 0R PA9 R48 0R R2OUT/MN5 R59 0R LCD backlight LED anode R66 0R PA11 R67 0R PA5 R68 0R PC13 R69 0R PA4 R70 0R Vref TSC R118 0R PA3 ZB_RSTN R119 0R PA5 IRQ1_ZBEE R120 0R PA4 IRQ0_ZBEE R121 0R PA6 SLP_TR Table 4-9. Default Not Populated Parts Reference Function J1, R1 External clock resource input Y1, R3, R7 Backup 12 MHz crystal R6, R8 Isolation on 12 MHZ clock source and GPIO expansion R9, R10 Isolation on 32 KHz clock source and GPIO expansion R22 Optional write protection NAND Flash R23 Optional pull-up for open drain output or equivalent device R24, R30 Differential impedance matching for RS485 cable
4-22 SAM4S-EK Development Board User Guide 11139A–ATARM–29-Nov-11
4.5 Connectors
4.5.1 Power Supply Connector J9
The SAM4S-EK evaluation board can be powered from a 5VDC power supply connected to the external power supply jack J9. The positive pole is the center pin. Figure 4-25. Power Supply Connector J9
4.5.2 USART Connector J5 With RTS/CTS Handshake Support
Figure 4-26. Male RS232/USART Connector J5 D1 Optional ESD protection for LCD touch panel R61, R63, RA2, RA3 Optional data bus termination for LCD controller JP4 Test mode selection for the SAM chip J2 Optional QFP socket for the SAM4 chip K1 Virtual component for QTouch keys set - implemented as copper areas S1 Virtual component for QTouch slider set - implemented as copper areas TPxx Surface-mounted test points (copper area) Table 4-9. Default Not Populated Parts Reference Function Table 4-10. Power Supply Connector J9 Signal Descriptions Pin Mnemonic Signal Description
1 Center +5vcc
2 Gnd Ground reference
SAM4S-EK Development Board User Guide 4-23 11139A–ATARM–29-Nov-11
4.5.3 UART Connector J7
Male RS232/UART connector J7
4.5.4 USB Device Connector J15
Figure 4-27. Micro-B USB Connector J15 Table 4-11. Serial COM1 Connector J5 Signal Descriptions Pin Mnemonic Signal Description 1, 4, 6, 9 NC NO CONNECTION
2 TXD TRANSMITTED DATA RS232 serial data output signal
3 RXD RECEIVED DATA RS232 serial data input signal
5 GND GROUND
7 RTS READY TO SEND Active-positive RS232 input signal
8 CTS CLEAR TO SEND Active-positive RS232 output signal
Table 4-12. Male RS232/UART Connector J7 Signal Descriptions Pin Mnemonic Signal Description 1, 4, 6, 7, 8, 9 NC NO CONNECTION Table 4-13. Micro-B USB Connector J15 Signal Descriptions Pin Mnemonic Signal Description
1 Vbus 5v power
2 DM Data -
3 DP Data +
4 Gnd Ground
5 Shield Shield
4-24 SAM4S-EK Development Board User Guide 11139A–ATARM–29-Nov-11
4.5.5 TFT LCD Connector J8
One 39-pin connector is available on the board to connect the LCD module, backlight and touch screen. Figure 4-28. LCD Connector J8 Table 4-14. LCD Connector J8 Signal Descriptions Pin Mnemonic Pin Mnemonic 1 3V3 2 LCD_DB17 (PC7)
3 LCD_DB16 (PC6) 4 LCD_DB15 (PC5)
5 LCD_DB14 (PC4) 6 LCD_DB13 (PC3)
7 LCD_DB12 (PC2) 8 LCD_DB11 (PC1)
9 LCD_DB10 (PC0) 10 LCD_DB09 (NC)
11 LCD_DB08 (NC) 12 LCD_DB07
13 LCD_DB06 (NC) 14 LCD_DB05 (NC)
15 LCD_DB04 (NC) 16 LCD_DB03 (NC)
17 LCD_DB02 (NC) 18 LCD_DB01 (NC)
19 LCD_DB00 (NC) 20 3V3
21 RD (PC11) 22 WR (PC8)
23 RS (PC19) 24 CS (PC15)
25 RESET 26 IM0
27 IM1 28 GND
29 LED-A 30 LED-K1
31 LED-K2 32 LED-K3
33 LED-K4 34 Y UP
35 Y DOWN 36 X RIGHT
37 X LEFT 38 NC
39 GND
SAM4S-EK Development Board User Guide 4-25 11139A–ATARM–29-Nov-11
4.5.6 JTAG Debugging Connector J6
This JTAG connector is a 20-way Insulation Displacement Connector (IDC) keyed box header (2.54 mm male) that mates with IDC sockets mounted on a ribbon cable. Its signal assignment is compatible with the SAM-ICE or any similar third-party interface. Figure 4-29. JTAG/ICE Connector J6 Table 4-15. JTAG/ICE Connector J13 Signal Descriptions Pin Mnemonic Description 1 VTref. 3.3V power This is the target reference voltage. It is used to check if the target has power, to create the logic-level reference for the input comparators and to control the output logic levels to the target. It is normally fed from Vdd on the target board and must not have a series resistor. 2 Vsupply. 3.3V power This pin is not connected in SAM-ICE. It is reserved for compatibility with other equipment. Connect to Vdd or leave open in target system. 3 nTRST TARGET RESET — Active-low output signal that resets the target JTAG Reset. Output from SAM-ICE to the Reset signal on the target JTAG port. Typically connected to nTRST on the target CPU. This pin is normally pulled HIGH on the target to avoid unintentional resets when there is no connection.
4 GND Common ground
TDI TEST DATA INPUT — Serial data output line, sampled on the rising edge of the TCK signal JTAG data input of target CPU. It is recommended that this pin is pulled to a defined state on the target board. Typically connected to TDI on target CPU.
6 GND Common ground
7 TMS TEST MODE SELECT –
JTAG mode set input of target CPU. This pin should be pulled up on the target. Typically connected to TMS on target CPU. Output signal that sequences the target’s JTAG state machine, sampled on the rising edge of the TCK signal.
8 GND Common ground
TCK TEST CLOCK — Output timing signal, for synchronizing test logic and control register access JTAG clock signal to target CPU. It is recommended that this pin is pulled to a defined state on the target board. Typically connected to TCK on target CPU.
10 GND Common ground
Input Return test clock signal from the target Some targets must synchronize the JTAG inputs to internal clocks. To assist in meeting this requirement, a returned and retimed TCK can be used to dynamically control the TCK rate. SAM-ICE supports adaptive clocking which waits for TCK changes to be echoed correctly before making further changes. Connect to RTCK if available, otherwise to GND.
12 GND Common ground
13 TDO JTAG TEST DATA OUTPUT —
Serial data input from the target JTAG data output from target CPU. Typically connected to TDO on target CPU.
14 GND Common ground
4-26 SAM4S-EK Development Board User Guide 11139A–ATARM–29-Nov-11
4.5.7 SD/MMC - MCI Connector J3
Figure 4-30. SD/MMC Connector J3 15 nSRST RESET — Active-low reset signal. Target CPU reset signal
16 GND Common ground
17 RFU This pin is not connected in SAM-ICE.
18 GND Common ground
19 RFU This pin is not connected in SAM-ICE.
20 GND Common ground
Table 4-15. JTAG/ICE Connector J13 Signal Descriptions (Continued) Pin Mnemonic Description Table 4-16. SD/MMC Connector J3 Signal Descriptions Pin Mnemonic Pin Mnemonic
1 RSV/DAT3 2 CDA
3 GND 4 VCC
5 CLK 6 GND
9 DAT2 10 Card Detect
11 GND 12
SAM4S-EK Development Board User Guide 4-27 11139A–ATARM–29-Nov-11
4.5.8 Analog Connector CN1 & CN2
Figure 4-31. Analog Input Connector CN1 and Analog Output CN2, Bottom View
4.5.9 RS485 Connector J14
Figure 4-32. RS485 Connector J14 Table 4-17. Analog Input, Output Connector CN1, CN2 Signal Descriptions Pin Mnemonic 1, 2, 3, 4 GND
5 Analog input PB1 for CN1 and analog output PB13 for CN2 respectively
Table 4-18. RS485 J14 Signal Descriptions Pin Mnemonic
1 A - non-inverted RS485 signal A
2 Frame ground
3 B - non-inverted RS485 signal B
4-28 SAM4S-EK Development Board User Guide 11139A–ATARM–29-Nov-11
4.5.10 Headphone Connector J11
Figure 4-33. Headphone J11
4.5.11 ZigBEE Connector J16
Figure 4-34. ZigBee Connector J16 Table 4-19. Headphone J11 Signal Descriptions Pin Mnemonic
1 AGND
2 Out left
5 Out Right
Table 4-20. Connector J16 Signal Descriptions Function Signal Name Port Pin Pin Port Signal Name Function Option on Misc. Port Set by Zero Ohm Resistor or Solder Shunts Reset /RST 1 2 Misc. EEPROM for MAC address, CAP array settings and serial number TST: test mode activation CLKM: RF chip clock output Interrupt Request IRQ 3 4 SLP_TR SLP_TR SPI chip select /SEL 5 6 MOSI SPI MOSI SPI MISO MISO 7 8 SCLK SPI CLK Power Supply GND GND 9 10 VCC VCC VCC Voltage range: 1.8v to 5.5v, typically regulated to 3.3v
SAM4S-EK Development Board User Guide 4-29 11139A–ATARM–29-Nov-11
4.5.12 PIO Expansion Port C Connector J12
Figure 4-35. PIO Expansion Connector J12 Table 4-21. Connector J12 Signal Descriptions Pin Mnemonic Pin Mnemonic 1 +5V or +3v3 2 +5V or +3v3
3 GND 4 GND
5 PC0 6 PC16
7 PC1 8 PC17
9 PC2 10 PC18
11 PC3 12 PC19
13 PC4 14 PC20
15 PC5 16 PC21
17 PC6 18 NC
19 PC7 20 NC
21 PC8 22 NC
23 PC9 24 NC
25 PC10 26 NC
27 PC11 28 NC
29 PC12 30 NC
31 PC13 32 NC
33 PC14 34 NC
35 PC15 36 NC
37 GND 38 GND
4-30 SAM4S-EK Development Board User Guide 11139A–ATARM–29-Nov-11
4.5.13 PIO Expansion Port A Connector J13
Figure 4-36. PIO Expansion Connector J13 Table 4-22. Connector J13 Signal Descriptions Pin Mnemonic Pin Mnemonic 1 +5V or +3v3 2 +5V or +3v3
5 NC 6 PA16
7 NC 8 PA17
9 NC 10 PA18
11 NC 12 PA19
13 NC 14 PA20
15 NC 16 PA21
17 PA6 18 PA22
19 PA7 20 PA23
21 PA8 22 PA24
23 PA9 24 PA25
25 PA10 26 PA26
27 PA11 28 PA27
29 PA12 30 PA28
31 PA13 32 PA29
33 PA14 34 PA30
35 PA15 36 PA31
SAM4S-EK Development Board User Guide 5-1 11139A–ATARM–29-Nov-11 Section 5 Schematics
5.1 Schematics
This section contains the following schematics: Block diagram General information Microcontroller NAND Flash, serial interface TFT LCD & Touch Audio & Power Supply USB, LEDs, push-buttons & ZigBEE
PIO A, B, C PIO A, B, C Sheet 3 Sheet 6 Sheet 5 LCD INTERFACE 2.8" 240x320 TFT TOUCH SCREEN AUDIO In (ADC) QTOUCH MIC PHONE JACK UART0 USART1 RS232 Sheet 4 HE 10 RS485 USART1 ICE Sheet 7 HE 10 ZIGBEE INTERFACE HSMCI ATMEL Cortex-M4 ARM Processor SAM4S (LQFP100) Micro SD NAND FLASH
5 V Input
PIO A, B, C Extension FS DEVICE POT ADC/ DAC AUDIO Out (DAC) POWER SUPPLY (3.3V) HE 14 LEDs, ButtonsBoard Configuration Sheet Sheet 2 REV DATEMODIF. DES. DATE VER. SCALE 1/1 REV. SHEET This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings. INIT EDITA XX-XXX-XXJH XXX Block Diagram 08-Mar-11 SAM4S-EK REV DATEMODIF. DES. DATE VER. SCALE 1/1 REV. SHEET This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings. INIT EDITA XX-XXX-XXJH XXX Block Diagram 08-Mar-11 SAM4S-EK REV DATEMODIF. DES. DATE VER. SCALE 1/1 REV. SHEET This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings. INIT EDITA XX-XXX-XXJH XXX Block Diagram 08-Mar-11 SAM4S-EK
JP20 Close to fix in mono speaker mode, no matter stereo plug state
3 J1, R1 External clock resource input
Y1, R3, R7 Backup 12MHz crystal R6, R8 Isolation between 12MHz clock source and GPIO line DEFAULT OPEN 1-2 OPEN OPEN CLOSE CLOSE CLOSE CLOSE OPEN R9, R10 Isolation between 32KHz clock source and GPIO line JUMPER and SOLDERDROP
4 R22 Optional write protection on NAND flash
R24, R30 D1 Optional ESD protection for LCD touch panel R61, R62, RA2, RA3 Optional databus termination for LCD controller RS485 bus termination enable Differential impedance matching for RS485 cable 1-2 OPEN OPEN OPEN 1-2
3 JP1 Close to select JTAG boundary scan
JP3 Close to reinitialize the Flash contents and some of its NVM bits JP4 Close for manufacturing test or fast programming mode JP5, JP6, JP7, JP8 Access for current measurement on each power rail
4 JP9 Nand Flash chip select enable
JP14, JP15 Sync close to degrade gain stage on microphone input JP17, JP19 Close to mux RIN/LIN into MONO-IN path within audio PA
5 LCD chip select enable
JP16, JP21 Close for impedance matching on AD/DA BNC port JP18 ADC input selection between BNC port and potentiometer 7 JP22, JP23, JP24 DC voltage selection between 3.3V and 5V on PIO expansion ports JP27 Power consumption measure for ZigBEE module JP25 Button BP2 disable JP30 DAC output between AUDIO left channel and BNC connector 1-2 CLOSE CLOSE A REV DATA
REVISION HISTORY
LCD, Touch items Audio, AD/DA, Power PAGE Block Diagram IO Expansion, USB, ZigBEE, LED, Button
DESCRIPTION
NAND Flash, RS232, RS485, MCI, JTAG TABLE OF CONTENTS NOTE
2011.03 ORIGINAL RELEASED
USB_DDP ERASE AUDIO OUT R AUDIO OUT L PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PB8 PB9 PB11 PB12 PB13 PB10 PB14 PIOB USAGE MIC INPUT ANA INPUT ZB_NPCS2 USER_PB1 JTAG JTAG JTAG JTAG CLK_12M CLK_12M USB_DDM TDWN_SNSK TLEFT_SNS TLEFT_SNSK TRIGHT_SNS TRIGHT_SNSK PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8 PC9 PC10 PC11 PC12 PC13 PC14 PC15 PIOC USAGE PC16 PC17 PC18 PC19 PC20 PC21 PC22 PC23 PC24 PC25 PC27 PC28 PC29 PC26 PC30 PC31 PIOC USAGE WR_LCD RD_LCD USER_PB2 EN_LCD NAND_NCS0 NSC1_LCD REGSEL_LCD LED_RED(POWER) USB_CNX TVALID_SNS TVALID_SNSK TUP_SNS TUP_SNSK TDWN_SNS NAND_OE NAND_WE NAND_ALE NAND_CLE NAND_RDYBSY PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PA8 PA9 PA10 PA11 PA12 PA13 PA14 PA15 PIOA USAGE PA16 PA17 PA18 PA19 PA20 PA21 PA22 PA23 PA24 PA25 PA27 PA28 PA29 PA26 PA30 PA31 PIOA USAGE TSLIDR_SL_SNS TSLIDR_SL_SNSK TSLIDR_SM_SNS TSLIDR_SM_SNSK TSLIDR_SR_SNS TSLIDR_SR_SNSK MCI_CD CLK_32K CLK_32K RX_UART0 TX_UART0 TSC_CS MISO MOSI SPCK ZB_SLPTR PIO MUXING TSC_IRQ/ZB_IRQ0 TSC_BUSY/ZB_IRQ1 ZB_RSTN LED_BLUE LED_GREEN RXD1 TXD1 COM1EN RTS1 CTS1 MCI JP26 CLOSE Button BP3 disable JP10, JP12 OPEN RS485 pull resistor selectors TEST POINT PAGE REFERENCE FUNCTION
3 TP1, TP2, TP3, TP4 GND
4 TP5 UART TXD
TP12 Optional audio PA input TP7 LCD backlight driver anode TP8, TP9 Aux ADC input for TSC TP6 UART RXD JP2 Analog reference voltage selection between 3.3V and 3.0V (1) Resistance Unit: "K" is "Kohm", "R" is "Ohm? (2) "nm" means the component is not populated by default R25 Disconnect RS485 Receive data from PA21 JP31 1-2 RS232 USART and RS485 selection JP29 1-2 AUDIO Amplifier power select between +5V and VCC33 REV DATEMODIF. DES. DATE VER. SCALE 1/1 REV. SHEET This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings. INIT EDITA XX-XXX-XXJH XXX Board Configuration 08-Mar-11 SAM4S-EK REV DATEMODIF. DES. DATE VER. SCALE 1/1 REV. SHEET This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings. INIT EDITA XX-XXX-XXJH XXX Board Configuration 08-Mar-11 SAM4S-EK REV DATEMODIF. DES. DATE VER. SCALE 1/1 REV. SHEET This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings. INIT EDITA XX-XXX-XXJH XXX Board Configuration 08-Mar-11 SAM4S-EK
SOCKET_THROUGHT_HOLE NOT POPULATED DNP LQFP100 PB2 PB3 PB10 PB11 PB4 PB6 PB7 PB5 NRST PB1 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA9 PA10 PA11 PA12 PA13 PA14 PA15 PA16 PA17 PA18 PA19 PA20 PA21 PA22 PA23 PA24 PA25 PA26 PA27 PA28 PA29 PA30 PA31 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8 PC9 PC10 PC11 PC12 PC13 PC14 PC15 PC16 PC17 PC18 PC19 PC20 PC21 PC22 PC23 PC24 PC25 PC26 PC27 PC28 PC29 PC30 PC31 XOUT32 PB0 JTAGSEL XIN32 PB14 PC12 PA23 PC23 PB11 PC24 PC22 PB12 PB10 PA19 PC15 PC13 PA22 PC18 JTAGSEL PB5 PC20 PB6 PC19 PC21 PB7 PA18 PA21 PC26 PA17 PC27 PB3 PB2 PC31 PB0 ADVREF PC29 PC30 PB1 PA25 PA26 PC3 PA24 PC4 PC5 PA12 XIN32 XOUT32 PC2 PA11 PA9 PC1 PA10 PA16 PC7 PC6 PA14 PA15 PA13 PC28 PA5 PA4 PA27 PC8 NRST PA28 PA30 PA3 PC10 PA29 TEST PC9 PC16 PC11 PA2 PC14 PA1 PA0 PC17 PB4 PA6 PC0 XIN PA20 PC25 PB13 XOUT PA31 PB0 PB6 PB7 PB9 PB8 PB10 PB11 PB1 PB2 PB12 PB3 PB14 PB13 PB4 PB5 PB13 PB14 PB12 ADVREF TEST XIN32 XOUT32 PA7 PA8 XIN XOUT PB8 PB9 PB13 PB14 VDDCORE DGND DGND DGND DGND VDDIO DGND DGND DGND VDDPLLVDDCORE DGND VDDINVDDOUT DGND VDDOUT VDDIN VDDIO VDDCORE VDDIO VDDCORE VDDIO VDDCORE VDDIO VDDIO VDDPLL DGND VDDOUT DGND VDDPLL VDDCORE VDDIO VDDIN +3V3 DGND DGND +3V3 +3V3 DGND DGND VCC33 +5V DGND DGND PB2 PB3 PB10 PB11 PB5 PB7 PB6 PB4 NRST PB1 PA[0..31] PC[0..31] PB[0..14] PB0 REV DATEMODIF. DES. DATE VER. SCALE 1/1 REV. SHEET This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings. INIT EDITA XX-XXX-XXJH XXX Microcontroller 08-Mar-11 SAM4S-EK REV DATEMODIF. DES. DATE VER. SCALE 1/1 REV. SHEET This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings. INIT EDITA XX-XXX-XXJH XXX Microcontroller 08-Mar-11 SAM4S-EK REV DATEMODIF. DES. DATE VER. SCALE 1/1 REV. SHEET This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings. INIT EDITA XX-XXX-XXJH XXX Microcontroller 08-Mar-11 SAM4S-EK TP3TP3 R3 0R nmR3 0R nm R6 0R nmR6 0R nm C21 4.7uFC21 4.7uF TP1TP1 R9 0R nmR9 0R nm C12 100nFC12 100nF R107 R107 C6 100nFC6 100nF + C24 10uF + C24 10uF JP3JP3 R1 0R nmR1 0R nm R4 0RR4 0R JP5 Header2 JP5 Header2 10uH-100mA 10uH-100mA 20pF 20pF C19 100nFC19 100nF R14 R14 20pF 20pF JP1 Header2 nm JP1 Header2 nm C20 4.7uFC20 4.7uF C9 100nFC9 100nF Y1Y1 1 2 C14 100nFC14 100nF 49.9R 1% 49.9R 1% JP7 Header2 JP7 Header2 R8 0R nmR8 0R nm JP2JP2 C18 100nFC18 100nF C70 4.7uF C70 4.7uF C11 100nFC11 100nF R7 0R nmR7 0R nm C17 100nFC17 100nF TP2TP2 TP4TP4 Socket-QFP100 nm Socket-QFP100 nm 100 C23 4.7uF C23 4.7uF AT91SAM4S-LQFP100 MN1 AT91SAM4S-LQFP100 AT91SAM4S-LQFP100 MN1 AT91SAM4S-LQFP100 PA0_PWMH0_TIOA0_A17 74 PA1_PWMH1_TIOB0_A18 72 PA2_PWMH2_SCK0_DATRG 67 PA3_TWD0_NPCS3 66 PA4_TWCK0_TCLK0 55 PA5_RXD0_NPCS3 53 PA6_TXD0_PCKO 52 PA7_RTS0_PWMH3 49 PA8_CTS0_AD12BTRG 48 PA9_URXD0_NPCS1 46 PA10_UTXD0_NPCS2 44 PA11_NPCS0_PWMH0 42 PA12_MISO_PWMH1 41 PA13_MOSI_PWMH2 33 PA14_SPCK_PWMH3 31 PA15_TF_TIOA1_PWML3 30 PA16_TK_TIOB1_PWML2 28 PA17_TD_PCK1_PWMH3_AD12B0 12 PA18_RD_PCK2_A14_AD12B1 14 PA19_RK_PWML0_A15_AD12B2 18 PA20_RF_PWML1_A16_AD12B3 24 PA21_RXD1_PCK1_AD12B8 15 PA22_TXD1_NPCS3_NCS2_AD12B9 20 PA23_SCK1_PWMH0_A19 22 VDDCORE85 JTAGSEL77 GND 45 GND 95 GND 70 GND 26 VDDIO27 VDDIO69 VDDIO91 PB8_XOUT96 PB9_XIN97 PB0_PWMH0_AD12B43 NRST60 VDDCORE56 ADVREF 1 PA25_CTS1_PWMH2_A23 38PA24_RTS1_PWMH1_A20 34 PB2_URXD1_NPCS2_AD12B67 PB3_UTXD1_PCK2_AD12B79 PB6_TMS_SWDIO79 PB4_TWD1_PWMH2_TDI51 PB5_TWCK1_PWML0_TDO76 PB7_TCK_SWCLK83 TEST61 PB12_PWML1_ERASE87 PB14_NPCS1_PWMH3_DACO1 99 VDDOUT11 PB1_PWMH1_AD12B55 PA26_DCD1_TIOA2_MCDA2 39 PA27_DTR1_TIOB2_MCDA3 57 PA28_DSR1_TCLK1_MCCDA 59 PA29_RI1_TCLK2_MCCK 63 PA30_PWML2_NPCS2_MCDA0 64 PA31_NPCS1_PCK2_MCDA1 81 VDDIN10 PB10_DDM88 PB11_DDP89 PB13_PWML2_PCK0_DACO0 93 VDDIO98 VDDCORE36 VDDCORE16 VDDPLL100 VDDIO50 GNDANA 2 PC0_D0_PWML025 PC1_D1_PWML147 PC2_D2_PWML243 PC3_D3_PWML340 PC4_D4_NPCS137 PC5_D535 PC6_D632 PC7_D729 PC8_NWR0_NWE58 PC9_NANDOE62 PC10_NANDWE65 PC11_NRD68 PC12_NCS3_AD12B1223 PC13_NWAIT_PWML0_AD12B1021 PC14_NCS071 PC15_NCS1PWML1_AD12B1119 PC16_A21_NANDALE73 PC17_A22_NANDCLE75 PC18_A0_NBS0_PWMH078 PC19_A1_PWMH180 PC20_A2_PWMH282 PC21_A3_PWMH384 PC22_A4_PWML386 PC23_A5_TIOA390 PC24_A6_TIOB392 PC25_A7_TCLK394 PC26_A8_TIOA413 PC27_A9_TIOB417 PC28_A10_TCLK454 PC29_A11_TIOA5_AD12B134 PC30_A12_TIOB5_AD12B146 PC31_A13_TCLK5_AD12B158 100nF 100nF C16 100nFC16 100nF C8 2.2uFC8 2.2uF Y2 12MHzY2 12MHz C22 100nF C22 100nF C7 100nFC7 100nF C13 4.7uF nmC13 4.7uF nm R11 R11 C15 100nFC15 100nF JP8 Header2 JP8 Header2 C1 20pFC1 20pF SMA nm SMA nm 2 3 R12 R12 JP4 Header2 nm JP4 Header2 nm R5 0RR5 0R R13 2.2K R13 2.2K 32.768KHz 32.768KHz 1 2 R10 0R nmR10 0R nm JP6 Header2 JP6 Header2 C10 100nFC10 100nF MN2 LM4040AIM3X-3.0 MN2 LM4040AIM3X-3.0 C2 20pFC2 20pF
PA21_485 PA25 PA24 PA21_232 PA22 PA23 PA29 PC18 PC14 PA6 PA26 PA27 PA30 PA31 PA21 PA21_232 PA21_485 +3V3 DGND +3V3 DGND +3V3 +3V3 DGND +3V3 FGND DGND +3V3 DGND +3V3 +3V3 DGND DGND +3V3 +3V3 +3V3 DGND +3V3 DGND +3V3 DGND DGND +3V3 +3V3 FGND FGND DGND PC[0..31] NRST PA10 PA9 PB5 PB7 PB6 PB4 PA[0..31] REV DATEMODIF. DES. DATE VER. SCALE 1/1 REV. SHEET This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings. INIT EDITA XX-XXX-XXJH XXX NAND Flash & Serial IF 08-Mar-11 SAM4S-EK REV DATEMODIF. DES. DATE VER. SCALE 1/1 REV. SHEET This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings. INIT EDITA XX-XXX-XXJH XXX NAND Flash & Serial IF 08-Mar-11 SAM4S-EK REV DATEMODIF. DES. DATE VER. SCALE 1/1 REV. SHEET This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings. INIT EDITA XX-XXX-XXJH XXX NAND Flash & Serial IF 08-Mar-11 SAM4S-EK MN3MN3 WE18 N.C66 VCC 37 CE9 RE8 N.C1120 WP19 N.C55 N.C11 N.C22 N.C33 N.C44 N.C1221 N.C1322 N.C1423 N.C1524 R/B7 N.C1726 N.C18 27N.C19 28 I/O0 29 N.C21 34N.C22 35 VSS 36 PRE 38N.C23 39 VCC 12 VSS 13 ALE17 N.C811 N.C710 N.C914 N.C1015 CLE16 N.C1625 N.C20 33 I/O1 30 I/O3 32I/O2 31 N.C27 47 N.C26 46 N.C25 45 I/O7 44I/O6 43I/O5 42I/O4 41 N.C24 40 N.C28 48 JP28Header2 nmJP28 Header2 nm R43 100K R43 100K C39 100nF C39 100nF R41 100K R41 100K C40 100nF C40 100nF MN4 ADM3485ARZ MN4 ADM3485ARZ RO1 RE2 DE3 DI4 VCC 8 GND 5 A 6 B 7 TP5TP5 + C25 10uF + C25 10uF R36 0RR36 0R C34 100nF C34 100nFC35 100nF C35 100nF R39 100K R39 100K C36 100nF C36 100nF C27 100nF C27 100nF R32 47K R32 47K R15 47K R15 47K J7J7 RA1 68Kx4 RA1 68Kx4 4 5 MN5 ADM3312EARU MN5 ADM3312EARU C1+ 6 C1- 20 C2+ 2 C2- 4 C3+ 24 C3- 22 VCC3 V+1 V-21 GND23 SD19 EN5 T1IN7 T1OUT 18 R1IN 15R1OUT10 T2IN8 T2OUT 17 R2IN 14R2OUT11 T3IN9 T3OUT 16 R3IN 13R3OUT12 R38 0RR38 0R JP31JP31 R28 0RR28 0R R46 100K R46 100K C31 4.7uF C31 4.7uF C32 100nF C32 100nF R35 0RR35 0R C37 100nF C37 100nF R30 0R nm R30 0R nm R18 10K R18 10K R21 47KR21 47K R16 47K R16 47K R17 10K R17 10K J4J4 C38 100nF C38 100nF R29 120R R29 120R C26 100nF C26 100nF C33 100nF C33 100nF TP6TP6 J5J5 R34 0RR34 0R C30 100nF C30 100nF R26 0RR26 0R HE10 20PTS HE10 20PTS VTref1 Vsupply 2 nTRST3 GND1 4 TDI5 GND2 6 TMS7 GND3 8 TCK9 GND4 10 RTCK11 GND5 12 TDO13 GND6 14 nSRST15 GND7 16 DBGRQ17 GND8 18 DBGACK19 GND9 20 C41 100nF C41 100nF R42 100K R42 100K JP11 Header2 JP11 Header2 C29 1uF C29 1uF R40 100K R40 100K JP12 Header2 JP12 Header2 R33 0RR33 0R R44 0RR44 0R TF01A TF01A DAT21 DAT32 CMD3 VCC4 CLK5 VSS6 DAT07 DAT18 GND10 CD9 Sh1 11 Sh2 12 Sh3 13 JP10 Header2 JP10 Header2 R19 0RR19 0R R22 0R nm R22 0R nm R47 0RR47 0R R48 0RR48 0R R31 0RR31 0R R37 47KR37 47K C42 100nF C42 100nF R27 0RR27 0R R23 10K R23 10KR25 0R nmR25 0R nm JP9 Header2 JP9 Header2 MN6 MAX3232CSE MN6 MAX3232CSE T1IN11 T2IN10 R1OUT12 R2OUT9 T1OUT 14 T2OUT 7R1IN 13 R2IN 8 V+2 C1+ 1 C1- 3 C2+ 4 C2- 5 V-6 VCC16 GND15 R20 0RR20 0R R24 0R nm R24 0R nm C28 100nF C28 100nF R45 100K R45 100K
LCD_DB10 LCD_DB11 LCD_DB12 LCD_DB13 LCD_DB14 LCD_DB15 LCD_DB16 LCD_DB17 LCD QTOUCH LCD TOUCH SCREEN LCD BACKLIGHT 22nF use X7R Six slots on PCB for LCD shield LED_A LED_K1 LED_K2 LED_K3 LED_K4 PC13 X_RIGHT X_LEFT Y_UP Y_DOWN PA12 PA13 PA14 PA17 PA11 X_RIGHT Y_UP X_LEFT Y_DOWN X_LEFT X_RIGHT Y_DOWN Y_UP LED_K4 LED_K3 LED_K2 LED_K1 LED_A PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 NRST PC15 PC19 PC11 PC8 PC25 PC24 PC31 PC30 PC29 PC28 PC23 PC22 PC27 PC26 PA1 PA0 PA3 PA2 PA5 PA4 PC13 PC24 PC25 PC26 PC27 PC28 PC29 PC30 PC31 LCD_DB9 LCD_DB8 LCD_DB7 LCD_DB6 LCD_DB5 LCD_DB4 LCD_DB3 LCD_DB2 LCD_DB1 LCD_DB0 LCD_DB0 LCD_DB4 LCD_DB9 LCD_DB5 LCD_DB7 LCD_DB6 LCD_DB8 LCD_DB1 LCD_DB3 LCD_DB2 PA16 PC23 PC22 +3V3 +3V3 DGND DGND DGND DGND DGND +3V3 +3V3 +3V3 AGND_TP +3V3 DGND +3V3 DGND AGND_TP DGND DGNDDGND DGND DGND DGND DGND NRST PC[0..31]PA[0..31] REV DATEMODIF. DES. DATE VER. SCALE 1/1 REV. SHEET This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings. INIT EDITA XX-XXX-XXJH XXX TFT-LCD & QTouch 08-Mar-11 SAM4S-EK REV DATEMODIF. DES. DATE VER. SCALE 1/1 REV. SHEET This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings. INIT EDITA XX-XXX-XXJH XXX TFT-LCD & QTouch 08-Mar-11 SAM4S-EK REV DATEMODIF. DES. DATE VER. SCALE 1/1 REV. SHEET This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings. INIT EDITA XX-XXX-XXJH XXX TFT-LCD & QTouch 08-Mar-11 SAM4S-EK R53 1KR53 1K R70 0RR70 0R R62 100K R62 100K PACDN044Y5R nm TVS, SOT23-5 PACDN044Y5R nm TVS, SOT23-5 R66 0RR66 0R R67 0RR67 0R R56 10K R56 10K R68 R68 C49 22nF C49 22nF R54 1KR54 1K R50 1KR50 1K C57 4.7uF C57 4.7uF R65 100K R65 100K R61 4.7K nmR61 4.7K nm RA3 4.7Kx4 nm RA3 4.7Kx4 nm 4 5 R60 1KR60 1K C50 22nF C50 22nF C55 1uF C55 1uF JP13 Header2JP13 Header2 R51 1KR51 1K C46 22nF C46 22nF MN8 AAT3155ITP-T1 MN8 AAT3155ITP-T1 C1+10 C1-9 EN/SET11 C2+ 7 C2- 6 OUTCP 8 IN5 GND4 D1 3 D2 2 D3 1 D4 12 C60 100nF C60 100nF + C43 10uF + C43 10uF 10uH-100mA 10uH-100mA C58 100nF C58 100nF R72 100K R72 100K FB1 BN03K314S300R FB1 BN03K314S300R C51 22nF C51 22nF C44 100nF C44 100nF R57 1KR57 1K QTouch Slider QTouch Slider SL SM SR SR PINs on BOT PIN 39 PIN 1 FTM280C34D PINs on BOT PIN 39 PIN 1 FTM280C34D R69 0RR69 0RTP9TP9 R64 47K R64 47K C61 4.7uF C61 4.7uF R52 1KR52 1K C47 22nF C47 22nF R58 4.7K R58 4.7K R55 1KR55 1K C56 1uF C56 1uF FH26-39S-0.3SHW FH26-39S-0.3SHW VDD1 DB172 DB163 DB154 DB145 DB136 DB127 DB118 DB109 DB910 DB811 DB712 DB613 DB514 DB415 DB316 DB217 DB118 DB019 VDD20 RD21 WR22 RS23 CS24 RESET25 IM026 IM127 GND28 LED-A29 LEDK130 LEDK231 LEDK332 LEDK433 Y+34 Y-35 X+36 X-37 NC38 GND39 R63 4.7K nmR63 4.7K nm C45 100nF C45 100nF C54 1uF C54 1uF R49 47K R49 47K R59 0RR59 0R RA2 4.7Kx4 nm RA2 4.7Kx4 nm 4 5 R71 R71 QTouch Key QTouch Key C48 22nF C48 22nF TP7TP7TP8TP8 C59 100nF C59 100nF C53 22nF C53 22nF MN7 ADS7843E MN7 ADS7843E XP2 YP3 XM4 YM5 DCLK 16 DIN 14 DOUT 12 CS 15 BUSY 13 PENIRQ 11 VREF 9 VCC1 1 VCC2 10 GND 6 IN37 IN48 R73 100K R73 100K C52 22nF C52 22nF R74 R74
JP14 and JP15 should be set or removed together AD5 DAC1 AUDIO IN DAC ADC AUDIO OUT AUDIO_OUTL AUDIO_OUTL AGND AGND AGND AVDD AGND VDD_AMP AGND AGND AGND DGND +5V DGND +5V DGND DGND DGND AGND AGND AGND AGND AVDD AGND AGND DGND AVDD AGND VCC33 AGND VCC33 DGND VDD_AMP AGND +3V3 DGND VCC33+5V DGND DGND DGND +5V VCC33 PB0 PB1 PB14 PB13 REV DATEMODIF. DES. DATE VER. SCALE 1/1 REV. SHEET This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings. INIT EDITA XX-XXX-XXJH XXX Audio & Power supply 08-Mar-11 SAM4S-EK REV DATEMODIF. DES. DATE VER. SCALE 1/1 REV. SHEET This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings. INIT EDITA XX-XXX-XXJH XXX Audio & Power supply 08-Mar-11 SAM4S-EK REV DATEMODIF. DES. DATE VER. SCALE 1/1 REV. SHEET This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings. INIT EDITA XX-XXX-XXJH XXX Audio & Power supply 08-Mar-11 SAM4S-EK C72 1nF C72 1nF JP19 Header2JP19 Header2 + C75 100uF-TAN-6.3V + C75 100uF-TAN-6.3V JP18JP18 C82 100nF C82 100nF R80 R80 C88 0.47uFC88 0.47uF + C65 22uF + C65 22uF C64 100nF C64 100nF R90 100K R90 100K C93 470pF C93 470pF C90 2.2uFC90 2.2uF C91 4.7uF C91 4.7uF C67 1uF C67 1uF CN1 BNC CN1 BNC +C81 220uF-TAN-6.3V +C81 220uF-TAN-6.3V C74 100nF C74 100nF R84 R84 R103 100KR103 100K R87 47K R87 47K R79 R79 FB3 BN03K314S300R FB3 BN03K314S300R R78 R78 R95 1KR95 1K MN14 MIC5219-3.3YMM MN14 MIC5219-3.3YMM IN2 EN1 BYP4 GND 5 GND 6 GND 7 GND 8 OUT 3 R77 470R R77 470R MN10 BNX002-01 MN10 BNX002-01 SV1 SG2 CV 3 CG1 4 CG2 5 CG3 6 C71 22nF C71 22nF R83 R83 C87 1uF C87 1uF R99 47KR99 47K R88 470R R88 470R JP20 Header2 JP20 Header2 C76 100nF C76 100nF R98 33KR98 33K + C66 22uF + C66 22uF CN3 BNC CN3 BNC C63 22uF C63 22uF JP30JP30 C62 100pF C62 100pF MN9 ZEN056V130A24LS MN9 ZEN056V130A24LS C77 4.7uF C77 4.7uF C86 0.47uFC86 0.47uF R85 R85 JP21 Header2 JP21 Header2 MN13 TPA0223DGQ MN13 TPA0223DGQ VDD3 RIN5 MONO-IN1 LIN9 LO/MO- 10 RO/MO+ 6 ST/MN 7 SHUTD0WN 2 BYPASS 4 GND 8 PAD 11 JP16 Header2 JP16 Header2 R92 102K 1% R92 102K 1% + C80 10uF + C80 10uF C85 0.47uFC85 0.47uF R109 49.9R R109 49.9R R100 33KR100 33K R105 33KR105 33K C73 22uF C73 22uF + C98 220uF-ELE-16V + C98 220uF-ELE-16V MN12 MIC29152WU Micrel's 1.5A LDO, TO263-5 MN12 MIC29152WU Micrel's 1.5A LDO, TO263-5 VIN2 VOUT 4 SD1 GND13 ADJ 5 GND26 R75 47KR75 47K MN11 TS922 MN11 TS922 IN1-2 IN1+3 OUT27 IN2-6 IN2+5 GND 4 VCC 8 OUT1 1 JP14 Header2JP14 Header2 +C83 220uF-TAN-6.3V +C83 220uF-TAN-6.3V R106 R106 JP29JP29 R76 47KR76 47K J11 Phonejack Stereo 3.5 J11 Phonejack Stereo 3.5 1R97 1KR97 1K R93 100K R93 100K VR1 10K VR VR1 10K VR 1 3 R102 100KR102 100KTP12 Test Pad SQ-40TH TP12 Test Pad SQ-40TH C84 0.47uFC84 0.47uF R96 49.9R R96 49.9R R89 169K 1% R89 169K 1% R91 R91 JP15 Header2 JP15 Header2 C89 10nF C89 10nF Power Jack 2.1mm Power Jack 2.1mm JP17 Header2JP17 Header2 C69 1nF C69 1nF J10J10 R86 47K R86 47K R104 47KR104 47K R101 100KR101 100K R82 R82 C68 1uF C68 1uF MIC1 SVB6050 MIC1 SVB6050 1 2 R94 R94 C79 1uF C79 1uF C78 10nF C78 10nF + C92 100uF-TAN-6.3V + C92 100uF-TAN-6.3V R81 100R R81 100R FB2 BN03K314S300R FB2 BN03K314S300R
IRQ0_ZBEE IRQ1_ZBEE SPIO_NPCS2# MISO MOSI SPCK SLP_TR ZB_RSTN PIO A USB LEDS ZIGBEE BUTTONS TWD1 TWCK1 PIO C PIO B PROTOTYPE AREA Pitch = 2.54MM Note: Pin1 is not on the indentation side Pin1 HE10 PA13 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8 PC9 PC10 PC11 PC12 PC13 PC14 PC15 PC19 PC17 PC21 PC16 PC20 PC18 PB6 PB1 PB3 PB7 PB4 PB0 PB5 PB2 PB14 PB9 PB11 PB12 PB8 PB13 PB10 PA6 PA9 PA11 PA14 PA13 PA7 PA8 PA12 PA10 PA15 PA22 PA27 PA23 PA29 PA30 PA25 PA21 PA28 PA24 PA26 PA31 PA16 PB2 PA12 PA14 PA15PA17 PA18 PB3 PC12 PA19 PA20 PC21 PC20 PB10 PB11 PA16 PA17 PA18 PA19 PA20 PB4 PB5 +3V3 +3V3 +3V3+3V3 DGND DGND DGND DGND DGND DGND +3V3 +3V3 +3V3 DGND DGND +3V3 DGND DGND +5V +3V3 +5V +5V+3V3 +3V3 +3V3 +5V DGND FGND FGND +3V3 DGND PC[0..31] PB[0..14] PA[0..31] NRST REV DATEMODIF. DES. DATE VER. SCALE 1/1 REV. SHEET This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings. INIT EDITA XX-XXX-XXJH XXX User IF & ZigBee 08-Mar-11 SAM4S-EK REV DATEMODIF. DES. DATE VER. SCALE 1/1 REV. SHEET This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings. INIT EDITA XX-XXX-XXJH XXX User IF & ZigBee 08-Mar-11 SAM4S-EK REV DATEMODIF. DES. DATE VER. SCALE 1/1 REV. SHEET This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings. INIT EDITA XX-XXX-XXJH XXX User IF & ZigBee 08-Mar-11 SAM4S-EK C94 10pF C94 10pF JP23JP23 R110 47KR110 47K C95 18pF C95 18pF R120 0RR120 0R R116 27RR116 27R 5V D- D+ ID G J15 USB Micro B 5V D- D+ ID G J15 USB Micro B JP26 Header2 JP26 Header2 R119 0RR119 0R D4 LED RedD4 LED Red R113 220R R113 220R RV1 V5.5MLA0603 RV1 V5.5MLA0603 R122 4.7K nm R122 4.7K nm JP22JP22 RV2 V5.5MLA0603 RV2 V5.5MLA0603 R118 0RR118 0R J14J14 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 R112 68KR112 68K Q1 IRLML2502 IRLML2502 J13J13 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 J12J12 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 JP27 Header2 JP27 Header2 R121 0RR121 0R BP1BP1 JP24JP24 R115 100KR115 100K C96 2.2nF C96 2.2nF C97 2.2uF C97 2.2uF J16 HE10 5x2 J16 HE10 5x2 1 2 3 4 5 6 7 8 9 10 R123 4.7K nm R123 4.7K nm D3 LED GreenD3 LED Green BP3BP3 R117 220R R117 220R R111 220R R111 220R D2 LED BlueD2 LED Blue R114 27RR114 27R JP25 Header2 JP25 Header2 BP2BP2
SAM4S-EK Development Board User Guide 6-1 11139A–ATARM–29-Nov-11 Section 6 Troubleshooting
6.1 Board Recovery
Closing JP3 and powering the board will assert ERASE and clear GPNVM bit 1, and thereby selects the boot from the ROM by default. The MCU will boot from the internal ROM to enable a SAM-BA connection through the UART. Connect the SAM4S-EK UART port (J3) to a PC COM port through an RS232 cross- over cable. You can then run the SAM-BA application from that PC to program the internal Flash of the MCU as well as the GPNVM bit 1.
SAM4S-EK Development Board User Guide 7-1 11139A–ATARM–29-Nov-11 Section 7
7.1 Revision History
Table 7-1. Document Comments Change Request Ref. 11139A Initial version.
11139A–ATARM–29-Nov-11 Headquarters International Atmel Corporation
2325 Orchard Parkway
San Jose, CA 95131 USA Atmel Asia Limited Unit 01-5 & 16, 19F BEA Tower, Millennium City 5
418 Kwun Tong Road
Kwun Tong, Kowloon HONG KONG Tel: (+852) 2245-6100 Fax: (+852) 2722-1369 Atmel Munich GmbH Business Campus Parkring 4 D-85748 Garching b. Munich GERMANY Fax: (+49) 89-3194621 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 JAPAN Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Product Contact Web Site www.atmel.com www.atmel.com/AT91SAM Technical Support AT91SAM Support Atmel technical support Sales Contacts www.atmel.com/contacts/ Literature Requests www.atmel.com/literature Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDEN- TAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make cha nges to specifica- tions and product descriptions at any time without notice. Atmel does not make any commitment to update the information contain ed herein. Unless specifically pro- vided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are n ot intended, authorized, or warranted for use as components in applications intended to support or sustain life. © 2011 Atmel Corporation. All rights reserved. Atmel ®, logo and combinations thereof DataFlash ®, SAM-BA ® and others are registered trade- marks or trademarks of Atmel Corporation or its subsidiaries. ARM ®, Thumb ® and the ARMPowered logo ® and others are registered trademarks or trademarks ARM Ltd. Windows ® and others are registered trademarks or trademarks of Microsoft Corporation in the US and/or other coun- tries. Other terms and product names may be trademarks of others.