ATSAM3308

ATSAM3308 ATMEL

Document overview

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Technical content

Features

 Eight DSPs and 24-bit Audio Router On-chip  32 kHz to 96 kHz Sampling Rate  16-bit Microcontroller On-chip  Variety of I/Os, including SmartMedia™ and DataFlash®  Embedded RAM for Single Chip Operation (768 Kbits)  Warm Start Power-down  1µA Typical Deep Power-down, 0.5 mW/MIPS Typical Operating  External Flash/ROM Capability  Available in a 100-lead TQFP Package  Ideal for Real-time Audio Applications – Wavetable Synthesis – MP3 Decoding – Effect Processing (Reverb, Echo, Chorus, Equalizer) – Filtering, Sampling Rate Conversion  Typical Applications: Karaoke, Professional Audio, Cellular Phones, Musical Instruments, Consumer Electronics

Description

The ATSAM3308 is a member of the new ATSAM3000 family that uses the DSP array technology. The ATSAM3308 includes eight 24-bit DSPs, a 24-bit Audio Router and a general-purpose 16-bit on-chip CISC microcontroller. Its high performance and flexibil- ity with 8-input/8-output channels enables implementation of audio applications in professional-quality sound production such as MP3 decoding with time stretch and pitch control, concurrent Wavetable synthesis, effect processing and digital mixing. A variety of I/Os, including external Wave ROM, SmartMedia ® and DataFlash® are pro- vided. Sampling rates up to 96 kHz at 24 bits are supported. Audio Processing ATSAM3308 Combined MIDI-Synthesize r and MP3 Decoder

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Figure 1. ATSAM3308 DSP Array Block Diagram DSP Array The ATSAM3308 includes eight on-chip DSPs. Bus. It can request external data such as compressed audio through the Async Bus. Each P24 RAM can be accessed through the Async Bus. including sample cache, pitch control, 2nd order filter and two envelope generators. 96 kHz. Each frame is divided into 64 time slots. Each slot is divided into 4 bus cycles.

6090A–DRMSD–08/04 allowing inter P24 communication at the current sampling rate. Slots 0 to 7 are reserved for a specific router DSP, which also handles audio out, audio in, and remix send. Async Bus The Async Bus has 24-bit data inside the chip and 16-bit data outside. The P16 processor normally masters the Async Bus; it can read/write the P24 memories and the external or embedded ROM/RAM. However, each P24 can request a bus mas- ter cycle for accessing external ROM/RAM or other P24 memories. This allows efficient intercommunication between several P24s on asynchronous block basis. Specific P24 instructions FLOAT and FIX convert fixed-point DSP data to floating-point 16 bits. This allows for 20-bit audio dynamic range when using 16-bit external memory. 16-bit Processor The P16 processor is widely used in ATSAM products. Using the P16 keeps large firm- ware investments from the ATSAM97xx series. A built-in ROM, connected to the P16 holds basic input/output software (BIOS) for peripherals such as UART, DataFlash, SmartMedia and MPU, as well as a debugger that uses a dedicated asynchronous serial line. The firmware can reside on external parallel ROM/Flash or it can be downloaded at power-up into the built-in 16k x 24 RAM from serial EEPROM, DataFlash, SmartMedia or host. MMU (Memory Management Unit) The MMU handles transfer requests between the external or embedded RAM/ROM, the P16 and the P24s through the Async Bus. The ATSAM3308 includes 16k x 24 RAM on chip. Router: Final ACC, MIX, Audio Out, Audio In This block includes RAM (accessed through the Async Bus) that defines the routing from the Sync Bus to/from the Audio I/O or back to the Sync Bus (mix send). It takes care of mix and accumulation from Sync Bus samples. Eight channels of audio in and eight channels of audio out are provided (4-stereo in/out, I2S format). The stereo audio in channels may have a different sampling rate than the audio out channels. In this case, one (or more) P24 takes care of sampling rate conversion. I/O The ATSAM3308 includes very versatile I/Os, that share common pins for reduced pin count and small IC footprint. Most I/Os, when not used for a specific function, remain available as firmware controlled general-purpose pins. The following peripherals are included on chip:  2 x 8-bit timers  2 x 16-bit timers  Parallel slave 8-bit port, MPU401 compatible  Parallel master 8-bit port, for connection to SmartMedia and/or LCD display, switches, etc.  2 x asynchronous bidirectional serial ports  Synchronous serial slave port (SPI type host connection).  SPI master bidirectional port for EEPROM or DataFlash connection.  Firmware controlled I/O pins.

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Figure 2. Host-controlled MP3 + High Quality Wavetable Player Figure 3. Musical Keyboard with Key Velocity

able synthesis or many I/O pins are required. of operation are host controlled and stand-alone. SmartMedia reserved sectors starting at sector # 1. Table 1. P24 Performance

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 Identical sharing number indicates multifunction pins.  Pd indicates a pin with built-in pull-down resistor.  Pu indicates a pin with built-in pull-up resistor. Table 2. Pinout by Pin Name PWR – Digital ground. All of these pins should be returned to a ground plane. PWROUT if the built-in power switch is used. VC33 13, 50, 83 PWR – Periphery power. All these pins should be returned to nominal 3.3V . I/O 1 General-purpose I/O; can be programmed individually as input or output. 100 In 3 Slave 8-bit interface chip select, active low. firmware will wait for SmartMedia SMPD.

firmware to know the operating frequency of the chip (see FS1). INT 8 Out 6 Serial slave synchronous interface data request, active low. corresponding CLAD3 - 0 is not used. DAAD3 - 0 if the corresponding WSAD3 - 0 is not used. or CLAD0 external rate when sampling rate conversion is requested. when sampling rate conversion is requested. DAAD3 - 1 have built-in pull-downs. They may be left open if not used. Table 2. Pinout by Pin Name (Continued)

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RAM/Flash/ROM at address 200:0000H. down. It may be left open if not used.

download from an external SmartMedia, DataFlash or host. should be grounded or left open for normal operation. available which allow warm restart of the chip.

• Test input. Should be grounded or left open.

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Table 3. ATSAM3308 Pinout by Pin Number

8 IRQ 33 RESET

20 VC18 45 WA21 SMCE

22 GND 47 VC18 72 X1 97 GND

23 DFCS

Figure 4. Thin Plastic 100-lead Quad Flat Pack (TQFP100B) Table 4. Package Dimensions in mm

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6090A–DRMSD–08/04

Electrical Characteristics

Absolute Maximum Ratings (*) Recommended Operating Conditions Note: 1. Operation at lower VC33 values down to VC18 is possible, however external timing may be impaired. Contact Atmel in case of use of these circuits with VC33 outside the recommended operating range. Maximum Ratings" may cause permanent dam- age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the Recommended Operating Conditions of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Voltage on any pin C18 + 0.3V Table 5. Recommended Operating Conditions

Table 6. DC Characteristics (T A = 25°C, VC18 =1.8V ± 10%, VC33 = 3.3V ± 10%)

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The Slave Parallel Interface is typically used to connect the chip to a host processor. Pins used: D7 - D0 (I/O), A0 (Input), WR (Input), RD (Input), IRQ (Output). Figure 6. Host Interface Write Cycle Table 7. Timing Parameters

Status register is read when A0 = 1, RD = 0, CS = 0. If 0, data from ATSAM3308 to host is pending and IRQ is high. Reading the data at A0 = 0 will set TE to 1 and clear IRQ. If 0, then ATSAM3308 is ready to accept DATA from host. Note: If status bit RF is not checked by host, write cycle time should not be lower than 3 µs. provides connection to SmartMedia or other peripherals such as LCD screens. Please refer to Atmel DataFlash datasheets for accurate SPI mode 0 timing. Figure 7. DataFlash Interface Typical Timing

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this interface. Therefore an external ROM/Flash/EEPROM is required. SCLK, therefore the host should change SDIN on the negative SCLK edge. SCLK low, indicates that SDIN will hold MSB data on the next rising SCLK. The data is stored internally into a 256 byte FIFO. sor to send data in burst mode. time between two bytes is 64 fck periods. The contents of the SDIN data are defined by the firmware. Figure 8. Serial Slave Interface Typical Timing Figure 9. Digital Audio Timing

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WCS1 ) of 4M words (total = 16 Mbytes). Figure 12. ROM/Flash Read Cycle PLL. pLCK = tCK /4. Typical value with crystal 12.288 MHz is pLCK = 20 ns.

1. Memory access time should be lower than tACE min. T ypical value with crystal 12.288 MHz is 90 ns.

Table 10. External Memory Parameters

Figure 13. External RAM/Flash Write Timing Table 11. External Flash Timing Parameters

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6090A–DRMSD–08/04 Reset and Power- down During power up, the RESET input should be held low until the crystal oscillator and PLL are stabilized, which takes max. 10 ms. After the low to high transition of RESET, the following happens:  All P24s enter an idle state.  P16 program execution starts in built-in ROM. The power-up sequence is as follows:  STIN is sensed. If HIGH, then the built-in debugger is started.  Addresses 0 & 1 from external ROM are checked. If "DR" is read, then control is transferred to address 400H from external ROM. S M C is sensed. If LOW, then the built-in loader waits for SmartMedia presence detect (SMPD). When detected, the firmware is down loaded from SmartMedia reserved sector 1 and started.  An attempt is made to read the first two bytes of an external EEPROM or DataFlash. If "DR" is read, then the built-in loader loads the firmware from the external EEPROM/DataFlash and starts it.  Firmware download from a host processor is assumed. 1. The 0ACh byte is written to the host, this raises IRQ. The host can recognize that the chip is ready to accept program download. Higher speed transfer can be reached by polling the parallel interface status (CS 2. The host sends the firmware size (in words) on two bytes (Low byte first). 3. The host sends the ATSAM3308 firmware. The firmware should begin with string "DR". 4. The 0ACh byte is written to the host, this raises IRQ. The host can recognize that the chip has accepted the firmware. 5. ATSAM3308 starts the firmware. If PDWN is asserted low, then the crystal oscillator and PLL will be stopped. If the power switch is used, then the chip enters a deep power down sleep mode, as power is removed from the core. To exit power down, PDWN has to be asserted high, then RESET applied. Other power reduction features allowing warm restart are controlled by firmware:  P24s can be individually stopped.  The clock frequency can be internally divided by 256.

6090A–DRMSD–08/04 Recommended Board Layout Like all HCMOS high integration ICs, following simple rules of board layout is mandatory for reliable operations:  GND, VC33, VC18 distribution, decoupling All GND, VC33, VC18 pins should be connected. A GND plane is strongly recom- mended. The board GND + VC33 distribution should be in grid form. Recommended VC18 decoupling is 0.1 µF at each corner of the IC with an additional 10 µF decoupling close to the crystal. VC33 requires a single 0.1 µF decoupling.  Crystal, LFT The paths between the crystal, the crystal compensation capacitors, the LFT filter R-C- R and the IC should be short and shielded. The ground return from the compensation capacitors and LFT filter should be the GND plane from the IC.  Buses Parallel layout from D0 - D7 and WA0 - WA21/WD0 - WD15 should be avoided. The D0 - D7 bus is an asynchronous type bus. Even on short distances, it can induce pulses on WA0 - WA21/WD0 - WD15 which can corrupt address and/or data on these buses. A ground plane should be implemented below the D0 - D7 bus that connects both to the host and to the IC GND. A ground plane should be implemented below the WA0 - WA21/WD0 - WD15 bus that connects both to the ROM/Flash grounds and to the IC.  Analog Section A specific AGND ground plane should be provided, which connects by a single trace to the GND ground. No digital signals should cross the AGND plane. Refer to the Codec vendor recommended layout for correct implementation of the analog section.

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Figure 14. Recommended Crystal Compensation and LFT Filter

6090A–DRMSD–08/04 Product Development and Debugging Atmel provides an integrated product development and debugging tool SamVS. SamVS runs under Windows® (98, ME, 2000, XP). Within the environment, it is possible to: E d i t A s s e m b l e  Debug on real target (In-circuit Emulation)  Program Flash, Dataflash, EEPROM, SmartMedia on target. Two dedicated IC pins, STIN and STOUT allow running firmware directly into the target using standard PC COM port communication at 57.6 Kbauds. Thus time-to-market is optimized by testing directly on the final prototype. A library of frequently used functions is available, such as:  Wavetable synthesis  Reverb/Chorus M P 3 d e c o d e  31-band equalizer  Parametric equalizer Atmel engineers are available to study customer-specific applications.

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www.atmel.com/literature 6090A–DRMSD–08/04 0M © Atmel Corporation 2004. All rights reserved. Atmel® and combinations thereof, Dream® and DataFlash® are the registered trademarks of Atmel Corporation or its subsidiaries. Windows® 98, Windows® 2000, Windows® ME and Windows® XP are the registered trademarks of Microsoft Corporation. SmartMedia™ is the trademark of SanDisk Corporation, MPEG Layer-3 audio decoding technology licensed from Fraunhofer and Thomson Multimedia. Other terms and product names may be the trademarks of others.